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2026-04-13 - 17:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3.osadl.org (updated Mon Apr 13, 2026 12:55:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2889499734141,126cyclictest121rcu_preempt11:41:304
2889199659278,127cyclictest121rcu_preempt09:22:191
288929965823,384cyclictest0-21swapper/209:27:402
288949965724,2cyclictest0-21swapper/409:27:394
288919965256,339cyclictest121rcu_preempt07:34:501
28891996373,3cyclictest0-21swapper/109:27:401
28890996374,382cyclictest0-21swapper/009:27:400
28890996371,126cyclictest0-21swapper/011:35:030
28896996362,3cyclictest0-21swapper/609:25:076
28895996351,383cyclictest0-21swapper/509:27:395
288949963237,380cyclictest0-21swapper/412:42:214
2889299630121,84cyclictest0-21swapper/207:53:562
288959962734,126cyclictest0-21swapper/512:39:455
2889099626285,211cyclictest4305-21diskmemload12:24:310
2889099626285,211cyclictest4305-21diskmemload12:24:300
288969962530,592cyclictest0-21swapper/609:18:286
288909962231,422cyclictest0-21swapper/009:30:190
288909962231,422cyclictest0-21swapper/009:30:180
288909961928,338cyclictest0-21swapper/012:40:170
288919960354,338cyclictest0-21swapper/108:23:561
28892995971,380cyclictest0-21swapper/209:21:482
28893995950,84cyclictest0-21swapper/312:42:003
28893995940,84cyclictest0-21swapper/309:29:493
28895995930,84cyclictest0-21swapper/512:42:015
28894995930,84cyclictest0-21swapper/412:15:094
2889399590332,85cyclictest0-21swapper/311:33:263
288929958532,340cyclictest0-21swapper/209:19:242
2889299584162,254cyclictest28957-21kworker/u16:312:42:112
288909957927,126cyclictest0-21swapper/011:52:510
2889799572489,3cyclictest711rcuc/709:37:567
288959957260,296cyclictest0-21swapper/511:33:425
288929956716,126cyclictest0-21swapper/211:33:402
288949956658,84cyclictest0-21swapper/409:21:484
288909956515,126cyclictest0-21swapper/009:24:490
288969956411,550cyclictest0-21swapper/609:20:296
288979956211,126cyclictest0-21swapper/709:17:447
2889499561135,295cyclictest0-21swapper/412:39:454
288969956047,297cyclictest0-21swapper/610:49:486
28896995598,42cyclictest0-21swapper/611:44:176
2889799555171,126cyclictest121rcu_preempt12:44:477
2889399549295,84cyclictest0-21swapper/312:38:403
2889499547252,42cyclictest14578-21ssh11:32:354
2889399547291,126cyclictest121rcu_preempt12:13:163
2889699544118,254cyclictest23759-21chrt07:53:576
288959954437,84cyclictest0-21swapper/509:17:265
2889699541116,83cyclictest0-21swapper/612:39:036
288929954175,211cyclictest0-21swapper/211:55:102
288969954033,388cyclictest28888-21cyclictest08:52:536
288969954032,428cyclictest0-21swapper/611:52:146
2889299540115,211cyclictest14253-21ssh10:57:562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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