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2026-07-12 - 14:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3.osadl.org (updated Sun Jul 12, 2026 00:55:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1975599792113,634cyclictest0-21swapper/200:11:352
197559971435,676cyclictest23531-21ssh00:03:162
1975499700269,296cyclictest27531-21diskmemload22:53:261
197539970023,211cyclictest0-21swapper/000:11:350
19755996898,507cyclictest0-21swapper/200:32:282
1975599677124,84cyclictest0-21swapper/200:20:592
197559967133,635cyclictest0-21swapper/223:12:342
197599964953,380cyclictest0-21swapper/622:17:366
197549962875,380cyclictest0-21swapper/100:03:341
197589962067,380cyclictest0-21swapper/523:57:035
1975899610100,507cyclictest0-21swapper/522:06:315
1975899605224,126cyclictest561ktimersoftd/500:01:545
19755996036,508cyclictest0-21swapper/223:37:372
197549960310,126cyclictest27945-21kworker/u16:122:43:131
197589960250,380cyclictest0-21swapper/522:21:595
19757996027,295cyclictest0-21swapper/400:04:304
19756995980,84cyclictest0-21swapper/322:22:503
197579959686,507cyclictest0-21swapper/421:58:114
197579959686,507cyclictest0-21swapper/421:58:114
197579959686,507cyclictest0-21swapper/421:58:114
197579959686,507cyclictest0-21swapper/421:58:104
19757995930,84cyclictest0-21swapper/422:06:504
19754995930,84cyclictest0-21swapper/100:24:051
197599959180,296cyclictest0-21swapper/623:20:206
1975899591334,48cyclictest0-21swapper/500:06:285
1975699591122,295cyclictest121rcu_preempt23:38:303
197559959080,507cyclictest0-21swapper/200:06:592
197559958675,508cyclictest0-21swapper/220:00:062
1975599586117,258cyclictest0-21swapper/219:59:262
1975599586117,258cyclictest0-21swapper/219:59:262
1975599585155,428cyclictest0-21swapper/222:22:592
1975599583115,465cyclictest23969-21ssh00:44:162
197579957967,83cyclictest0-21swapper/400:05:234
197539957872,84cyclictest0-21swapper/022:24:540
197559956960,126cyclictest0-21swapper/221:58:102
197559956960,126cyclictest0-21swapper/221:58:102
197559956960,126cyclictest0-21swapper/221:58:102
197559956960,126cyclictest0-21swapper/221:58:102
1975599569101,83cyclictest0-21swapper/222:06:572
197569956599,211cyclictest0-21swapper/323:14:183
197599956351,508cyclictest0-21swapper/621:58:106
197599956351,508cyclictest0-21swapper/621:58:106
197599956351,508cyclictest0-21swapper/621:58:106
197599956351,508cyclictest0-21swapper/621:58:106
197589956111,126cyclictest0-21swapper/523:14:175
197569956150,508cyclictest0-21swapper/321:58:103
197569956150,508cyclictest0-21swapper/321:58:103
197569956150,508cyclictest0-21swapper/321:58:103
197569956150,508cyclictest0-21swapper/321:58:103
197539956193,465cyclictest0-21swapper/000:01:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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