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2026-08-26 - 16:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3.osadl.org (updated Wed Aug 26, 2026 12:54:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27684997286,719cyclictest0-21swapper/009:39:310
276849970526,676cyclictest0-21swapper/009:19:500
27688996801,676cyclictest0-21swapper/409:45:314
276889966468,338cyclictest0-21swapper/411:24:024
2768599661582,77cyclictest231rcuc/109:10:211
2769199652143,127cyclictest0-21swapper/711:12:227
2768799636550,84cyclictest391rcuc/310:43:333
2768699627199,169cyclictest29768-21sh11:12:392
2768899625200,422cyclictest3282-21diskmemload12:18:434
276889962329,591cyclictest64450irq/122-eth008:59:064
276889962171,84cyclictest0-21swapper/409:17:254
2768899617188,296cyclictest11044-21kworker/4:009:22:224
276849960555,84cyclictest7737-21ssh12:10:390
27691995980,381cyclictest0-21swapper/711:24:367
2768499596256,337cyclictest4904-1kworker/u17:112:33:480
27687995940,84cyclictest0-21swapper/310:10:163
27686995940,84cyclictest14101-21runrttasks10:10:172
27686995940,84cyclictest0-21swapper/209:19:492
27688995931,41cyclictest121rcu_preempt09:56:584
27687995930,84cyclictest0-21swapper/310:50:333
27687995930,84cyclictest0-21swapper/309:19:483
27684995930,42cyclictest0-21swapper/009:48:450
276889959282,507cyclictest0-21swapper/410:53:224
27688995920,83cyclictest27682-21cyclictest10:10:174
276859958978,338cyclictest0-21swapper/109:55:571
27684995890,3cyclictest0-21swapper/009:11:450
276889958734,549cyclictest0-21swapper/411:11:244
2768899580239,338cyclictest32531-21nscd11:07:484
276859957727,211cyclictest25-21ksoftirqd/110:50:251
276849957262,507cyclictest0-21swapper/010:53:350
276869957059,508cyclictest0-21swapper/211:23:352
276869957059,211cyclictest0-21swapper/212:21:412
2768599569486,2cyclictest231rcuc/107:47:261
2768599569486,2cyclictest231rcuc/107:47:251
276889956815,86cyclictest0-21swapper/411:38:034
276889956614,515cyclictest0-21swapper/410:24:594
276849956614,169cyclictest0-21swapper/011:22:420
276889956513,169cyclictest0-21swapper/409:06:334
276889956349,253cyclictest4439-21cron12:10:004
276889956349,253cyclictest4439-21cron12:10:004
276889956349,253cyclictest4439-21cron12:10:004
27684995607,550cyclictest0-21swapper/011:06:510
276869955851,211cyclictest0-21swapper/209:25:572
27688995551,550cyclictest0-21swapper/411:34:504
2768699553297,126cyclictest0-21swapper/210:39:232
276869955080,84cyclictest33-21ksoftirqd/209:05:292
276849955084,84cyclictest121rcu_preempt09:55:570
276909954836,303cyclictest0-21swapper/610:12:206
276899954838,507cyclictest0-21swapper/511:12:235
27684995470,3cyclictest0-21swapper/012:18:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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