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2025-09-14 - 06:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3.osadl.org (updated Sun Sep 14, 2025 00:50:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2729928449,30sleep50-21swapper/519:09:075
2725428450,30sleep70-21swapper/719:08:297
2646628453,25sleep60-21swapper/619:05:236
2719528348,30sleep20-21swapper/219:07:352
2699528348,30sleep30-21swapper/319:05:283
2729528147,29sleep10-21swapper/119:09:031
2705228050,25sleep40-21swapper/419:06:174
2733027743,29sleep00-21swapper/019:09:340
49602520,0sleep60-21swapper/619:25:006
271842520,0sleep70-21swapper/723:58:127
166112520,0sleep20-21swapper/222:03:172
301402470,0sleep30-21swapper/321:00:173
53912460,0sleep60-21swapper/622:45:006
172572450,0sleep00-21swapper/023:53:240
2779899410,1cyclictest0-21swapper/719:10:127
115252410,0sleep70-21swapper/722:31:407
27792993327,3cyclictest650-21nscd00:11:132
27791992926,2cyclictest0-21swapper/119:51:181
27791992710,15cyclictest121rcu_preempt00:24:581
27791992710,13cyclictest121rcu_preempt22:36:061
27791992610,14cyclictest121rcu_preempt22:50:131
27791992610,14cyclictest121rcu_preempt00:15:331
27792992525,0cyclictest0-21swapper/222:42:162
27791992510,11cyclictest121rcu_preempt00:05:391
27791992410,12cyclictest121rcu_preempt00:25:401
27791992317,3cyclictest121rcu_preempt23:32:061
27791992314,4cyclictest121rcu_preempt22:10:171
27791992311,11cyclictest121rcu_preempt00:00:071
27791992310,5cyclictest121rcu_preempt21:10:211
27791992310,11cyclictest121rcu_preempt23:25:371
27791992310,11cyclictest121rcu_preempt22:59:511
27791992310,11cyclictest121rcu_preempt22:43:441
27791992310,11cyclictest121rcu_preempt22:16:251
27791992310,11cyclictest121rcu_preempt21:19:571
27791992310,11cyclictest121rcu_preempt00:32:251
27791992211,7cyclictest121rcu_preempt20:55:181
27791992211,7cyclictest121rcu_preempt20:55:181
27791992210,6cyclictest121rcu_preempt23:03:021
27791992210,11cyclictest121rcu_preempt23:54:381
27791992210,10cyclictest121rcu_preempt23:45:451
27791992210,10cyclictest121rcu_preempt21:32:051
27791992210,10cyclictest121rcu_preempt21:27:211
27791992210,10cyclictest121rcu_preempt21:02:011
27797992120,1cyclictest16136-21nscd20:50:146
27796992116,5cyclictest30794-21munin-node00:09:095
27796992110,3cyclictest0-21swapper/519:50:205
27792992117,4cyclictest30794-21munin-node23:52:502
27791992112,6cyclictest121rcu_preempt21:48:531
27791992111,6cyclictest121rcu_preempt22:08:531
27791992110,9cyclictest121rcu_preempt23:23:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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