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2025-08-28 - 22:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3.osadl.org (updated Thu Aug 28, 2025 12:50:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1120329864,30sleep10-21swapper/107:05:501
1127229048,37sleep40-21swapper/407:06:504
1130128651,30sleep60-21swapper/607:07:156
1142828551,29sleep30-21swapper/307:09:063
1093028434,43sleep00-21swapper/007:05:250
889627843,30sleep70-21swapper/707:05:097
1119427640,29sleep20-21swapper/207:05:432
1121727539,29sleep50-21swapper/507:06:025
315822520,0sleep70-21swapper/711:35:147
143322450,0sleep70-21swapper/709:53:387
106372450,0sleep60-21swapper/608:00:156
274602430,0sleep50-21swapper/507:35:005
11928992928,0cyclictest0-21swapper/712:10:237
11922992711,13cyclictest121rcu_preempt12:25:181
11922992710,15cyclictest121rcu_preempt12:33:501
11922992710,15cyclictest121rcu_preempt11:50:181
11926992626,0cyclictest0-21swapper/512:30:055
11922992610,12cyclictest121rcu_preempt10:27:561
11922992515,8cyclictest131rcu_sched12:21:181
11922992510,11cyclictest121rcu_preempt12:11:151
11922992410,9cyclictest0-21swapper/111:15:121
11922992410,12cyclictest121rcu_preempt11:33:061
11922992410,12cyclictest121rcu_preempt10:16:181
11922992410,12cyclictest0-21swapper/110:00:231
11922992410,11cyclictest121rcu_preempt09:53:561
11925992322,1cyclictest0-21swapper/412:31:514
11922992312,9cyclictest121rcu_preempt11:36:211
11922992310,9cyclictest121rcu_preempt09:45:191
11922992310,11cyclictest121rcu_preempt12:35:521
11922992310,11cyclictest121rcu_preempt12:17:321
11922992310,11cyclictest121rcu_preempt12:08:211
11922992310,11cyclictest121rcu_preempt11:09:331
11922992310,10cyclictest121rcu_preempt10:10:131
11922992310,10cyclictest121rcu_preempt09:15:231
11923992210,9cyclictest0-21swapper/212:35:442
11922992221,1cyclictest734-21gmain10:53:581
11922992211,9cyclictest121rcu_preempt07:15:171
11922992210,9cyclictest0-21swapper/107:10:121
11922992210,8cyclictest121rcu_preempt09:37:281
11922992210,11cyclictest121rcu_preempt09:20:291
11922992210,10cyclictest121rcu_preempt12:00:591
11922992210,10cyclictest121rcu_preempt11:45:291
11922992210,10cyclictest121rcu_preempt11:01:501
11922992114,5cyclictest121rcu_preempt10:05:291
11922992111,8cyclictest121rcu_preempt11:13:251
11922992111,8cyclictest121rcu_preempt10:41:061
11922992111,7cyclictest121rcu_preempt11:44:591
11922992111,7cyclictest121rcu_preempt09:55:311
11922992111,7cyclictest121rcu_preempt08:10:161
11922992111,6cyclictest121rcu_preempt09:29:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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