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2025-11-29 - 09:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3.osadl.org (updated Fri Nov 28, 2025 12:50:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1045828753,30sleep60-21swapper/607:08:196
1040228543,37sleep70-21swapper/707:07:337
1043528150,26sleep10-21swapper/107:07:581
1052127946,29sleep30-21swapper/307:09:133
1043627944,30sleep20-21swapper/207:08:002
1039127845,29sleep50-21swapper/507:07:225
1036327868,6sleep40-21swapper/407:06:574
798127743,30sleep00-21swapper/007:05:080
21632620,0sleep00-21swapper/011:05:210
122902620,0sleep20-21swapper/208:55:192
11011995454,0cyclictest0-21swapper/408:55:114
144602530,0sleep20-21swapper/211:42:462
11012995310,42cyclictest0-21swapper/511:51:325
11011995310,43cyclictest0-21swapper/411:10:134
11009995310,0cyclictest0-21swapper/212:29:042
11012995252,0cyclictest0-21swapper/512:08:005
11011995210,42cyclictest0-21swapper/408:30:014
11013995150,0cyclictest0-21swapper/610:15:156
11010995151,0cyclictest0-21swapper/310:10:183
11010995150,0cyclictest0-21swapper/312:10:123
11013995010,39cyclictest0-21swapper/612:27:586
11011995050,0cyclictest0-21swapper/409:50:134
188732490,0sleep40-21swapper/412:00:174
11014994949,0cyclictest0-21swapper/711:35:557
11012994949,0cyclictest0-21swapper/510:46:245
11010994948,0cyclictest0-21swapper/312:38:473
11007994910,38cyclictest0-21swapper/011:54:000
11012994848,0cyclictest0-21swapper/511:55:205
11012994810,38cyclictest0-21swapper/512:30:175
11014994747,0cyclictest0-21swapper/712:36:377
11009994747,0cyclictest0-21swapper/212:33:292
11009994746,0cyclictest0-21swapper/211:05:122
265592460,0sleep30-21swapper/312:04:483
11013994646,0cyclictest0-21swapper/612:15:136
11011994646,0cyclictest0-21swapper/412:22:174
1101099460,46cyclictest0-21swapper/311:15:113
11008994646,0cyclictest0-21swapper/112:29:421
11007994646,0cyclictest0-21swapper/011:27:090
11013994544,0cyclictest0-21swapper/612:05:166
11012994545,0cyclictest0-21swapper/511:10:215
11011994510,34cyclictest0-21swapper/411:20:154
11014994444,0cyclictest0-21swapper/711:21:157
11013994444,0cyclictest0-21swapper/611:32:586
1101099440,0cyclictest0-21swapper/312:06:553
11009994444,0cyclictest0-21swapper/211:55:112
11008994410,34cyclictest0-21swapper/112:35:351
11007994444,0cyclictest0-21swapper/009:40:150
11007994442,1cyclictest0-21swapper/011:18:320
173052430,0sleep70-21swapper/710:57:187
11014994343,0cyclictest0-21swapper/709:45:227
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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