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2025-10-14 - 15:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3.osadl.org (updated Tue Oct 14, 2025 12:50:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
230428551,30sleep50-21swapper/507:09:395
204128268,10sleep60-21swapper/607:05:556
209228046,29sleep10-21swapper/107:06:391
200728046,29sleep20-21swapper/207:05:272
218727945,29sleep40-21swapper/407:08:024
217727945,30sleep30-21swapper/307:07:523
217227843,30sleep70-21swapper/707:07:487
213627744,29sleep00-21swapper/007:07:180
325322460,0sleep50-21swapper/509:35:185
198442460,0sleep20-21swapper/209:45:162
15652400,0sleep70-21swapper/708:55:017
276199350,34cyclictest0-21swapper/407:10:004
2762992810,13cyclictest0-21swapper/509:05:205
2758992727,0cyclictest0-21swapper/112:36:581
276499269,10cyclictest711rcuc/709:05:227
2759992614,11cyclictest18577-1kworker/2:2H12:19:492
2956222410,0sleep10-21swapper/111:23:321
2762992410,11cyclictest0-21swapper/511:05:065
2764992320,1cyclictest721ktimersoftd/710:55:227
2762992311,10cyclictest121rcu_preempt08:52:115
2762992310,9cyclictest0-21swapper/512:36:145
2762992310,9cyclictest0-21swapper/510:33:555
2762992310,0cyclictest0-21swapper/509:48:295
275999235,11cyclictest0-21swapper/209:05:192
2762992217,4cyclictest647-21nscd12:13:035
2762992210,9cyclictest0-21swapper/511:55:505
2762992210,8cyclictest0-21swapper/510:00:015
2762992210,10cyclictest121rcu_preempt10:45:195
2762992210,10cyclictest0-21swapper/510:42:235
2763992121,0cyclictest0-21swapper/607:10:016
2762992110,9cyclictest0-21swapper/512:03:025
2762992110,9cyclictest0-21swapper/508:09:395
2762992110,8cyclictest0-21swapper/512:05:525
2762992110,8cyclictest0-21swapper/511:47:405
2762992110,8cyclictest0-21swapper/511:35:115
2762992110,8cyclictest0-21swapper/511:32:305
2762992110,8cyclictest0-21swapper/511:24:035
2762992110,8cyclictest0-21swapper/511:16:355
2762992110,8cyclictest0-21swapper/510:17:185
2762992110,8cyclictest0-21swapper/510:13:195
2762992110,8cyclictest0-21swapper/509:55:075
2762992110,8cyclictest0-21swapper/509:15:195
2762992110,8cyclictest0-21swapper/508:38:115
2762992110,8cyclictest0-21swapper/507:15:405
2762992110,8cyclictest0-21swapper/507:15:395
2762992110,6cyclictest0-21swapper/512:17:015
2762992110,6cyclictest0-21swapper/511:53:315
2762992110,6cyclictest0-21swapper/510:07:295
2761992119,2cyclictest0-21swapper/409:06:574
2760992121,0cyclictest0-21swapper/309:05:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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