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2026-04-28 - 01:56

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #5, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot3s.osadl.org (updated Mon Apr 27, 2026 12:44:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127052238164,24sleep20-21swapper/207:07:142
127902203165,26sleep00-21swapper/007:08:210
126032202165,25sleep30-21swapper/307:05:543
109562201164,24sleep10-21swapper/107:05:041
340321770,4sleep21301199cyclictest09:10:262
13011991131,110cyclictest0-21swapper/208:55:592
102042680,6sleep01299799cyclictest10:40:220
13011994830,4cyclictest32053-21memory11:30:192
1299799369,13cyclictest0-21swapper/009:45:010
1299799369,13cyclictest0-21swapper/009:45:010
1299799368,13cyclictest3925-21idleruntime-cro09:15:010
1299799335,13cyclictest20879-21munin-run08:40:010
1299799327,12cyclictest8925-21munin-run10:40:010
1299799321,23cyclictest87350irq/126-enp1s0-09:20:230
1301199311,21cyclictest0-21swapper/209:00:112
1301199311,20cyclictest0-21swapper/208:08:192
1301199311,10cyclictest1715-21diskmemload10:35:032
13016993015,9cyclictest0-21swapper/309:42:043
13016993015,9cyclictest0-21swapper/309:42:043
13011993026,3cyclictest0-21swapper/209:54:102
1301199301,20cyclictest0-21swapper/210:44:072
1301199301,12cyclictest0-21swapper/210:10:512
1301199300,13cyclictest0-21swapper/209:33:472
1301699291,20cyclictest0-21swapper/311:43:293
1301199291,23cyclictest0-21swapper/209:23:032
1301199291,14cyclictest0-21swapper/211:43:232
1301199291,11cyclictest1010-21hddtemp_smartct10:20:152
1301199291,11cyclictest0-21swapper/210:01:032
1299799291,13cyclictest19932-21munin-run11:05:010
1301699283,18cyclictest0-21swapper/310:54:453
1301699283,18cyclictest0-21swapper/310:54:453
1301699281,19cyclictest0-21swapper/311:18:093
1301199281,13cyclictest0-21swapper/212:29:152
1301199281,12cyclictest0-21swapper/212:20:072
1301199281,11cyclictest0-21swapper/210:09:432
1299799285,11cyclictest7359-21perf11:50:010
1301699272,17cyclictest0-21swapper/310:42:543
13016992715,3cyclictest0-21swapper/311:25:193
1301699271,18cyclictest0-21swapper/312:37:273
1301699271,18cyclictest0-21swapper/311:57:123
1301699271,18cyclictest0-21swapper/311:11:383
1301699271,18cyclictest0-21swapper/310:58:553
1301199279,9cyclictest0-21swapper/207:40:072
1301199279,3cyclictest0-21swapper/211:00:312
1301199277,9cyclictest0-21swapper/209:06:592
1301199277,9cyclictest0-21swapper/208:38:392
13011992713,3cyclictest0-21swapper/211:51:192
1301199271,12cyclictest0-21swapper/212:38:472
1301199271,12cyclictest0-21swapper/212:11:072
1301199271,12cyclictest0-21swapper/210:52:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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