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2026-07-02 - 06:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot4.osadl.org (updated Thu Jul 02, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13679212864,6sleep20-21swapper/219:06:072
8664211668,8sleep00-21swapper/019:05:050
13643210797,7sleep30-21swapper/319:05:413
13209210795,7sleep10-21swapper/119:05:221
48702700,1sleep30-21swapper/300:15:003
48702700,1sleep30-21swapper/300:15:003
78782650,1sleep010-21rcuc/023:45:180
267962620,0sleep00-21swapper/022:10:150
312742610,1sleep031280-21kthreadcore22:40:180
237012600,1sleep30-21swapper/321:10:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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