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2026-08-13 - 12:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot4.osadl.org (updated Thu Aug 13, 2026 00:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29188216395,65sleep10-21swapper/119:08:521
290802117106,6sleep20-21swapper/219:07:282
291402113103,7sleep00-21swapper/019:08:140
289792111102,6sleep30-21swapper/319:06:093
97142870,0sleep29713-21ssh00:28:022
291922720,0sleep30-21swapper/300:35:243
97052660,1sleep29709-21kthreadcore21:10:192
73622660,0sleep30-21swapper/323:59:193
288882630,0sleep10-21swapper/123:10:221
313602600,1sleep338-21rcuc/300:10:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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