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2026-01-22 - 06:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot4.osadl.org (updated Thu Jan 22, 2026 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22211211960,7sleep20-21swapper/219:05:312
223112115101,11sleep00-21swapper/019:06:490
22297210850,6sleep10-21swapper/119:06:381
22426210494,7sleep30-21swapper/319:08:213
132642630,0sleep30-21swapper/323:33:063
201272610,0sleep2301ktimersoftd/220:30:162
195312610,0sleep30-21swapper/323:07:473
99192590,1sleep30-21swapper/322:09:223
292012580,0sleep00-21swapper/022:45:120
43062570,0sleep10-21swapper/120:15:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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