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2026-03-23 - 20:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot4.osadl.org (updated Mon Mar 23, 2026 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28539212662,6sleep00-21swapper/007:07:360
286902122112,7sleep10-21swapper/107:09:351
28442212262,7sleep30-21swapper/307:06:243
23391210798,6sleep20-21swapper/207:05:032
148392650,0sleep00-21swapper/012:10:160
108072560,0sleep10-21swapper/107:45:221
194582550,0sleep019465-21kthreadcore11:15:170
323662540,1sleep032369-21kthreadcore08:35:190
186262530,0sleep30-21swapper/308:50:193
2889599320,31cyclictest0-21swapper/110:51:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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