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2025-11-08 - 11:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack5slot4.osadl.org (updated Sat Nov 08, 2025 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16356214381,6sleep10-21swapper/119:08:221
16447214276,7sleep30-21swapper/319:09:313
16389212062,6sleep20-21swapper/219:08:462
15779210696,6sleep00-21swapper/019:05:250
90982710,0sleep30-21swapper/323:50:213
322922630,1sleep232295-21kthreadcore19:45:182
186622620,0sleep10-21swapper/120:55:221
235482610,0sleep00-21swapper/022:52:460
270002600,0sleep10-21swapper/120:35:231
55382590,3sleep120-21rcuc/123:33:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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