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2026-01-20 - 22:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Tue Jan 20, 2026 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26877212057,6sleep10-21swapper/107:08:441
26898210696,7sleep20-21swapper/207:09:012
26891210696,7sleep00-21swapper/007:08:550
26354210695,6sleep30-21swapper/307:05:243
221592700,0sleep30-21swapper/311:20:413
326672690,0sleep10-21swapper/111:40:171
73372660,0sleep10-21swapper/111:56:521
43082650,0sleep30-21swapper/309:50:203
292552630,0sleep30-21swapper/309:46:513
156582610,1sleep20-21swapper/212:29:582
315402600,1sleep331543-21kthreadcore11:25:213
46582590,0sleep30-21swapper/311:15:043
38732580,0sleep30-21swapper/310:05:113
252782560,0sleep00-21swapper/010:13:480
277632540,1sleep30-21swapper/309:19:403
317122520,0sleep00-21swapper/010:01:470
235652440,0sleep323570-21kthreadcore11:50:173
27191992926,2cyclictest0-21swapper/207:15:122
27181992918,10cyclictest0-21swapper/009:52:500
2719199280,26cyclictest30687-21ssh09:47:572
2718699280,27cyclictest0-21swapper/112:06:331
2718699280,27cyclictest0-21swapper/108:30:301
2719199270,26cyclictest0-21swapper/212:10:162
2719199270,26cyclictest0-21swapper/211:59:302
2719199270,26cyclictest0-21swapper/210:16:102
2719199270,26cyclictest0-21swapper/207:20:152
2718699270,26cyclictest0-21swapper/112:30:271
2718699270,26cyclictest0-21swapper/111:17:291
2718699270,26cyclictest0-21swapper/109:46:271
2718699270,26cyclictest0-21swapper/108:40:061
2719199261,24cyclictest0-21swapper/209:12:272
2719199261,23cyclictest0-21swapper/210:00:222
2719199260,25cyclictest0-21swapper/210:28:352
2718699262,18cyclictest0-21swapper/111:25:221
2718699260,25cyclictest0-21swapper/111:05:081
2718699260,25cyclictest0-21swapper/108:17:091
2718699260,25cyclictest0-21swapper/107:35:061
2718699260,25cyclictest0-21swapper/107:29:591
2718699260,21cyclictest0-21swapper/110:27:161
2718199260,5cyclictest0-21swapper/012:02:210
2718199260,25cyclictest0-21swapper/012:17:450
2719199250,24cyclictest0-21swapper/207:27:032
27186992523,2cyclictest0-21swapper/111:34:031
27186992523,2cyclictest0-21swapper/107:33:441
27186992523,1cyclictest0-21swapper/109:12:451
27186992521,3cyclictest0-21swapper/110:13:311
27186992516,8cyclictest0-21swapper/110:22:341
2718699251,20cyclictest0-21swapper/112:35:211
2718699250,24cyclictest0-21swapper/112:29:461
2718699250,24cyclictest0-21swapper/109:34:421
2718699250,24cyclictest0-21swapper/108:14:511
2718699250,24cyclictest0-21swapper/107:51:151
179352250,0sleep30-21swapper/311:34:433
2719199243,20cyclictest0-21swapper/212:36:322
2719199243,20cyclictest0-21swapper/212:16:272
2719199242,21cyclictest0-21swapper/210:45:552
27191992421,2cyclictest0-21swapper/211:04:172
27191992421,2cyclictest0-21swapper/209:56:062
27191992420,3cyclictest0-21swapper/208:41:422
2719199240,23cyclictest0-21swapper/212:00:082
2719199240,23cyclictest0-21swapper/211:21:552
2719199240,19cyclictest24929-21ssh11:36:032
2719199240,19cyclictest0-21swapper/207:40:442
2719199240,18cyclictest0-21swapper/211:54:262
2719199240,18cyclictest0-21swapper/209:15:212
27186992421,3cyclictest0-21swapper/110:18:081
2718699240,23cyclictest0-21swapper/111:01:381
2718699240,23cyclictest0-21swapper/109:43:191
2718699240,23cyclictest0-21swapper/109:19:361
2718699240,23cyclictest0-21swapper/108:50:351
2718699240,23cyclictest0-21swapper/108:22:241
2718699240,18cyclictest0-21swapper/112:19:461
2718199242,2cyclictest0-21swapper/011:28:190
2718199241,17cyclictest0-21swapper/010:26:160
27181992410,4cyclictest0-21swapper/012:39:380
2718199240,8cyclictest0-21swapper/010:22:240
2718199240,18cyclictest0-21swapper/009:48:030
2718199240,18cyclictest0-21swapper/009:12:390
2719199232,20cyclictest0-21swapper/211:33:012
2719199232,20cyclictest0-21swapper/211:08:232
2719199232,20cyclictest0-21swapper/210:14:232
2719199230,22cyclictest0-21swapper/212:30:562
2719199230,22cyclictest0-21swapper/211:48:252
2719199230,22cyclictest0-21swapper/211:44:062
2719199230,22cyclictest0-21swapper/210:38:342
2719199230,17cyclictest0-21swapper/210:22:152
2719199230,17cyclictest0-21swapper/210:05:462
27186992320,3cyclictest0-21swapper/108:05:051
2718699230,22cyclictest0-21swapper/112:23:041
2718699230,22cyclictest0-21swapper/111:52:021
2718699230,22cyclictest0-21swapper/111:39:571
2718699230,22cyclictest0-21swapper/110:34:121
2718699230,22cyclictest0-21swapper/110:07:411
2718699230,22cyclictest0-21swapper/109:01:421
2718699230,17cyclictest0-21swapper/110:03:261
2718199236,15cyclictest0-21swapper/009:40:150
2718199233,18cyclictest0-21swapper/012:22:460
2718199232,3cyclictest0-21swapper/010:19:360
2718199232,15cyclictest0-21swapper/011:16:230
27181992314,2cyclictest0-21swapper/011:49:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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