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2026-01-22 - 18:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Thu Jan 22, 2026 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5184212059,6sleep10-21swapper/107:06:421
5180211757,7sleep20-21swapper/207:06:392
5407210696,6sleep00-21swapper/007:09:380
5109210293,6sleep30-21swapper/307:05:433
219592710,0sleep00-21swapper/010:00:210
291052630,0sleep10-21swapper/111:12:201
159552630,0sleep10-21swapper/108:10:211
289992620,2sleep120-21rcuc/111:25:261
138632620,1sleep30-21swapper/309:36:063
196942580,0sleep10-21swapper/110:55:101
277172570,0sleep00-21swapper/010:58:050
198482570,0sleep119853-21kthreadcore10:00:191
284272560,0sleep20-21swapper/210:18:032
318362550,1sleep00-21swapper/012:10:150
561799280,27cyclictest0-21swapper/209:41:342
561599288,18cyclictest0-21swapper/111:30:101
561599281,26cyclictest0-21swapper/108:33:221
561599280,27cyclictest0-21swapper/111:06:361
561799270,26cyclictest0-21swapper/212:22:042
561799270,26cyclictest0-21swapper/211:58:092
561799270,26cyclictest0-21swapper/211:51:332
561799270,26cyclictest0-21swapper/209:36:382
561799270,26cyclictest0-21swapper/209:20:592
561599270,26cyclictest0-21swapper/110:41:051
561599270,26cyclictest0-21swapper/108:57:201
561599270,26cyclictest0-21swapper/107:11:491
561799260,25cyclictest0-21swapper/211:25:242
561799260,25cyclictest0-21swapper/209:57:452
561799260,25cyclictest0-21swapper/207:47:532
561599260,25cyclictest0-21swapper/112:26:131
561599260,25cyclictest0-21swapper/111:45:061
561599260,25cyclictest0-21swapper/111:19:431
561599260,25cyclictest0-21swapper/110:46:351
561599260,25cyclictest0-21swapper/108:38:311
561099260,26cyclictest0-21swapper/010:37:390
561099260,25cyclictest0-21swapper/010:17:470
561099260,25cyclictest0-21swapper/009:30:590
561799250,24cyclictest0-21swapper/212:04:332
5615992518,7cyclictest0-21swapper/108:06:371
561599250,24cyclictest0-21swapper/110:09:501
561599250,24cyclictest0-21swapper/109:37:321
561599250,24cyclictest0-21swapper/109:03:321
561599250,18cyclictest0-21swapper/112:00:391
561799242,21cyclictest0-21swapper/212:16:162
5617992416,7cyclictest0-21swapper/209:52:472
5617992415,8cyclictest0-21swapper/210:32:572
561799241,22cyclictest0-21swapper/210:27:462
561799240,23cyclictest0-21swapper/211:20:572
5615992422,2cyclictest0-21swapper/110:50:511
5615992415,8cyclictest0-21swapper/109:52:161
561599240,23cyclictest0-21swapper/112:10:091
561599240,23cyclictest0-21swapper/110:36:391
561599240,23cyclictest0-21swapper/109:07:051
561599240,23cyclictest0-21swapper/107:49:191
561599240,18cyclictest0-21swapper/109:16:181
5610992417,6cyclictest0-21swapper/012:25:470
561099240,23cyclictest1039-21ssh09:16:500
261642240,0sleep10-21swapper/112:06:441
561799233,14cyclictest0-21swapper/212:25:182
561799232,20cyclictest0-21swapper/211:45:252
561799230,22cyclictest0-21swapper/212:39:292
561799230,22cyclictest0-21swapper/212:06:362
561799230,22cyclictest0-21swapper/207:15:332
561599232,20cyclictest0-21swapper/111:23:181
5615992321,2cyclictest0-21swapper/109:43:231
5615992319,3cyclictest0-21swapper/108:53:561
561599231,21cyclictest0-21swapper/112:30:331
561599230,22cyclictest0-21swapper/111:52:541
561599230,22cyclictest0-21swapper/110:21:521
561599230,22cyclictest0-21swapper/109:48:391
561599230,22cyclictest0-21swapper/109:11:071
561599230,17cyclictest0-21swapper/111:42:051
561599230,17cyclictest0-21swapper/110:16:591
561099232,15cyclictest0-21swapper/010:10:560
5610992314,8cyclictest0-21swapper/011:18:580
561099230,22cyclictest0-21swapper/012:01:530
561099230,22cyclictest0-21swapper/009:51:500
561099230,17cyclictest0-21swapper/012:21:280
561099230,17cyclictest0-21swapper/011:39:120
561799222,19cyclictest0-21swapper/211:14:142
561799222,19cyclictest0-21swapper/209:31:222
561799222,19cyclictest0-21swapper/209:26:542
561799221,20cyclictest0-21swapper/212:30:532
561799221,20cyclictest0-21swapper/211:37:042
561799220,21cyclictest0-21swapper/211:33:152
561799220,21cyclictest0-21swapper/211:04:432
561799220,21cyclictest0-21swapper/210:22:412
561799220,21cyclictest0-21swapper/210:10:032
561799220,21cyclictest0-21swapper/209:15:482
561799220,21cyclictest0-21swapper/208:37:442
561799220,21cyclictest0-21swapper/207:30:132
5615992220,2cyclictest0-21swapper/107:32:441
5615992218,3cyclictest0-21swapper/107:25:271
5615992215,7cyclictest0-21swapper/107:35:011
561599220,21cyclictest0-21swapper/112:35:101
561599220,21cyclictest0-21swapper/112:20:311
561599220,21cyclictest0-21swapper/111:56:511
561599220,21cyclictest0-21swapper/110:32:141
561599220,21cyclictest0-21swapper/110:27:031
561599220,21cyclictest0-21swapper/110:10:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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