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2026-09-05 - 05:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Sat Sep 05, 2026 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8419214181,8sleep00-21swapper/019:08:270
8397212969,6sleep30-21swapper/319:08:093
82302126117,6sleep20-21swapper/219:06:002
1355221210,0sleep113554-21grep23:00:121
82932110100,7sleep10-21swapper/119:06:481
292472880,0sleep129246-21ssh22:37:491
274102650,0sleep30-21swapper/323:46:573
307352620,0sleep10-21swapper/123:49:351
313402610,1sleep131343-21kthreadcore20:50:191
288342610,0sleep30-21swapper/300:01:073
283892590,0sleep20-21swapper/221:40:462
171782590,0sleep00-21swapper/021:09:590
214912560,1sleep30-21swapper/300:12:373
124182560,1sleep30-21swapper/321:05:153
240602550,5sleep0870699cyclictest23:18:180
33612540,1sleep00-21swapper/023:23:260
871599281,26cyclictest0-21swapper/220:24:542
871099285,22cyclictest0-21swapper/121:17:261
79652280,0sleep10-21swapper/122:15:141
871599270,26cyclictest0-21swapper/223:04:372
871599270,26cyclictest0-21swapper/222:55:062
871599270,26cyclictest0-21swapper/222:13:082
871599270,26cyclictest0-21swapper/220:50:592
871599270,26cyclictest0-21swapper/220:16:432
871599270,21cyclictest0-21swapper/222:17:212
871099270,26cyclictest0-21swapper/120:14:581
8715992623,2cyclictest0-21swapper/223:23:162
8715992622,3cyclictest0-21swapper/200:28:052
8715992618,7cyclictest0-21swapper/200:32:172
871599260,2cyclictest22542-21ssh00:13:262
871599260,25cyclictest0-21swapper/223:48:492
871599260,25cyclictest0-21swapper/222:30:272
871599260,25cyclictest0-21swapper/221:55:572
871599260,25cyclictest0-21swapper/221:46:302
871599260,25cyclictest0-21swapper/220:49:122
871599260,25cyclictest0-21swapper/220:09:282
871599260,25cyclictest0-21swapper/220:00:452
871599260,25cyclictest0-21swapper/219:35:502
871599260,25cyclictest0-21swapper/219:24:022
871599260,25cyclictest0-21swapper/200:36:112
871099266,15cyclictest0-21swapper/122:48:351
8710992622,3cyclictest0-21swapper/121:31:591
8715992518,7cyclictest0-21swapper/223:33:102
871599250,3cyclictest0-21swapper/220:55:122
871599250,24cyclictest0-21swapper/222:35:592
871599250,24cyclictest0-21swapper/221:15:412
871599250,24cyclictest0-21swapper/200:04:232
871599250,1cyclictest0-21swapper/221:23:232
871599250,19cyclictest17046-21diskmemload23:57:412
8710992516,8cyclictest0-21swapper/122:12:451
871099250,24cyclictest0-21swapper/123:50:591
871099250,24cyclictest0-21swapper/123:08:501
871099250,24cyclictest0-21swapper/119:51:521
8706992510,14cyclictest0-21swapper/022:08:370
870699250,24cyclictest0-21swapper/023:01:290
870699250,24cyclictest0-21swapper/022:35:380
870699250,24cyclictest0-21swapper/022:32:150
870699250,24cyclictest0-21swapper/021:43:300
870699250,24cyclictest0-21swapper/021:14:050
870699250,24cyclictest0-21swapper/000:37:470
871599242,21cyclictest0-21swapper/223:40:102
8715992421,3cyclictest0-21swapper/219:56:452
8715992420,3cyclictest0-21swapper/219:11:592
871599240,3cyclictest0-21swapper/223:52:322
871599240,23cyclictest0-21swapper/223:05:552
871599240,23cyclictest0-21swapper/222:06:212
871599240,23cyclictest0-21swapper/200:18:082
871599240,18cyclictest5432-21ssh21:31:022
8710992415,8cyclictest0-21swapper/121:38:581
871099240,23cyclictest0-21swapper/123:55:061
871099240,23cyclictest0-21swapper/121:40:301
871099240,22cyclictest0-21swapper/122:55:371
871099240,19cyclictest0-21swapper/123:32:261
871099240,18cyclictest0-21swapper/100:35:001
870699240,23cyclictest0-21swapper/023:35:420
870699240,23cyclictest0-21swapper/021:15:020
870699240,23cyclictest0-21swapper/000:13:510
870699240,23cyclictest0-21swapper/000:01:180
871599239,13cyclictest0-21swapper/219:25:132
8715992321,2cyclictest0-21swapper/223:19:132
871599231,3cyclictest0-21swapper/221:02:222
871599231,21cyclictest0-21swapper/223:35:252
871599231,21cyclictest0-21swapper/220:25:552
871599231,21cyclictest0-21swapper/220:13:212
871599231,21cyclictest0-21swapper/219:52:582
871599230,18cyclictest0-21swapper/222:51:182
871599230,18cyclictest0-21swapper/222:51:182
871099239,13cyclictest0-21swapper/122:05:131
8710992315,7cyclictest0-21swapper/100:15:491
871099230,22cyclictest0-21swapper/123:40:411
871099230,22cyclictest0-21swapper/123:39:341
871099230,22cyclictest0-21swapper/123:25:061
871099230,22cyclictest0-21swapper/123:23:381
871099230,22cyclictest0-21swapper/123:16:251
871099230,22cyclictest0-21swapper/122:40:461
871099230,22cyclictest0-21swapper/122:23:411
871099230,22cyclictest0-21swapper/122:02:401
871099230,22cyclictest0-21swapper/121:48:531
871099230,22cyclictest0-21swapper/121:29:011
871099230,22cyclictest0-21swapper/121:21:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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