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2026-03-05 - 02:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Thu Mar 05, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
92392126114,7sleep10-21swapper/119:07:311
90822113103,7sleep30-21swapper/319:05:273
93762110100,7sleep20-21swapper/219:09:152
9096210898,7sleep00-21swapper/019:05:370
188812660,0sleep20-21swapper/221:40:012
120652620,1sleep30-21swapper/319:35:193
82472570,0sleep00-21swapper/021:00:180
100982560,0sleep338-21rcuc/322:55:183
164002520,1sleep10-21swapper/121:05:201
9611992723,3cyclictest0-21swapper/222:20:262
961199270,26cyclictest0-21swapper/221:17:112
961199270,26cyclictest0-21swapper/220:54:522
961199270,26cyclictest0-21swapper/220:03:102
961199270,26cyclictest0-21swapper/200:17:342
960799271,25cyclictest8-21rcu_preempt21:40:021
960799270,26cyclictest0-21swapper/123:19:261
960799270,26cyclictest0-21swapper/123:05:051
960799270,26cyclictest0-21swapper/122:58:441
960799270,26cyclictest0-21swapper/122:54:201
960799270,26cyclictest0-21swapper/122:39:081
960799270,26cyclictest0-21swapper/122:34:561
960799270,26cyclictest0-21swapper/122:26:081
960799270,26cyclictest0-21swapper/122:23:151
960799270,26cyclictest0-21swapper/121:45:441
960799270,26cyclictest0-21swapper/121:11:201
960799270,26cyclictest0-21swapper/120:22:071
960799270,26cyclictest0-21swapper/119:41:131
960799270,26cyclictest0-21swapper/119:37:361
960799270,26cyclictest0-21swapper/100:25:481
960799270,26cyclictest0-21swapper/100:13:511
960399270,7cyclictest16026-21awk22:35:000
960399270,26cyclictest0-21swapper/022:05:530
960799260,25cyclictest0-21swapper/123:59:381
960799260,25cyclictest0-21swapper/123:52:511
960799260,25cyclictest0-21swapper/123:42:451
960799260,25cyclictest0-21swapper/123:11:541
960799260,25cyclictest0-21swapper/120:16:551
960799260,25cyclictest0-21swapper/119:31:371
960799260,25cyclictest0-21swapper/119:16:371
960799260,25cyclictest0-21swapper/119:12:371
960799260,25cyclictest0-21swapper/100:23:361
9603992618,7cyclictest749-21snmpd22:16:440
9603992618,7cyclictest749-21snmpd20:58:460
9611992522,2cyclictest0-21swapper/223:48:052
9611992521,3cyclictest0-21swapper/223:56:272
961199250,24cyclictest0-21swapper/222:05:202
960799250,24cyclictest0-21swapper/121:32:411
960799250,24cyclictest0-21swapper/121:24:561
960799250,24cyclictest0-21swapper/119:59:041
9603992518,6cyclictest749-21snmpd23:50:570
9603992518,6cyclictest749-21snmpd23:29:320
9603992518,6cyclictest749-21snmpd19:55:280
9603992518,6cyclictest749-21snmpd19:49:420
9603992517,7cyclictest749-21snmpd22:11:380
9603992517,7cyclictest749-21snmpd20:18:370
9611992422,1cyclictest0-21swapper/222:10:112
961199240,23cyclictest0-21swapper/223:51:322
9607992422,2cyclictest0-21swapper/119:28:371
9607992417,7cyclictest0-21swapper/121:17:501
9603992418,5cyclictest749-21snmpd23:12:150
9603992417,6cyclictest749-21snmpd23:21:230
9603992417,6cyclictest749-21snmpd21:06:410
9603992417,6cyclictest749-21snmpd20:23:070
9603992417,6cyclictest749-21snmpd19:15:580
9603992416,7cyclictest749-21snmpd23:04:350
9603992416,7cyclictest749-21snmpd22:46:120
961199231,21cyclictest0-21swapper/222:33:322
961199230,22cyclictest0-21swapper/219:56:282
961199230,17cyclictest0-21swapper/219:54:322
9603992315,7cyclictest749-21snmpd19:39:580
960399230,18cyclictest280-21systemd-journal20:54:170
961199220,21cyclictest0-21swapper/221:25:592
961199220,21cyclictest0-21swapper/221:25:592
960799220,21cyclictest0-21swapper/120:52:461
960799220,21cyclictest0-21swapper/120:25:571
960799220,21cyclictest0-21swapper/100:37:091
960799220,21cyclictest0-21swapper/100:01:411
9603992216,5cyclictest749-21snmpd20:25:220
9603992216,5cyclictest749-21snmpd19:11:010
9603992214,7cyclictest749-21snmpd20:37:250
9603992214,7cyclictest749-21snmpd00:38:300
961199214,15cyclictest0-21swapper/221:40:202
961199213,17cyclictest0-21swapper/220:30:202
961199211,19cyclictest0-21swapper/223:15:202
961199210,20cyclictest0-21swapper/223:28:272
961199210,20cyclictest0-21swapper/222:35:212
961199210,20cyclictest0-21swapper/221:59:122
961199210,20cyclictest0-21swapper/221:20:272
961199210,20cyclictest0-21swapper/220:41:072
961199210,20cyclictest0-21swapper/219:40:142
961199210,20cyclictest0-21swapper/219:15:092
961199210,20cyclictest0-21swapper/200:12:492
961199210,18cyclictest0-21swapper/222:48:032
961199210,15cyclictest0-21swapper/223:34:042
960799210,2cyclictest0-21swapper/123:33:201
960799210,2cyclictest0-21swapper/121:54:411
960799210,2cyclictest0-21swapper/119:20:011
960799210,20cyclictest0-21swapper/123:49:381
960799210,20cyclictest0-21swapper/123:29:211
960799210,20cyclictest0-21swapper/122:10:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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