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2026-04-09 - 03:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Thu Apr 09, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62452117107,7sleep10-21swapper/119:09:541
6147211076,30sleep20-21swapper/219:08:382
6067210999,7sleep00-21swapper/019:07:370
5930210997,7sleep30-21swapper/319:05:513
83802670,0sleep00-21swapper/000:25:180
189102610,1sleep30-21swapper/319:15:193
47682580,1sleep30-21swapper/320:30:163
231852580,0sleep30-21swapper/300:35:213
231852580,0sleep30-21swapper/300:35:213
287032570,0sleep30-21swapper/300:15:113
316862550,0sleep30-21swapper/323:20:133
245582540,0sleep30-21swapper/319:50:153
209662540,0sleep00-21swapper/021:40:220
642799291,27cyclictest0-21swapper/219:16:312
642799280,27cyclictest0-21swapper/219:20:232
642399280,27cyclictest0-21swapper/122:10:161
642399280,27cyclictest0-21swapper/120:20:301
641899280,27cyclictest0-21swapper/020:02:420
642799270,26cyclictest0-21swapper/222:23:142
642399270,26cyclictest1674-21taskset20:27:591
642399270,26cyclictest0-21swapper/122:05:161
642399270,26cyclictest0-21swapper/121:06:291
642399270,26cyclictest0-21swapper/100:31:151
641899270,26cyclictest0-21swapper/021:55:420
641899270,26cyclictest0-21swapper/019:37:260
642799260,25cyclictest0-21swapper/223:21:012
642799260,25cyclictest0-21swapper/223:04:292
642399260,26cyclictest0-21swapper/122:16:181
642399260,25cyclictest0-21swapper/122:37:341
642399260,25cyclictest0-21swapper/120:08:271
642399260,25cyclictest0-21swapper/119:14:411
6423992522,3cyclictest0-21swapper/123:30:461
6423992517,7cyclictest0-21swapper/100:38:271
6423992517,7cyclictest0-21swapper/100:38:261
642399250,24cyclictest0-21swapper/123:29:551
642399250,24cyclictest0-21swapper/100:07:011
642799243,20cyclictest0-21swapper/200:34:152
642399240,24cyclictest0-21swapper/100:03:591
641899240,23cyclictest0-21swapper/020:16:060
641899240,1cyclictest0-21swapper/019:15:110
642799232,17cyclictest0-21swapper/223:35:102
6423992320,2cyclictest0-21swapper/122:27:161
6418992315,7cyclictest0-21swapper/023:11:340
3263622310,3sleep30-21swapper/321:51:513
642799224,16cyclictest0-21swapper/219:30:222
6427992219,2cyclictest0-21swapper/222:33:252
6427992218,3cyclictest0-21swapper/220:41:572
642799221,20cyclictest0-21swapper/222:41:252
642799220,21cyclictest0-21swapper/222:16:282
642799220,21cyclictest0-21swapper/220:17:232
642799220,21cyclictest0-21swapper/200:18:032
6423992220,2cyclictest0-21swapper/122:34:351
6423992214,7cyclictest24573-21kthreadcore21:15:201
6423992214,7cyclictest24573-21kthreadcore21:15:201
642399220,21cyclictest0-21swapper/121:55:271
642399220,21cyclictest0-21swapper/121:50:451
642399220,21cyclictest0-21swapper/121:47:541
642399220,21cyclictest0-21swapper/121:33:571
642399220,21cyclictest0-21swapper/121:26:481
642399220,21cyclictest0-21swapper/120:00:101
642399220,21cyclictest0-21swapper/119:57:021
641899220,21cyclictest0-21swapper/019:56:470
6427992117,3cyclictest0-21swapper/223:09:042
6427992117,2cyclictest25676-21sadc23:15:012
642799210,20cyclictest0-21swapper/223:48:162
642799210,20cyclictest0-21swapper/221:31:272
642799210,20cyclictest0-21swapper/221:17:302
642799210,20cyclictest0-21swapper/221:17:302
642799210,20cyclictest0-21swapper/221:13:422
642799210,20cyclictest0-21swapper/220:47:182
642799210,20cyclictest0-21swapper/220:14:572
6423992119,2cyclictest0-21swapper/120:48:241
6423992119,2cyclictest0-21swapper/119:54:441
6423992117,3cyclictest0-21swapper/119:32:381
642399210,3cyclictest0-21swapper/121:44:481
642399210,2cyclictest0-21swapper/123:54:291
642399210,2cyclictest0-21swapper/123:41:281
642399210,20cyclictest0-21swapper/123:57:101
642399210,20cyclictest0-21swapper/123:39:471
642399210,20cyclictest0-21swapper/123:08:011
642399210,20cyclictest0-21swapper/123:02:461
642399210,20cyclictest0-21swapper/122:50:371
642399210,20cyclictest0-21swapper/121:23:451
642399210,20cyclictest0-21swapper/121:11:241
642399210,20cyclictest0-21swapper/120:58:271
642399210,20cyclictest0-21swapper/120:38:121
642399210,20cyclictest0-21swapper/120:31:121
642399210,20cyclictest0-21swapper/120:11:241
642399210,20cyclictest0-21swapper/119:44:381
642399210,20cyclictest0-21swapper/119:18:321
642399210,20cyclictest0-21swapper/100:19:171
6418992118,3cyclictest0-21swapper/022:19:480
6418992118,2cyclictest749-21snmpd22:05:330
6418992118,2cyclictest749-21snmpd00:19:140
6418992117,2cyclictest20356-21sadc21:15:000
642799207,7cyclictest0-21swapper/221:45:122
642799206,9cyclictest0-21swapper/221:00:112
6427992018,1cyclictest749-21snmpd22:37:222
6427992018,1cyclictest749-21snmpd21:43:542
6427992018,1cyclictest749-21snmpd20:59:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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