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2026-01-24 - 23:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Fri Jan 23, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20459211857,7sleep00-21swapper/007:09:260
1180921140,11sleep02066899cyclictest09:30:130
20392210595,7sleep20-21swapper/207:08:342
20251210293,6sleep30-21swapper/307:06:433
20264210061,8sleep10-21swapper/107:06:541
14242710,0sleep20-21swapper/210:05:562
54072560,0sleep20-21swapper/212:00:232
118452560,0sleep00-21swapper/010:10:220
40732550,0sleep00-21swapper/009:54:520
312992550,1sleep231301-21kthreadcore09:10:152
311962410,0sleep20-21swapper/211:55:262
2066899290,13cyclictest0-21swapper/011:34:270
2067999280,27cyclictest0-21swapper/209:51:062
2067499280,27cyclictest0-21swapper/112:23:051
2067499280,27cyclictest0-21swapper/111:26:311
2067999270,26cyclictest0-21swapper/208:35:382
2067499270,26cyclictest0-21swapper/111:50:401
2067499270,26cyclictest0-21swapper/111:00:511
2067499270,26cyclictest0-21swapper/110:57:121
2067499270,26cyclictest0-21swapper/110:52:431
2067499270,26cyclictest0-21swapper/110:26:431
2067499270,26cyclictest0-21swapper/110:03:021
2067499270,26cyclictest0-21swapper/109:46:181
2067499270,26cyclictest0-21swapper/109:27:291
2067499270,26cyclictest0-21swapper/109:22:531
2067499270,26cyclictest0-21swapper/109:17:471
2067499270,26cyclictest0-21swapper/107:36:051
20679992615,10cyclictest0-21swapper/209:20:112
2067999260,25cyclictest0-21swapper/212:32:052
2067499260,25cyclictest0-21swapper/109:13:501
20668992618,7cyclictest750-21snmpd10:37:430
20668992615,10cyclictest0-21swapper/009:40:410
2066899260,3cyclictest0-21swapper/009:11:310
2066899260,2cyclictest0-21swapper/009:46:200
2066899260,25cyclictest0-21swapper/012:23:340
2066899260,25cyclictest0-21swapper/009:36:560
2066899260,19cyclictest0-21swapper/011:50:470
2066899260,14cyclictest0-21swapper/010:20:400
174402260,1sleep338-21rcuc/308:59:363
2067499250,24cyclictest0-21swapper/109:38:031
2066899259,15cyclictest0-21swapper/012:00:230
2066899257,16cyclictest0-21swapper/009:26:280
20668992518,6cyclictest750-21snmpd09:06:080
2066899250,24cyclictest0-21swapper/009:17:370
2066899250,13cyclictest0-21swapper/011:39:150
2066899250,12cyclictest0-21swapper/009:58:480
2066899250,12cyclictest0-21swapper/009:58:480
20679992422,2cyclictest0-21swapper/211:23:052
2067999240,23cyclictest0-21swapper/210:11:492
2067999240,18cyclictest0-21swapper/212:23:082
2067999240,17cyclictest0-21swapper/211:36:592
2067499248,15cyclictest0-21swapper/109:34:301
2066899243,1cyclictest0-21swapper/011:42:250
20668992418,5cyclictest750-21snmpd10:54:520
20668992414,4cyclictest0-21swapper/010:19:340
20668992410,5cyclictest18512-21awk07:35:000
2066899240,2cyclictest0-21swapper/009:20:470
2066899240,1cyclictest0-21swapper/010:00:510
2067999232,20cyclictest0-21swapper/212:18:342
20679992317,6cyclictest0-21swapper/211:15:282
2067999230,22cyclictest0-21swapper/210:00:032
2067999230,22cyclictest0-21swapper/209:37:092
2067999230,21cyclictest0-21swapper/210:15:532
20674992314,8cyclictest0-21swapper/110:14:181
2067499230,22cyclictest0-21swapper/110:19:031
20668992317,5cyclictest750-21snmpd08:34:410
20668992317,5cyclictest750-21snmpd07:54:340
20668992316,6cyclictest750-21snmpd12:36:110
20668992316,6cyclictest750-21snmpd08:45:140
20668992316,6cyclictest750-21snmpd08:28:350
2066899231,2cyclictest0-21swapper/010:25:200
2066899230,2cyclictest0-21swapper/012:16:280
2066899230,18cyclictest0-21swapper/011:55:490
20679992219,2cyclictest750-21snmpd10:37:492
20679992218,2cyclictest13746-21/usr/sbin/munin07:55:222
2067999221,20cyclictest0-21swapper/211:14:432
2067999220,3cyclictest0-21swapper/207:53:022
2067999220,21cyclictest0-21swapper/211:32:582
2067999220,21cyclictest0-21swapper/210:25:272
2067999220,21cyclictest0-21swapper/209:34:252
2067999220,21cyclictest0-21swapper/209:17:282
2067999220,21cyclictest0-21swapper/208:31:502
2067999220,16cyclictest0-21swapper/210:22:022
2067999220,16cyclictest0-21swapper/209:55:342
2067999220,16cyclictest0-21swapper/209:55:342
20674992215,7cyclictest0-21swapper/112:01:491
2067499220,21cyclictest0-21swapper/111:30:091
2067499220,21cyclictest0-21swapper/110:23:401
2067499220,21cyclictest0-21swapper/110:06:151
2067499220,21cyclictest0-21swapper/108:10:131
2067499220,17cyclictest0-21swapper/109:50:451
20668992216,5cyclictest750-21snmpd08:57:200
20668992216,5cyclictest750-21snmpd07:15:190
20668992216,5cyclictest750-21snmpd07:13:180
20668992215,6cyclictest750-21snmpd11:11:390
20668992214,7cyclictest750-21snmpd08:51:080
2066899220,8cyclictest0-21swapper/011:27:040
2066899220,4cyclictest0-21swapper/011:23:370
2066899220,3cyclictest0-21swapper/010:05:170
2066899220,2cyclictest17097-21smartctl11:45:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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