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2026-01-17 - 16:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Sat Jan 17, 2026 12:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18314210696,7sleep00-21swapper/007:07:440
18270210595,7sleep10-21swapper/107:07:091
18124210595,6sleep20-21swapper/207:05:252
846921020,0sleep28468-21ssh10:24:302
1311329282,7sleep30-21swapper/307:05:103
325902740,0sleep30-21swapper/311:30:163
13602730,0sleep20-21swapper/209:53:172
209032630,1sleep020909-21kthreadcore07:35:180
264932590,1sleep2301ktimersoftd/211:26:142
126792590,0sleep10-21swapper/110:10:591
97632580,1sleep30-21swapper/310:51:343
70102560,0sleep10-21swapper/110:23:201
88922550,0sleep20-21swapper/211:20:132
207632540,0sleep10-21swapper/110:56:051
303802530,0sleep30-21swapper/309:24:553
116142400,0sleep229-21rcuc/209:15:202
1866899280,26cyclictest0-21swapper/211:56:012
1866899270,26cyclictest0-21swapper/211:35:562
1866899270,26cyclictest0-21swapper/211:08:452
1866899270,26cyclictest0-21swapper/210:27:412
1866899270,26cyclictest0-21swapper/209:11:042
1866899270,26cyclictest0-21swapper/207:13:032
1866899260,25cyclictest0-21swapper/212:29:132
1866899260,22cyclictest3709-21kworker/u8:212:36:402
1866199260,19cyclictest0-21swapper/011:00:530
18668992523,1cyclictest0-21swapper/210:38:382
18661992523,1cyclictest0-21swapper/011:24:050
18661992521,3cyclictest0-21swapper/012:18:460
1866899246,16cyclictest0-21swapper/209:21:472
1866899242,21cyclictest0-21swapper/211:40:552
18668992417,7cyclictest0-21swapper/208:58:312
18668992410,13cyclictest0-21swapper/209:36:152
1866899240,3cyclictest0-21swapper/210:08:472
1866599248,15cyclictest0-21swapper/110:28:341
1866199240,18cyclictest0-21swapper/009:51:460
1866899232,20cyclictest0-21swapper/211:45:342
1866899232,20cyclictest0-21swapper/210:52:382
18668992319,2cyclictest19394-21sadc08:04:592
1866899230,22cyclictest0-21swapper/210:49:052
1866899230,22cyclictest0-21swapper/210:32:432
1866899230,18cyclictest0-21swapper/209:58:212
1866899230,18cyclictest0-21swapper/209:33:202
18665992319,3cyclictest0-21swapper/109:13:551
1866599231,3cyclictest0-21swapper/110:35:441
1866599230,22cyclictest0-21swapper/111:57:521
1866199232,20cyclictest0-21swapper/009:23:380
1866199230,22cyclictest0-21swapper/012:38:000
1866199230,22cyclictest0-21swapper/012:14:460
1866199230,22cyclictest0-21swapper/010:43:160
1866199230,22cyclictest0-21swapper/010:15:560
1866199230,22cyclictest0-21swapper/009:26:350
1866199230,22cyclictest0-21swapper/009:26:340
1866199230,17cyclictest0-21swapper/011:05:560
1866199230,17cyclictest0-21swapper/009:12:530
1866199230,17cyclictest0-21swapper/008:44:300
1866199230,17cyclictest0-21swapper/007:45:000
1866199230,16cyclictest0-21swapper/010:45:180
1866199230,11cyclictest0-21swapper/012:01:120
18668992219,2cyclictest750-21snmpd07:26:242
18668992218,2cyclictest750-21snmpd12:15:122
1866899221,20cyclictest0-21swapper/208:50:162
18668992210,1cyclictest0-21swapper/212:10:332
1866899220,21cyclictest0-21swapper/212:24:392
1866899220,21cyclictest0-21swapper/212:02:292
1866899220,21cyclictest0-21swapper/211:17:282
1866899220,21cyclictest0-21swapper/207:17:362
1866899220,20cyclictest28644-21ssh10:19:052
1866899220,16cyclictest0-21swapper/210:02:072
18665992218,3cyclictest0-21swapper/111:50:161
1866599220,3cyclictest0-21swapper/112:10:571
1866599220,3cyclictest0-21swapper/109:25:351
1866599220,3cyclictest0-21swapper/109:25:341
1866599220,21cyclictest0-21swapper/112:30:021
1866599220,21cyclictest0-21swapper/112:30:011
1866599220,21cyclictest0-21swapper/112:07:161
1866599220,21cyclictest0-21swapper/112:01:361
1866599220,21cyclictest0-21swapper/111:34:241
1866599220,21cyclictest0-21swapper/111:27:091
1866599220,21cyclictest0-21swapper/111:15:331
1866599220,21cyclictest0-21swapper/111:07:511
1866599220,21cyclictest0-21swapper/110:46:361
1866599220,21cyclictest0-21swapper/110:41:291
1866599220,21cyclictest0-21swapper/110:01:441
1866599220,21cyclictest0-21swapper/109:30:461
1866599220,21cyclictest0-21swapper/107:56:041
1866599220,21cyclictest0-21swapper/107:50:511
1866599220,21cyclictest0-21swapper/107:29:151
1866199227,14cyclictest0-21swapper/009:32:370
1866199225,16cyclictest0-21swapper/011:36:060
1866199222,19cyclictest0-21swapper/011:46:140
1866199220,21cyclictest0-21swapper/012:27:240
1866199220,21cyclictest0-21swapper/012:23:280
1866199220,21cyclictest0-21swapper/012:06:160
1866199220,21cyclictest0-21swapper/011:33:550
1866199220,21cyclictest0-21swapper/010:58:160
1866199220,21cyclictest0-21swapper/010:50:550
1866199220,21cyclictest0-21swapper/010:37:410
1866199220,21cyclictest0-21swapper/010:32:580
1866199220,21cyclictest0-21swapper/010:28:480
1866199220,21cyclictest0-21swapper/010:23:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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