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2026-01-17 - 02:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Sat Jan 17, 2026 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24699210996,7sleep00-21swapper/019:08:480
24453210696,7sleep20-21swapper/219:05:382
24640210595,7sleep10-21swapper/119:08:021
19437210595,7sleep30-21swapper/319:05:033
166372680,0sleep30-21swapper/323:45:183
82672620,0sleep00-21swapper/019:50:120
301552600,0sleep338-21rcuc/323:38:013
294192600,0sleep10-21swapper/122:30:131
250672600,0sleep30-21swapper/319:35:183
240312600,0sleep10-21swapper/121:19:441
313282590,0sleep10-21swapper/119:15:011
170592590,0sleep20-21swapper/221:56:032
34822580,0sleep30-21swapper/322:18:553
268522550,0sleep00-21swapper/020:35:140
190022540,0sleep10-21swapper/123:45:561
24973993329,3cyclictest0-21swapper/222:05:082
24973993013,16cyclictest0-21swapper/220:50:112
2496999300,9cyclictest0-21swapper/122:45:021
24969992915,11cyclictest20316-21ssh23:34:361
2496999290,27cyclictest0-21swapper/123:16:071
2497399280,27cyclictest0-21swapper/222:29:592
2497399280,27cyclictest0-21swapper/222:01:492
2497399280,27cyclictest0-21swapper/220:02:302
2496999280,3cyclictest0-21swapper/122:07:091
2496999280,27cyclictest0-21swapper/100:39:101
2496999280,26cyclictest0-21swapper/122:44:341
2496999280,18cyclictest0-21swapper/100:34:551
2496999280,16cyclictest0-21swapper/121:42:071
2497399270,26cyclictest0-21swapper/223:23:112
2497399270,26cyclictest0-21swapper/222:19:282
2497399270,26cyclictest0-21swapper/221:43:032
2497399270,26cyclictest0-21swapper/221:21:512
2497399270,26cyclictest0-21swapper/220:20:262
2497399270,26cyclictest0-21swapper/220:15:022
2497399270,26cyclictest0-21swapper/219:45:042
2496999270,4cyclictest0-21swapper/122:59:571
2496999270,26cyclictest0-21swapper/123:42:451
2496999270,26cyclictest0-21swapper/122:50:261
2496999270,26cyclictest0-21swapper/122:00:551
2496999270,26cyclictest0-21swapper/120:46:181
2496999270,26cyclictest0-21swapper/120:37:181
2496999270,26cyclictest0-21swapper/120:08:381
2496999270,26cyclictest0-21swapper/119:46:501
2496999270,26cyclictest0-21swapper/100:10:481
2496999270,26cyclictest0-21swapper/100:05:271
2496999270,25cyclictest0-21swapper/123:22:231
2496999270,23cyclictest0-21swapper/121:37:141
2496999270,21cyclictest0-21swapper/121:34:071
2496999270,19cyclictest0-21swapper/122:27:441
2496999270,17cyclictest0-21swapper/123:25:331
2497399260,25cyclictest0-21swapper/223:15:272
2497399260,25cyclictest0-21swapper/220:34:362
2497399260,25cyclictest0-21swapper/219:40:552
2496999260,2cyclictest0-21swapper/122:39:261
2496999260,25cyclictest0-21swapper/123:35:501
2496999260,25cyclictest0-21swapper/121:50:181
2496999260,25cyclictest0-21swapper/120:28:091
2496999260,25cyclictest0-21swapper/120:28:081
2496999260,25cyclictest0-21swapper/120:17:381
2496999260,25cyclictest0-21swapper/100:24:291
2496999260,23cyclictest0-21swapper/100:25:481
2496999260,20cyclictest0-21swapper/119:39:201
2497399250,24cyclictest0-21swapper/223:31:142
2497399250,24cyclictest0-21swapper/223:14:552
2497399250,24cyclictest0-21swapper/221:08:182
2497399250,19cyclictest0-21swapper/223:56:322
2496999250,24cyclictest2405-21ssh23:12:261
2496999250,24cyclictest0-21swapper/121:11:481
2496999250,12cyclictest0-21swapper/123:06:271
2496799250,24cyclictest0-21swapper/022:12:200
2496799250,24cyclictest0-21swapper/021:22:390
2496799250,23cyclictest23733-21sensors_temp00:15:210
2497399244,18cyclictest0-21swapper/223:35:192
24973992422,2cyclictest0-21swapper/223:46:202
24973992422,2cyclictest0-21swapper/221:51:212
24973992417,7cyclictest0-21swapper/220:26:232
24973992417,7cyclictest0-21swapper/220:26:232
2497399241,22cyclictest0-21swapper/220:45:392
2497399240,23cyclictest0-21swapper/223:00:382
24969992418,5cyclictest0-21swapper/123:51:061
2496999240,22cyclictest0-21swapper/100:16:541
2496999240,20cyclictest0-21swapper/121:47:471
2496999240,19cyclictest0-21swapper/119:32:131
2496999240,18cyclictest0-21swapper/123:56:041
2496999240,18cyclictest0-21swapper/121:56:311
2496999240,15cyclictest0-21swapper/122:11:551
2496999240,15cyclictest0-21swapper/100:01:121
2496799240,23cyclictest0-21swapper/023:10:420
2496799240,23cyclictest0-21swapper/021:39:540
2496799240,23cyclictest0-21swapper/000:06:400
2497399232,20cyclictest0-21swapper/222:14:012
2497399232,20cyclictest0-21swapper/200:14:162
24973992320,2cyclictest0-21swapper/221:16:422
2497399231,21cyclictest0-21swapper/220:11:532
2497399230,22cyclictest0-21swapper/222:48:242
2496999230,22cyclictest0-21swapper/122:22:051
2496999230,22cyclictest0-21swapper/120:33:201
2496999230,19cyclictest0-21swapper/123:00:081
2496999230,19cyclictest0-21swapper/121:25:091
2496999230,17cyclictest0-21swapper/121:22:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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