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2026-09-20 - 00:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Sat Sep 19, 2026 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13289212261,8sleep00-21swapper/007:06:270
13287212271,9sleep30-21swapper/307:06:263
13388212061,8sleep20-21swapper/207:07:462
13372210595,7sleep10-21swapper/107:07:331
189442660,0sleep2301ktimersoftd/212:23:192
216512650,1sleep30-21swapper/311:15:033
220142630,0sleep1211ktimersoftd/110:45:201
185072630,1sleep30-21swapper/309:20:223
158002630,0sleep00-21swapper/012:07:310
220642600,0sleep3391ktimersoftd/309:35:483
196452600,0sleep20-21swapper/210:03:592
28362590,0sleep10-21swapper/110:51:081
73632580,1sleep30-21swapper/309:58:323
327042580,0sleep10-21swapper/108:50:161
86142560,0sleep10-21swapper/111:35:321
297202560,0sleep30-21swapper/311:04:053
111612560,0sleep30-21swapper/309:18:343
112582520,0sleep00-21swapper/010:55:210
1374399360,28cyclictest0-21swapper/212:29:242
1374399270,26cyclictest0-21swapper/211:30:402
1374399270,26cyclictest0-21swapper/208:39:112
1374399270,26cyclictest0-21swapper/207:34:532
1374399270,26cyclictest0-21swapper/207:28:442
1374399270,25cyclictest21861-21diskmemload09:37:592
1374399270,22cyclictest0-21swapper/210:50:172
1373999270,26cyclictest0-21swapper/111:13:591
1373999270,26cyclictest0-21swapper/109:05:091
1373999270,26cyclictest0-21swapper/109:05:091
1374399260,25cyclictest0-21swapper/211:25:292
1374399260,25cyclictest0-21swapper/209:31:212
1374399260,25cyclictest0-21swapper/208:06:052
1374399260,25cyclictest0-21swapper/207:53:262
1373999261,24cyclictest0-21swapper/109:38:181
1373999260,25cyclictest0-21swapper/111:24:111
1373999260,25cyclictest0-21swapper/111:03:111
13737992624,1cyclictest0-21swapper/011:03:350
13743992523,2cyclictest0-21swapper/209:02:542
13743992521,3cyclictest0-21swapper/208:50:352
1374399250,25cyclictest0-21swapper/207:57:172
1373999250,24cyclictest0-21swapper/110:01:301
1373999250,20cyclictest0-21swapper/112:17:051
1373799250,24cyclictest0-21swapper/010:17:060
1373799250,24cyclictest0-21swapper/007:55:130
1374399242,21cyclictest0-21swapper/210:18:122
1374399242,21cyclictest0-21swapper/209:40:342
1374399241,22cyclictest0-21swapper/211:44:412
1374399240,23cyclictest0-21swapper/207:18:552
1373999241,22cyclictest0-21swapper/109:26:271
1373999240,23cyclictest0-21swapper/110:34:561
1373999240,23cyclictest0-21swapper/109:53:511
1373999240,23cyclictest0-21swapper/109:40:101
1373999240,23cyclictest0-21swapper/109:17:021
1373999240,23cyclictest0-21swapper/109:12:461
1373999240,18cyclictest0-21swapper/112:03:021
1373999240,18cyclictest0-21swapper/112:03:011
1373799240,23cyclictest20078-21kthreadcore11:55:210
1373799240,23cyclictest0-21swapper/009:46:330
1373799240,18cyclictest0-21swapper/010:40:410
1374399232,20cyclictest0-21swapper/211:18:462
13743992321,2cyclictest0-21swapper/207:21:492
13743992320,3cyclictest0-21swapper/210:38:592
1374399230,17cyclictest0-21swapper/212:16:262
1374399230,17cyclictest0-21swapper/211:12:342
1374399230,17cyclictest0-21swapper/209:46:392
1373999232,20cyclictest1107-21sh11:46:451
1373999232,15cyclictest0-21swapper/111:50:561
1373999231,21cyclictest0-21swapper/110:20:401
1373999231,16cyclictest0-21swapper/112:34:161
1373999230,22cyclictest0-21swapper/112:12:291
1373999230,22cyclictest0-21swapper/110:15:321
1373999230,22cyclictest0-21swapper/110:09:381
1373999230,18cyclictest0-21swapper/112:29:481
1373999230,18cyclictest0-21swapper/109:24:001
1373999230,17cyclictest0-21swapper/112:06:271
1373999230,17cyclictest0-21swapper/111:06:501
1373999230,17cyclictest0-21swapper/110:40:481
1373999230,17cyclictest0-21swapper/110:28:421
1373999230,16cyclictest0-21swapper/111:30:061
1373799237,15cyclictest0-21swapper/010:29:420
1373799232,19cyclictest0-21swapper/011:35:110
1373799232,15cyclictest0-21swapper/010:22:180
13737992312,10cyclictest0-21swapper/010:51:220
1373799230,22cyclictest0-21swapper/009:35:380
1373799230,22cyclictest0-21swapper/009:34:220
1373799230,17cyclictest0-21swapper/011:27:430
1374399222,19cyclictest0-21swapper/212:10:022
1374399222,19cyclictest0-21swapper/209:27:042
13743992220,2cyclictest0-21swapper/211:21:492
13743992220,1cyclictest0-21swapper/212:38:282
1374399221,20cyclictest0-21swapper/211:03:192
1374399221,1cyclictest0-21swapper/211:48:402
1374399220,3cyclictest0-21swapper/209:11:112
1374399220,3cyclictest0-21swapper/208:47:572
1374399220,21cyclictest0-21swapper/212:07:442
1374399220,21cyclictest0-21swapper/211:38:212
1374399220,21cyclictest0-21swapper/210:55:332
1374399220,21cyclictest0-21swapper/210:25:302
1374399220,21cyclictest0-21swapper/210:23:062
1374399220,21cyclictest0-21swapper/209:52:422
1374399220,21cyclictest0-21swapper/208:03:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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