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2026-03-02 - 18:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Mon Mar 02, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25128216998,6sleep10-21swapper/107:07:111
25127212565,7sleep00-21swapper/007:07:100
25343212463,7sleep30-21swapper/307:09:583
253312118108,7sleep20-21swapper/207:09:492
287562650,0sleep20-21swapper/209:30:242
257242610,4sleep02550299cyclictest12:20:220
24472610,0sleep00-21swapper/009:10:160
297572560,1sleep129763-21kthreadcore07:10:191
265402560,0sleep20-21swapper/207:10:152
109622560,1sleep3391ktimersoftd/307:20:183
15662530,0sleep10-21swapper/111:30:221
2550699280,27cyclictest0-21swapper/109:18:211
2550999270,26cyclictest0-21swapper/211:37:142
2550999270,26cyclictest0-21swapper/209:57:372
2550699270,26cyclictest0-21swapper/111:58:261
2550699270,26cyclictest0-21swapper/110:50:561
2550699270,26cyclictest0-21swapper/110:43:311
2550699270,26cyclictest0-21swapper/110:13:211
2550699270,26cyclictest0-21swapper/109:44:371
2550699270,26cyclictest0-21swapper/109:23:151
2550699270,26cyclictest0-21swapper/109:09:361
2550699270,26cyclictest0-21swapper/108:48:361
2550699270,26cyclictest0-21swapper/108:14:061
2550299270,26cyclictest0-21swapper/012:10:170
2550999261,24cyclictest0-21swapper/208:34:242
2550999260,25cyclictest0-21swapper/208:22:062
2550699260,3cyclictest0-21swapper/109:52:031
2550699260,25cyclictest0-21swapper/112:37:411
2550699260,25cyclictest0-21swapper/112:30:071
2550699260,25cyclictest0-21swapper/111:51:131
2550699260,25cyclictest0-21swapper/110:30:001
2550699260,25cyclictest0-21swapper/110:06:071
2550699260,25cyclictest0-21swapper/108:23:511
2550699260,25cyclictest0-21swapper/107:59:051
2550699260,25cyclictest0-21swapper/107:28:561
2550699260,25cyclictest0-21swapper/107:16:081
2550999251,23cyclictest0-21swapper/211:27:162
2550999250,24cyclictest0-21swapper/209:11:122
2550699250,24cyclictest0-21swapper/111:36:281
2550699250,24cyclictest0-21swapper/111:03:581
2550699250,24cyclictest0-21swapper/109:47:181
2550699250,24cyclictest0-21swapper/109:27:071
2550699250,24cyclictest0-21swapper/109:04:181
2550699250,16cyclictest0-21swapper/108:50:111
2550299250,24cyclictest0-21swapper/007:10:170
25509992420,3cyclictest0-21swapper/207:16:012
2550999240,23cyclictest0-21swapper/210:08:392
2550999240,17cyclictest29510-21gzip07:38:312
2550699240,23cyclictest0-21swapper/111:40:491
2550699240,23cyclictest0-21swapper/111:06:291
2550699240,19cyclictest0-21swapper/112:01:291
2550699240,18cyclictest0-21swapper/107:34:261
2550999238,13cyclictest0-21swapper/210:55:152
2550999231,3cyclictest0-21swapper/208:10:132
25506992321,2cyclictest0-21swapper/111:21:201
25506992317,5cyclictest749-21snmpd12:05:251
25506992316,7cyclictest0-21swapper/112:24:141
25506992316,7cyclictest0-21swapper/108:34:541
2550699230,22cyclictest28022-21vmstat10:55:251
2550699230,22cyclictest0-21swapper/111:13:371
2550699230,22cyclictest0-21swapper/108:56:361
2550699230,18cyclictest0-21swapper/110:00:541
2550999221,3cyclictest0-21swapper/208:40:212
2550999220,21cyclictest0-21swapper/208:02:312
2550999220,21cyclictest0-21swapper/207:25:292
2550999220,15cyclictest0-21swapper/207:40:132
2550699222,16cyclictest0-21swapper/111:24:591
25506992220,2cyclictest0-21swapper/112:13:561
25506992218,3cyclictest0-21swapper/107:35:561
2550699221,3cyclictest0-21swapper/107:21:351
2550699221,20cyclictest0-21swapper/110:25:551
2550699221,20cyclictest0-21swapper/107:54:351
2550699220,21cyclictest0-21swapper/109:38:361
2550299220,20cyclictest12462-21turbostat07:25:010
25509992119,1cyclictest749-21snmpd10:42:552
25509992117,3cyclictest0-21swapper/210:02:212
2550999211,3cyclictest0-21swapper/208:09:022
2550999211,19cyclictest0-21swapper/209:42:582
2550999210,20cyclictest0-21swapper/212:27:352
2550999210,20cyclictest0-21swapper/208:37:162
2550999210,20cyclictest0-21swapper/207:32:322
25506992117,4cyclictest0-21swapper/109:14:571
25506992117,2cyclictest749-21snmpd12:15:131
25506992116,5cyclictest0-21swapper/109:57:091
25506992114,7cyclictest0-21swapper/111:48:561
2550699210,2cyclictest20788-21sshd08:26:321
2550699210,20cyclictest0-21swapper/111:17:111
2550699210,20cyclictest0-21swapper/110:45:511
2550699210,20cyclictest0-21swapper/110:38:331
2550699210,20cyclictest0-21swapper/110:22:401
2550699210,20cyclictest0-21swapper/110:22:391
2550699210,20cyclictest0-21swapper/109:32:091
2550699210,20cyclictest0-21swapper/108:17:481
2550699210,20cyclictest0-21swapper/107:44:381
25502992119,1cyclictest749-21snmpd09:32:030
25509992018,2cyclictest0-21swapper/207:46:082
25509992018,1cyclictest9709-21cat09:45:152
25509992018,1cyclictest749-21snmpd12:21:192
25509992018,1cyclictest749-21snmpd12:17:112
25509992018,1cyclictest749-21snmpd12:11:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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