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2026-01-19 - 12:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Mon Jan 19, 2026 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24943216694,7sleep20-21swapper/219:05:252
25241210694,7sleep00-21swapper/019:07:260
20049210595,7sleep30-21swapper/319:05:053
2520429888,7sleep10-21swapper/119:06:591
68262670,0sleep30-21swapper/320:45:173
68262670,0sleep30-21swapper/320:45:163
180912630,0sleep20-21swapper/221:43:392
67682620,1sleep120-21rcuc/122:20:191
224362610,0sleep20-21swapper/220:00:192
297122600,0sleep20-21swapper/220:05:182
247422590,0sleep20-21swapper/221:31:492
246182580,1sleep338-21rcuc/323:10:153
236152560,0sleep10-21swapper/100:32:291
264042540,0sleep10-21swapper/122:29:071
52892520,0sleep10-21swapper/123:30:001
25598993015,9cyclictest0-21swapper/023:13:240
2560699280,27cyclictest0-21swapper/122:33:121
2560999270,26cyclictest0-21swapper/222:34:392
2560999270,26cyclictest0-21swapper/221:17:252
2560699270,26cyclictest0-21swapper/122:36:561
2560699270,26cyclictest0-21swapper/120:50:101
2560699270,26cyclictest0-21swapper/120:16:151
2560699270,26cyclictest0-21swapper/119:39:061
2559899270,26cyclictest0-21swapper/023:53:180
2559899270,26cyclictest0-21swapper/022:43:300
2559899270,26cyclictest0-21swapper/019:56:340
2559899270,26cyclictest0-21swapper/019:46:090
2559899270,26cyclictest0-21swapper/019:37:060
2560999260,25cyclictest0-21swapper/222:05:052
2560999260,25cyclictest0-21swapper/200:07:492
2560699269,16cyclictest0-21swapper/121:30:351
2560699260,25cyclictest0-21swapper/123:06:111
2560699260,25cyclictest0-21swapper/120:10:401
2560699260,25cyclictest0-21swapper/100:14:201
2560699260,25cyclictest0-21swapper/100:05:171
2560699260,24cyclictest0-21swapper/123:47:281
2560699260,24cyclictest0-21swapper/123:47:271
25598992623,3cyclictest0-21swapper/019:21:470
2560999250,24cyclictest0-21swapper/222:50:352
25606992522,3cyclictest0-21swapper/120:49:011
25606992522,3cyclictest0-21swapper/120:49:011
25606992520,4cyclictest0-21swapper/122:00:351
2560699250,24cyclictest0-21swapper/122:09:171
2560699250,24cyclictest0-21swapper/121:57:441
25598992516,8cyclictest0-21swapper/021:41:320
2559899250,24cyclictest18204-21ssh00:02:160
2560999240,3cyclictest0-21swapper/223:24:412
2560999240,23cyclictest0-21swapper/222:36:332
2560999240,23cyclictest0-21swapper/222:23:212
2560999240,22cyclictest0-21swapper/222:18:082
25606992421,3cyclictest0-21swapper/120:31:251
25606992421,3cyclictest0-21swapper/119:45:311
25606992418,6cyclictest0-21swapper/123:25:571
2560699240,23cyclictest0-21swapper/121:27:091
2560699240,19cyclictest0-21swapper/122:56:151
25598992422,2cyclictest0-21swapper/021:31:560
25598992421,2cyclictest0-21swapper/022:36:440
2559899240,23cyclictest0-21swapper/023:18:090
2560999232,20cyclictest0-21swapper/222:42:292
2560999232,20cyclictest0-21swapper/222:14:012
25609992319,3cyclictest0-21swapper/200:25:112
2560999230,22cyclictest0-21swapper/223:39:382
2560999230,22cyclictest0-21swapper/223:07:082
2560999230,22cyclictest0-21swapper/221:26:412
2560999230,22cyclictest0-21swapper/200:33:352
2560999230,22cyclictest0-21swapper/200:20:002
2560999230,21cyclictest0-21swapper/223:45:472
2560999230,21cyclictest0-21swapper/223:45:462
2560699238,9cyclictest0-21swapper/123:12:121
25606992320,2cyclictest0-21swapper/119:42:071
25606992319,3cyclictest0-21swapper/122:45:211
25606992319,3cyclictest0-21swapper/121:08:431
25606992319,3cyclictest0-21swapper/119:51:331
2560699230,22cyclictest0-21swapper/123:58:551
2560699230,22cyclictest0-21swapper/123:24:481
2560699230,22cyclictest0-21swapper/123:01:271
2560699230,22cyclictest0-21swapper/121:40:491
2560699230,22cyclictest0-21swapper/121:37:101
2560699230,22cyclictest0-21swapper/119:21:251
2560699230,22cyclictest0-21swapper/100:21:061
2560699230,18cyclictest0-21swapper/122:54:401
2560699230,17cyclictest0-21swapper/123:36:081
2560699230,17cyclictest0-21swapper/122:15:081
2560699230,16cyclictest0-21swapper/121:10:021
2559899230,22cyclictest0-21swapper/021:17:470
2559899230,17cyclictest0-21swapper/023:47:500
2559899230,17cyclictest0-21swapper/023:47:490
2559899230,17cyclictest0-21swapper/022:12:320
2559899230,17cyclictest0-21swapper/021:56:530
2560999222,19cyclictest0-21swapper/221:47:272
2560999220,21cyclictest0-21swapper/222:00:562
2560999220,21cyclictest0-21swapper/221:23:362
2560999220,21cyclictest0-21swapper/200:13:122
2560999220,21cyclictest0-21swapper/200:04:582
2560999220,20cyclictest0-21swapper/223:34:552
2560999220,20cyclictest0-21swapper/200:37:252
25606992219,2cyclictest0-21swapper/119:14:551
25606992218,3cyclictest0-21swapper/119:16:061
2560699221,15cyclictest0-21swapper/100:16:021
2560699220,3cyclictest0-21swapper/122:40:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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