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2026-01-23 - 19:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Fri Jan 23, 2026 00:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19413212160,8sleep00-21swapper/019:06:360
14356211959,6sleep30-21swapper/319:05:073
19617211857,6sleep10-21swapper/119:09:141
14350210696,7sleep20-21swapper/219:05:022
209721030,3sleep01983199cyclictest22:05:500
165922900,0sleep00-21swapper/020:30:180
278172670,1sleep30-21swapper/319:15:123
106552670,0sleep20-21swapper/200:28:282
326022650,0sleep30-21swapper/322:05:213
69832640,1sleep00-21swapper/022:35:220
321632620,0sleep132168-21kthreadcore19:45:171
26662620,0sleep20-21swapper/222:06:172
112362620,0sleep20-21swapper/220:25:192
170932610,0sleep10-21swapper/122:55:101
228622580,0sleep30-21swapper/322:55:403
113222570,0sleep011316-21ssh23:05:180
305762560,0sleep00-21swapper/000:22:500
214252560,1sleep00-21swapper/000:05:190
18062550,0sleep10-21swapper/122:47:531
188732540,0sleep10-21swapper/121:19:401
300092530,0sleep30-21swapper/323:40:173
247872440,0sleep224792-21mailstats21:20:252
1984099297,17cyclictest28432-21kworker/2:100:06:482
1984099270,26cyclictest0-21swapper/223:43:462
1984099270,26cyclictest0-21swapper/220:55:182
1983199270,4cyclictest0-21swapper/023:50:170
1984099260,25cyclictest0-21swapper/200:00:312
1983199260,25cyclictest0-21swapper/021:54:290
1984099250,24cyclictest0-21swapper/200:34:162
1983599257,17cyclictest0-21swapper/123:07:111
1983199250,24cyclictest1169-21ssh22:47:240
1984099242,21cyclictest0-21swapper/223:45:252
1984099240,23cyclictest0-21swapper/223:19:182
1984099240,23cyclictest0-21swapper/222:57:212
1984099240,23cyclictest0-21swapper/221:43:222
1984099240,23cyclictest0-21swapper/200:19:222
1984099240,23cyclictest0-21swapper/200:12:572
1984099240,18cyclictest0-21swapper/221:16:062
1984099240,18cyclictest0-21swapper/200:39:082
1983599241,21cyclictest0-21swapper/100:20:111
1983199240,23cyclictest0-21swapper/019:41:540
1983199240,17cyclictest0-21swapper/022:55:070
1984099238,9cyclictest0-21swapper/220:30:172
1984099232,20cyclictest0-21swapper/223:08:262
1984099232,20cyclictest0-21swapper/222:35:242
19840992319,3cyclictest0-21swapper/222:11:472
19840992316,6cyclictest0-21swapper/223:34:052
1984099231,21cyclictest0-21swapper/223:04:062
1984099231,21cyclictest0-21swapper/220:17:362
1984099230,22cyclictest0-21swapper/222:49:232
1984099230,22cyclictest0-21swapper/222:40:242
1984099230,22cyclictest0-21swapper/221:56:212
1984099230,22cyclictest0-21swapper/200:21:582
1984099230,17cyclictest0-21swapper/223:55:402
1983599230,22cyclictest0-21swapper/119:36:321
1983199232,20cyclictest0-21swapper/022:41:110
19831992314,8cyclictest0-21swapper/000:12:520
1983199230,18cyclictest0-21swapper/021:59:080
1983199230,17cyclictest0-21swapper/023:31:070
1984099225,15cyclictest0-21swapper/222:00:232
19840992213,8cyclictest0-21swapper/221:35:112
1984099221,20cyclictest0-21swapper/223:20:392
1984099221,20cyclictest0-21swapper/221:27:552
1984099220,21cyclictest0-21swapper/223:38:542
1984099220,21cyclictest0-21swapper/222:32:102
1984099220,21cyclictest0-21swapper/221:50:562
1984099220,21cyclictest0-21swapper/221:31:162
1984099220,20cyclictest22824-21apt-get23:25:112
1984099220,16cyclictest0-21swapper/223:10:492
1984099220,16cyclictest0-21swapper/219:18:222
19835992218,3cyclictest0-21swapper/122:30:321
1983599220,21cyclictest0-21swapper/123:58:431
1983599220,21cyclictest0-21swapper/123:15:541
1983599220,21cyclictest0-21swapper/121:38:131
1983599220,21cyclictest0-21swapper/120:26:431
1983599220,21cyclictest0-21swapper/120:22:431
1983599220,21cyclictest0-21swapper/119:14:421
1983599220,21cyclictest0-21swapper/100:17:281
1983199222,19cyclictest0-21swapper/000:31:100
1983199220,21cyclictest0-21swapper/023:43:370
1983199220,21cyclictest0-21swapper/023:19:300
1983199220,21cyclictest0-21swapper/022:25:330
1983199220,21cyclictest0-21swapper/022:10:060
1983199220,21cyclictest0-21swapper/021:12:340
1983199220,21cyclictest0-21swapper/020:05:120
1983199220,16cyclictest0-21swapper/022:21:210
1983199220,16cyclictest0-21swapper/021:44:140
1983199220,16cyclictest0-21swapper/000:26:490
19840992119,1cyclictest750-21snmpd22:23:022
19840992114,6cyclictest0-21swapper/221:46:002
1984099211,18cyclictest0-21swapper/220:40:142
1984099210,20cyclictest0-21swapper/223:51:392
1984099210,20cyclictest0-21swapper/222:51:142
1984099210,20cyclictest0-21swapper/222:27:072
1984099210,20cyclictest0-21swapper/222:17:242
1984099210,20cyclictest0-21swapper/220:04:302
1984099210,15cyclictest0-21swapper/221:13:022
19835992118,3cyclictest0-21swapper/123:30:341
19835992118,3cyclictest0-21swapper/122:13:411
19835992118,2cyclictest0-21swapper/123:24:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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