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2026-03-08 - 06:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Sun Mar 08, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117212119110,6sleep20-21swapper/219:07:212
118872115105,7sleep30-21swapper/319:09:323
11630211297,12sleep00-21swapper/019:06:110
117932110100,7sleep10-21swapper/119:08:161
8822560,0sleep20-21swapper/222:45:182
1210699280,27cyclictest0-21swapper/223:51:122
1210699280,27cyclictest0-21swapper/222:23:322
1210699280,27cyclictest0-21swapper/221:49:062
1210699280,27cyclictest0-21swapper/220:16:272
1210699280,27cyclictest0-21swapper/219:57:182
1210699280,27cyclictest0-21swapper/219:11:442
1210199280,27cyclictest0-21swapper/122:12:531
1209899280,27cyclictest0-21swapper/020:20:270
1210699270,26cyclictest0-21swapper/223:08:172
1210699270,26cyclictest0-21swapper/222:15:592
1210699270,26cyclictest0-21swapper/220:59:492
1210699270,26cyclictest0-21swapper/220:45:432
1210699270,26cyclictest0-21swapper/220:45:422
1210699270,26cyclictest0-21swapper/220:23:232
1210699270,26cyclictest0-21swapper/220:03:152
12101992723,2cyclictest12619-21apt20:34:591
1209899270,26cyclictest0-21swapper/023:31:120
1209899270,26cyclictest0-21swapper/022:58:110
1209899270,26cyclictest0-21swapper/022:45:120
1209899270,26cyclictest0-21swapper/022:30:110
1209899270,26cyclictest0-21swapper/022:16:040
1209899270,26cyclictest0-21swapper/022:08:550
1209899270,26cyclictest0-21swapper/021:55:010
1209899270,26cyclictest0-21swapper/021:41:280
1209899270,26cyclictest0-21swapper/021:29:130
1209899270,26cyclictest0-21swapper/021:21:160
1209899270,26cyclictest0-21swapper/021:07:310
1209899270,26cyclictest0-21swapper/020:50:580
1209899270,26cyclictest0-21swapper/020:36:220
1209899270,26cyclictest0-21swapper/020:12:210
1209899270,26cyclictest0-21swapper/020:07:150
1209899270,26cyclictest0-21swapper/020:02:590
1209899270,26cyclictest0-21swapper/019:24:170
1209899270,26cyclictest0-21swapper/019:12:590
1209899270,26cyclictest0-21swapper/000:37:030
1209899270,26cyclictest0-21swapper/000:37:030
12106992623,3cyclictest0-21swapper/219:42:562
12106992622,3cyclictest0-21swapper/221:13:102
1210699260,25cyclictest0-21swapper/222:37:142
1210699260,25cyclictest0-21swapper/222:31:562
1210699260,25cyclictest0-21swapper/222:25:382
1210699260,25cyclictest0-21swapper/219:16:462
1210199260,25cyclictest0-21swapper/121:53:341
1210199260,25cyclictest0-21swapper/120:21:421
1210199260,25cyclictest0-21swapper/100:39:581
1210199260,25cyclictest0-21swapper/100:39:571
1210199260,25cyclictest0-21swapper/100:26:571
1209899260,26cyclictest0-21swapper/021:36:340
1209899260,25cyclictest0-21swapper/022:44:290
1209899260,25cyclictest0-21swapper/021:04:460
1209899260,25cyclictest0-21swapper/019:26:370
1209899260,25cyclictest0-21swapper/000:31:520
12106992523,2cyclictest0-21swapper/200:17:362
12106992422,2cyclictest0-21swapper/222:58:502
1210699241,22cyclictest0-21swapper/219:22:232
1210699241,22cyclictest0-21swapper/200:11:402
12101992422,2cyclictest0-21swapper/119:26:221
1210199240,23cyclictest0-21swapper/123:26:241
1210199240,23cyclictest0-21swapper/121:34:571
1210199240,23cyclictest0-21swapper/119:32:051
12106992321,2cyclictest0-21swapper/220:29:302
12106992318,4cyclictest0-21swapper/221:15:432
1210699231,4cyclictest0-21swapper/220:14:002
1210699231,4cyclictest0-21swapper/219:32:482
1210699231,3cyclictest0-21swapper/222:51:352
1210699231,21cyclictest0-21swapper/223:33:072
1210699231,21cyclictest0-21swapper/222:07:462
1210699231,21cyclictest0-21swapper/221:37:072
1210699231,21cyclictest0-21swapper/200:39:012
1210699231,21cyclictest0-21swapper/200:39:002
1210699231,21cyclictest0-21swapper/200:00:362
12101992321,2cyclictest0-21swapper/123:04:151
277502220,1sleep027755-21gltestperf23:40:150
12106992219,3cyclictest0-21swapper/221:29:252
12106992218,3cyclictest0-21swapper/221:05:572
1210699221,3cyclictest0-21swapper/223:22:512
1210699221,20cyclictest0-21swapper/223:26:572
1210699221,20cyclictest0-21swapper/222:11:342
1210699221,20cyclictest0-21swapper/222:01:162
1210699220,3cyclictest0-21swapper/200:34:422
1210699220,21cyclictest0-21swapper/223:41:152
1210699220,21cyclictest0-21swapper/223:36:362
1210699220,21cyclictest0-21swapper/221:40:012
1210699220,21cyclictest0-21swapper/220:39:102
1210699220,21cyclictest0-21swapper/200:09:362
12101992219,2cyclictest0-21swapper/120:16:501
1210199220,21cyclictest0-21swapper/122:37:081
1210199220,21cyclictest0-21swapper/119:38:111
1209899220,21cyclictest0-21swapper/023:36:090
1209899220,21cyclictest0-21swapper/023:01:260
1209899220,21cyclictest0-21swapper/021:13:160
1209899220,21cyclictest0-21swapper/020:16:030
1209899220,21cyclictest0-21swapper/000:14:030
1209899220,21cyclictest0-21swapper/000:06:340
12106992119,2cyclictest0-21swapper/221:55:042
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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