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2025-11-28 - 20:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Fri Nov 28, 2025 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
212222111102,6sleep30-21swapper/307:06:253
21360210997,7sleep20-21swapper/207:08:122
21338210999,7sleep00-21swapper/007:07:540
21154210897,7sleep10-21swapper/107:05:301
219552720,0sleep20-21swapper/209:53:532
281732710,1sleep120-21rcuc/109:55:231
234342670,1sleep123440-21kthreadcore07:35:171
16362660,0sleep20-21swapper/212:00:182
162602650,0sleep10-21swapper/109:32:041
134282600,0sleep10-21swapper/111:31:501
276642590,0sleep20-21swapper/211:56:022
9812580,1sleep30-21swapper/310:00:143
92862570,0sleep10-21swapper/109:10:221
294842460,0sleep010-21rcuc/009:21:180
2166099333,27cyclictest0-21swapper/009:11:460
2166099311,21cyclictest0-21swapper/008:45:020
2166099304,22cyclictest0-21swapper/009:25:180
2167099291,27cyclictest0-21swapper/210:33:252
2166099293,9cyclictest12809-21kworker/0:110:14:490
2166099290,3cyclictest0-21swapper/011:34:570
2166099290,3cyclictest0-21swapper/009:47:070
2166099290,26cyclictest8287-21basename12:05:000
2166099290,17cyclictest20138-21cat11:20:000
2166099290,17cyclictest0-21swapper/012:28:260
21670992824,3cyclictest0-21swapper/209:27:152
2167099280,27cyclictest0-21swapper/212:33:232
2167099280,27cyclictest0-21swapper/212:14:112
2167099280,27cyclictest0-21swapper/211:25:182
2166399280,27cyclictest0-21swapper/110:30:571
2166399280,27cyclictest0-21swapper/110:03:091
2166399280,27cyclictest0-21swapper/109:39:541
2166099281,21cyclictest0-21swapper/010:01:120
2166099280,1cyclictest0-21swapper/011:59:070
2167099270,26cyclictest0-21swapper/212:17:552
2167099270,26cyclictest0-21swapper/211:35:432
2167099270,26cyclictest0-21swapper/211:33:472
2167099270,26cyclictest0-21swapper/209:38:392
2167099270,26cyclictest0-21swapper/209:23:202
2167099270,26cyclictest0-21swapper/207:42:072
21663992723,3cyclictest0-21swapper/107:15:421
2166399270,26cyclictest0-21swapper/112:36:141
2166399270,26cyclictest0-21swapper/112:30:491
2166399270,26cyclictest0-21swapper/112:12:321
2166399270,26cyclictest0-21swapper/112:05:231
2166399270,26cyclictest0-21swapper/111:56:531
2166399270,26cyclictest0-21swapper/111:25:311
2166399270,26cyclictest0-21swapper/110:47:511
2166399270,26cyclictest0-21swapper/110:39:581
2166399270,26cyclictest0-21swapper/110:27:071
2166399270,26cyclictest0-21swapper/109:48:331
2166399270,26cyclictest0-21swapper/108:48:411
2166399270,26cyclictest0-21swapper/108:02:431
2166399270,26cyclictest0-21swapper/107:41:051
21660992715,11cyclictest0-21swapper/010:52:220
2166099270,26cyclictest0-21swapper/009:53:320
2167099260,25cyclictest0-21swapper/211:00:512
2167099260,25cyclictest0-21swapper/207:36:432
2166399260,25cyclictest0-21swapper/112:18:141
2166399260,25cyclictest0-21swapper/111:53:321
2166399260,25cyclictest0-21swapper/111:44:261
2166399260,25cyclictest0-21swapper/110:41:221
21660992618,7cyclictest10272-21snmpd07:24:330
21660992615,10cyclictest0-21swapper/011:25:560
2166099260,2cyclictest0-21swapper/012:12:500
2166099260,25cyclictest0-21swapper/008:44:470
2166099260,23cyclictest0-21swapper/009:38:050
2166099260,20cyclictest0-21swapper/012:17:190
2166099260,19cyclictest3762-21diskmemload11:35:460
2166099260,17cyclictest0-21swapper/010:47:130
21670992518,6cyclictest0-21swapper/210:58:192
2167099250,24cyclictest0-21swapper/207:57:352
21663992522,3cyclictest0-21swapper/111:12:421
2166399250,24cyclictest0-21swapper/110:07:141
2166399250,20cyclictest0-21swapper/111:06:251
2166099253,12cyclictest0-21swapper/011:00:130
2166099252,14cyclictest0-21swapper/010:27:020
21660992518,5cyclictest32578-21ls12:35:000
21660992513,11cyclictest0-21swapper/011:45:180
2166099251,17cyclictest0-21swapper/012:38:360
2166099250,4cyclictest0-21swapper/010:31:480
2166099250,2cyclictest1560-21kthreadcore09:05:200
2166099250,2cyclictest0-21swapper/010:06:490
2166099250,1cyclictest0-21swapper/011:54:560
2166099250,1cyclictest0-21swapper/010:19:260
2166099250,16cyclictest0-21swapper/010:37:470
2166099250,15cyclictest0-21swapper/010:57:370
2167099242,21cyclictest0-21swapper/209:19:242
2167099240,23cyclictest0-21swapper/210:16:332
2166399240,23cyclictest0-21swapper/110:16:401
2166399240,23cyclictest0-21swapper/109:27:251
21660992417,6cyclictest10272-21snmpd07:54:050
21660992416,7cyclictest10272-21snmpd08:34:080
21660992416,7cyclictest10272-21snmpd08:15:080
2166099241,11cyclictest0-21swapper/009:30:120
21660992410,11cyclictest0-21swapper/011:21:190
2166099240,21cyclictest0-21swapper/011:42:330
2166099240,18cyclictest0-21swapper/007:46:410
879322319,3sleep30-21swapper/307:21:003
615822319,3sleep30-21swapper/308:42:333
2658422319,3sleep30-21swapper/307:37:333
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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