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2026-03-03 - 06:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Tue Mar 03, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16824213272,7sleep20-21swapper/219:07:512
169772121111,7sleep10-21swapper/119:09:511
16757211562,50sleep00-21swapper/019:07:010
168252113104,6sleep30-21swapper/319:07:513
142372760,0sleep00-21swapper/000:20:160
186442680,0sleep00-21swapper/021:00:210
327252670,0sleep10-21swapper/120:15:251
208742650,0sleep30-21swapper/321:35:013
322122640,1sleep132216-21kthreadcore22:40:181
203002610,1sleep338-21rcuc/319:10:163
197222610,0sleep30-21swapper/323:55:173
217152590,1sleep10-21swapper/119:40:171
267612560,1sleep326764-21kthreadcore21:10:183
145202490,0sleep10-21swapper/123:20:231
1716499391,12cyclictest0-21swapper/220:40:122
1716499280,27cyclictest0-21swapper/222:20:172
1716499270,26cyclictest0-21swapper/221:19:242
1716499270,26cyclictest0-21swapper/219:55:482
1716499270,26cyclictest0-21swapper/219:16:532
17164992618,7cyclictest749-21snmpd23:24:132
17164992618,7cyclictest749-21snmpd22:06:552
17164992617,8cyclictest749-21snmpd00:34:242
1716499260,3cyclictest0-21swapper/221:27:092
1716499260,3cyclictest0-21swapper/221:27:092
1716499260,25cyclictest0-21swapper/222:15:222
17159992623,2cyclictest0-21swapper/123:28:071
17159992623,2cyclictest0-21swapper/100:29:061
17164992518,6cyclictest749-21snmpd20:31:182
1716499251,23cyclictest0-21swapper/222:04:312
1716499250,3cyclictest0-21swapper/200:13:502
17159992523,2cyclictest0-21swapper/121:23:241
17159992521,3cyclictest0-21swapper/120:36:361
17159992518,7cyclictest0-21swapper/122:01:461
17159992517,8cyclictest0-21swapper/119:31:561
1716499243,20cyclictest0-21swapper/220:05:122
17164992422,2cyclictest0-21swapper/221:49:522
17164992418,5cyclictest749-21snmpd20:14:482
17164992416,7cyclictest749-21snmpd23:39:332
17164992416,7cyclictest749-21snmpd00:29:442
1716499241,22cyclictest0-21swapper/220:39:152
17159992422,2cyclictest0-21swapper/121:51:251
17159992422,2cyclictest0-21swapper/121:06:481
17159992420,3cyclictest0-21swapper/123:16:521
17159992417,6cyclictest0-21swapper/100:23:081
1715999240,23cyclictest0-21swapper/121:03:091
17164992321,2cyclictest0-21swapper/222:44:402
17164992318,4cyclictest749-21snmpd20:58:242
17164992317,5cyclictest749-21snmpd21:08:282
17164992316,6cyclictest749-21snmpd23:29:352
17164992315,7cyclictest749-21snmpd21:04:542
17164992315,7cyclictest749-21snmpd20:21:212
17164992314,8cyclictest749-21snmpd00:18:332
1716499231,21cyclictest0-21swapper/220:52:122
17159992321,2cyclictest0-21swapper/122:48:021
1715999231,20cyclictest0-21swapper/120:02:321
1715999230,22cyclictest0-21swapper/100:09:451
1716499221,2cyclictest13234-21hddtemp_smartct00:20:152
1716499221,20cyclictest0-21swapper/220:17:302
1716499221,13cyclictest0-21swapper/223:15:102
1716499220,21cyclictest0-21swapper/221:59:382
1716499220,21cyclictest0-21swapper/221:53:552
1716499220,21cyclictest0-21swapper/219:41:352
1716499220,21cyclictest0-21swapper/200:38:322
17159992218,3cyclictest0-21swapper/123:33:281
1715999221,20cyclictest0-21swapper/122:15:161
1715999220,3cyclictest0-21swapper/119:58:421
1715999220,21cyclictest0-21swapper/123:55:231
1715999220,21cyclictest0-21swapper/123:52:151
1715999220,21cyclictest0-21swapper/123:48:151
1715999220,21cyclictest0-21swapper/123:42:051
1715999220,21cyclictest0-21swapper/123:36:591
1715999220,21cyclictest0-21swapper/122:37:131
1715999220,21cyclictest0-21swapper/122:20:041
1715999220,21cyclictest0-21swapper/122:11:011
1715999220,21cyclictest0-21swapper/122:05:321
1715999220,21cyclictest0-21swapper/121:42:051
1715999220,21cyclictest0-21swapper/121:17:001
1715999220,21cyclictest0-21swapper/120:56:481
1715999220,21cyclictest0-21swapper/120:43:061
1715999220,21cyclictest0-21swapper/120:34:181
1715999220,21cyclictest0-21swapper/120:29:211
1715999220,21cyclictest0-21swapper/120:11:271
1715999220,21cyclictest0-21swapper/119:38:321
1715999220,21cyclictest0-21swapper/119:16:051
1715599220,21cyclictest0-21swapper/022:40:380
1715599220,21cyclictest0-21swapper/022:34:290
1715599220,21cyclictest0-21swapper/019:21:010
91372210,0sleep00-21swapper/019:55:180
242312210,0sleep30-21swapper/323:30:183
17164992117,3cyclictest0-21swapper/222:45:142
17164992117,2cyclictest7613-21perl20:25:152
17164992115,5cyclictest749-21snmpd19:12:172
17164992114,6cyclictest749-21snmpd22:11:462
17164992114,6cyclictest749-21snmpd19:23:232
17164992113,7cyclictest749-21snmpd22:31:042
17164992113,2cyclictest0-21swapper/223:10:442
1716499210,20cyclictest0-21swapper/223:56:022
1716499210,20cyclictest0-21swapper/222:36:552
1716499210,20cyclictest0-21swapper/220:45:192
1716499210,20cyclictest0-21swapper/219:36:282
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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