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2026-05-20 - 11:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Wed May 20, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16694213068,6sleep10-21swapper/119:05:441
16933212765,8sleep30-21swapper/319:08:513
170142122112,7sleep20-21swapper/219:09:542
16730211596,7sleep00-21swapper/019:06:120
14382670,2sleep340-21ksoftirqd/320:20:153
253402640,1sleep225345-21mailstats19:40:212
241502620,1sleep10-21swapper/121:35:181
260232600,0sleep10-21swapper/120:10:201
155932590,0sleep10-21swapper/121:30:131
177522550,0sleep00-21swapper/022:55:190
131142550,0sleep30-21swapper/319:30:173
190112540,1sleep119017-21kthreadcore19:10:211
44832530,0sleep20-21swapper/223:40:222
1720099270,26cyclictest0-21swapper/221:07:192
1720099260,25cyclictest0-21swapper/222:10:372
1720099260,25cyclictest0-21swapper/220:05:342
17200992523,2cyclictest0-21swapper/220:29:552
17200992523,2cyclictest0-21swapper/200:14:472
1719099250,24cyclictest0-21swapper/000:20:200
1720099240,22cyclictest0-21swapper/220:40:112
17195992422,2cyclictest0-21swapper/120:43:281
17195992421,3cyclictest0-21swapper/121:57:131
1719099249,13cyclictest0-21swapper/021:50:260
17200992321,2cyclictest0-21swapper/221:54:552
1720099231,21cyclictest0-21swapper/200:26:112
1720099230,22cyclictest0-21swapper/223:55:232
17195992321,2cyclictest0-21swapper/123:33:141
17195992321,2cyclictest0-21swapper/119:53:401
17195992321,2cyclictest0-21swapper/100:08:181
17195992320,3cyclictest0-21swapper/122:03:581
17195992319,3cyclictest0-21swapper/119:59:011
1720099225,15cyclictest0-21swapper/223:18:052
17200992220,2cyclictest0-21swapper/221:11:492
17200992218,3cyclictest0-21swapper/222:56:402
1720099220,21cyclictest0-21swapper/223:52:422
1720099220,21cyclictest0-21swapper/222:49:322
1720099220,21cyclictest0-21swapper/220:38:222
1720099220,21cyclictest0-21swapper/219:27:342
1720099220,21cyclictest0-21swapper/200:31:482
1720099220,21cyclictest0-21swapper/200:02:562
17195992220,2cyclictest0-21swapper/123:44:591
17195992220,2cyclictest0-21swapper/121:08:581
17195992220,2cyclictest0-21swapper/120:16:011
17195992220,2cyclictest0-21swapper/119:32:161
17195992219,3cyclictest0-21swapper/100:04:271
17195992218,3cyclictest0-21swapper/121:45:371
17195992218,3cyclictest0-21swapper/121:44:431
1719599220,3cyclictest0-21swapper/122:15:101
1719599220,3cyclictest0-21swapper/119:25:371
1719599220,2cyclictest23057-21if_enp1s019:15:001
1719599220,21cyclictest0-21swapper/123:47:561
1719599220,21cyclictest0-21swapper/123:15:531
1719599220,21cyclictest0-21swapper/122:47:441
1719599220,21cyclictest0-21swapper/122:25:491
1719599220,21cyclictest0-21swapper/122:11:221
1719599220,21cyclictest0-21swapper/122:05:111
1719599220,21cyclictest0-21swapper/121:29:521
1719599220,21cyclictest0-21swapper/121:24:581
1719599220,21cyclictest0-21swapper/121:19:401
1719599220,21cyclictest0-21swapper/121:19:401
1719599220,21cyclictest0-21swapper/120:35:181
1719599220,21cyclictest0-21swapper/119:48:331
1719599220,21cyclictest0-21swapper/119:39:011
1719599220,21cyclictest0-21swapper/100:13:501
1719099220,21cyclictest0-21swapper/023:16:440
92402210,0sleep30-21swapper/323:20:013
17200992118,2cyclictest749-21snmpd23:13:532
17200992118,2cyclictest749-21snmpd21:42:172
17200992117,3cyclictest0-21swapper/223:45:232
17200992116,4cyclictest0-21swapper/222:40:152
1720099210,20cyclictest0-21swapper/222:30:522
1720099210,20cyclictest0-21swapper/222:21:532
1720099210,20cyclictest0-21swapper/219:56:342
1720099210,20cyclictest0-21swapper/219:34:462
1720099210,20cyclictest0-21swapper/219:18:472
1720099210,20cyclictest0-21swapper/219:11:422
1720099210,20cyclictest0-21swapper/200:07:572
17195992119,2cyclictest0-21swapper/123:25:031
17195992118,3cyclictest0-21swapper/123:57:501
17195992118,3cyclictest0-21swapper/119:40:371
17195992118,3cyclictest0-21swapper/100:20:051
1719599210,21cyclictest0-21swapper/120:00:511
1719599210,20cyclictest0-21swapper/123:51:331
1719599210,20cyclictest0-21swapper/123:36:151
1719599210,20cyclictest0-21swapper/123:13:511
1719599210,20cyclictest0-21swapper/123:08:171
1719599210,20cyclictest0-21swapper/123:02:051
1719599210,20cyclictest0-21swapper/122:55:551
1719599210,20cyclictest0-21swapper/122:53:431
1719599210,20cyclictest0-21swapper/122:30:201
1719599210,20cyclictest0-21swapper/121:53:551
1719599210,20cyclictest0-21swapper/121:14:071
1719599210,20cyclictest0-21swapper/120:51:281
1719599210,20cyclictest0-21swapper/120:20:251
1719599210,20cyclictest0-21swapper/120:08:311
1719599210,20cyclictest0-21swapper/119:21:461
1719599210,20cyclictest0-21swapper/100:39:451
1719599210,20cyclictest0-21swapper/100:39:441
1719599210,20cyclictest0-21swapper/100:30:331
1719599210,20cyclictest0-21swapper/100:15:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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