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2026-01-15 - 06:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Thu Jan 15, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4811211760,54sleep00-21swapper/019:06:580
4930210873,31sleep20-21swapper/219:08:332
4881210495,6sleep30-21swapper/319:07:543
4137210492,7sleep10-21swapper/119:05:231
106952650,0sleep310700-21cpuspeed_turbos20:10:123
279062630,0sleep30-21swapper/321:20:203
243492630,0sleep20-21swapper/222:15:222
181572600,0sleep30-21swapper/321:10:233
235842590,0sleep00-21swapper/020:20:180
225002590,0sleep00-21swapper/023:40:170
225002590,0sleep00-21swapper/023:40:170
96682580,2sleep120-21rcuc/123:00:171
219932570,0sleep30-21swapper/320:20:133
191662560,1sleep319167-21xargs21:40:223
212132550,0sleep30-21swapper/323:10:173
173432540,0sleep00-21swapper/020:15:170
173432540,0sleep00-21swapper/020:15:170
116712530,0sleep00-21swapper/021:05:190
522599320,30cyclictest0-21swapper/221:10:102
522199300,29cyclictest0-21swapper/100:20:111
522199280,27cyclictest0-21swapper/120:52:461
522199280,27cyclictest0-21swapper/120:42:521
522199280,27cyclictest0-21swapper/120:39:521
522199280,27cyclictest0-21swapper/119:20:361
522599270,26cyclictest8-21rcu_preempt22:43:592
522599270,26cyclictest0-21swapper/219:34:212
5221992717,3cyclictest0-21swapper/121:46:521
522199270,26cyclictest0-21swapper/123:16:381
522199270,26cyclictest0-21swapper/122:55:431
522199270,26cyclictest0-21swapper/121:50:541
522199270,26cyclictest0-21swapper/121:42:541
522199270,26cyclictest0-21swapper/121:25:031
522199270,26cyclictest0-21swapper/121:21:341
522199270,26cyclictest0-21swapper/100:39:511
522199270,26cyclictest0-21swapper/100:28:011
522599260,25cyclictest0-21swapper/220:41:522
522199260,25cyclictest0-21swapper/123:30:441
522199260,25cyclictest0-21swapper/122:21:131
522199260,25cyclictest0-21swapper/121:39:061
522199260,25cyclictest0-21swapper/119:15:451
522199260,25cyclictest0-21swapper/100:07:261
5225992521,3cyclictest0-21swapper/223:25:352
5225992511,13cyclictest0-21swapper/221:15:192
522599250,20cyclictest0-21swapper/219:28:592
5221992522,2cyclictest0-21swapper/121:58:101
5221992421,2cyclictest0-21swapper/123:06:281
5225992321,2cyclictest0-21swapper/219:14:502
5225992319,3cyclictest0-21swapper/200:17:562
5221992319,3cyclictest0-21swapper/123:36:551
522199230,22cyclictest0-21swapper/123:48:591
522199230,22cyclictest0-21swapper/122:14:561
5219992315,8cyclictest0-21swapper/023:09:440
5225992220,2cyclictest0-21swapper/221:41:442
5225992219,3cyclictest0-21swapper/200:37:512
522599221,3cyclictest0-21swapper/219:54:452
522599220,21cyclictest0-21swapper/221:48:192
522599220,16cyclictest0-21swapper/223:40:142
522599220,16cyclictest0-21swapper/223:40:142
5221992219,3cyclictest0-21swapper/121:34:521
5221992218,3cyclictest0-21swapper/100:12:131
522199220,3cyclictest0-21swapper/122:29:201
522199220,21cyclictest0-21swapper/119:56:391
522199220,21cyclictest0-21swapper/119:37:551
93792210,1sleep39384-21unixbench_singl22:00:253
522599217,9cyclictest0-21swapper/223:10:222
522599212,18cyclictest0-21swapper/222:58:482
5225992118,2cyclictest0-21swapper/221:59:312
5225992118,2cyclictest0-21swapper/220:56:222
5225992117,3cyclictest0-21swapper/223:34:472
522599210,2cyclictest0-21swapper/200:32:062
522599210,21cyclictest0-21swapper/222:10:282
522599210,20cyclictest0-21swapper/223:49:312
522599210,20cyclictest0-21swapper/220:29:122
522599210,20cyclictest0-21swapper/219:57:452
522599210,20cyclictest0-21swapper/200:05:472
522199215,14cyclictest0-21swapper/120:10:201
5221992118,3cyclictest0-21swapper/121:17:521
522199210,21cyclictest0-21swapper/121:03:101
522199210,20cyclictest0-21swapper/123:42:321
522199210,20cyclictest0-21swapper/123:42:321
522199210,20cyclictest0-21swapper/123:11:261
522199210,20cyclictest0-21swapper/122:46:431
522199210,20cyclictest0-21swapper/122:36:131
522199210,20cyclictest0-21swapper/122:06:281
522199210,20cyclictest0-21swapper/120:46:281
522199210,20cyclictest0-21swapper/120:28:511
522199210,20cyclictest0-21swapper/120:22:091
522199210,20cyclictest0-21swapper/120:00:241
522199210,20cyclictest0-21swapper/119:44:421
522199210,20cyclictest0-21swapper/100:31:361
5219992118,2cyclictest5079-21cron00:24:590
5219992117,2cyclictest750-21snmpd19:25:420
5225992018,1cyclictest750-21snmpd23:37:382
5225992018,1cyclictest750-21snmpd22:28:072
5225992018,1cyclictest750-21snmpd19:44:152
5225992018,1cyclictest750-21snmpd00:21:142
5225992017,3cyclictest0-21swapper/220:02:242
5225992016,3cyclictest0-21swapper/200:28:342
522599201,13cyclictest0-21swapper/222:48:292
522599200,2cyclictest0-21swapper/219:21:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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