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2025-06-16 - 20:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Mon Jun 16, 2025 12:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27171214996,7sleep30-21swapper/307:07:463
272852111102,6sleep00-21swapper/007:09:150
271372110101,6sleep10-21swapper/107:07:191
27066210898,7sleep20-21swapper/207:06:242
216652660,0sleep10-21swapper/111:00:211
81672650,0sleep20-21swapper/212:15:252
157692650,6sleep22751999cyclictest11:32:552
327452630,2sleep3391ktimersoftd/311:40:263
276672630,1sleep010-21rcuc/010:10:210
169112630,1sleep116914-21kthreadcore08:45:241
115922600,0sleep30-21swapper/310:55:183
76132590,1sleep00-21swapper/010:51:030
197752580,1sleep30-21swapper/310:40:203
288592570,0sleep10-21swapper/109:35:211
35612550,0sleep00-21swapper/007:40:190
232892550,0sleep10-21swapper/111:51:401
141702540,0sleep10-21swapper/109:29:481
141702540,0sleep10-21swapper/109:29:481
74262530,0sleep30-21swapper/311:29:323
158802530,0sleep20-21swapper/209:45:412
2751999281,26cyclictest0-21swapper/209:51:232
27519992714,7cyclictest10272-21snmpd09:31:242
2751999270,26cyclictest0-21swapper/210:56:132
2751999270,26cyclictest0-21swapper/209:15:322
27515992723,3cyclictest0-21swapper/109:19:591
2751599270,26cyclictest0-21swapper/112:18:381
2751599270,26cyclictest0-21swapper/111:45:021
2751599270,26cyclictest0-21swapper/111:37:021
2751599270,26cyclictest0-21swapper/111:33:321
2751599270,26cyclictest0-21swapper/111:07:531
2751599270,26cyclictest0-21swapper/107:56:491
2751599270,26cyclictest0-21swapper/107:24:291
2751999260,25cyclictest0-21swapper/209:06:052
2751599265,20cyclictest0-21swapper/111:40:301
2751599260,25cyclictest0-21swapper/111:20:021
2751599260,25cyclictest0-21swapper/107:37:371
2751599260,25cyclictest0-21swapper/107:28:521
2751599260,25cyclictest0-21swapper/107:11:201
107802260,21sleep10-21swapper/109:10:161
2751999250,24cyclictest0-21swapper/212:34:532
2751999250,24cyclictest0-21swapper/207:13:502
27515992523,2cyclictest0-21swapper/110:53:241
2751599250,24cyclictest0-21swapper/112:38:091
2751599250,24cyclictest0-21swapper/110:10:091
2751599250,24cyclictest0-21swapper/109:20:361
2751099250,24cyclictest0-21swapper/008:18:090
2751999241,4cyclictest0-21swapper/211:00:342
2751999241,22cyclictest0-21swapper/212:11:142
2751999240,22cyclictest0-21swapper/210:12:172
2751599240,23cyclictest0-21swapper/110:23:561
2751599240,23cyclictest0-21swapper/110:09:141
2751599240,17cyclictest0-21swapper/112:11:571
2751099247,16cyclictest0-21swapper/009:24:300
27510992416,7cyclictest0-21swapper/011:52:530
2751099240,23cyclictest0-21swapper/011:35:180
2751099240,23cyclictest0-21swapper/011:30:260
2751099240,18cyclictest0-21swapper/011:19:150
2751099240,18cyclictest0-21swapper/010:34:270
889422319,3sleep30-21swapper/307:17:153
27519992320,3cyclictest0-21swapper/209:42:202
2751999231,21cyclictest0-21swapper/209:36:572
2751999230,22cyclictest0-21swapper/211:58:542
2751999230,22cyclictest0-21swapper/211:07:142
2751999230,22cyclictest0-21swapper/210:40:272
2751999230,22cyclictest0-21swapper/210:15:482
2751999230,22cyclictest0-21swapper/209:11:182
2751999230,17cyclictest0-21swapper/211:26:552
27515992316,7cyclictest0-21swapper/109:41:561
2751599230,22cyclictest0-21swapper/112:33:201
2751599230,22cyclictest0-21swapper/112:27:381
2751599230,22cyclictest0-21swapper/110:55:421
2751599230,22cyclictest0-21swapper/110:48:131
2751599230,22cyclictest0-21swapper/109:55:561
2751599230,22cyclictest0-21swapper/109:08:021
2751599230,17cyclictest0-21swapper/110:16:181
2751599230,17cyclictest0-21swapper/109:49:261
27510992316,7cyclictest0-21swapper/012:13:180
27510992316,7cyclictest0-21swapper/011:59:320
27510992314,8cyclictest0-21swapper/011:27:320
2751099231,21cyclictest0-21swapper/009:46:230
2751099230,22cyclictest0-21swapper/012:37:480
2751099230,22cyclictest0-21swapper/012:15:330
2751099230,22cyclictest0-21swapper/011:03:580
2751099230,22cyclictest0-21swapper/010:48:430
2751099230,22cyclictest0-21swapper/009:53:250
2751099230,22cyclictest0-21swapper/009:26:280
2751099230,22cyclictest0-21swapper/009:26:270
2512622318,3sleep30-21swapper/308:54:483
2751999222,19cyclictest0-21swapper/211:16:362
2751999221,3cyclictest0-21swapper/208:44:492
2751999221,20cyclictest0-21swapper/210:26:442
2751999221,20cyclictest0-21swapper/209:01:542
2751999221,20cyclictest0-21swapper/208:38:502
2751999221,19cyclictest604-21systemctl11:40:272
2751999220,21cyclictest0-21swapper/212:05:302
2751999220,21cyclictest0-21swapper/211:50:062
2751999220,21cyclictest0-21swapper/211:46:422
2751999220,21cyclictest0-21swapper/211:10:442
2751999220,21cyclictest0-21swapper/210:39:462
2751999220,21cyclictest0-21swapper/208:09:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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