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2026-05-12 - 21:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Tue May 12, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
523215293,6sleep20-21swapper/207:09:242
32728212866,8sleep30-21swapper/307:06:043
522212765,7sleep10-21swapper/107:09:231
506210898,7sleep00-21swapper/007:09:100
313332660,0sleep30-21swapper/309:25:233
111652650,5sleep077099cyclictest09:10:200
200012590,0sleep10-21swapper/112:10:171
147492580,1sleep010-21rcuc/012:05:200
41742570,1sleep14177-21kthreadcore10:30:171
20182570,0sleep00-21swapper/011:25:190
200272530,0sleep020032-21kthreadcore10:15:180
77599280,27cyclictest0-21swapper/111:46:241
77599280,27cyclictest0-21swapper/111:11:341
77599280,27cyclictest0-21swapper/109:52:411
77599280,27cyclictest0-21swapper/109:06:581
77999270,26cyclictest0-21swapper/210:02:342
77999270,26cyclictest0-21swapper/207:58:452
775992723,3cyclictest0-21swapper/107:55:311
77599270,26cyclictest0-21swapper/112:15:151
77599270,26cyclictest0-21swapper/111:59:451
77599270,26cyclictest0-21swapper/111:42:481
77599270,26cyclictest0-21swapper/111:35:441
77599270,26cyclictest0-21swapper/111:23:061
77599270,26cyclictest0-21swapper/109:17:281
77599270,26cyclictest0-21swapper/107:52:271
77599270,26cyclictest0-21swapper/107:49:271
779992618,7cyclictest0-21swapper/209:19:202
779992618,7cyclictest0-21swapper/207:40:152
77999260,25cyclictest0-21swapper/208:24:512
775992623,3cyclictest0-21swapper/111:30:331
775992623,2cyclictest0-21swapper/107:19:391
77599260,25cyclictest0-21swapper/112:08:321
77599260,25cyclictest0-21swapper/108:34:011
77599260,25cyclictest0-21swapper/107:14:571
779992518,7cyclictest0-21swapper/209:22:552
77999250,25cyclictest0-21swapper/212:18:572
77999250,24cyclictest8-21rcu_preempt09:05:342
77999250,24cyclictest0-21swapper/208:49:552
775992522,3cyclictest0-21swapper/110:05:081
775992522,3cyclictest0-21swapper/107:44:121
77599250,24cyclictest0-21swapper/109:45:461
77999241,22cyclictest0-21swapper/210:07:202
77999240,23cyclictest0-21swapper/212:33:182
775992422,2cyclictest0-21swapper/112:27:241
775992422,2cyclictest0-21swapper/111:04:491
775992422,2cyclictest0-21swapper/110:29:231
775992422,2cyclictest0-21swapper/110:16:471
775992422,2cyclictest0-21swapper/109:12:321
775992422,2cyclictest0-21swapper/108:55:041
775992422,2cyclictest0-21swapper/108:28:431
775992422,2cyclictest0-21swapper/107:39:061
775992418,6cyclictest0-21swapper/112:31:351
77999231,21cyclictest0-21swapper/212:29:362
77999230,23cyclictest0-21swapper/209:51:022
77999230,22cyclictest0-21swapper/212:36:242
775992321,2cyclictest0-21swapper/111:17:271
775992321,2cyclictest0-21swapper/110:47:461
775992321,2cyclictest0-21swapper/110:40:201
775992321,2cyclictest0-21swapper/110:14:051
775992321,2cyclictest0-21swapper/110:14:041
775992321,2cyclictest0-21swapper/109:56:131
775992321,2cyclictest0-21swapper/109:30:401
775992321,2cyclictest0-21swapper/108:53:521
779992220,2cyclictest0-21swapper/207:17:032
779992216,5cyclictest0-21swapper/211:02:402
779992216,1cyclictest5123-21/usr/sbin/munin09:35:222
779992215,7cyclictest0-21swapper/211:12:452
77999221,3cyclictest0-21swapper/211:29:292
77999221,20cyclictest0-21swapper/208:18:332
77999220,21cyclictest0-21swapper/209:02:052
77999220,21cyclictest0-21swapper/208:32:582
77999220,21cyclictest0-21swapper/208:11:372
775992220,2cyclictest0-21swapper/112:38:121
775992220,2cyclictest0-21swapper/112:21:031
775992220,2cyclictest0-21swapper/111:50:291
775992219,3cyclictest0-21swapper/109:28:051
77599220,3cyclictest0-21swapper/111:07:201
77599220,21cyclictest0-21swapper/111:25:051
77599220,21cyclictest0-21swapper/108:49:141
77599220,21cyclictest0-21swapper/108:15:571
77599220,21cyclictest0-21swapper/108:08:001
77599220,21cyclictest0-21swapper/108:01:271
770992219,2cyclictest749-21snmpd07:17:510
77099220,21cyclictest0-21swapper/011:14:200
77999217,13cyclictest0-21swapper/210:33:372
779992119,2cyclictest0-21swapper/210:26:352
779992119,1cyclictest749-21snmpd09:31:252
779992119,1cyclictest749-21snmpd08:08:392
779992118,3cyclictest0-21swapper/208:35:082
779992118,2cyclictest749-21snmpd09:55:442
779992117,3cyclictest0-21swapper/212:01:542
779992117,3cyclictest0-21swapper/210:40:322
77999211,19cyclictest0-21swapper/211:58:092
77999210,3cyclictest0-21swapper/211:24:332
77999210,2cyclictest0-21swapper/207:29:272
77999210,20cyclictest0-21swapper/212:11:422
77999210,20cyclictest0-21swapper/211:49:572
77999210,20cyclictest0-21swapper/211:39:302
77999210,20cyclictest0-21swapper/211:07:412
77999210,20cyclictest0-21swapper/210:46:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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