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2025-12-06 - 01:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Fri Dec 05, 2025 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18164212258,7sleep10-21swapper/107:05:511
18103212162,7sleep20-21swapper/207:05:042
184632110101,6sleep00-21swapper/007:09:430
18394210795,7sleep30-21swapper/307:08:503
1205121030,0sleep00-21swapper/011:40:170
144502700,0sleep30-21swapper/312:30:203
17482690,0sleep30-21swapper/312:25:193
95202680,0sleep10-21swapper/110:30:221
148332590,0sleep10-21swapper/107:55:171
42112580,0sleep00-21swapper/012:25:210
272022580,0sleep00-21swapper/011:30:480
108252570,0sleep20-21swapper/209:40:192
233332560,0sleep340-21ksoftirqd/310:37:133
315502550,0sleep231556-21kthreadcore07:25:182
151812530,0sleep30-21swapper/312:00:113
123872400,0sleep012388-21grep09:25:190
1865499300,14cyclictest0-21swapper/111:36:391
1865799291,27cyclictest0-21swapper/208:52:062
1865499290,27cyclictest0-21swapper/112:30:121
1865499290,27cyclictest0-21swapper/110:16:021
1865799280,27cyclictest0-21swapper/210:22:322
1865499280,3cyclictest0-21swapper/108:16:081
1865499280,27cyclictest0-21swapper/108:53:181
118332280,0sleep20-21swapper/209:59:062
1865799270,26cyclictest0-21swapper/211:39:172
1865799270,26cyclictest0-21swapper/211:00:262
1865799270,26cyclictest0-21swapper/209:46:552
1865799270,26cyclictest0-21swapper/208:34:212
1865499270,26cyclictest0-21swapper/110:52:101
1865499270,26cyclictest0-21swapper/109:57:491
1865499270,26cyclictest0-21swapper/108:22:281
1865499270,26cyclictest0-21swapper/108:00:261
1865499270,26cyclictest0-21swapper/107:50:521
1865499270,16cyclictest0-21swapper/111:22:501
18647992723,3cyclictest0-21swapper/012:19:120
1716122718,3sleep30-21swapper/308:05:493
18657992622,3cyclictest0-21swapper/208:03:472
1865799261,1cyclictest0-21swapper/211:25:232
1865799260,25cyclictest0-21swapper/211:13:072
1865799260,25cyclictest0-21swapper/207:30:062
1865499264,21cyclictest0-21swapper/110:42:481
1865499263,14cyclictest0-21swapper/111:55:111
1865499260,25cyclictest0-21swapper/110:37:111
1865499260,25cyclictest0-21swapper/108:10:591
1865499260,23cyclictest0-21swapper/112:25:101
1865499260,20cyclictest0-21swapper/109:14:141
1865499260,13cyclictest0-21swapper/112:39:501
1865499260,13cyclictest0-21swapper/109:39:541
1864799260,24cyclictest279422chrt11:49:240
18657992521,3cyclictest0-21swapper/209:16:512
1865799250,24cyclictest0-21swapper/212:26:332
1865799250,24cyclictest0-21swapper/211:19:502
1865799250,19cyclictest16048-21ssh11:09:132
1865499253,18cyclictest0-21swapper/109:41:031
1865499253,15cyclictest0-21swapper/111:32:481
18654992517,6cyclictest19797-21grep09:45:191
1865499251,13cyclictest31218-21sensors_temp09:50:211
1865499251,10cyclictest0-21swapper/108:25:141
1865499250,24cyclictest0-21swapper/109:33:471
1865499250,24cyclictest0-21swapper/109:33:461
1865499250,20cyclictest0-21swapper/112:09:111
1865499250,19cyclictest0-21swapper/107:43:181
1865499243,8cyclictest0-21swapper/109:24:361
18654992422,2cyclictest0-21swapper/109:27:421
18654992416,7cyclictest0-21swapper/110:47:321
1865499241,22cyclictest0-21swapper/107:18:261
1865499240,23cyclictest0-21swapper/110:06:221
1865499240,23cyclictest0-21swapper/109:18:311
1865499240,23cyclictest0-21swapper/108:45:041
1865499240,21cyclictest0-21swapper/110:01:011
1865499240,20cyclictest0-21swapper/111:14:001
1865499240,19cyclictest0-21swapper/111:25:251
1865499240,17cyclictest0-21swapper/110:22:501
1864799240,23cyclictest0-21swapper/011:52:030
1865799232,20cyclictest0-21swapper/211:50:522
1865799231,20cyclictest24832-21perl12:05:172
1865799230,22cyclictest0-21swapper/210:42:142
1865499231,21cyclictest0-21swapper/110:28:191
1865499231,21cyclictest0-21swapper/108:07:181
1865499231,16cyclictest0-21swapper/111:06:311
1865499230,22cyclictest0-21swapper/112:20:561
1865499230,22cyclictest0-21swapper/112:16:591
1865499230,22cyclictest0-21swapper/112:04:391
1865499230,22cyclictest0-21swapper/110:55:021
1865499230,22cyclictest0-21swapper/108:32:251
1865499230,20cyclictest0-21swapper/112:14:481
1865499230,19cyclictest0-21swapper/111:40:101
1865499230,17cyclictest0-21swapper/111:15:551
1865499230,16cyclictest0-21swapper/111:04:451
1864799230,22cyclictest0-21swapper/012:38:540
1864799230,22cyclictest0-21swapper/011:00:360
1864799230,22cyclictest0-21swapper/010:45:590
1864799230,22cyclictest0-21swapper/009:52:190
1864799230,22cyclictest0-21swapper/009:34:170
1864799230,22cyclictest0-21swapper/009:34:170
3161622218,3sleep30-21swapper/308:39:063
1865799222,19cyclictest0-21swapper/212:22:432
1865799222,19cyclictest0-21swapper/210:38:322
1865799222,15cyclictest0-21swapper/210:10:282
18657992215,6cyclictest0-21swapper/210:17:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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