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2026-03-04 - 01:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Tue Mar 03, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
321812125116,6sleep20-21swapper/207:09:582
2259621130,5sleep03235299cyclictest08:25:130
32042211198,7sleep00-21swapper/007:08:120
318832110101,6sleep10-21swapper/107:06:091
31885210999,7sleep30-21swapper/307:06:113
168652730,0sleep10-21swapper/110:40:171
133512650,0sleep20-21swapper/208:15:162
65312610,0sleep10-21swapper/110:30:211
305602600,0sleep3391ktimersoftd/311:20:203
288882580,1sleep10-21swapper/109:55:201
3235999281,26cyclictest0-21swapper/211:30:552
3235999280,26cyclictest31868-21/usr/sbin/munin08:05:182
3235799280,27cyclictest0-21swapper/111:43:201
3235799280,27cyclictest0-21swapper/110:10:191
3235999270,26cyclictest0-21swapper/208:22:452
3235799270,26cyclictest0-21swapper/112:39:571
3235799270,26cyclictest0-21swapper/112:31:381
3235799270,26cyclictest0-21swapper/112:01:171
3235799270,26cyclictest0-21swapper/108:45:481
3235799270,26cyclictest0-21swapper/108:27:061
3235799270,26cyclictest0-21swapper/107:55:301
3235999260,25cyclictest0-21swapper/209:29:552
3235799260,25cyclictest0-21swapper/107:23:091
3235799260,25cyclictest0-21swapper/107:17:031
3235799260,25cyclictest0-21swapper/107:13:391
32359992522,2cyclictest0-21swapper/211:10:072
3235999250,24cyclictest0-21swapper/207:26:242
32357992521,3cyclictest0-21swapper/112:29:031
3235799250,24cyclictest0-21swapper/112:06:121
3235799250,24cyclictest0-21swapper/108:30:121
3235799250,24cyclictest0-21swapper/108:21:181
32359992422,2cyclictest0-21swapper/212:13:022
32359992422,2cyclictest0-21swapper/209:46:462
3235999240,23cyclictest0-21swapper/211:29:532
32352992421,2cyclictest0-21swapper/010:00:150
3235299240,1cyclictest0-21swapper/011:05:000
79382230,1sleep30-21swapper/307:15:103
32359992320,3cyclictest0-21swapper/211:47:282
3235999231,3cyclictest0-21swapper/210:36:132
3235999230,22cyclictest0-21swapper/208:10:152
32357992321,2cyclictest0-21swapper/109:43:071
32357992320,3cyclictest0-21swapper/110:48:021
32357992320,2cyclictest0-21swapper/111:54:591
3235799231,3cyclictest0-21swapper/110:16:071
3235799231,21cyclictest0-21swapper/108:59:361
3235799231,21cyclictest0-21swapper/107:50:061
3235799230,22cyclictest0-21swapper/109:34:521
3235799230,22cyclictest0-21swapper/108:15:571
32352992321,1cyclictest0-21swapper/010:25:190
32359992219,2cyclictest749-21snmpd11:44:292
32359992218,3cyclictest0-21swapper/210:23:262
32359992218,3cyclictest0-21swapper/209:02:302
32359992215,7cyclictest0-21swapper/212:25:422
3235999220,21cyclictest0-21swapper/210:10:252
3235999220,21cyclictest0-21swapper/209:33:072
3235799228,13cyclictest0-21swapper/110:05:161
32357992220,1cyclictest5326-21irqcore09:35:161
32357992218,3cyclictest0-21swapper/111:55:371
32357992218,3cyclictest0-21swapper/108:40:211
32357992218,3cyclictest0-21swapper/108:06:391
32357992217,4cyclictest0-21swapper/110:26:011
32357992215,7cyclictest0-21swapper/111:14:261
3235799221,3cyclictest0-21swapper/111:21:281
3235799221,20cyclictest0-21swapper/110:56:441
3235799221,20cyclictest0-21swapper/110:20:521
3235799221,20cyclictest0-21swapper/107:25:361
3235799220,3cyclictest0-21swapper/110:52:191
3235799220,3cyclictest0-21swapper/109:12:181
3235799220,3cyclictest0-21swapper/107:42:421
3235799220,21cyclictest0-21swapper/112:19:031
3235799220,21cyclictest0-21swapper/112:19:021
3235799220,21cyclictest0-21swapper/111:36:381
3235799220,21cyclictest0-21swapper/111:07:581
3235799220,21cyclictest0-21swapper/111:01:221
3235799220,21cyclictest0-21swapper/109:20:251
3235799220,21cyclictest0-21swapper/109:07:151
3235799220,20cyclictest10129-21seq11:34:341
3235999212,18cyclictest0-21swapper/209:35:462
32359992119,1cyclictest8-21rcu_preempt09:14:092
32359992118,2cyclictest0-21swapper/212:08:032
32359992118,2cyclictest0-21swapper/208:47:512
32359992118,2cyclictest0-21swapper/207:32:272
32359992117,3cyclictest0-21swapper/209:52:342
32359992117,3cyclictest0-21swapper/208:02:092
3235999210,20cyclictest0-21swapper/210:30:252
3235999210,20cyclictest0-21swapper/210:04:312
3235999210,20cyclictest0-21swapper/208:27:362
3235999210,20cyclictest0-21swapper/207:24:232
3235799216,14cyclictest0-21swapper/112:10:161
32357992117,3cyclictest0-21swapper/111:26:591
32357992117,3cyclictest0-21swapper/109:53:441
32357992117,3cyclictest0-21swapper/109:17:521
32357992117,3cyclictest0-21swapper/107:45:361
3235799210,3cyclictest0-21swapper/109:25:561
3235799210,20cyclictest0-21swapper/110:38:431
3235799210,20cyclictest0-21swapper/110:01:371
3235799210,20cyclictest0-21swapper/109:49:431
3235799210,20cyclictest0-21swapper/108:51:121
3235799210,20cyclictest0-21swapper/108:51:121
3235799210,20cyclictest0-21swapper/108:38:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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