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2026-01-18 - 11:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Sun Jan 18, 2026 00:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31985211355,6sleep10-21swapper/119:05:321
26959210696,7sleep00-21swapper/019:05:100
32142210596,6sleep20-21swapper/219:07:342
26957210493,8sleep30-21swapper/319:05:103
256472910,1sleep325651-21kthreadcore00:20:183
89522630,0sleep1211ktimersoftd/122:35:141
157782620,0sleep30-21swapper/319:50:153
30802600,1sleep00-21swapper/021:22:030
55732580,1sleep30-21swapper/323:56:483
18062570,0sleep331380-21kworker/3:121:21:023
253292560,0sleep30-21swapper/319:30:123
19752550,1sleep01982-21kthreadcore20:05:170
204822390,0sleep30-21swapper/322:25:193
3250099290,28cyclictest0-21swapper/200:39:282
3250099270,26cyclictest0-21swapper/221:20:422
3250099270,26cyclictest0-21swapper/221:01:422
3250099270,26cyclictest0-21swapper/220:26:212
3249099270,26cyclictest0-21swapper/022:53:170
3249099270,26cyclictest0-21swapper/020:30:160
3250099260,25cyclictest0-21swapper/223:23:412
3249099260,25cyclictest0-21swapper/021:16:210
32500992523,1cyclictest0-21swapper/221:10:152
3250099251,18cyclictest10631-21python322:20:222
3250099250,24cyclictest0-21swapper/223:51:192
3250099250,24cyclictest0-21swapper/219:37:452
3250099250,23cyclictest0-21swapper/221:42:432
3250099250,18cyclictest0-21swapper/221:35:422
32500992421,2cyclictest7588-21turbostat.cron23:45:012
3250099240,23cyclictest0-21swapper/223:45:162
3250099240,23cyclictest0-21swapper/223:33:262
3250099240,23cyclictest0-21swapper/222:26:552
3250099240,23cyclictest0-21swapper/222:13:022
3250099240,23cyclictest0-21swapper/220:12:472
3250099240,23cyclictest0-21swapper/220:12:462
3250099240,23cyclictest0-21swapper/200:17:182
3250099240,22cyclictest0-21swapper/221:26:582
3250099240,19cyclictest0-21swapper/200:24:012
3249299240,23cyclictest0-21swapper/123:01:571
3249099240,23cyclictest7356-21ssh21:51:270
3249099240,23cyclictest0-21swapper/021:57:110
108332240,0sleep30-21swapper/323:17:103
3250099233,19cyclictest0-21swapper/200:32:002
3250099232,20cyclictest0-21swapper/222:43:232
32500992318,5cyclictest0-21swapper/222:51:212
32500992312,3cyclictest0-21swapper/200:05:442
3250099231,21cyclictest0-21swapper/223:59:522
3250099231,21cyclictest0-21swapper/221:56:202
3250099230,22cyclictest0-21swapper/223:37:592
3250099230,22cyclictest0-21swapper/223:10:122
3250099230,1cyclictest31175-21ssh22:02:012
3250099230,17cyclictest0-21swapper/221:33:552
3250099230,17cyclictest0-21swapper/221:15:522
3249299230,21cyclictest0-21swapper/121:04:031
32490992316,6cyclictest0-21swapper/023:11:030
3249099230,22cyclictest0-21swapper/023:32:490
3249099230,22cyclictest0-21swapper/022:05:280
3249099230,17cyclictest0-21swapper/000:12:210
3250099222,19cyclictest0-21swapper/223:29:312
32500992212,9cyclictest0-21swapper/222:56:582
3250099221,20cyclictest0-21swapper/222:33:042
3250099221,20cyclictest0-21swapper/222:05:442
3250099220,3cyclictest0-21swapper/221:46:162
3250099220,21cyclictest0-21swapper/223:05:292
3250099220,21cyclictest0-21swapper/223:00:042
3250099220,21cyclictest0-21swapper/219:54:332
3250099220,21cyclictest0-21swapper/200:29:342
3250099220,21cyclictest0-21swapper/200:11:052
3250099220,16cyclictest0-21swapper/221:50:512
3250099220,15cyclictest0-21swapper/222:45:052
3249299221,3cyclictest0-21swapper/119:16:381
3249299220,3cyclictest0-21swapper/120:03:121
3249299220,3cyclictest0-21swapper/100:21:041
3249299220,21cyclictest0-21swapper/123:43:271
3249299220,21cyclictest0-21swapper/123:39:061
3249299220,21cyclictest0-21swapper/123:26:031
3249299220,21cyclictest0-21swapper/121:18:271
3249299220,21cyclictest0-21swapper/120:53:271
3249299220,21cyclictest0-21swapper/120:33:001
3249299220,21cyclictest0-21swapper/120:13:531
3249299220,21cyclictest0-21swapper/120:13:531
3249299220,21cyclictest0-21swapper/100:29:341
3249099220,21cyclictest0-21swapper/021:36:450
3249099220,21cyclictest0-21swapper/000:20:430
3250099215,15cyclictest0-21swapper/200:01:532
32500992118,2cyclictest750-21snmpd20:09:532
3250099210,20cyclictest0-21swapper/222:36:392
3250099210,20cyclictest0-21swapper/220:54:452
3250099210,15cyclictest0-21swapper/223:16:432
3250099210,15cyclictest0-21swapper/222:16:342
32492992117,3cyclictest0-21swapper/119:51:351
32492992117,3cyclictest0-21swapper/119:22:241
32492992117,2cyclictest4660-21ssh21:36:191
3249299210,2cyclictest0-21swapper/120:09:081
3249299210,20cyclictest0-21swapper/123:50:401
3249299210,20cyclictest0-21swapper/123:49:121
3249299210,20cyclictest0-21swapper/123:14:321
3249299210,20cyclictest0-21swapper/122:41:221
3249299210,20cyclictest0-21swapper/122:18:461
3249299210,20cyclictest0-21swapper/121:55:041
3249299210,20cyclictest0-21swapper/121:33:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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