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2025-11-29 - 22:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Sat Nov 29, 2025 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8081215576,8sleep10-21swapper/107:06:431
2560121330,7sleep1850099cyclictest12:12:271
82672123114,6sleep30-21swapper/307:09:093
8241211596,7sleep20-21swapper/207:08:482
80652110101,6sleep00-21swapper/007:06:300
144312910,0sleep30-21swapper/310:27:103
304172720,0sleep10-21swapper/110:51:561
54892700,0sleep35494-21cpuspeed_turbos08:55:133
291802620,0sleep00-21swapper/011:41:180
72842600,0sleep10-21swapper/111:15:161
227242580,0sleep338-21rcuc/311:05:203
191002580,1sleep120-21rcuc/111:20:191
106232580,1sleep30-21swapper/309:53:183
144982570,0sleep00-21swapper/011:00:200
164892540,0sleep30-21swapper/311:35:193
321382490,0sleep30-21swapper/310:05:113
849599330,27cyclictest0-21swapper/011:26:040
8495993215,4cyclictest0-21swapper/012:13:110
8506992915,13cyclictest22765-21diskmemload09:30:122
850699291,27cyclictest0-21swapper/211:52:432
850699280,27cyclictest0-21swapper/210:07:322
850699280,27cyclictest0-21swapper/208:57:002
850099280,27cyclictest0-21swapper/111:52:131
850699270,26cyclictest0-21swapper/212:31:552
850699270,26cyclictest0-21swapper/211:17:192
850699270,26cyclictest0-21swapper/211:03:362
850699270,26cyclictest0-21swapper/210:45:112
850699270,26cyclictest0-21swapper/209:59:552
850699270,26cyclictest0-21swapper/209:44:582
850699270,26cyclictest0-21swapper/209:22:072
850699270,26cyclictest0-21swapper/209:06:152
850699270,26cyclictest0-21swapper/208:53:302
850699270,26cyclictest0-21swapper/208:18:032
850699270,26cyclictest0-21swapper/208:05:562
850699270,26cyclictest0-21swapper/207:45:022
850699270,26cyclictest0-21swapper/207:30:022
850699270,26cyclictest0-21swapper/207:22:322
850699270,26cyclictest0-21swapper/207:11:072
850099270,26cyclictest0-21swapper/112:04:431
850099270,26cyclictest0-21swapper/110:19:111
850099270,26cyclictest0-21swapper/109:56:071
850099270,26cyclictest0-21swapper/109:23:491
850099270,26cyclictest0-21swapper/108:43:091
8506992622,3cyclictest0-21swapper/211:29:242
8506992618,7cyclictest0-21swapper/212:04:462
850699260,26cyclictest0-21swapper/210:58:542
850699260,26cyclictest0-21swapper/207:16:462
850699260,25cyclictest0-21swapper/212:25:012
850699260,25cyclictest0-21swapper/211:37:542
850699260,25cyclictest0-21swapper/211:20:062
850699260,25cyclictest0-21swapper/211:10:452
850699260,25cyclictest0-21swapper/210:36:232
850699260,25cyclictest0-21swapper/210:28:082
850699260,25cyclictest0-21swapper/210:16:032
850699260,25cyclictest0-21swapper/208:47:242
8500992623,3cyclictest0-21swapper/111:05:091
850099260,25cyclictest0-21swapper/110:45:171
850099260,25cyclictest0-21swapper/109:01:031
850099260,20cyclictest0-21swapper/112:06:161
8506992522,3cyclictest0-21swapper/212:15:522
8506992522,3cyclictest0-21swapper/208:23:482
8506992521,3cyclictest0-21swapper/211:09:192
850699250,24cyclictest0-21swapper/210:01:432
850699250,24cyclictest0-21swapper/208:41:332
8500992523,2cyclictest0-21swapper/112:26:491
8500992516,8cyclictest0-21swapper/112:35:331
850099250,24cyclictest0-21swapper/112:20:111
850099250,24cyclictest0-21swapper/111:02:081
850099250,24cyclictest0-21swapper/109:07:031
850099250,24cyclictest0-21swapper/108:52:051
8506992422,2cyclictest0-21swapper/210:31:082
8506992421,3cyclictest0-21swapper/208:02:232
850699241,22cyclictest0-21swapper/210:22:022
850699241,22cyclictest0-21swapper/209:02:332
850699240,23cyclictest0-21swapper/208:33:482
8500992422,2cyclictest0-21swapper/107:44:531
8500992420,3cyclictest0-21swapper/111:39:121
8500992410,13cyclictest0-21swapper/109:32:501
850099240,23cyclictest0-21swapper/110:58:271
850099240,23cyclictest0-21swapper/109:35:151
850099240,23cyclictest0-21swapper/109:35:151
850099240,23cyclictest0-21swapper/109:11:431
849599240,23cyclictest0-21swapper/009:45:420
849599240,17cyclictest0-21swapper/012:15:070
8506992322,1cyclictest0-21swapper/210:12:322
8506992320,3cyclictest0-21swapper/209:52:312
8506992316,6cyclictest0-21swapper/209:39:112
8506992316,6cyclictest0-21swapper/209:39:102
850699230,22cyclictest0-21swapper/209:16:322
850699230,22cyclictest0-21swapper/208:11:262
8500992314,8cyclictest0-21swapper/109:40:561
850099231,21cyclictest0-21swapper/110:42:291
850099231,21cyclictest0-21swapper/110:33:441
850099231,21cyclictest0-21swapper/110:00:031
850099230,22cyclictest0-21swapper/110:37:441
849599236,16cyclictest0-21swapper/010:45:420
8495992316,7cyclictest0-21swapper/011:55:540
8495992316,6cyclictest0-21swapper/011:53:290
849599230,22cyclictest0-21swapper/012:38:250
849599230,22cyclictest0-21swapper/012:20:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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