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2026-01-21 - 22:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Wed Jan 21, 2026 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
300211655,7sleep00-21swapper/007:09:580
32648210796,6sleep20-21swapper/207:08:272
32726210495,6sleep10-21swapper/107:09:271
32639210493,8sleep30-21swapper/307:08:203
122422720,1sleep00-21swapper/008:15:130
97842690,0sleep10-21swapper/108:10:171
180452650,0sleep20-21swapper/211:17:072
137162650,0sleep10-21swapper/109:39:211
13462650,0sleep10-21swapper/112:35:121
95572620,0sleep3391ktimersoftd/309:10:063
244332610,1sleep340-21ksoftirqd/309:56:363
22272580,0sleep30-21swapper/307:35:203
16792580,0sleep30-21swapper/311:38:193
261652570,0sleep03-21ksoftirqd/009:44:550
216582570,0sleep00-21swapper/010:37:120
272492550,0sleep10-21swapper/112:03:201
285042540,0sleep10-21swapper/112:17:501
267702540,0sleep00-21swapper/009:30:180
156562510,0sleep30-21swapper/310:49:203
478994615,30cyclictest0-21swapper/112:05:111
473993315,17cyclictest0-21swapper/012:05:110
48099301,2cyclictest0-21swapper/208:55:112
47899290,28cyclictest0-21swapper/112:29:541
47899280,27cyclictest0-21swapper/110:15:431
48099270,26cyclictest0-21swapper/209:05:272
47899270,26cyclictest0-21swapper/112:21:511
47399270,26cyclictest0-21swapper/009:11:120
47399270,26cyclictest0-21swapper/007:36:220
48099260,25cyclictest28822-21ssh11:21:272
48099260,25cyclictest0-21swapper/210:37:582
47899260,25cyclictest0-21swapper/108:23:441
48099250,24cyclictest0-21swapper/212:14:482
478992522,2cyclictest0-21swapper/110:58:431
47899251,18cyclictest0-21swapper/109:15:131
47899251,18cyclictest0-21swapper/109:15:131
47899250,24cyclictest0-21swapper/110:29:081
47899250,24cyclictest0-21swapper/110:20:511
47899250,24cyclictest0-21swapper/109:56:511
47899250,24cyclictest0-21swapper/108:54:321
47899250,24cyclictest0-21swapper/108:33:501
47899250,24cyclictest0-21swapper/107:49:461
47899250,24cyclictest0-21swapper/107:44:461
473992516,8cyclictest0-21swapper/009:20:010
48099242,21cyclictest0-21swapper/211:53:172
480992417,6cyclictest0-21swapper/211:09:292
480992413,4cyclictest0-21swapper/212:35:092
48099241,22cyclictest0-21swapper/212:01:062
48099240,23cyclictest24738-21ssh12:30:182
48099240,23cyclictest0-21swapper/210:14:242
48099240,22cyclictest0-21swapper/209:59:482
47899240,23cyclictest0-21swapper/112:31:391
47899240,1cyclictest0-21swapper/109:31:471
47899240,18cyclictest0-21swapper/110:51:021
47899240,17cyclictest0-21swapper/109:10:461
47399240,23cyclictest0-21swapper/010:57:580
47399240,23cyclictest0-21swapper/010:10:460
47399240,23cyclictest0-21swapper/009:58:010
47399240,18cyclictest0-21swapper/009:49:440
47399240,18cyclictest0-21swapper/009:38:160
46342240,1sleep010-21rcuc/007:40:130
48099232,20cyclictest0-21swapper/211:26:012
48099232,20cyclictest0-21swapper/211:00:262
48099232,20cyclictest0-21swapper/209:35:202
48099231,21cyclictest0-21swapper/211:31:102
48099231,21cyclictest0-21swapper/210:18:152
48099230,22cyclictest0-21swapper/212:22:412
48099230,22cyclictest0-21swapper/210:20:042
48099230,22cyclictest0-21swapper/209:16:192
48099230,22cyclictest0-21swapper/209:16:182
48099230,17cyclictest0-21swapper/210:01:422
47899238,13cyclictest0-21swapper/110:45:151
47899236,16cyclictest0-21swapper/111:59:091
47899235,17cyclictest0-21swapper/111:05:151
478992314,8cyclictest0-21swapper/110:33:551
478992314,8cyclictest0-21swapper/109:20:101
47899230,22cyclictest0-21swapper/109:40:251
47899230,21cyclictest0-21swapper/112:14:381
47899230,18cyclictest0-21swapper/111:50:171
47899230,17cyclictest24383-21turbostat11:35:001
47899230,17cyclictest0-21swapper/111:47:531
47899230,17cyclictest0-21swapper/109:50:301
47399230,22cyclictest0-21swapper/012:20:470
47399230,22cyclictest0-21swapper/011:12:580
47399230,22cyclictest0-21swapper/010:53:190
47399230,22cyclictest0-21swapper/010:03:220
47399230,22cyclictest0-21swapper/007:28:280
47399230,18cyclictest0-21swapper/012:11:410
47399230,17cyclictest0-21swapper/011:08:030
48099222,19cyclictest0-21swapper/210:31:072
48099222,19cyclictest0-21swapper/209:40:432
480992218,2cyclictest750-21snmpd11:44:022
48099221,20cyclictest0-21swapper/210:29:132
48099221,20cyclictest0-21swapper/209:51:402
48099221,20cyclictest0-21swapper/207:23:172
48099220,21cyclictest0-21swapper/212:17:282
48099220,21cyclictest0-21swapper/211:36:552
48099220,21cyclictest0-21swapper/211:10:082
48099220,21cyclictest0-21swapper/210:53:042
48099220,21cyclictest0-21swapper/209:20:392
48099220,21cyclictest0-21swapper/209:10:212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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