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2025-12-11 - 20:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Thu Dec 11, 2025 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30756212462,7sleep10-21swapper/107:07:571
253742116104,7sleep20-21swapper/207:05:122
309132109100,6sleep30-21swapper/307:09:593
306262109100,6sleep00-21swapper/007:06:150
151762620,0sleep10-21swapper/109:25:211
123892620,1sleep312394-21kthreadcore07:45:193
33852600,1sleep20-21swapper/208:05:162
207832600,0sleep20-21swapper/209:12:202
83122590,1sleep30-21swapper/312:27:043
25472580,1sleep32550-21missed_timers11:00:203
96362560,0sleep10-21swapper/108:35:231
95452550,0sleep20-21swapper/209:24:342
262542550,0sleep00-21swapper/009:50:150
3110099291,3cyclictest0-21swapper/211:48:572
3110099290,27cyclictest0-21swapper/210:41:232
3110099282,20cyclictest0-21swapper/209:51:372
31100992816,10cyclictest0-21swapper/210:20:182
3110099281,2cyclictest0-21swapper/210:45:292
3110099281,21cyclictest0-21swapper/212:25:102
3110099280,27cyclictest0-21swapper/210:53:242
3110099280,26cyclictest0-21swapper/211:29:402
3110099280,21cyclictest0-21swapper/212:08:052
31100992715,10cyclictest0-21swapper/212:39:222
3110099271,25cyclictest0-21swapper/209:33:382
3110099270,3cyclictest0-21swapper/211:10:122
3110099270,26cyclictest0-21swapper/211:20:242
3110099270,26cyclictest0-21swapper/207:50:392
3110099270,21cyclictest0-21swapper/211:52:062
3110099270,16cyclictest0-21swapper/212:34:542
31091992723,2cyclictest22042-21sshd08:46:220
3109199270,26cyclictest0-21swapper/010:35:170
31100992617,1cyclictest15617-21lldpd07:40:562
3110099261,10cyclictest0-21swapper/211:00:122
3110099260,2cyclictest0-21swapper/207:28:062
3110099260,25cyclictest0-21swapper/210:06:292
3110099260,25cyclictest0-21swapper/210:01:052
3110099260,25cyclictest0-21swapper/208:38:432
3110099260,20cyclictest0-21swapper/212:11:452
3109599260,25cyclictest0-21swapper/110:33:081
31091992623,2cyclictest15644-21ssh11:08:300
3110099253,13cyclictest0-21swapper/210:25:232
31100992515,9cyclictest0-21swapper/209:38:302
31100992514,4cyclictest0-21swapper/208:15:132
31100992513,10cyclictest0-21swapper/209:55:122
3110099250,24cyclictest0-21swapper/211:07:292
31095992516,8cyclictest0-21swapper/111:06:431
3109599250,24cyclictest0-21swapper/111:32:461
3109599250,24cyclictest0-21swapper/110:28:361
3109599250,24cyclictest0-21swapper/109:19:261
3109199250,24cyclictest0-21swapper/009:43:180
3109199250,24cyclictest0-21swapper/009:28:190
3109199250,24cyclictest0-21swapper/009:15:220
3110099243,14cyclictest0-21swapper/212:21:022
3110099243,14cyclictest0-21swapper/212:21:022
3110099242,21cyclictest0-21swapper/211:42:052
31100992417,1cyclictest10272-21snmpd10:30:052
31100992413,10cyclictest0-21swapper/211:58:352
3110099241,17cyclictest0-21swapper/211:31:162
3110099240,23cyclictest0-21swapper/212:04:342
3110099240,23cyclictest0-21swapper/210:39:312
3110099240,23cyclictest0-21swapper/209:25:312
3110099240,22cyclictest13516-21turbostat.cron08:15:002
3109599241,22cyclictest0-21swapper/109:57:271
3109599240,18cyclictest0-21swapper/112:21:171
3109599240,18cyclictest0-21swapper/112:21:161
3109599240,18cyclictest0-21swapper/111:13:391
31091992415,8cyclictest0-21swapper/011:24:170
3109199240,18cyclictest0-21swapper/011:52:450
437822319,3sleep30-21swapper/308:32:093
3110099233,19cyclictest0-21swapper/210:19:372
3110099233,11cyclictest0-21swapper/208:02:572
31100992316,2cyclictest0-21swapper/209:17:012
31100992315,1cyclictest10272-21snmpd08:54:312
31100992314,1cyclictest10272-21snmpd08:43:342
3110099231,21cyclictest0-21swapper/211:16:472
3110099231,15cyclictest0-21swapper/207:15:502
3110099230,16cyclictest0-21swapper/210:13:452
3109599237,15cyclictest0-21swapper/111:57:351
31095992321,1cyclictest0-21swapper/110:58:571
31095992315,7cyclictest0-21swapper/110:37:281
31095992314,8cyclictest0-21swapper/110:07:091
3109599230,22cyclictest0-21swapper/112:02:081
3109599230,22cyclictest0-21swapper/111:51:061
3109599230,22cyclictest0-21swapper/111:35:251
3109599230,22cyclictest0-21swapper/111:26:161
3109599230,22cyclictest0-21swapper/110:47:251
3109599230,22cyclictest0-21swapper/110:21:551
3109599230,22cyclictest0-21swapper/109:46:581
3109599230,22cyclictest0-21swapper/109:44:191
3109599230,18cyclictest0-21swapper/110:41:061
3109199231,6cyclictest0-21swapper/009:34:500
31091992315,7cyclictest0-21swapper/012:08:160
31091992314,8cyclictest0-21swapper/012:32:210
3109199231,21cyclictest0-21swapper/011:04:480
3109199230,22cyclictest0-21swapper/012:21:170
3109199230,22cyclictest0-21swapper/012:21:170
3109199230,22cyclictest0-21swapper/010:42:290
3109199230,21cyclictest0-21swapper/009:35:590
2786422319,3sleep30-21swapper/308:51:003
1053622319,3sleep30-21swapper/307:43:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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