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2026-08-25 - 18:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack5slot4.osadl.org (updated Tue Aug 25, 2026 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15310214483,7sleep30-21swapper/307:05:313
156332112103,6sleep10-21swapper/107:09:411
15424211199,8sleep00-21swapper/007:07:000
15329210697,6sleep20-21swapper/207:05:462
145932650,0sleep00-21swapper/008:00:210
28062640,0sleep30-21swapper/312:15:143
266592630,0sleep20-21swapper/212:39:452
149492590,0sleep20-21swapper/211:50:382
230292560,0sleep10-21swapper/112:23:301
192072560,1sleep30-21swapper/312:20:273
71042550,0sleep20-21swapper/207:55:192
44022550,0sleep20-21swapper/209:28:072
10042550,0sleep20-21swapper/211:17:292
160832530,0sleep10-21swapper/108:05:151
266782500,0sleep226684-21kthreadcore07:15:182
148862440,1sleep338-21rcuc/309:19:223
235152430,4sleep01582599cyclictest10:17:540
1582599315,25cyclictest0-21swapper/009:50:220
1583499281,26cyclictest0-21swapper/210:18:412
1583499280,27cyclictest0-21swapper/208:26:392
1583499271,25cyclictest0-21swapper/212:17:312
1583499270,26cyclictest0-21swapper/211:40:422
1583499270,26cyclictest0-21swapper/211:11:092
1583499270,26cyclictest0-21swapper/211:07:392
1583499270,26cyclictest0-21swapper/208:15:142
1583499270,26cyclictest0-21swapper/208:11:302
1583499270,26cyclictest0-21swapper/207:21:052
1582599270,26cyclictest0-21swapper/008:55:280
1583499260,25cyclictest0-21swapper/210:40:382
1583499260,25cyclictest0-21swapper/209:18:282
1583499260,25cyclictest0-21swapper/208:45:242
1583499260,25cyclictest0-21swapper/207:43:502
1583499250,24cyclictest19373-21ssh10:57:442
1583499250,24cyclictest0-21swapper/210:52:332
1582599250,24cyclictest0-21swapper/011:03:120
183612240,0sleep00-21swapper/012:06:340
15834992421,2cyclictest0-21swapper/209:53:592
1583499240,23cyclictest0-21swapper/211:27:412
1583499240,23cyclictest0-21swapper/211:01:422
1582999241,22cyclictest0-21swapper/111:21:391
1582599240,23cyclictest0-21swapper/012:02:240
1582599240,23cyclictest0-21swapper/011:39:420
1582599240,23cyclictest0-21swapper/010:35:380
1582599240,23cyclictest0-21swapper/010:34:200
1583499236,3cyclictest0-21swapper/211:56:592
1583499232,20cyclictest0-21swapper/209:34:032
15834992317,6cyclictest0-21swapper/209:58:402
15834992316,6cyclictest0-21swapper/211:20:232
1583499230,22cyclictest0-21swapper/211:30:312
1583499230,22cyclictest0-21swapper/209:45:452
1583499230,17cyclictest0-21swapper/212:33:222
1582999231,3cyclictest0-21swapper/112:37:551
1582599230,22cyclictest0-21swapper/012:34:230
1582599230,22cyclictest0-21swapper/011:50:300
1582599230,22cyclictest0-21swapper/011:42:510
1582599230,22cyclictest0-21swapper/011:31:420
1582599230,22cyclictest0-21swapper/011:25:410
1582599230,22cyclictest0-21swapper/010:57:090
1582599230,22cyclictest0-21swapper/009:24:310
1582599230,17cyclictest0-21swapper/009:33:110
1582599230,17cyclictest0-21swapper/009:28:440
1583499227,14cyclictest0-21swapper/209:35:192
1583499225,16cyclictest0-21swapper/209:10:362
15834992218,3cyclictest0-21swapper/209:05:122
15834992216,5cyclictest0-21swapper/209:20:092
15834992215,6cyclictest0-21swapper/212:09:462
1583499221,20cyclictest0-21swapper/208:44:412
1583499221,20cyclictest0-21swapper/207:45:422
1583499220,21cyclictest0-21swapper/212:27:322
1583499220,21cyclictest0-21swapper/211:45:422
1583499220,21cyclictest0-21swapper/211:45:422
1583499220,21cyclictest0-21swapper/210:20:162
1583499220,21cyclictest0-21swapper/210:09:262
1583499220,21cyclictest0-21swapper/210:00:562
1583499220,21cyclictest0-21swapper/209:41:582
1583499220,21cyclictest0-21swapper/209:03:012
1583499220,21cyclictest0-21swapper/208:54:482
1583499220,20cyclictest0-21swapper/210:26:542
1583499220,16cyclictest0-21swapper/210:30:292
15829992219,2cyclictest18085-21cat11:40:001
1582999221,20cyclictest0-21swapper/110:19:591
1582999220,3cyclictest0-21swapper/111:09:001
1582999220,21cyclictest0-21swapper/112:11:191
1582999220,21cyclictest0-21swapper/110:33:281
1582999220,21cyclictest0-21swapper/109:38:311
1582999220,21cyclictest0-21swapper/108:31:351
1582999220,21cyclictest0-21swapper/107:51:411
1582999220,21cyclictest0-21swapper/107:17:221
1582999220,20cyclictest24676-21diskmemload11:33:151
1582599226,15cyclictest0-21swapper/007:40:260
15825992215,6cyclictest0-21swapper/009:14:040
1582599221,20cyclictest0-21swapper/012:36:210
1582599220,21cyclictest0-21swapper/012:21:380
1582599220,21cyclictest0-21swapper/012:10:080
1582599220,21cyclictest0-21swapper/011:48:340
1582599220,21cyclictest0-21swapper/011:48:340
1582599220,21cyclictest0-21swapper/011:21:520
1582599220,21cyclictest0-21swapper/011:07:010
1582599220,21cyclictest0-21swapper/010:54:360
1582599220,21cyclictest0-21swapper/010:43:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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