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2025-12-17 - 19:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Fri Dec 12, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25876212968,7sleep30-21swapper/319:08:533
25650212263,6sleep00-21swapper/019:05:570
256362117108,6sleep10-21swapper/119:05:461
25850211074,8sleep20-21swapper/219:08:322
3035321020,0sleep30-21swapper/300:15:163
143372620,1sleep30-21swapper/322:46:003
289352610,1sleep128939-21kthreadcore21:50:221
251202590,0sleep30-21swapper/321:16:083
36412560,0sleep00-21swapper/000:34:520
155652560,1sleep115572-21irqcore20:20:191
15352550,0sleep20-21swapper/221:00:252
101272550,0sleep310135-21kthreadcore20:40:183
200542540,0sleep20-21swapper/223:36:452
183662530,0sleep00-21swapper/019:25:180
214232510,5sleep22614099cyclictest23:21:322
163072500,0sleep116313-21kthreadcore22:15:221
2613799340,17cyclictest0-21swapper/100:25:151
2613799300,29cyclictest0-21swapper/122:50:391
2613799300,29cyclictest0-21swapper/122:50:391
2613799290,21cyclictest0-21swapper/122:48:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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