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2025-05-03 - 02:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Sat May 03, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19639211775,8sleep10-21swapper/119:06:381
19759211563,49sleep20-21swapper/219:08:122
197372114101,10sleep00-21swapper/019:07:530
196312112102,7sleep30-21swapper/319:06:333
2767321080,1sleep30-21swapper/320:35:193
303922750,0sleep00-21swapper/023:25:200
303922750,0sleep00-21swapper/023:25:200
198362740,0sleep20-21swapper/221:32:012
87222710,0sleep00-21swapper/022:44:380
149072620,0sleep10-21swapper/122:00:211
112372620,0sleep10-21swapper/122:15:151
223262580,1sleep122325-21smartctl00:25:171
293822570,0sleep20-21swapper/221:20:232
114652570,0sleep120-21rcuc/100:20:001
298082560,0sleep2301ktimersoftd/220:10:142
231402560,0sleep00-21swapper/000:08:300
65782550,0sleep10-21swapper/119:50:191
127512550,0sleep20-21swapper/220:50:162
268352490,5sleep02007199cyclictest23:08:010
2007799311,22cyclictest0-21swapper/221:09:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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