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2026-08-15 - 13:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Sat Aug 15, 2026 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11554215374,8sleep10-21swapper/119:07:241
11474213170,6sleep30-21swapper/319:06:233
11558212464,7sleep00-21swapper/019:07:270
115772113103,7sleep20-21swapper/219:07:422
2260321030,0sleep122602-21ssh23:44:121
2260321030,0sleep122602-21ssh23:44:121
159902710,0sleep10-21swapper/122:45:151
148852630,1sleep20-21swapper/223:25:222
271862620,0sleep10-21swapper/122:08:101
59512610,0sleep10-21swapper/122:26:001
14452610,0sleep00-21swapper/020:50:190
49972580,0sleep20-21swapper/223:50:172
295032580,0sleep00-21swapper/023:45:310
312812570,5sleep11191199cyclictest21:27:441
211262570,0sleep00-21swapper/023:55:560
194752570,0sleep00-21swapper/021:35:440
128602570,1sleep30-21swapper/321:00:183
96812550,0sleep010-21rcuc/022:15:140
36682540,0sleep30-21swapper/323:07:293
37322530,0sleep10-21swapper/121:44:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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