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2026-02-16 - 09:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Mon Feb 16, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127412135126,6sleep10-21swapper/119:08:421
12678212525,8sleep00-21swapper/019:07:520
12525212566,7sleep20-21swapper/219:05:552
12768212463,7sleep30-21swapper/319:09:043
168421100,0sleep30-21swapper/323:45:163
312652720,1sleep120-21rcuc/122:45:141
287912670,0sleep30-21swapper/321:15:183
143192670,0sleep00-21swapper/000:25:170
296212640,1sleep30-21swapper/300:10:153
120022640,0sleep30-21swapper/319:35:143
194852590,0sleep10-21swapper/122:35:131
291002580,0sleep10-21swapper/100:10:121
195362560,0sleep10-21swapper/100:30:141
247802540,0sleep30-21swapper/323:05:193
50582530,0sleep10-21swapper/120:25:181
105632520,1sleep310568-21kthreadcore21:55:193
1301499291,27cyclictest0-21swapper/200:27:502
1301499270,26cyclictest0-21swapper/221:01:392
1301499260,25cyclictest0-21swapper/219:48:062
1301499260,25cyclictest0-21swapper/200:35:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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