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2025-09-18 - 08:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Thu Sep 18, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21754212867,7sleep30-21swapper/319:07:333
218942114105,6sleep10-21swapper/119:09:241
218112110100,7sleep00-21swapper/019:08:170
16323210797,7sleep20-21swapper/219:05:042
142052650,1sleep120-21rcuc/121:30:241
82382610,0sleep20-21swapper/220:15:202
107242610,1sleep20-21swapper/219:50:212
60472580,0sleep30-21swapper/300:00:243
260332580,1sleep326036-21kthreadcore21:00:183
145922550,0sleep30-21swapper/322:50:133
2211399350,34cyclictest0-21swapper/223:20:142
22109993018,11cyclictest0-21swapper/122:33:071
22113992924,4cyclictest0-21swapper/223:05:132
2211399281,26cyclictest0-21swapper/221:44:482
136852280,1sleep113688-21gltestperf20:50:191
2211399270,26cyclictest0-21swapper/219:14:082
2210999270,26cyclictest0-21swapper/123:20:181
2210999270,26cyclictest0-21swapper/122:20:391
2210999270,26cyclictest0-21swapper/120:36:381
2210999270,26cyclictest0-21swapper/120:26:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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