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2026-09-29 - 10:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Tue Sep 29, 2026 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2204421170,0sleep30-21swapper/322:49:073
10071210960,11sleep30-21swapper/319:09:443
9779210695,6sleep10-21swapper/119:05:571
9763210696,7sleep00-21swapper/019:05:430
5683210696,6sleep20-21swapper/219:05:182
324692780,0sleep30-21swapper/321:29:473
152992740,0sleep10-21swapper/121:20:241
22002680,0sleep30-21swapper/322:54:553
120672660,0sleep012072-21needreboot22:15:190
107422650,0sleep00-21swapper/019:35:190
323862620,0sleep20-21swapper/220:50:172
188832610,0sleep10-21swapper/122:20:011
37722600,0sleep30-21swapper/323:35:293
26102600,0sleep30-21swapper/322:11:293
312022580,0sleep00-21swapper/023:49:000
290262580,0sleep10-21swapper/122:50:291
23852570,0sleep10-21swapper/100:04:511
186992560,0sleep10-21swapper/123:43:121
116702560,0sleep20-21swapper/222:30:232
58092530,0sleep10-21swapper/121:17:041
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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