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2025-06-28 - 23:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Sat Jun 28, 2025 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8447216596,7sleep00-21swapper/007:07:020
8383213775,8sleep30-21swapper/307:06:143
84332111102,6sleep10-21swapper/107:06:511
8531210898,7sleep20-21swapper/207:08:082
71521050,0sleep10-21swapper/108:50:151
180682670,0sleep20-21swapper/210:15:072
325152660,0sleep30-21swapper/310:40:003
36102610,0sleep20-21swapper/212:17:302
220882590,0sleep10-21swapper/110:15:221
45242550,0sleep00-21swapper/011:31:480
121942550,0sleep212197-21kthreadcore07:10:242
5822540,0sleep30-21swapper/309:47:373
316602530,0sleep10-21swapper/108:45:231
8844993516,18cyclictest0-21swapper/009:50:140
885299291,27cyclictest0-21swapper/209:42:232
884899280,27cyclictest0-21swapper/112:33:091
8852992715,1cyclictest8838-21cyclictest08:15:152
885299270,26cyclictest0-21swapper/211:40:532
885299270,26cyclictest0-21swapper/210:53:522
885299270,26cyclictest0-21swapper/208:35:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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