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2025-11-02 - 12:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack5slot4.osadl.org (updated Sun Nov 02, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
56112112103,6sleep10-21swapper/119:06:121
58782111101,7sleep30-21swapper/319:09:393
59062109100,6sleep00-21swapper/019:10:000
5582210898,7sleep20-21swapper/219:05:492
33472730,6sleep1607799cyclictest20:55:131
199962600,3sleep338-21rcuc/321:40:133
317682590,1sleep031776-21kthreadcore22:45:190
277482580,0sleep229-21rcuc/200:00:192
102002580,0sleep20-21swapper/220:05:202
266762560,0sleep00-21swapper/021:41:420
303142540,0sleep00-21swapper/020:50:140
163422530,0sleep30-21swapper/321:21:383
64802490,0sleep26485-21kthreadcore23:35:202
607799350,24cyclictest0-21swapper/122:01:111
318722320,0sleep30-21swapper/323:15:303
608199311,3cyclictest0-21swapper/223:05:132
6077993016,14cyclictest0-21swapper/100:26:251
607799291,22cyclictest0-21swapper/122:36:241
607799282,21cyclictest0-21swapper/123:37:061
607799282,21cyclictest0-21swapper/121:40:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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