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2026-06-14 - 13:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Sun Jun 14, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20195213072,7sleep20-21swapper/219:08:072
20037212865,6sleep10-21swapper/119:06:061
200912112102,7sleep30-21swapper/319:06:483
20026210898,7sleep00-21swapper/019:05:570
279342870,0sleep00-21swapper/020:40:150
307522670,0sleep10-21swapper/121:10:201
303732600,0sleep30-21swapper/320:10:223
311452590,0sleep10-21swapper/100:30:201
300542590,1sleep010-21rcuc/019:15:170
65742570,1sleep16579-21kthreadcore23:40:181
286852570,1sleep30-21swapper/319:15:123
276402560,0sleep30-21swapper/322:35:153
246282450,0sleep224633-21kthreadcore19:10:182
2050999290,28cyclictest0-21swapper/222:25:112
20504992920,2cyclictest0-21swapper/123:53:171
2050999270,26cyclictest0-21swapper/222:21:482
2050999270,26cyclictest0-21swapper/200:09:202
20509992622,2cyclictest28298-21munin-run23:05:012
2050999260,25cyclictest0-21swapper/222:54:282
20509992523,2cyclictest0-21swapper/219:35:172
20509992521,3cyclictest0-21swapper/219:15:202
2050999250,24cyclictest0-21swapper/200:21:472
2050999240,23cyclictest0-21swapper/222:35:252
20509992318,4cyclictest0-21swapper/221:13:182
2050999230,17cyclictest0-21swapper/223:17:322
2050499230,21cyclictest0-21swapper/119:16:571
20509992220,2cyclictest0-21swapper/219:29:112
20509992218,3cyclictest0-21swapper/222:13:212
20509992218,3cyclictest0-21swapper/200:17:252
2050999220,21cyclictest0-21swapper/221:33:302
2050999220,21cyclictest0-21swapper/220:50:532
2050499220,3cyclictest0-21swapper/122:22:551
2050499220,21cyclictest0-21swapper/123:45:151
2050499220,21cyclictest0-21swapper/123:14:391
2050499220,21cyclictest0-21swapper/122:54:481
2050499220,21cyclictest0-21swapper/122:45:071
2050499220,21cyclictest0-21swapper/122:38:421
2050499220,21cyclictest0-21swapper/122:29:361
2050499220,21cyclictest0-21swapper/122:12:511
2050499220,21cyclictest0-21swapper/120:51:381
2050499220,21cyclictest0-21swapper/120:22:141
2050499220,21cyclictest0-21swapper/120:15:381
2050499220,21cyclictest0-21swapper/120:02:381
2050499220,21cyclictest0-21swapper/100:02:461
2049999220,16cyclictest0-21swapper/019:56:590
20509992118,1cyclictest752-21lldpd20:46:572
20509992116,4cyclictest749-21snmpd20:35:472
20509992113,7cyclictest0-21swapper/200:25:222
2050999210,3cyclictest0-21swapper/222:07:212
2050999210,2cyclictest0-21swapper/223:48:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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