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2026-07-29 - 18:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Mon Jul 27, 2026 00:44:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17799213980,7sleep20-21swapper/219:06:282
177852116107,6sleep00-21swapper/019:06:180
17912211199,7sleep30-21swapper/319:07:573
17798210595,7sleep10-21swapper/119:06:271
290352730,0sleep00-21swapper/022:35:200
106732690,0sleep30-21swapper/319:55:183
238542660,0sleep10-21swapper/122:18:501
166652640,0sleep20-21swapper/221:19:512
59062620,0sleep10-21swapper/123:35:201
26452620,1sleep00-21swapper/021:12:520
130282590,0sleep20-21swapper/222:41:062
132902580,0sleep00-21swapper/022:27:580
287512570,0sleep328758-21kthreadcore20:40:193
13772570,1sleep21384-21kthreadcore19:20:172
114802570,0sleep00-21swapper/000:35:040
105252570,0sleep10-21swapper/122:25:441
186102560,0sleep10-21swapper/120:05:171
56732540,0sleep30-21swapper/323:06:113
263462540,0sleep00-21swapper/023:45:120
165782540,0sleep10-21swapper/100:21:511
114412540,0sleep20-21swapper/222:13:182
97432530,0sleep30-21swapper/322:11:553
206312530,1sleep320633-21kthreadcore20:35:183
309502510,0sleep30-21swapper/320:45:113
184723228,3sleep30-21swapper/320:18:213
1824299280,27cyclictest0-21swapper/122:21:301
1824299280,27cyclictest0-21swapper/121:28:171
1824699270,26cyclictest0-21swapper/223:57:212
1824299270,26cyclictest0-21swapper/123:56:261
1824299270,26cyclictest0-21swapper/123:50:271
1824299270,26cyclictest0-21swapper/123:31:201
1824299270,26cyclictest0-21swapper/123:22:131
1824299270,26cyclictest0-21swapper/122:43:401
1824299270,26cyclictest0-21swapper/122:10:071
1824299270,26cyclictest0-21swapper/122:05:421
1824299270,26cyclictest0-21swapper/122:01:071
1824299270,26cyclictest0-21swapper/121:56:511
1824299270,26cyclictest0-21swapper/121:51:031
1824299270,26cyclictest0-21swapper/121:49:151
1824299270,26cyclictest0-21swapper/121:42:421
1824299270,26cyclictest0-21swapper/121:37:451
1824299270,26cyclictest0-21swapper/121:09:531
1824299270,26cyclictest0-21swapper/120:55:291
1824299270,26cyclictest0-21swapper/120:51:381
1824299270,26cyclictest0-21swapper/120:37:141
1824299270,26cyclictest0-21swapper/120:17:561
1824299270,26cyclictest0-21swapper/120:13:301
1824299270,26cyclictest0-21swapper/120:01:021
1824299270,26cyclictest0-21swapper/119:58:591
1824299270,26cyclictest0-21swapper/119:47:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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