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2025-12-02 - 14:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Tue Dec 02, 2025 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2961321140,0sleep029599-21munin-run20:50:000
6262211363,8sleep10-21swapper/119:08:011
63632110101,6sleep30-21swapper/319:09:193
63332110100,7sleep00-21swapper/019:08:560
6216210898,7sleep20-21swapper/219:07:262
212872730,0sleep30-21swapper/320:15:143
137712700,1sleep20-21swapper/222:35:482
233962640,1sleep023402-21kthreadcore20:15:190
71092610,1sleep07114-21gltestperf23:05:190
253012550,4sleep0657499cyclictest23:44:320
137262530,0sleep00-21swapper/023:54:530
658299280,27cyclictest0-21swapper/221:35:112
658299273,23cyclictest0-21swapper/200:33:172
658299270,26cyclictest0-21swapper/222:40:012
658299270,26cyclictest0-21swapper/222:12:092
658299270,26cyclictest0-21swapper/221:54:302
658299270,26cyclictest0-21swapper/219:23:472
658299260,25cyclictest0-21swapper/223:33:442
658299260,25cyclictest0-21swapper/223:05:012
658299260,25cyclictest0-21swapper/222:27:312
658299260,25cyclictest0-21swapper/221:25:542
658299260,25cyclictest0-21swapper/200:05:262
658299260,24cyclictest30725-21ssh00:18:352
6582992522,3cyclictest0-21swapper/220:23:582
658299250,24cyclictest0-21swapper/223:00:382
658299250,24cyclictest0-21swapper/221:31:102
658299250,24cyclictest0-21swapper/200:35:122
658299250,23cyclictest0-21swapper/223:50:552
658299240,18cyclictest0-21swapper/200:10:522
658299237,14cyclictest0-21swapper/223:25:102
658299232,20cyclictest0-21swapper/223:56:372
658299232,20cyclictest0-21swapper/223:11:572
658299232,20cyclictest0-21swapper/221:55:492
6582992315,6cyclictest0-21swapper/221:12:432
658299231,21cyclictest0-21swapper/219:18:352
658299230,22cyclictest0-21swapper/222:57:372
658299230,22cyclictest0-21swapper/222:22:002
658299230,22cyclictest0-21swapper/221:24:072
658299230,17cyclictest0-21swapper/223:45:232
658299230,17cyclictest0-21swapper/221:45:122
658299230,16cyclictest0-21swapper/222:15:032
58382230,1sleep30-21swapper/320:00:213
658299227,10cyclictest0-21swapper/219:35:142
658299222,19cyclictest0-21swapper/222:30:452
658299222,19cyclictest0-21swapper/221:40:242
6582992219,3cyclictest0-21swapper/219:12:532
6582992215,6cyclictest0-21swapper/221:16:112
658299220,21cyclictest0-21swapper/223:35:542
658299220,21cyclictest0-21swapper/223:20:322
658299220,21cyclictest0-21swapper/223:17:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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