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2025-08-22 - 00:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Thu Aug 21, 2025 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11664212263,6sleep20-21swapper/207:08:562
114662111101,7sleep30-21swapper/307:06:213
115652110101,6sleep00-21swapper/007:07:390
114222109100,6sleep10-21swapper/107:05:471
16822730,1sleep30-21swapper/309:12:573
314182560,0sleep20-21swapper/209:10:232
161512550,0sleep00-21swapper/011:22:440
15862550,0sleep30-21swapper/312:30:203
82372280,1sleep28243-21kthreadcore07:30:232
1191099280,27cyclictest0-21swapper/209:53:332
1191099280,27cyclictest0-21swapper/207:25:082
1190899280,27cyclictest0-21swapper/111:38:141
1191099270,26cyclictest0-21swapper/209:29:542
11908992723,3cyclictest0-21swapper/110:30:541
1190899270,26cyclictest0-21swapper/112:02:441
1190899270,26cyclictest0-21swapper/111:24:531
1190899270,26cyclictest0-21swapper/111:08:281
1190899270,26cyclictest0-21swapper/108:49:111
1190899270,26cyclictest0-21swapper/108:20:541
1190899270,26cyclictest0-21swapper/107:25:481
1190899270,26cyclictest0-21swapper/107:17:231
1190899270,26cyclictest0-21swapper/107:13:151
1190499270,26cyclictest0-21swapper/012:01:560
1190499270,26cyclictest0-21swapper/009:32:340
1190499270,26cyclictest0-21swapper/007:26:120
1191099260,25cyclictest0-21swapper/212:15:142
1191099260,25cyclictest0-21swapper/211:32:532
1191099260,25cyclictest0-21swapper/211:09:292
1191099260,25cyclictest0-21swapper/208:01:022
1190899260,26cyclictest0-21swapper/108:57:121
1190899260,25cyclictest0-21swapper/112:31:361
1190899260,25cyclictest0-21swapper/111:50:591
1190899260,25cyclictest0-21swapper/111:49:501
1190899260,25cyclictest0-21swapper/111:42:471
1190899260,25cyclictest0-21swapper/111:28:501
1190899260,25cyclictest0-21swapper/111:16:291
1190899260,25cyclictest0-21swapper/110:55:081
1190899260,25cyclictest0-21swapper/110:22:581
1190899260,25cyclictest0-21swapper/109:46:521
1190899260,25cyclictest0-21swapper/109:34:491
1190899260,25cyclictest0-21swapper/108:12:351
1190899260,25cyclictest0-21swapper/107:44:571
1190899260,25cyclictest0-21swapper/107:35:081
1190899260,25cyclictest0-21swapper/107:31:391
1190499260,25cyclictest0-21swapper/010:22:520
1191099250,24cyclictest0-21swapper/210:00:372
1190899250,24cyclictest0-21swapper/109:15:041
1190899250,24cyclictest0-21swapper/108:18:031
1190499250,24cyclictest0-21swapper/012:22:150
1190499250,24cyclictest0-21swapper/011:19:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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