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2025-06-17 - 02:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: ondemand
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack5slot4.osadl.org (updated Tue Jun 17, 2025 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21200216697,6sleep00-21swapper/019:08:180
21191214579,6sleep10-21swapper/119:08:101
21327212162,7sleep20-21swapper/219:09:562
21271210898,7sleep30-21swapper/319:09:123
311632650,0sleep30-21swapper/321:37:143
283392640,1sleep10-21swapper/123:45:181
105132640,1sleep3391ktimersoftd/322:15:193
200312620,0sleep00-21swapper/023:10:000
129992590,0sleep30-21swapper/323:54:223
134482580,0sleep30-21swapper/323:37:553
34282570,1sleep30-21swapper/323:15:413
248962570,0sleep024902-21kthreadcore20:30:180
41682560,0sleep10-21swapper/121:10:081
288322560,0sleep20-21swapper/223:13:512
201662560,0sleep010-21rcuc/021:31:180
47622550,0sleep30-21swapper/322:45:203
283782550,0sleep20-21swapper/221:51:472
2150899360,35cyclictest0-21swapper/220:00:132
2150399290,3cyclictest0-21swapper/120:55:121
21508992723,3cyclictest0-21swapper/219:27:302
2150399270,26cyclictest0-21swapper/122:19:231
2150399270,26cyclictest0-21swapper/121:25:521
2150399270,26cyclictest0-21swapper/120:39:461
2150399270,26cyclictest0-21swapper/120:03:221
2150399270,26cyclictest0-21swapper/100:34:121
2150399270,26cyclictest0-21swapper/100:20:061
2150399270,26cyclictest0-21swapper/100:14:481
2150899260,25cyclictest0-21swapper/222:43:112
2150899260,25cyclictest0-21swapper/222:35:362
2150899260,25cyclictest0-21swapper/222:09:532
2150899260,25cyclictest0-21swapper/220:51:342
2150899260,25cyclictest0-21swapper/219:42:342
2150399260,25cyclictest0-21swapper/120:44:311
2150399260,25cyclictest0-21swapper/119:36:481
2150399260,25cyclictest0-21swapper/119:12:331
21496992616,9cyclictest0-21swapper/023:14:590
2149699260,25cyclictest0-21swapper/023:26:200
2149699260,25cyclictest0-21swapper/019:52:180
2150399250,24cyclictest0-21swapper/121:54:451
2150399250,24cyclictest0-21swapper/121:00:101
2150399250,24cyclictest0-21swapper/100:08:571
2149699250,24cyclictest0-21swapper/022:31:460
2149699250,19cyclictest18563-21munin-run20:55:000
21508992423,1cyclictest0-21swapper/220:13:362
21508992420,3cyclictest0-21swapper/223:53:522
21508992411,12cyclictest0-21swapper/219:15:122
2150899240,18cyclictest0-21swapper/222:16:302
2150899240,18cyclictest0-21swapper/200:00:262
2150399240,23cyclictest0-21swapper/123:02:201
2150399240,23cyclictest0-21swapper/122:52:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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