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2026-08-21 - 18:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Aug 21, 2026 13:02:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1227499231218,8cyclictest1367-21dbus-daemon09:35:1837
1227499231218,8cyclictest1367-21dbus-daemon09:35:1737
1229999221213,4cyclictest2466-21CPU21
1229999221213,4cyclictest2466-21CPU21
1229999221213,4cyclictest2466-21CPU21
1227499208181,12cyclictest3541-21CPU37
1227499208181,12cyclictest3541-21CPU37
1229999206200,4cyclictest0-21swapper/2810:26:0521
1229999206200,4cyclictest0-21swapper/2810:26:0521
1229999206200,4cyclictest0-21swapper/2810:26:0421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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