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2026-09-02 - 10:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Sep 02, 2026 01:01:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26255992331,228cyclictest0-21swapper/2122:59:2614
26255992331,228cyclictest0-21swapper/2122:59:2614
26255992311,221cyclictest0-21swapper/2123:05:2914
26255992311,221cyclictest0-21swapper/2123:05:2814
26255992291,220cyclictest0-21swapper/2100:35:1914
26255992291,220cyclictest0-21swapper/2100:35:1814
26255992291,220cyclictest0-21swapper/2100:35:1814
26255992272,220cyclictest2466-21CPU14
26255992272,220cyclictest2466-21CPU14
26255992271,214cyclictest0-21swapper/2100:32:2514
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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