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2026-07-28 - 11:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Jul 28, 2026 01:01:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31371992191,209cyclictest0-21swapper/3121:30:2125
31371992191,209cyclictest0-21swapper/3121:30:2125
3136799219215,2cyclictest0-21swapper/2821:25:1621
3136799219215,2cyclictest0-21swapper/2821:25:1621
3136999216209,3cyclictest4408-21CPU22
3136999216209,3cyclictest4408-21CPU22
3136999216209,3cyclictest4408-21CPU22
3136999216205,8cyclictest12951-21sshd00:14:1622
3136999216205,8cyclictest12951-21sshd00:14:1622
3133999214204,5cyclictest0-21swapper/321:40:4723
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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