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2025-12-05 - 22:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Dec 05, 2025 13:01:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
356799290252,14cyclictest0-21swapper/3809:10:1532
356799290252,14cyclictest0-21swapper/3809:10:1532
356799290252,14cyclictest0-21swapper/3809:10:1532
356799237216,9cyclictest0-21swapper/3812:25:2032
356799237216,9cyclictest0-21swapper/3812:25:2032
356799237216,9cyclictest0-21swapper/3812:25:2032
356799237205,15cyclictest0-21swapper/3811:15:1932
356799237205,15cyclictest0-21swapper/3811:15:1932
356799225206,5cyclictest3078-21CPU32
356799225206,5cyclictest3078-21CPU32
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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