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2025-12-04 - 14:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Dec 04, 2025 13:01:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2328399278248,13cyclictest6717-21NetworkChangeNo12:10:1914
2328399278248,13cyclictest6717-21NetworkChangeNo12:10:1914
2328399278248,13cyclictest6717-21NetworkChangeNo12:10:1914
2327299268240,13cyclictest34380-21inotify_reader09:55:185
2327299268240,13cyclictest34380-21inotify_reader09:55:185
2327299268240,13cyclictest34380-21inotify_reader09:55:185
2327299263240,11cyclictest0-21swapper/1311:40:195
2327299263240,11cyclictest0-21swapper/1311:40:195
2328499261254,4cyclictest15978-21CPU15
2328499261254,4cyclictest15978-21CPU15
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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