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2025-11-22 - 02:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Nov 22, 2025 01:00:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2488299300296,2cyclictest0-21swapper/1900:17:1811
2488299300296,2cyclictest0-21swapper/1900:17:1811
2488299253215,26cyclictest23380-21inotify_reader20:50:1811
2488299253215,26cyclictest23380-21inotify_reader20:50:1811
2488299242227,4cyclictest0-21swapper/1923:30:1911
2488299242227,4cyclictest0-21swapper/1923:30:1911
2488299242209,14cyclictest0-21swapper/1919:40:2211
2488299235206,15cyclictest21436-21TaskSchedulerSi23:55:1611
2488299235206,15cyclictest21436-21TaskSchedulerSi23:55:1611
2488299235206,15cyclictest21436-21TaskSchedulerSi23:55:1611
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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