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2026-08-17 - 22:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Aug 17, 2026 13:02:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3724199200193,5cyclictest0-21swapper/911:36:2339
3724199200193,5cyclictest0-21swapper/911:36:2239
3724199200191,5cyclictest2456-21CPU39
3724199200191,5cyclictest2456-21CPU39
3724199200191,5cyclictest2456-21CPU39
3724199196186,7cyclictest0-21swapper/911:02:0439
3724199196186,7cyclictest0-21swapper/911:02:0439
3723499194114,57cyclictest4408-21CPU34
3723499194114,57cyclictest4408-21CPU34
3724199193186,5cyclictest0-21swapper/909:30:2839
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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