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2026-02-18 - 11:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Feb 18, 2026 01:03:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2142799220207,8cyclictest2459-21CPU20
2142799220207,8cyclictest2459-21CPU20
2142499212203,7cyclictest0-21swapper/2422:40:1517
2142499212203,7cyclictest0-21swapper/2422:40:1417
2142499212203,7cyclictest0-21swapper/2422:40:1417
2142499209203,3cyclictest0-21swapper/2422:25:4217
2142499209203,3cyclictest0-21swapper/2422:25:4217
2140199205194,9cyclictest0-21swapper/421:47:5934
2140199205194,9cyclictest0-21swapper/421:47:5934
2140199205194,9cyclictest0-21swapper/421:47:5934
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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