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2026-01-27 - 01:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Jan 26, 2026 13:00:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
287299218214,2cyclictest0-21swapper/2907:25:0022
287299218214,2cyclictest0-21swapper/2907:25:0022
286999206202,2cyclictest0-21swapper/2610:15:2019
286999206202,2cyclictest0-21swapper/2610:15:2019
286999206202,2cyclictest0-21swapper/2610:15:2019
285499204193,4cyclictest0-21swapper/1409:19:346
285499204193,4cyclictest0-21swapper/1409:19:346
283999196192,2cyclictest12524-21kworker/u81:2-writeback07:19:5812
283999196192,2cyclictest12524-21kworker/u81:2-writeback07:19:5812
286899193181,10cyclictest0-21swapper/2508:40:0518
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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