You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-20 - 00:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Feb 19, 2026 13:03:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2025999240216,17cyclictest0-21swapper/2512:20:1818
2025999240216,17cyclictest0-21swapper/2512:20:1718
2025999227207,9cyclictest0-21swapper/2511:05:1918
2025999227207,9cyclictest0-21swapper/2511:05:1918
2025999215209,4cyclictest0-21swapper/2508:50:1518
2025999215209,4cyclictest0-21swapper/2508:50:1418
2025999214204,6cyclictest3610-21CPU18
2025999214204,6cyclictest3610-21CPU18
2025999213206,5cyclictest0-21swapper/2509:25:3418
2025999213206,5cyclictest0-21swapper/2509:25:3318
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional