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2026-03-20 - 17:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Mar 20, 2026 13:02:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1864399218203,10cyclictest0-21swapper/3710:40:1131
1864399218203,10cyclictest0-21swapper/3710:40:1131
1864399218203,10cyclictest0-21swapper/3710:40:1131
1864599216210,4cyclictest0-21swapper/3908:15:0133
1864599216210,4cyclictest0-21swapper/3908:15:0033
1864599216210,4cyclictest0-21swapper/3908:15:0033
1864599205199,4cyclictest17483-21nfsd09:15:5733
1864599205199,4cyclictest17483-21nfsd09:15:5633
1864599204198,4cyclictest0-21swapper/3911:25:2933
1864599204198,4cyclictest0-21swapper/3911:25:2933
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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