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2025-12-18 - 14:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Dec 18, 2025 12:59:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3426499229190,17cyclictest0-21swapper/2312:01:2616
3426499229190,17cyclictest0-21swapper/2312:01:2616
3424299226180,43cyclictest3544-21CPU35
3424299226180,43cyclictest3544-21CPU35
3425799204188,10cyclictest0-21swapper/1712:07:179
3425799204188,10cyclictest0-21swapper/1712:07:179
3425499204193,9cyclictest4410-21qemu-system-x8610:02:156
3425499204193,9cyclictest4410-21qemu-system-x8610:02:146
3424299198193,2cyclictest0-21swapper/511:20:0735
3424299198193,2cyclictest0-21swapper/511:20:0635
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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