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2026-07-24 - 15:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jul 24, 2026 13:02:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20541992501,245cyclictest0-21swapper/009:40:230
20541992501,245cyclictest0-21swapper/009:40:230
20541992501,245cyclictest0-21swapper/009:40:020
20541992501,245cyclictest0-21swapper/009:40:020
20541992481,243cyclictest4398-21qemu-system-x8612:03:260
20541992481,243cyclictest4398-21qemu-system-x8612:03:250
20541992461,242cyclictest0-21swapper/011:20:200
20541992461,242cyclictest0-21swapper/011:20:200
20541992461,242cyclictest0-21swapper/011:20:200
20541992431,239cyclictest0-21swapper/012:20:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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