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2025-06-29 - 01:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Jun 28, 2025 13:02:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3857899272252,9cyclictest0-21swapper/3410:20:2128
3857899272252,9cyclictest0-21swapper/3410:20:2128
3857899272252,9cyclictest0-21swapper/3410:20:2128
3857899261258,2cyclictest0-21swapper/3409:54:1728
3857899261258,2cyclictest0-21swapper/3409:54:1728
3857899261258,2cyclictest0-21swapper/3409:54:1728
3857899226212,3cyclictest0-21swapper/3410:35:2328
3857899226212,3cyclictest0-21swapper/3410:35:2328
3857899226212,3cyclictest0-21swapper/3410:35:2228
38542992172,5cyclictest15983-21CPU23
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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