You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-09-21 - 17:53
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Sep 21, 2026 13:02:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2495899227208,11cyclictest0-21swapper/3311:10:2627
2495899227208,11cyclictest0-21swapper/3311:10:2627
2495899216209,5cyclictest0-21swapper/3312:10:1627
2495899216209,5cyclictest0-21swapper/3312:10:1627
2495899216209,5cyclictest0-21swapper/3312:10:1627
2495899214207,5cyclictest0-21swapper/3312:33:5327
2495899214207,5cyclictest0-21swapper/3312:33:5327
2495899214205,7cyclictest0-21swapper/3309:40:5927
2495899214205,7cyclictest0-21swapper/3309:40:5927
2495899214195,9cyclictest5079-2110-uname10:25:1627
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional