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2026-09-22 - 09:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Sep 22, 2026 01:01:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
509299217199,12cyclictest0-21swapper/3322:20:1327
509299217199,12cyclictest0-21swapper/3322:20:1327
509299217189,15cyclictest0-21swapper/3321:55:2027
509299217189,15cyclictest0-21swapper/3321:55:2027
509299215183,21cyclictest0-21swapper/3300:30:1927
509299215183,21cyclictest0-21swapper/3300:30:1927
509299212191,14cyclictest755-21systemd-journal00:27:0127
509299212191,14cyclictest755-21systemd-journal00:27:0027
509299212191,14cyclictest755-21systemd-journal00:27:0027
509299211183,22cyclictest2454-21CPU27
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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