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2026-07-06 - 02:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Jul 06, 2026 01:02:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2371699193132,53cyclictest0-21swapper/323:00:5123
2371699193132,53cyclictest0-21swapper/323:00:5023
2372199184173,9cyclictest0-21swapper/722:34:0537
2372199184173,9cyclictest0-21swapper/722:34:0437
2372199184173,9cyclictest0-21swapper/722:34:0437
2374699182173,6cyclictest0-21swapper/2721:20:3620
2374699182173,6cyclictest0-21swapper/2721:20:3520
23714991829,2cyclictest0-21swapper/121:00:201
23714991829,2cyclictest0-21swapper/121:00:191
23714991829,2cyclictest0-21swapper/121:00:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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