You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-25 - 11:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Jan 25, 2026 01:00:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
946199198158,29cyclictest0-21swapper/3200:31:5226
946199198158,29cyclictest0-21swapper/3200:31:5226
945999198190,6cyclictest0-21swapper/3123:19:0325
945999198190,6cyclictest0-21swapper/3123:19:0325
942699192185,5cyclictest0-21swapper/321:46:3223
942699192185,5cyclictest0-21swapper/321:46:3223
943599189135,46cyclictest0-21swapper/1100:32:103
943599189135,46cyclictest0-21swapper/1100:32:103
945999183169,12cyclictest0-21swapper/3123:24:5525
945999183169,12cyclictest0-21swapper/3123:24:5525
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional