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2026-01-16 - 07:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jan 16, 2026 01:00:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3473299214197,10cyclictest0-21swapper/3822:02:0732
3473299214197,10cyclictest0-21swapper/3822:02:0732
3472699212203,6cyclictest0-21swapper/3400:08:2528
3472699212203,6cyclictest0-21swapper/3400:08:2528
3472699211195,9cyclictest171rcu_preempt23:26:3828
3472699211195,9cyclictest171rcu_preempt23:26:3828
3469099208203,3cyclictest0-21swapper/419:45:1534
3469099208203,3cyclictest0-21swapper/419:45:1534
3473399206191,9cyclictest0-21swapper/3921:49:5033
3473399206191,9cyclictest0-21swapper/3921:49:5033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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