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2026-04-26 - 02:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Apr 26, 2026 01:02:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1918499208136,61cyclictest2447-21CPU20
1918299196178,15cyclictest0-21swapper/2500:08:4418
1918299196178,15cyclictest0-21swapper/2500:08:4418
1918299196178,15cyclictest0-21swapper/2500:08:4418
1916799192163,23cyclictest2456-21CPU4
1916799192163,23cyclictest2456-21CPU4
1915799190181,7cyclictest0-21swapper/322:24:1323
1915799190181,7cyclictest0-21swapper/322:24:1223
1918499189169,18cyclictest0-21swapper/2722:14:0620
1918499189169,18cyclictest0-21swapper/2722:14:0620
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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