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2026-02-25 - 00:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Feb 24, 2026 13:03:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1350599219200,17cyclictest0-21swapper/712:25:0037
1350599219200,17cyclictest0-21swapper/712:24:5937
13509992183,81cyclictest37354-21CPU2
13509992183,81cyclictest37354-21CPU2
1350399215202,7cyclictest3548-21CPU36
1350399215202,7cyclictest3548-21CPU36
1350399215202,7cyclictest3548-21CPU36
1350399213193,14cyclictest3548-21CPU36
1350399213193,14cyclictest3548-21CPU36
1350399213193,14cyclictest3548-21CPU36
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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