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2025-12-16 - 20:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Dec 16, 2025 13:00:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4060399236228,4cyclictest2462-21CPU36
4060399236228,4cyclictest2462-21CPU36
4060899219210,6cyclictest0-21swapper/1112:08:453
4060899219210,6cyclictest0-21swapper/1112:08:453
4060899219210,6cyclictest0-21swapper/1112:08:443
4060899217204,10cyclictest29296-21uname12:05:023
4060899217204,10cyclictest29296-21uname12:05:023
4060899217204,10cyclictest29296-21uname12:05:023
40620992031,32cyclictest0-21swapper/2007:25:1613
40620992031,32cyclictest0-21swapper/2007:25:1513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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