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2026-08-14 - 01:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Aug 13, 2026 13:02:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21861992931,2cyclictest0-21swapper/1309:35:125
21861992931,2cyclictest0-21swapper/1309:35:125
21861992652,256cyclictest37270-21CPU5
21861992652,256cyclictest37270-21CPU5
21861992652,256cyclictest37270-21CPU5
21861992641,2cyclictest0-21swapper/1310:05:145
21861992641,2cyclictest0-21swapper/1310:05:145
21861992481,241cyclictest0-21swapper/1309:55:255
21861992481,241cyclictest0-21swapper/1309:55:255
21861992481,241cyclictest0-21swapper/1309:55:245
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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