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2026-04-19 - 03:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Apr 19, 2026 01:01:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
328899207112,91cyclictest37267-21CPU13
328899207112,91cyclictest37267-21CPU13
327199200139,55cyclictest0-21swapper/521:14:3435
327199200139,55cyclictest0-21swapper/521:14:3435
327199200139,55cyclictest0-21swapper/521:14:3435
327299198188,6cyclictest0-21swapper/622:01:5936
327299198188,6cyclictest0-21swapper/622:01:5936
328899197136,20cyclictest0-21swapper/2022:13:3013
328899197136,20cyclictest0-21swapper/2022:13:3013
328899197136,20cyclictest0-21swapper/2022:13:3013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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