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2026-06-29 - 06:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Jun 29, 2026 01:02:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2500299203138,59cyclictest37355-21CPU33
2500299203138,59cyclictest37355-21CPU33
2500299203138,59cyclictest37355-21CPU33
2495899202192,3cyclictest0-21swapper/223:46:2212
2495899202192,3cyclictest0-21swapper/223:46:2212
2499899201198,2cyclictest0-21swapper/3522:50:2229
2499899201198,2cyclictest0-21swapper/3522:50:2229
2497899196127,61cyclictest37356-21CPU11
2497899196127,61cyclictest37356-21CPU11
24999991900,186cyclictest37346-21qemu-system-x8600:10:1730
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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