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2026-02-28 - 13:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 28, 2026 01:02:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
593599274261,11cyclictest373-21kswapd100:07:4825
593599274261,11cyclictest373-21kswapd100:07:4825
593599274261,11cyclictest373-21kswapd100:07:4825
593499270259,9cyclictest373-21kswapd100:07:4924
593499270259,9cyclictest373-21kswapd100:07:4924
593499270259,9cyclictest373-21kswapd100:07:4924
594099267262,4cyclictest373-21kswapd100:07:5028
594099267262,4cyclictest373-21kswapd100:07:5028
594099267262,4cyclictest373-21kswapd100:07:5028
594599260247,11cyclictest373-21kswapd100:07:5433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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