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2026-06-08 - 04:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Jun 08, 2026 01:01:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3887399226206,18cyclictest0-21swapper/321:55:0123
3887399226206,18cyclictest0-21swapper/321:55:0123
3890599201195,4cyclictest0-21swapper/3022:45:3224
3890599201195,4cyclictest0-21swapper/3022:45:3124
3890399199178,13cyclictest171rcu_preempt21:20:0021
3890399199178,13cyclictest171rcu_preempt21:20:0021
3890399199178,13cyclictest171rcu_preempt21:20:0021
3887499199193,4cyclictest0-21swapper/419:57:1734
3890399197188,5cyclictest37353-21CPU21
3890399197188,5cyclictest37353-21CPU21
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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