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2026-08-27 - 14:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Aug 27, 2026 13:02:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3321699229226,2cyclictest0-21swapper/2008:05:1813
3322699218189,14cyclictest0-21swapper/2910:22:0022
3322699218189,14cyclictest0-21swapper/2910:22:0022
3322699214204,8cyclictest0-21swapper/2910:51:2622
3322699214204,8cyclictest0-21swapper/2910:51:2622
3321799211183,10cyclictest171rcu_preempt12:01:1314
3321799211183,10cyclictest171rcu_preempt12:01:1314
3319399203169,30cyclictest0-21swapper/107:30:411
3319399203169,30cyclictest0-21swapper/107:30:411
3320099202166,21cyclictest0-21swapper/712:00:5137
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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