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2026-06-25 - 20:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Jun 25, 2026 13:03:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128299256233,7cyclictest0-21swapper/211:00:2012
128299256233,7cyclictest0-21swapper/211:00:1912
128299223215,6cyclictest0-21swapper/210:47:5312
128299223215,6cyclictest0-21swapper/210:47:5312
128299222210,9cyclictest1711-21sshd09:31:0012
128299222210,9cyclictest1711-21sshd09:31:0012
130299217186,18cyclictest0-21swapper/1608:20:468
130299217186,18cyclictest0-21swapper/1608:20:468
128299214207,3cyclictest37267-21CPU12
128299214207,3cyclictest37267-21CPU12
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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