You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-29 - 23:08
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Nov 29, 2025 13:01:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
871399245234,3cyclictest0-21swapper/1907:50:1911
871399245234,3cyclictest0-21swapper/1907:50:1911
871399245226,8cyclictest4911-21CPU11
871399245226,8cyclictest4911-21CPU11
871399245226,8cyclictest4911-21CPU11
871399245226,8cyclictest0-21swapper/1909:00:1911
871399245226,8cyclictest0-21swapper/1909:00:1911
8686992257,209cyclictest33518-21inotify_reader07:45:1838
8686992257,209cyclictest33518-21inotify_reader07:45:1838
878199223202,10cyclictest11726-21inotify_reader11:30:1933
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional