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2026-05-30 - 06:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat May 30, 2026 01:01:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1141199206189,10cyclictest0-21swapper/3222:57:4126
1141199206189,10cyclictest0-21swapper/3222:57:4026
1139999202198,2cyclictest0-21swapper/2100:08:5914
1139999202198,2cyclictest0-21swapper/2100:08:5914
1139999202198,2cyclictest0-21swapper/2100:08:5814
1141699199193,2cyclictest0-21swapper/3422:33:0528
1141699199193,2cyclictest0-21swapper/3422:33:0528
1141799197188,7cyclictest0-21swapper/3523:20:1329
1141799197188,7cyclictest0-21swapper/3523:20:1329
1140799196149,36cyclictest0-21swapper/2823:20:4421
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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