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2025-11-23 - 11:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Nov 23, 2025 01:01:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1941599268233,18cyclictest0-21swapper/3119:35:2725
1941599268233,18cyclictest0-21swapper/3119:35:2725
1941599264239,10cyclictest0-21swapper/3121:05:1925
1941599264239,10cyclictest0-21swapper/3121:05:1925
1941599264239,10cyclictest0-21swapper/3121:05:1925
1941599264233,13cyclictest31195-21NetworkChangeNo22:45:1925
1941599264233,13cyclictest31195-21NetworkChangeNo22:45:1925
193819924629,196cyclictest0-21swapper/219:20:2112
193819924629,196cyclictest0-21swapper/219:20:2112
1942399233224,7cyclictest0-21swapper/3623:15:3730
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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