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2026-05-28 - 20:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu May 28, 2026 13:02:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1863099201191,8cyclictest0-21swapper/1509:10:007
1863099201191,8cyclictest0-21swapper/1509:10:007
1864399184104,71cyclictest0-21swapper/2612:30:1519
1864399184104,71cyclictest0-21swapper/2612:30:1519
1864399184104,71cyclictest0-21swapper/2612:30:1419
1863799182149,14cyclictest0-21swapper/2112:36:0814
1863799182149,14cyclictest0-21swapper/2112:36:0714
1863799182149,14cyclictest0-21swapper/2112:36:0714
1862999181163,11cyclictest4410-21qemu-system-x8612:14:106
1862999181163,11cyclictest4410-21qemu-system-x8612:14:106
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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