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2026-06-11 - 08:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Jun 11, 2026 01:02:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40551992440,2cyclictest0-21swapper/3423:20:0128
40551992440,2cyclictest0-21swapper/3423:20:0128
40551992440,2cyclictest0-21swapper/3423:20:0128
40551992440,2cyclictest0-21swapper/3421:33:0228
40551992440,2cyclictest0-21swapper/3421:33:0228
40551992390,2cyclictest0-21swapper/3422:55:2028
40551992390,2cyclictest0-21swapper/3422:55:2028
40551992390,236cyclictest0-21swapper/3423:44:4028
40551992390,236cyclictest0-21swapper/3423:44:4028
40551992381,2cyclictest0-21swapper/3422:33:2228
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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