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2026-03-01 - 14:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Mar 01, 2026 13:03:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2989999224195,17cyclictest0-21swapper/1911:34:0211
2989999224195,17cyclictest0-21swapper/1911:34:0211
2988299216171,15cyclictest0-21swapper/511:12:4135
2988299216171,15cyclictest0-21swapper/511:12:4135
2989999207180,17cyclictest0-21swapper/1910:46:3711
2989999207180,17cyclictest0-21swapper/1910:46:3611
2989999203190,9cyclictest1748150nfsd11:27:0411
2989999203190,9cyclictest1748150nfsd11:27:0411
2989999203190,9cyclictest1748150nfsd11:27:0411
2991399200192,4cyclictest2462-21CPU26
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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