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2026-08-28 - 03:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Aug 28, 2026 01:01:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3084399235230,3cyclictest15054-21kworker/u81:2+events_unbound22:40:5218
3084399235230,3cyclictest15054-21kworker/u81:2+events_unbound22:40:5118
3081499213208,3cyclictest10860-21kworker/u81:5+events_unbound23:35:121
3081499213208,3cyclictest10860-21kworker/u81:5+events_unbound23:35:121
3081499213208,3cyclictest10860-21kworker/u81:5+events_unbound23:35:121
3082999212205,5cyclictest1-21systemd22:41:034
3082999212205,5cyclictest1-21systemd22:41:034
3082599210197,11cyclictest0-21swapper/1021:40:292
3082599210197,11cyclictest0-21swapper/1021:40:292
3082299209201,5cyclictest0-21swapper/800:16:3038
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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