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2026-02-24 - 00:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Feb 23, 2026 13:03:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2038099211168,38cyclictest3609-21CPU16
2038099211168,38cyclictest3609-21CPU16
2038099211168,38cyclictest3609-21CPU16
2039099206195,9cyclictest0-21swapper/3010:36:2624
2039099206195,9cyclictest0-21swapper/3010:36:2624
2039099206195,9cyclictest0-21swapper/3010:36:2624
20388992021,190cyclictest0-21swapper/2807:50:1921
20388992021,190cyclictest0-21swapper/2807:50:1921
2036299197136,58cyclictest0-21swapper/611:12:0236
2036299197136,58cyclictest0-21swapper/611:12:0236
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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