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2026-05-25 - 12:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon May 25, 2026 01:02:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3670399224212,9cyclictest2466-21CPU17
3670399224212,9cyclictest2466-21CPU17
3667299210126,51cyclictest4407-21CPU1
3667299210126,51cyclictest4407-21CPU1
3667299210126,51cyclictest4407-21CPU1
3671999208142,63cyclictest0-21swapper/3800:22:1332
3671999208142,63cyclictest0-21swapper/3800:22:1332
3671999207119,84cyclictest0-21swapper/3820:40:1532
3671999207119,84cyclictest0-21swapper/3820:40:1532
3671299207183,13cyclictest0-21swapper/3121:15:2525
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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