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2026-06-09 - 08:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Jun 09, 2026 01:00:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
418499233226,4cyclictest21860-21kworker/u81:4+events_unbound00:05:1336
418499233226,4cyclictest21860-21kworker/u81:4+events_unbound00:05:1336
419499204195,5cyclictest2454-21CPU5
419499204195,5cyclictest2454-21CPU5
420299203191,9cyclictest0-21swapper/2020:06:5513
4190991982,3cyclictest3541-21CPU39
4190991982,3cyclictest3541-21CPU39
420299195191,2cyclictest0-21swapper/2021:25:0113
420299195191,2cyclictest0-21swapper/2021:25:0013
421699194183,9cyclictest0-21swapper/3221:50:1626
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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