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2026-01-31 - 03:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Jan 31, 2026 01:00:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2647999220161,49cyclictest0-21swapper/3722:10:1431
2647999220161,49cyclictest0-21swapper/3722:10:1431
2645299200193,5cyclictest0-21swapper/1323:03:335
2645299200193,5cyclictest0-21swapper/1323:03:335
2644699195148,29cyclictest0-21swapper/800:14:4538
2644699195148,29cyclictest0-21swapper/800:14:4538
2644699195148,29cyclictest0-21swapper/800:14:4538
2643899192150,27cyclictest0-21swapper/100:07:351
2643899192150,27cyclictest0-21swapper/100:07:341
2644799190176,12cyclictest0-21swapper/919:50:2439
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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