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2026-01-11 - 04:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Jan 11, 2026 01:00:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1530499227199,18cyclictest0-21swapper/300:30:3023
1530499227199,18cyclictest0-21swapper/300:30:2923
1530799222205,14cyclictest0-21swapper/522:26:2135
1530799222205,14cyclictest0-21swapper/522:26:2035
1530799222205,14cyclictest0-21swapper/522:26:2035
1530499212189,17cyclictest0-21swapper/322:32:5723
1530499212189,17cyclictest0-21swapper/322:32:5723
1530499212182,19cyclictest0-21swapper/323:16:5923
1530499212182,19cyclictest0-21swapper/323:16:5923
1530799205196,7cyclictest0-21swapper/521:28:3135
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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