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2026-05-03 - 20:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun May 03, 2026 13:03:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1421199217193,22cyclictest0-21swapper/2012:09:3613
1421199217193,22cyclictest0-21swapper/2012:09:3513
1418899202192,8cyclictest0-21swapper/111:27:501
1418899202192,8cyclictest0-21swapper/111:27:501
1418899202192,8cyclictest0-21swapper/111:27:501
1419099199184,8cyclictest34820-21kworker/u81:5-events_unbound11:37:0423
1419099199184,8cyclictest34820-21kworker/u81:5-events_unbound11:37:0423
1418899197160,20cyclictest37352-21CPU1
1418899197160,20cyclictest37352-21CPU1
1421399193172,16cyclictest0-21swapper/2211:31:3415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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