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2025-10-13 - 21:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Oct 13, 2025 13:02:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
97909925156,105cyclictest0-21swapper/1507:45:167
97909925156,105cyclictest0-21swapper/1507:45:167
980299245226,9cyclictest777-21sshd12:05:1916
980299245226,9cyclictest777-21sshd12:05:1916
980299245226,9cyclictest777-21sshd12:05:1916
9805992077,171cyclictest11903-21CPU19
9805992077,171cyclictest11903-21CPU19
980299207170,18cyclictest25773-21inotify_reader10:35:2016
980299207170,18cyclictest25773-21inotify_reader10:35:2016
980299207170,18cyclictest25773-21inotify_reader10:35:2016
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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