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2026-06-10 - 20:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Jun 10, 2026 13:01:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1913992541,249cyclictest0-21swapper/2411:20:1217
1913992541,249cyclictest0-21swapper/2411:20:1217
1913992532,246cyclictest3609-21CPU17
1913992532,246cyclictest3609-21CPU17
1913992521,246cyclictest1021-21sshd10:20:1917
1913992521,246cyclictest1021-21sshd10:20:1917
1913992451,241cyclictest0-21swapper/2410:40:2017
1913992451,241cyclictest0-21swapper/2410:40:2017
1913992451,241cyclictest0-21swapper/2410:40:2017
1913992431,2cyclictest0-21swapper/2410:16:0117
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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