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2026-08-07 - 01:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Aug 06, 2026 13:02:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
10569992311,225cyclictest0-21swapper/3810:15:1832
10569992311,225cyclictest0-21swapper/3810:15:1732
10569992311,225cyclictest0-21swapper/3810:15:1732
105539921183,111cyclictest0-21swapper/2409:30:2017
105539921183,111cyclictest0-21swapper/2409:30:2017
1052799208200,5cyclictest0-21swapper/309:10:1523
1052799208200,5cyclictest0-21swapper/309:10:1523
1052799208200,5cyclictest0-21swapper/309:10:1423
1052799204194,8cyclictest0-21swapper/309:55:2523
1052799204194,8cyclictest0-21swapper/309:55:2423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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