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2026-03-09 - 22:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Mar 09, 2026 13:02:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
681999234229,3cyclictest0-21swapper/2411:30:1717
681999234229,3cyclictest0-21swapper/2411:30:1717
682399230224,3cyclictest0-21swapper/2810:20:1921
682399230224,3cyclictest0-21swapper/2810:20:1921
682399230224,3cyclictest0-21swapper/2810:20:1921
682099227211,11cyclictest0-21swapper/2512:00:1518
682099227211,11cyclictest0-21swapper/2512:00:1418
682099224215,5cyclictest3610-21CPU18
682099224215,5cyclictest3610-21CPU18
679799223217,4cyclictest0-21swapper/509:00:0435
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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