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2026-01-08 - 19:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Jan 08, 2026 13:00:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3878599216200,14cyclictest0-21swapper/011:15:440
3878599216200,14cyclictest0-21swapper/011:15:440
3883099198144,26cyclictest0-21swapper/3811:58:4332
3883099198144,26cyclictest0-21swapper/3811:58:4332
3879599194189,3cyclictest0-21swapper/709:41:3337
3879599194189,3cyclictest0-21swapper/709:41:3337
3879399187178,4cyclictest0-21swapper/612:26:1636
3879399187178,4cyclictest0-21swapper/612:26:1636
3879099185143,39cyclictest0-21swapper/411:07:2834
3879099185143,39cyclictest0-21swapper/411:07:2734
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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