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2026-01-23 - 13:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa >
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jan 23, 2026 01:00:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2517099239210,25cyclictest2447-21CPU12
2517099239210,25cyclictest2447-21CPU12
2517799222216,2cyclictest0-21swapper/919:20:2139
2517799222216,2cyclictest0-21swapper/919:20:2139
2516899211201,8cyclictest0-21swapper/122:31:261
2516899211201,8cyclictest0-21swapper/122:31:261
2516899211201,8cyclictest0-21swapper/122:31:261
2519899208203,4cyclictest0-21swapper/2623:05:4019
2519899208203,4cyclictest0-21swapper/2623:05:4019
2519899208203,4cyclictest0-21swapper/2623:05:3919
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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