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2026-09-06 - 03:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Sep 06, 2026 01:02:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3115999237225,10cyclictest0-21swapper/3322:26:1127
3115999237225,10cyclictest0-21swapper/3322:26:1127
3115999237225,10cyclictest0-21swapper/3322:26:1127
3112899232220,6cyclictest0-21swapper/500:20:5135
3112899232220,6cyclictest0-21swapper/500:20:5035
3112899232210,15cyclictest0-21swapper/521:30:1935
3112899232210,15cyclictest0-21swapper/521:30:1935
3112899232210,15cyclictest0-21swapper/521:30:1935
3112899230219,8cyclictest0-21swapper/523:25:1535
3112899230219,8cyclictest0-21swapper/523:25:1535
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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