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2026-07-20 - 09:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Jul 20, 2026 01:01:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11786992461,241cyclictest0-21swapper/921:36:2739
11786992461,241cyclictest0-21swapper/921:36:2739
11786992451,2cyclictest0-21swapper/900:10:3939
11786992451,2cyclictest0-21swapper/900:10:3939
11786992444,237cyclictest1-21systemd00:27:3239
11786992444,237cyclictest1-21systemd00:27:3239
11786992444,237cyclictest1-21systemd00:27:3239
11786992441,4cyclictest0-21swapper/922:19:2139
11786992441,4cyclictest0-21swapper/922:19:2039
11786992421,237cyclictest0-21swapper/920:40:1439
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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