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2025-09-13 - 18:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Sep 13, 2025 13:02:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3501199218189,18cyclictest0-21swapper/509:54:4635
3501199218189,18cyclictest0-21swapper/509:54:4635
35005992137,193cyclictest39576-21sshd12:35:211
35005992137,193cyclictest39576-21sshd12:35:201
35005992137,193cyclictest39576-21sshd12:35:201
35005992125,201cyclictest0-21swapper/107:45:201
35005992125,201cyclictest0-21swapper/107:45:201
35036992111,203cyclictest0-21swapper/2612:20:2019
35036992111,203cyclictest0-21swapper/2612:20:1919
35036992111,203cyclictest0-21swapper/2612:20:1919
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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