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2026-04-18 - 08:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Apr 18, 2026 01:01:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
166499232225,5cyclictest0-21swapper/223:02:4412
166499232225,5cyclictest0-21swapper/223:02:4312
166799229215,9cyclictest0-21swapper/523:39:5935
166799229215,9cyclictest0-21swapper/523:39:5935
166599227221,4cyclictest0-21swapper/323:05:2823
166599227221,4cyclictest0-21swapper/323:05:2823
168299223207,8cyclictest0-21swapper/2022:29:2313
168299223207,8cyclictest0-21swapper/2022:29:2313
168299223207,8cyclictest0-21swapper/2022:29:2213
168799221208,6cyclictest0-21swapper/2523:10:0118
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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