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2026-08-30 - 18:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Aug 30, 2026 13:02:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1203199237231,3cyclictest0-21swapper/3110:25:0125
1203199237231,3cyclictest0-21swapper/3110:25:0125
1203199237231,3cyclictest0-21swapper/3110:25:0025
1203799225209,12cyclictest0-21swapper/3711:35:1331
1203799225209,12cyclictest0-21swapper/3711:35:1331
1203799225209,12cyclictest0-21swapper/3711:35:1231
1200299225207,8cyclictest0-21swapper/810:42:5038
1200299225207,8cyclictest0-21swapper/810:42:5038
1200299225207,8cyclictest0-21swapper/810:42:5038
1199399225205,17cyclictest0-21swapper/012:04:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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