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2026-06-05 - 13:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jun 05, 2026 01:01:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2308499230216,10cyclictest0-21swapper/223:55:0012
2308499230216,10cyclictest0-21swapper/223:55:0012
2308499219211,6cyclictest0-21swapper/200:37:2912
2308499219211,6cyclictest0-21swapper/200:37:2812
2308499213206,5cyclictest0-21swapper/200:00:4612
2308499213206,5cyclictest0-21swapper/200:00:4612
230909921117,191cyclictest0-21swapper/721:35:4837
230909921117,191cyclictest0-21swapper/721:35:4837
2309199208200,5cyclictest0-21swapper/822:48:4938
2309199208200,5cyclictest0-21swapper/822:48:4938
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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