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2026-01-26 - 00:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Jan 25, 2026 13:00:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1998799224215,5cyclictest3545-21CPU33
1998799224215,5cyclictest3545-21CPU33
1998799221214,5cyclictest0-21swapper/3909:20:2133
1998799221214,5cyclictest0-21swapper/3909:20:2133
1998799220211,6cyclictest0-21swapper/3911:15:0133
1998799220211,6cyclictest0-21swapper/3911:15:0133
1998799218207,8cyclictest0-21swapper/3911:36:0233
1998799218207,8cyclictest0-21swapper/3911:36:0233
1998799218207,8cyclictest0-21swapper/3911:36:0233
1998799216209,5cyclictest0-21swapper/3909:57:4433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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