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2026-01-10 - 05:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Jan 10, 2026 01:00:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3949099383375,6cyclictest372-21kswapd022:20:1023
3949099383375,6cyclictest372-21kswapd022:20:1023
3949299366333,25cyclictest372-21kswapd000:10:0635
3949299366333,25cyclictest372-21kswapd000:10:0635
3949299366333,25cyclictest372-21kswapd000:10:0635
3952199347322,17cyclictest372-21kswapd000:05:2221
3952199347322,17cyclictest372-21kswapd000:05:2221
3952199347322,17cyclictest372-21kswapd000:05:2221
3952199347322,17cyclictest372-21kswapd000:05:2221
3952099340336,3cyclictest372-21kswapd023:34:1920
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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