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2026-08-08 - 16:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Aug 08, 2026 13:02:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2123699227223,2cyclictest0-21swapper/2512:20:1418
2123699227223,2cyclictest0-21swapper/2512:20:1418
2123699227223,2cyclictest0-21swapper/2512:20:1418
2124399212198,11cyclictest3544-21CPU26
2124399212198,11cyclictest3544-21CPU26
2121599205151,48cyclictest3610-21CPU37
2121599205151,48cyclictest3610-21CPU37
2121599205151,48cyclictest3610-21CPU37
2120999202192,8cyclictest0-21swapper/111:52:141
2120999202192,8cyclictest0-21swapper/111:52:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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