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2026-02-28 - 00:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Feb 27, 2026 13:03:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2974199219203,12cyclictest0-21swapper/3410:04:0428
2974199219203,12cyclictest0-21swapper/3410:04:0328
2972599218210,5cyclictest0-21swapper/2110:59:5814
2972599218210,5cyclictest0-21swapper/2110:59:5814
2972299217211,4cyclictest0-21swapper/1807:55:2010
2970799216213,2cyclictest0-21swapper/507:55:2835
2973899215208,4cyclictest0-21swapper/3112:16:3825
2973899215208,4cyclictest0-21swapper/3112:16:3825
2972599215201,11cyclictest0-21swapper/2112:39:5914
2972599215201,11cyclictest0-21swapper/2112:39:5914
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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