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2026-09-07 - 04:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Sep 07, 2026 01:02:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38822992641,256cyclictest0-21swapper/3600:25:2230
38822992641,256cyclictest0-21swapper/3600:25:2230
38822992641,256cyclictest0-21swapper/3600:25:2230
38822992601,4cyclictest17483-21nfsd23:35:2230
38822992601,4cyclictest17483-21nfsd23:35:2230
38822992590,4cyclictest17723-21sshd22:10:2330
38822992590,4cyclictest17723-21sshd22:10:2330
38822992561,241cyclictest0-21swapper/3622:30:2130
38822992561,241cyclictest0-21swapper/3622:30:2130
38822992531,246cyclictest0-21swapper/3621:45:2030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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