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2026-01-01 - 11:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Jan 01, 2026 01:00:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
298999207158,46cyclictest0-21swapper/3623:31:4930
298999207158,46cyclictest0-21swapper/3623:31:4930
295199190179,4cyclictest0-21swapper/420:25:0434
296999189127,51cyclictest4407-21CPU13
296999189127,51cyclictest4407-21CPU13
296999189127,51cyclictest4407-21CPU13
294799188164,11cyclictest0-21swapper/022:53:140
294799188164,11cyclictest0-21swapper/022:53:140
294799181170,9cyclictest0-21swapper/000:01:540
294799181170,9cyclictest0-21swapper/000:01:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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