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2026-06-28 - 04:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Jun 28, 2026 01:02:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
688999225217,5cyclictest0-21swapper/2622:00:1919
688999225217,5cyclictest0-21swapper/2622:00:1819
688999218197,11cyclictest0-21swapper/2623:32:0319
688999218197,11cyclictest0-21swapper/2623:32:0319
688999213199,11cyclictest0-21swapper/2622:05:2819
688999213199,11cyclictest0-21swapper/2622:05:2819
688999213199,11cyclictest0-21swapper/2622:05:2819
686099213206,5cyclictest0-21swapper/322:40:2723
686099213206,5cyclictest0-21swapper/322:40:2623
686099213206,5cyclictest0-21swapper/322:40:2623
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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