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2026-06-18 - 04:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Jun 18, 2026 01:02:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2547199227185,28cyclictest0-21swapper/2721:15:1420
2547199227185,28cyclictest0-21swapper/2721:15:1420
2548199225220,3cyclictest0-21swapper/3622:05:1430
2548199225220,3cyclictest0-21swapper/3622:05:1430
2548199225220,3cyclictest0-21swapper/3622:05:1430
2546499218204,9cyclictest0-21swapper/2019:40:2713
2546899216192,16cyclictest0-21swapper/2422:40:0917
2546899216192,16cyclictest0-21swapper/2422:40:0817
2546499214200,9cyclictest0-21swapper/2023:47:1513
2546499214200,9cyclictest0-21swapper/2023:47:1513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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