You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-02 - 21:28
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Jun 02, 2026 13:02:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3944599208198,8cyclictest0-21swapper/209:15:1512
3944599208198,8cyclictest0-21swapper/209:15:1512
3944599208198,8cyclictest0-21swapper/209:15:1512
3944599203191,9cyclictest0-21swapper/210:40:1112
3944599203191,9cyclictest0-21swapper/210:40:1012
3944599203191,9cyclictest0-21swapper/210:40:1012
394729919617,173cyclictest1442-21gdbus12:00:2018
394729919617,173cyclictest1442-21gdbus12:00:1918
3944599196188,4cyclictest37263-21CPU12
3944599196188,4cyclictest37263-21CPU12
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional