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2025-12-03 - 23:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Dec 03, 2025 13:01:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2962699248208,22cyclictest0-21swapper/1607:20:198
2962699248208,22cyclictest0-21swapper/1607:20:188
2962999245242,2cyclictest0-21swapper/1811:25:0510
2962999245242,2cyclictest0-21swapper/1811:25:0510
2962999245242,2cyclictest0-21swapper/1811:25:0410
2960399228215,5cyclictest16579-21inotify_reader07:10:1823
2960399228215,5cyclictest16579-21inotify_reader07:10:1823
2965999225199,16cyclictest0-21swapper/3710:00:1531
2965999225199,16cyclictest0-21swapper/3710:00:1531
2965999225199,16cyclictest0-21swapper/3710:00:1531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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