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2026-07-24 - 02:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jul 24, 2026 01:01:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4093899242224,11cyclictest0-21swapper/1123:29:503
4093899242224,11cyclictest0-21swapper/1123:29:493
4093899241222,12cyclictest0-21swapper/1100:25:323
4093899241222,12cyclictest0-21swapper/1100:25:323
4093899232217,8cyclictest0-21swapper/1122:20:473
4093899232217,8cyclictest0-21swapper/1122:20:473
4093899229220,6cyclictest0-21swapper/1122:25:193
4093899229220,6cyclictest0-21swapper/1122:25:193
4093899228217,7cyclictest3548-21CPU3
4093899228217,7cyclictest3548-21CPU3
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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