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2026-04-17 - 20:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Apr 17, 2026 13:02:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6701992471,242cyclictest37346-21qemu-system-x8609:26:210
6701992471,242cyclictest37346-21qemu-system-x8609:26:200
6701992450,242cyclictest0-21swapper/009:15:480
6701992450,242cyclictest0-21swapper/009:15:470
6701992371,233cyclictest0-21swapper/010:56:460
6701992371,233cyclictest0-21swapper/010:56:450
6701992361,232cyclictest17230-21systemd11:40:270
6701992361,232cyclictest17230-21systemd11:40:270
6701992361,232cyclictest17230-21systemd11:40:270
6701992361,232cyclictest0-21swapper/010:00:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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