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2025-07-12 - 11:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Jul 12, 2025 01:01:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1679699333328,3cyclictest0-21swapper/2123:46:3614
1679699333328,3cyclictest0-21swapper/2123:46:3614
1679699333328,3cyclictest0-21swapper/2123:46:3614
1677499249235,3cyclictest0-21swapper/900:30:2039
1677499249235,3cyclictest0-21swapper/900:30:2039
1677799242237,3cyclictest0-21swapper/1200:15:194
1677799242237,3cyclictest0-21swapper/1200:15:194
1680699240189,28cyclictest0-21swapper/3000:09:5324
1680699240189,28cyclictest0-21swapper/3000:09:5324
1680699240189,28cyclictest0-21swapper/3000:09:5324
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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