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2026-08-24 - 12:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Aug 24, 2026 01:03:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2644099241237,2cyclictest0-21swapper/2600:15:1519
2644099241237,2cyclictest0-21swapper/2600:15:1519
2644099241237,2cyclictest0-21swapper/2600:15:1519
2641099224216,6cyclictest0-21swapper/200:30:1912
2641099224216,6cyclictest0-21swapper/200:30:1912
2641099224216,6cyclictest0-21swapper/200:30:1812
2643499217200,14cyclictest32585-21kworker/u81:2+events_unbound23:18:2116
2643499217200,14cyclictest32585-21kworker/u81:2+events_unbound23:18:2116
2643499217200,14cyclictest32585-21kworker/u81:2+events_unbound23:18:2116
2643099211139,69cyclictest373-21kswapd100:11:1711
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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