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2025-11-15 - 13:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Nov 15, 2025 01:00:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2033799272249,14cyclictest20989-21TaskSchedulerSi20:40:1829
2033799272249,14cyclictest20989-21TaskSchedulerSi20:40:1829
2033799248217,12cyclictest0-21swapper/3519:45:2329
2033799248217,12cyclictest0-21swapper/3519:45:2329
2032299244225,5cyclictest4905-21CPU17
2032299244225,5cyclictest4905-21CPU17
2028599243221,5cyclictest4636-21CPU1
2028599243221,5cyclictest4636-21CPU1
20326992371,230cyclictest0-21swapper/2721:25:1920
20326992371,230cyclictest0-21swapper/2721:25:1920
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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