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2026-04-22 - 04:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Apr 22, 2026 01:01:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2530999219210,6cyclictest0-21swapper/521:55:1635
2530999219210,6cyclictest0-21swapper/521:55:1635
2530999219210,6cyclictest0-21swapper/521:55:1635
2530999213197,9cyclictest37267-21CPU35
2530999213197,9cyclictest37267-21CPU35
253399920391,100cyclictest2462-21CPU22
253399920391,100cyclictest2462-21CPU22
2530999203192,7cyclictest25984-21expr23:10:1435
2530999203192,7cyclictest25984-21expr23:10:1335
2530999203192,7cyclictest25984-21expr23:10:1335
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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