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2026-09-19 - 07:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Sep 19, 2026 01:01:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3063099230224,3cyclictest0-21swapper/1520:30:147
3063099230224,3cyclictest0-21swapper/1520:30:137
3063899222217,3cyclictest14522-21kworker/u81:0+events_unbound00:09:2114
3063899222217,3cyclictest14522-21kworker/u81:0+events_unbound00:09:2114
3066099210167,19cyclictest0-21swapper/3922:12:1033
3066099210167,19cyclictest0-21swapper/3922:12:1033
3065799208201,4cyclictest2462-21CPU31
3065799208201,4cyclictest2462-21CPU31
3061599207203,2cyclictest14522-21kworker/u81:0+events_unbound00:13:331
3061599207203,2cyclictest14522-21kworker/u81:0+events_unbound00:13:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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