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2025-09-13 - 10:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Sep 13, 2025 01:01:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3941099250246,2cyclictest0-21swapper/520:00:2635
3941099250246,2cyclictest0-21swapper/520:00:2635
3941099249208,27cyclictest0-21swapper/522:40:1935
3941099249208,27cyclictest0-21swapper/522:40:1835
3941099249208,27cyclictest0-21swapper/522:40:1835
3941099236193,27cyclictest28321-21inotify_reader21:55:1935
3941099236193,27cyclictest28321-21inotify_reader21:55:1935
394339922956,159cyclictest21538-21inotify_reader22:10:1818
394339922956,159cyclictest21538-21inotify_reader22:10:1818
394339922956,159cyclictest21538-21inotify_reader22:10:1818
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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