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2026-02-04 - 23:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Feb 04, 2026 13:03:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12681992432,4cyclictest37264-21CPU27
12681992432,4cyclictest37264-21CPU27
12681992423,233cyclictest3544-21CPU27
12681992423,233cyclictest3544-21CPU27
12681992421,3cyclictest2327-21qemu-system-x8611:20:1727
12681992421,3cyclictest2327-21qemu-system-x8611:20:1627
12681992421,3cyclictest2327-21qemu-system-x8611:20:1627
12681992371,3cyclictest0-21swapper/3310:15:1127
12681992371,3cyclictest0-21swapper/3310:15:1027
12681992371,3cyclictest0-21swapper/3309:15:5227
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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