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2026-02-03 - 03:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Feb 03, 2026 01:02:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17025992192,4cyclictest37358-21CPU37
17025992192,4cyclictest37358-21CPU37
1703199210201,6cyclictest1442-21gdbus23:52:555
1703199210201,6cyclictest1442-21gdbus23:52:545
1703199210201,6cyclictest1442-21gdbus23:52:545
1703199208197,8cyclictest37346-21qemu-system-x8623:29:515
1703199208197,8cyclictest37346-21qemu-system-x8623:29:505
1703199208197,8cyclictest37346-21qemu-system-x8623:29:505
1703199204198,4cyclictest0-21swapper/1321:40:095
1703199204198,4cyclictest0-21swapper/1321:40:085
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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