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2026-05-11 - 22:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon May 11, 2026 13:03:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9323992071,2cyclictest0-21swapper/107:10:281
9323992071,2cyclictest0-21swapper/107:10:271
9323992030,4cyclictest17484-21nfsd07:40:511
9323992001,4cyclictest17484-21nfsd07:34:421
9323992001,4cyclictest17484-21nfsd07:34:421
9323991981,3cyclictest0-21swapper/107:15:261
9323991981,3cyclictest0-21swapper/107:15:261
93329919524,161cyclictest0-21swapper/910:30:1539
93329919524,161cyclictest0-21swapper/910:30:1539
9323991912,5cyclictest2456-21CPU1
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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