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2026-03-12 - 00:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Mar 11, 2026 13:02:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1066199193163,18cyclictest0-21swapper/3009:44:1824
1066199193163,18cyclictest0-21swapper/3009:44:1824
1066199193163,18cyclictest0-21swapper/3009:44:1824
1064499190163,23cyclictest0-21swapper/1710:58:599
1064499190163,23cyclictest0-21swapper/1710:58:599
1064399189178,9cyclictest0-21swapper/1612:36:368
1064399189178,9cyclictest0-21swapper/1612:36:368
1062699188166,19cyclictest0-21swapper/110:40:401
1062699188166,19cyclictest0-21swapper/110:40:401
1066299185174,9cyclictest0-21swapper/3110:42:2625
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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