You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-28 - 18:06
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Jun 28, 2026 13:03:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1408699231224,5cyclictest0-21swapper/3907:22:2633
1408699231224,5cyclictest0-21swapper/3907:22:2633
14048992231,69cyclictest0-21swapper/609:40:1236
14048992231,69cyclictest0-21swapper/609:40:1236
14048992231,69cyclictest0-21swapper/609:40:1236
14056992040,196cyclictest0-21swapper/1209:50:214
14056992040,196cyclictest0-21swapper/1209:50:204
14056992040,196cyclictest0-21swapper/1209:50:204
1407899203172,12cyclictest171rcu_preempt12:32:5525
1407899203172,12cyclictest171rcu_preempt12:32:5525
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional