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2026-02-28 - 20:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 28, 2026 13:04:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3423299214206,6cyclictest0-21swapper/710:25:0437
3423299214206,6cyclictest0-21swapper/710:25:0437
3423299214206,6cyclictest0-21swapper/710:25:0437
3422599211203,6cyclictest0-21swapper/011:11:550
3422599211203,6cyclictest0-21swapper/011:11:550
3423299210201,5cyclictest0-21swapper/710:25:1537
3423299210201,5cyclictest0-21swapper/710:25:1537
3423299210201,5cyclictest0-21swapper/710:25:1537
3422799210203,5cyclictest0-21swapper/211:39:1312
3422799210203,5cyclictest0-21swapper/211:39:1312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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