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2026-08-07 - 15:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Aug 07, 2026 13:02:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2534499229196,22cyclictest0-21swapper/2912:36:5222
2534499229196,22cyclictest0-21swapper/2912:36:5222
2530999225202,17cyclictest0-21swapper/012:08:320
2530999225202,17cyclictest0-21swapper/012:08:320
2531999219213,4cyclictest0-21swapper/812:31:1338
2531999219213,4cyclictest0-21swapper/812:31:1338
2531999215209,4cyclictest0-21swapper/808:01:3938
2531999215209,4cyclictest0-21swapper/808:01:3938
2531799215212,2cyclictest0-21swapper/608:45:1636
2531799215212,2cyclictest0-21swapper/608:45:1636
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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