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2025-12-31 - 10:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Dec 31, 2025 01:00:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
797999236230,3cyclictest20277-21systemd22:39:360
797999236230,3cyclictest20277-21systemd22:39:360
798599215187,25cyclictest0-21swapper/523:31:3335
798599215187,25cyclictest0-21swapper/523:31:3335
798599215187,25cyclictest0-21swapper/523:31:3235
797999209197,10cyclictest0-21swapper/000:01:090
797999209197,10cyclictest0-21swapper/000:01:090
797999206192,8cyclictest0-21swapper/021:22:430
797999206192,8cyclictest0-21swapper/021:22:420
800699202194,6cyclictest21446-21kworker/u80:3-poll_mpt2sas0_statu19:43:3415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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