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2026-02-07 - 16:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 07, 2026 13:03:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12503992480,3cyclictest22496-21sshd12:03:4213
12503992480,3cyclictest22496-21sshd12:03:4213
12503992480,3cyclictest22496-21sshd12:03:4213
12503992412,6cyclictest4408-21CPU13
12503992412,6cyclictest4408-21CPU13
12503992412,6cyclictest4408-21CPU13
12503992401,2cyclictest0-21swapper/2011:35:0413
12503992401,2cyclictest0-21swapper/2011:35:0313
12503992391,3cyclictest0-21swapper/2007:20:2813
12503992391,3cyclictest0-21swapper/2007:20:2813
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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