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2026-06-30 - 07:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Jun 30, 2026 01:01:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3372499246240,4cyclictest0-21swapper/3322:05:2027
3372499246240,4cyclictest0-21swapper/3322:05:2027
3372499231222,6cyclictest33252-21cat22:25:1527
3372499231222,6cyclictest33252-21cat22:25:1527
3372499230215,12cyclictest0-21swapper/3321:45:3627
3372499230215,12cyclictest0-21swapper/3321:45:3627
3372499213205,6cyclictest0-21swapper/3321:25:1827
3372499213205,6cyclictest0-21swapper/3321:25:1827
3372499211206,4cyclictest0-21swapper/3300:09:1127
3372499211206,4cyclictest0-21swapper/3300:09:1127
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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