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2026-05-27 - 19:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed May 27, 2026 13:02:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1336699203198,3cyclictest0-21swapper/107:10:111
1336699203198,3cyclictest0-21swapper/107:10:111
1339399198187,5cyclictest0-21swapper/2409:40:0917
1339399198187,5cyclictest0-21swapper/2409:40:0917
1339399198184,5cyclictest0-21swapper/2408:24:5317
1339399198184,5cyclictest0-21swapper/2408:24:5317
1339399195188,6cyclictest0-21swapper/2411:13:3517
1339399195188,6cyclictest0-21swapper/2411:13:3517
1339399195188,6cyclictest0-21swapper/2411:13:3517
1337299194186,6cyclictest0-21swapper/711:08:2537
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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