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2026-01-11 - 17:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Jan 11, 2026 13:01:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3224499223215,6cyclictest0-21swapper/2112:35:5914
3224499223215,6cyclictest0-21swapper/2112:35:5814
3221899215209,3cyclictest23712-21sshd12:03:431
3221899215209,3cyclictest23712-21sshd12:03:431
3221899215209,3cyclictest23712-21sshd12:03:431
3221899209204,4cyclictest0-21swapper/111:56:531
3221899209204,4cyclictest0-21swapper/111:56:531
3221899209204,4cyclictest0-21swapper/111:56:521
3222499208200,6cyclictest0-21swapper/511:44:0035
3222499208200,6cyclictest0-21swapper/511:44:0035
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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