You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-18 - 14:51
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Nov 18, 2025 13:02:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1290499366362,2cyclictest0-21swapper/1709:40:209
1290499366362,2cyclictest0-21swapper/1709:40:209
1290499366362,2cyclictest0-21swapper/1709:40:209
1289799270226,18cyclictest3079-21CPU4
1289799270226,18cyclictest3079-21CPU4
1290499251203,20cyclictest36796-21nfsd09:35:249
1290499251203,20cyclictest36796-21nfsd09:35:239
1290499251203,20cyclictest36796-21nfsd09:35:239
1292499244223,12cyclictest16865-21NetworkChangeNo08:00:2124
1292499244223,12cyclictest16865-21NetworkChangeNo08:00:2124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional