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2026-02-14 - 10:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 14, 2026 01:02:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3311599239234,3cyclictest0-21swapper/3900:20:1433
3311599239234,3cyclictest0-21swapper/3900:20:1333
3311599239234,3cyclictest0-21swapper/3900:20:1333
3307999225177,42cyclictest4407-21CPU39
3307999225177,42cyclictest4407-21CPU39
3309399215205,8cyclictest0-21swapper/2022:35:2313
3309399215205,8cyclictest0-21swapper/2022:35:2213
3309399215205,8cyclictest0-21swapper/2022:35:2213
3306999212205,3cyclictest3610-21CPU0
3306999212205,3cyclictest3610-21CPU0
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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