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2026-08-22 - 08:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Aug 22, 2026 01:02:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
824399235210,23cyclictest0-21swapper/2521:20:2218
824399235210,23cyclictest0-21swapper/2521:20:2118
822899229222,5cyclictest0-21swapper/1223:36:504
822899229222,5cyclictest0-21swapper/1223:36:504
822899229222,5cyclictest0-21swapper/1223:36:494
823799216199,13cyclictest0-21swapper/2000:30:1413
823799216199,13cyclictest0-21swapper/2000:30:1313
823799216185,23cyclictest0-21swapper/2000:10:0013
823799216185,23cyclictest0-21swapper/2000:10:0013
824399214204,8cyclictest0-21swapper/2521:15:4018
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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