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2026-03-04 - 16:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Mar 04, 2026 13:03:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3775299221213,5cyclictest0-21swapper/1708:10:149
3775299209199,7cyclictest0-21swapper/1712:39:419
3775299209199,7cyclictest0-21swapper/1712:39:419
3775399208201,4cyclictest1360-21systemd-logind09:25:5510
3775399208201,4cyclictest1360-21systemd-logind09:25:5410
3774099206197,5cyclictest0-21swapper/711:34:3437
3774099206197,5cyclictest0-21swapper/711:34:3437
3774099206197,5cyclictest0-21swapper/711:34:3337
3775399203173,21cyclictest0-21swapper/1811:17:4910
3775399203173,21cyclictest0-21swapper/1811:17:4910
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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