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2026-08-18 - 23:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Aug 18, 2026 13:01:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2744499220212,5cyclictest0-21swapper/3711:41:5031
2744499220212,5cyclictest0-21swapper/3711:41:5031
2744499220212,5cyclictest0-21swapper/3711:41:4931
2744499206198,6cyclictest0-21swapper/3708:21:5331
2744499206198,6cyclictest0-21swapper/3708:21:5331
2741899200196,2cyclictest0-21swapper/1408:35:126
2741899200196,2cyclictest0-21swapper/1408:35:126
2740499200189,9cyclictest28279-21kworker/u80:0-ext4-rsv-conversion10:41:0723
2740499200189,9cyclictest28279-21kworker/u80:0-ext4-rsv-conversion10:41:0723
2742599199195,2cyclictest0-21swapper/2008:45:1513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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