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2026-09-11 - 11:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Sep 11, 2026 01:02:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2593199220209,9cyclictest0-21swapper/2919:20:2522
2593199220209,9cyclictest0-21swapper/2919:20:2422
2593299208195,8cyclictest0-21swapper/3022:42:4024
2593299208195,8cyclictest0-21swapper/3022:42:3924
2591999206196,5cyclictest3542-21CPU11
2591999206196,5cyclictest3542-21CPU11
2590699206201,2cyclictest0-21swapper/720:01:5337
2593499203192,7cyclictest0-21swapper/3221:40:3226
2593499203192,7cyclictest0-21swapper/3221:40:3126
2592799198179,17cyclictest0-21swapper/2519:41:0818
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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