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2026-05-23 - 09:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat May 23, 2026 01:02:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
845199219204,12cyclictest0-21swapper/1422:15:016
845199219204,12cyclictest0-21swapper/1422:15:016
845199207199,3cyclictest37351-21CPU6
845199207199,3cyclictest37351-21CPU6
845199207199,3cyclictest37351-21CPU6
846799206197,6cyclictest0-21swapper/2722:35:0120
846799206197,6cyclictest0-21swapper/2722:35:0120
846799206197,6cyclictest0-21swapper/2722:35:0120
845199204195,7cyclictest0-21swapper/1400:10:176
845199204195,7cyclictest0-21swapper/1400:10:176
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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