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2026-03-05 - 05:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Mar 05, 2026 01:02:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4037199345334,8cyclictest373-21kswapd123:35:0511
4037199345334,8cyclictest373-21kswapd123:35:0511
4037199345334,8cyclictest373-21kswapd123:35:0511
4039199279274,3cyclictest373-21kswapd123:37:3431
4039199279274,3cyclictest373-21kswapd123:37:3331
4036799252247,3cyclictest373-21kswapd121:10:128
4036799252247,3cyclictest373-21kswapd121:10:128
4037199231226,3cyclictest0-21swapper/1921:15:1411
4037199231226,3cyclictest0-21swapper/1921:15:1411
4037499228203,23cyclictest0-21swapper/2121:57:2814
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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