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2025-12-23 - 22:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Dec 23, 2025 13:01:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31890992541,247cyclictest0-21swapper/1712:09:359
31890992541,247cyclictest0-21swapper/1712:09:359
31890992541,247cyclictest0-21swapper/1712:09:359
31890992530,250cyclictest0-21swapper/1711:55:259
31890992530,250cyclictest0-21swapper/1711:55:249
31890992500,247cyclictest0-21swapper/1710:34:479
31890992500,247cyclictest0-21swapper/1710:34:479
31890992500,247cyclictest0-21swapper/1710:34:469
31890992361,228cyclictest0-21swapper/1710:35:149
31890992361,228cyclictest0-21swapper/1710:35:149
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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