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2026-05-28 - 08:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu May 28, 2026 01:01:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2114899241170,66cyclictest372-21kswapd000:07:2034
2114899241170,66cyclictest372-21kswapd000:07:2034
2115899214202,8cyclictest2327-21qemu-system-x8620:40:145
2115899214202,8cyclictest2327-21qemu-system-x8620:40:145
2115899213188,22cyclictest0-21swapper/1321:25:145
2115899213188,22cyclictest0-21swapper/1321:25:135
2117599210173,32cyclictest0-21swapper/2823:10:5121
2117599210173,32cyclictest0-21swapper/2823:10:5021
2115899208200,4cyclictest2456-21CPU5
2115899208200,4cyclictest2456-21CPU5
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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