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2026-07-26 - 06:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Jul 26, 2026 01:01:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3432499240235,3cyclictest19034-21kworker/u81:1+events_unbound00:08:1735
3432499240235,3cyclictest19034-21kworker/u81:1+events_unbound00:08:1735
3432499240235,3cyclictest19034-21kworker/u81:1+events_unbound00:08:1635
3436099217213,2cyclictest0-21swapper/3520:05:1629
3431999210202,6cyclictest0-21swapper/021:13:350
3431999210202,6cyclictest0-21swapper/021:13:350
3434599209181,25cyclictest0-21swapper/2100:27:1814
3434599209181,25cyclictest0-21swapper/2100:27:1714
3435399198186,8cyclictest0-21swapper/2822:55:0321
3435399198186,8cyclictest0-21swapper/2822:55:0321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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