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2025-12-29 - 08:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Dec 29, 2025 01:00:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2354699213205,6cyclictest3443-21nfsd21:25:3719
2354699213205,6cyclictest3443-21nfsd21:25:3719
2354699203189,12cyclictest0-21swapper/2621:32:2619
2354699203189,12cyclictest0-21swapper/2621:32:2619
2354699203189,12cyclictest0-21swapper/2621:32:2519
2354699200190,9cyclictest0-21swapper/2623:25:0019
2354699200190,9cyclictest0-21swapper/2623:24:5919
2355599199178,18cyclictest2327-21qemu-system-x8622:45:1728
2355599199178,18cyclictest2327-21qemu-system-x8622:45:1728
2353799195182,11cyclictest0-21swapper/1921:40:1311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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