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2026-06-20 - 22:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Jun 20, 2026 13:02:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3611199204196,6cyclictest0-21swapper/1509:11:067
3611199204196,6cyclictest0-21swapper/1509:11:067
3611199198193,4cyclictest0-21swapper/1509:35:077
3611199198193,4cyclictest0-21swapper/1509:35:067
3611199198193,4cyclictest0-21swapper/1509:35:067
3611199197192,4cyclictest0-21swapper/1509:05:267
3611199197192,4cyclictest0-21swapper/1509:05:257
3611199197192,4cyclictest0-21swapper/1509:05:257
3612899196188,4cyclictest3544-21CPU22
3612899196188,4cyclictest3544-21CPU22
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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