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2026-01-30 - 02:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jan 30, 2026 01:00:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3339999203199,2cyclictest0-21swapper/2123:55:1814
3339999203199,2cyclictest0-21swapper/2123:55:1814
3339999203199,2cyclictest0-21swapper/2123:55:1814
3339899193185,5cyclictest0-21swapper/2020:15:1413
3339899193185,5cyclictest0-21swapper/2020:15:1413
3339899191185,4cyclictest0-21swapper/2021:20:0913
3339899191185,4cyclictest0-21swapper/2021:20:0913
3338499189136,47cyclictest0-21swapper/900:36:0739
3338499189136,47cyclictest0-21swapper/900:36:0739
3340799187178,6cyclictest0-21swapper/2822:13:2121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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