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2026-02-25 - 14:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Feb 25, 2026 13:02:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2536599215208,4cyclictest0-21swapper/3311:40:2127
2536599215208,4cyclictest0-21swapper/3311:40:2027
2536599215208,4cyclictest0-21swapper/3311:40:2027
2532699214207,4cyclictest4398-21qemu-system-x8607:25:131
2533499208201,3cyclictest3548-21CPU38
2533499208201,3cyclictest3548-21CPU38
2532699207200,5cyclictest0-21swapper/110:18:241
2532699207200,5cyclictest0-21swapper/110:18:241
2532699207198,5cyclictest3609-21CPU1
2532699207198,5cyclictest3609-21CPU1
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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