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2026-04-26 - 22:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Apr 26, 2026 13:03:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2590499215211,2cyclictest0-21swapper/1010:30:202
2590499215211,2cyclictest0-21swapper/1010:30:192
2590499215211,2cyclictest0-21swapper/1010:30:192
2589699197155,35cyclictest0-21swapper/310:53:5123
2589699197155,35cyclictest0-21swapper/310:53:5123
2589699196154,40cyclictest0-21swapper/310:45:0323
2589699196154,40cyclictest0-21swapper/310:45:0323
2589699196154,40cyclictest0-21swapper/310:45:0323
2591199191187,2cyclictest0-21swapper/1410:35:196
2591199191187,2cyclictest0-21swapper/1410:35:196
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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