You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-13 - 06:48
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Jun 13, 2026 01:01:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1495999212205,4cyclictest0-21swapper/323:26:0123
1495999212205,4cyclictest0-21swapper/323:26:0123
1495999210203,5cyclictest0-21swapper/321:32:1223
1495999210203,5cyclictest0-21swapper/321:32:1223
1499599206197,3cyclictest3543-21CPU29
1499599206197,3cyclictest3543-21CPU29
1498199206158,37cyclictest0-21swapper/2223:17:0515
1498199206158,37cyclictest0-21swapper/2223:17:0515
1495999204199,4cyclictest0-21swapper/323:32:2923
1495999204199,4cyclictest0-21swapper/323:32:2923
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional