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2026-09-01 - 20:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Sep 01, 2026 13:01:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1938199229160,57cyclictest0-21swapper/2010:50:1813
1938199229160,57cyclictest0-21swapper/2010:50:1813
1935899219202,13cyclictest14395-21lxd11:55:171
1935899219202,13cyclictest14395-21lxd11:55:161
1936299217151,50cyclictest0-21swapper/511:00:0035
1936299217151,50cyclictest0-21swapper/511:00:0035
1935899210173,24cyclictest0-21swapper/111:51:431
1935899210173,24cyclictest0-21swapper/111:51:421
1935899210173,24cyclictest0-21swapper/111:51:421
1936399207204,2cyclictest0-21swapper/610:45:1436
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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