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2025-11-19 - 17:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Nov 19, 2025 13:02:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
146829924824,195cyclictest0-21swapper/2808:40:2121
146829924824,195cyclictest0-21swapper/2808:40:2121
146829924824,195cyclictest0-21swapper/2808:40:2121
1464699228205,8cyclictest4905-21CPU6
1464699228205,8cyclictest4905-21CPU6
14640992231,211cyclictest0-21swapper/812:00:1938
14640992231,211cyclictest0-21swapper/812:00:1938
1464399222209,2cyclictest0-21swapper/1108:20:183
1464399222209,2cyclictest0-21swapper/1108:20:183
14640992181,206cyclictest0-21swapper/809:15:2038
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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