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2026-05-31 - 06:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun May 31, 2026 01:01:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3845099208204,2cyclictest0-21swapper/1522:05:167
3845099208204,2cyclictest0-21swapper/1522:05:167
3846099198192,3cyclictest2461-21CPU16
3846099198192,3cyclictest2461-21CPU16
38464991951,106cyclictest0-21swapper/2700:20:2420
38464991951,106cyclictest0-21swapper/2700:20:2320
3843799194180,7cyclictest3547-21CPU12
3843799194180,7cyclictest3547-21CPU12
3846399192186,4cyclictest0-21swapper/2623:53:4719
3846399192186,4cyclictest0-21swapper/2623:53:4719
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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