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2025-11-21 - 01:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Nov 20, 2025 13:01:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2396099259237,4cyclictest9334-21CPU5
2396099259237,4cyclictest9334-21CPU5
2396099259237,4cyclictest9334-21CPU5
239959922833,168cyclictest9334-21CPU29
239959922833,168cyclictest9334-21CPU29
239959922833,168cyclictest9334-21CPU29
2399999227224,2cyclictest0-21swapper/3912:25:1533
2399999227224,2cyclictest0-21swapper/3912:25:1533
2399499226221,3cyclictest0-21swapper/3412:25:1328
2399499226221,3cyclictest0-21swapper/3412:25:1328
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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