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2026-04-20 - 12:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Apr 20, 2026 01:01:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1200799216210,5cyclictest0-21swapper/2223:49:1515
1200799216210,5cyclictest0-21swapper/2223:49:1515
1198499212202,7cyclictest0-21swapper/200:13:2112
1198499212202,7cyclictest0-21swapper/200:13:2112
1198499212202,7cyclictest0-21swapper/200:13:2012
1200799208201,3cyclictest37268-21CPU15
1200799208201,3cyclictest37268-21CPU15
1200799198191,5cyclictest0-21swapper/2219:55:0315
1200799198191,5cyclictest0-21swapper/2219:55:0315
1198399196191,4cyclictest0-21swapper/120:10:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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