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2026-06-29 - 19:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Jun 29, 2026 13:02:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1560499221215,3cyclictest1-21systemd11:35:1710
1560499221215,3cyclictest1-21systemd11:35:1710
156249921813,2cyclictest0-21swapper/3411:04:0028
156249921813,2cyclictest0-21swapper/3411:04:0028
156249921813,2cyclictest0-21swapper/3411:04:0028
1559499212207,2cyclictest0-21swapper/1110:20:203
1559499212207,2cyclictest0-21swapper/1110:20:203
1560699208202,3cyclictest0-21swapper/2010:25:1613
1560699208202,3cyclictest0-21swapper/2010:25:1513
1560699208202,3cyclictest0-21swapper/2010:25:1513
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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