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2026-04-24 - 19:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Apr 24, 2026 13:01:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
40699196182,10cyclictest2462-21CPU27
40699196182,10cyclictest2462-21CPU27
40699191184,6cyclictest0-21swapper/3310:16:0527
40699191184,6cyclictest0-21swapper/3310:16:0427
40699191184,6cyclictest0-21swapper/3310:16:0427
38099191185,4cyclictest0-21swapper/1109:47:083
38099191185,4cyclictest0-21swapper/1109:47:083
38099191180,7cyclictest0-21swapper/1109:40:153
38099191180,7cyclictest0-21swapper/1109:40:153
40299189163,6cyclictest0-21swapper/2911:42:2522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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