You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-13 - 16:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Feb 13, 2026 13:03:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
608399221204,12cyclictest0-21swapper/2212:29:4115
608399221204,12cyclictest0-21swapper/2212:29:4115
608399221204,12cyclictest0-21swapper/2212:29:4015
608399213195,16cyclictest0-21swapper/2210:30:1915
608399213195,16cyclictest0-21swapper/2210:30:1815
609099212189,13cyclictest0-21swapper/2710:40:0820
609099212189,13cyclictest0-21swapper/2710:40:0820
608399212200,10cyclictest0-21swapper/2209:36:2115
608399212200,10cyclictest0-21swapper/2209:36:2115
606199207201,4cyclictest0-21swapper/307:17:0523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional