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2025-12-09 - 07:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Dec 09, 2025 01:01:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3623699334330,2cyclictest0-21swapper/123:39:481
3623699334330,2cyclictest0-21swapper/123:39:481
3623699334330,2cyclictest0-21swapper/123:39:481
3626799276245,8cyclictest36795-21nfsd23:30:1821
3626799276245,8cyclictest36795-21nfsd23:30:1821
36255992681,257cyclictest0-21swapper/1700:15:229
36255992681,257cyclictest0-21swapper/1700:15:229
36255992681,257cyclictest0-21swapper/1700:15:229
3627899257227,16cyclictest15982-21CPU31
3627899257227,16cyclictest15982-21CPU31
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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