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2026-01-12 - 17:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Jan 12, 2026 13:00:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3485099206201,4cyclictest0-21swapper/3507:18:3229
3485099206201,4cyclictest0-21swapper/3507:18:3129
3484299206197,6cyclictest38621-21kworker/u81:4+events_unbound12:36:4620
3484299206197,6cyclictest38621-21kworker/u81:4+events_unbound12:36:4620
3484299206197,6cyclictest38621-21kworker/u81:4+events_unbound12:36:4520
3485199203194,5cyclictest0-21swapper/3608:35:1730
3485199203194,5cyclictest0-21swapper/3608:35:1730
3481399203196,3cyclictest37354-21CPU34
3481399203196,3cyclictest37354-21CPU34
3481399203196,3cyclictest37354-21CPU34
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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