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2026-08-10 - 21:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Aug 10, 2026 13:02:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
272579926099,157cyclictest0-21swapper/209:03:1812
272579926099,157cyclictest0-21swapper/209:03:1812
2727099211204,5cyclictest0-21swapper/1310:40:135
2727099211204,5cyclictest0-21swapper/1310:40:135
2727999203197,3cyclictest20371-21sshd11:10:4215
2727999203197,3cyclictest20371-21sshd11:10:4215
2728999202194,6cyclictest0-21swapper/2911:57:3722
2728999202194,6cyclictest0-21swapper/2911:57:3722
2727099202198,2cyclictest0-21swapper/1310:20:005
2727099202198,2cyclictest0-21swapper/1310:19:595
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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