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2026-08-06 - 00:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Aug 05, 2026 13:01:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
583299207198,7cyclictest0-21swapper/3912:00:2933
583299207198,7cyclictest0-21swapper/3912:00:2933
583299207198,7cyclictest0-21swapper/3912:00:2833
583299196188,5cyclictest0-21swapper/3910:44:0733
583299196188,5cyclictest0-21swapper/3910:44:0733
580599191185,3cyclictest0-21swapper/1509:14:497
580599191185,3cyclictest0-21swapper/1509:14:497
582599190183,5cyclictest0-21swapper/3310:00:1327
582599190183,5cyclictest0-21swapper/3310:00:1327
5828991897,174cyclictest0-21swapper/3512:30:2029
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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