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2026-07-07 - 14:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Jul 07, 2026 13:02:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
328899261248,11cyclictest0-21swapper/810:00:0238
328899261248,11cyclictest0-21swapper/810:00:0238
328899240234,4cyclictest0-21swapper/810:43:2238
328899240234,4cyclictest0-21swapper/810:43:2238
328899240234,4cyclictest0-21swapper/810:43:2138
328899237231,3cyclictest4363-21sshd10:27:4638
328899237231,3cyclictest4363-21sshd10:27:4638
328899237231,3cyclictest4363-21sshd10:27:4638
328899224217,6cyclictest0-21swapper/810:16:5138
328899224217,6cyclictest0-21swapper/810:16:5038
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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