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2026-05-07 - 21:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu May 07, 2026 13:02:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2109599219213,4cyclictest0-21swapper/3707:55:2031
2106399210203,5cyclictest0-21swapper/1112:09:553
2106399210203,5cyclictest0-21swapper/1112:09:543
2106399209199,7cyclictest0-21swapper/1110:27:003
2106399209199,7cyclictest0-21swapper/1110:27:003
2106399207200,5cyclictest0-21swapper/1112:16:153
2106399207200,5cyclictest0-21swapper/1112:16:153
2106399207200,5cyclictest0-21swapper/1112:16:153
2106399205180,22cyclictest0-21swapper/1111:55:133
2106399205180,22cyclictest0-21swapper/1111:55:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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