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2026-09-24 - 02:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Sep 24, 2026 01:02:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2665499221214,3cyclictest3610-21CPU18
2665499221214,3cyclictest3610-21CPU18
2663999219213,3cyclictest0-21swapper/1221:30:014
2663999219213,3cyclictest0-21swapper/1221:30:004
2665499212199,9cyclictest0-21swapper/2522:20:0018
2665499212199,9cyclictest0-21swapper/2522:20:0018
2665499206193,7cyclictest37357-21CPU18
2665499206193,7cyclictest37357-21CPU18
2665499204197,5cyclictest0-21swapper/2523:29:2818
2665499204197,5cyclictest0-21swapper/2523:29:2718
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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