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2026-06-27 - 16:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Jun 27, 2026 13:01:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2097299218210,6cyclictest0-21swapper/1711:26:129
2097299218210,6cyclictest0-21swapper/1711:26:119
2097299204195,6cyclictest36354-21run-parts12:23:329
2097299204195,6cyclictest36354-21run-parts12:23:319
2097499201197,2cyclictest0-21swapper/1911:40:2211
2097499201197,2cyclictest0-21swapper/1911:40:2111
2097499201197,2cyclictest0-21swapper/1911:40:2111
20986991961,4cyclictest3543-21CPU21
20986991961,4cyclictest3543-21CPU21
2099699195146,36cyclictest0-21swapper/3710:41:5531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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