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2026-02-15 - 11:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Feb 15, 2026 01:01:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33044992361,3cyclictest0-21swapper/019:35:230
33044992361,3cyclictest0-21swapper/019:35:230
33044992321,2cyclictest0-21swapper/019:15:160
33044992321,2cyclictest0-21swapper/019:15:150
33044992311,2cyclictest0-21swapper/019:32:330
33044992311,2cyclictest0-21swapper/019:32:320
33044992281,223cyclictest0-21swapper/019:53:120
33044992281,223cyclictest0-21swapper/019:53:110
33044992251,3cyclictest0-21swapper/020:52:200
33044992211,3cyclictest0-21swapper/019:20:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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