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2026-06-21 - 23:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Jun 21, 2026 13:02:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25163992460,2cyclictest0-21swapper/3810:18:5532
25163992460,2cyclictest0-21swapper/3810:18:5432
25163992430,2cyclictest0-21swapper/3809:59:4632
25163992430,2cyclictest0-21swapper/3809:59:4532
25163992430,2cyclictest0-21swapper/3809:59:4532
25163992381,233cyclictest0-21swapper/3810:03:0132
25163992381,233cyclictest0-21swapper/3810:03:0032
25163992381,233cyclictest0-21swapper/3810:03:0032
25163992380,2cyclictest0-21swapper/3810:10:1432
25163992380,2cyclictest0-21swapper/3810:10:1332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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