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2026-08-16 - 04:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Aug 16, 2026 01:01:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1873099218211,4cyclictest0-21swapper/019:20:180
1873099218211,4cyclictest0-21swapper/019:20:180
1873299215212,2cyclictest0-21swapper/222:00:2112
1873299215212,2cyclictest0-21swapper/222:00:2112
1873099206195,8cyclictest0-21swapper/019:35:280
1875899205172,30cyclictest0-21swapper/2222:15:5015
1875899205172,30cyclictest0-21swapper/2222:15:5015
1874199205153,41cyclictest17482-21nfsd00:07:1139
1874199205153,41cyclictest17482-21nfsd00:07:1139
1873099204143,25cyclictest0-21swapper/023:45:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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