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2026-02-09 - 19:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Feb 09, 2026 13:03:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2183699225216,4cyclictest0-21swapper/3410:13:0628
2183699225216,4cyclictest0-21swapper/3410:13:0628
2183699225216,4cyclictest0-21swapper/3410:13:0628
2183699209200,6cyclictest1392-21gdbus10:20:1128
2183699209200,6cyclictest1392-21gdbus10:20:1128
2183699209200,6cyclictest1392-21gdbus10:20:1128
2180799203196,5cyclictest0-21swapper/912:06:0039
2180799203196,5cyclictest0-21swapper/912:05:5939
2180799203196,5cyclictest0-21swapper/912:05:5939
2183699197190,5cyclictest0-21swapper/3410:00:1328
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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