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2026-02-23 - 10:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Feb 23, 2026 01:03:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
532999217211,4cyclictest0-21swapper/1020:00:002
532999217211,4cyclictest0-21swapper/1020:00:002
535099205198,5cyclictest0-21swapper/2720:30:1920
535099199195,2cyclictest0-21swapper/2722:28:1220
535099199195,2cyclictest0-21swapper/2722:28:1220
532999194187,4cyclictest2466-21CPU2
532999194187,4cyclictest2466-21CPU2
5328991931,3cyclictest0-21swapper/919:36:4939
535099192182,8cyclictest0-21swapper/2722:11:2820
535099192182,8cyclictest0-21swapper/2722:11:2820
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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