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2026-04-24 - 07:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Apr 24, 2026 01:01:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3784199202196,4cyclictest0-21swapper/2421:05:2017
3784199202196,4cyclictest0-21swapper/2421:05:2017
3784199202196,4cyclictest0-21swapper/2421:05:2017
3781699201119,57cyclictest0-21swapper/319:10:0223
3781699201119,57cyclictest0-21swapper/319:10:0223
3782799199193,4cyclictest0-21swapper/1222:56:374
3782799199193,4cyclictest0-21swapper/1222:56:374
3784199198185,8cyclictest0-21swapper/2423:20:5817
3784199198185,8cyclictest0-21swapper/2423:20:5817
3784199195189,4cyclictest0-21swapper/2419:20:0117
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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