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2026-05-21 - 07:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu May 21, 2026 01:01:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3742899214208,5cyclictest0-21swapper/1223:44:594
3742899214208,5cyclictest0-21swapper/1223:44:594
3742899214208,5cyclictest0-21swapper/1223:44:594
3742099213195,16cyclictest0-21swapper/521:10:2635
3742099213195,16cyclictest0-21swapper/521:10:2635
3742899209200,6cyclictest4398-21qemu-system-x8623:08:074
3742899209200,6cyclictest4398-21qemu-system-x8623:08:074
3742499208204,2cyclictest0-21swapper/923:25:2039
3742499208204,2cyclictest0-21swapper/923:25:2039
3742899202193,7cyclictest0-21swapper/1223:11:284
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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