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2026-08-15 - 03:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Aug 15, 2026 01:01:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2794399243232,8cyclictest0-21swapper/119:15:151
2794399243232,8cyclictest0-21swapper/119:15:151
2796299216207,4cyclictest0-21swapper/1620:25:018
2794399215209,4cyclictest17484-21nfsd21:47:281
2794399215209,4cyclictest17484-21nfsd21:47:271
2798399214205,7cyclictest0-21swapper/3521:00:4429
2798399214205,7cyclictest0-21swapper/3521:00:4429
2794399213203,5cyclictest0-21swapper/121:30:161
2794399213203,5cyclictest0-21swapper/121:30:161
2794399213203,5cyclictest0-21swapper/121:30:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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