You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-29 - 05:41
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Jul 29, 2026 01:01:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
363099276271,3cyclictest18656-21kworker/u81:2+events_unbound22:42:1212
363099276271,3cyclictest18656-21kworker/u81:2+events_unbound22:42:1212
368899210187,12cyclictest0-21swapper/3820:15:2632
368899210187,12cyclictest0-21swapper/3820:15:2632
368599210200,7cyclictest0-21swapper/3520:20:1229
368599210200,7cyclictest0-21swapper/3520:20:1129
367699202194,6cyclictest0-21swapper/2721:30:0220
367699202194,6cyclictest0-21swapper/2721:30:0120
366599202199,2cyclictest0-21swapper/1820:35:2110
366599202199,2cyclictest0-21swapper/1820:35:2110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional