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2026-02-10 - 08:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Feb 10, 2026 01:02:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4027999209201,6cyclictest0-21swapper/3019:15:2424
4027999209201,6cyclictest0-21swapper/3019:15:2424
4028899198189,7cyclictest0-21swapper/3600:13:0030
4028899198189,7cyclictest0-21swapper/3600:13:0030
4028899198189,7cyclictest0-21swapper/3600:12:5930
4027299198142,40cyclictest0-21swapper/2419:30:2117
4027299198142,40cyclictest0-21swapper/2419:30:2117
4027999194179,12cyclictest0-21swapper/3019:20:0524
4027999194179,12cyclictest0-21swapper/3019:20:0424
4024699186174,9cyclictest1442-21gdbus23:06:081
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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