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2026-05-08 - 21:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri May 08, 2026 13:02:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3624499224216,5cyclictest0-21swapper/2910:00:0022
3624499224216,5cyclictest0-21swapper/2910:00:0022
3623599216212,2cyclictest0-21swapper/2009:35:2813
3623599216212,2cyclictest0-21swapper/2009:35:2813
3621499206193,9cyclictest0-21swapper/310:53:2223
3621499206193,9cyclictest0-21swapper/310:53:2123
3621499206193,9cyclictest0-21swapper/310:53:2123
3621499205189,10cyclictest0-21swapper/310:24:5223
3621499205189,10cyclictest0-21swapper/310:24:5223
3623199204148,53cyclictest37270-21CPU10
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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