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2026-03-13 - 00:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Mar 12, 2026 13:04:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
887099219209,8cyclictest0-21swapper/2508:30:1418
887099219209,8cyclictest0-21swapper/2508:30:1418
886399203154,39cyclictest0-21swapper/1911:30:3411
886399203154,39cyclictest0-21swapper/1911:30:3311
886399203154,39cyclictest0-21swapper/1911:30:3311
885799203196,5cyclictest0-21swapper/1311:07:575
885799203196,5cyclictest0-21swapper/1311:07:575
885799203196,5cyclictest0-21swapper/1311:07:575
886799202193,7cyclictest0-21swapper/2207:21:2915
885199202197,3cyclictest0-21swapper/907:10:1339
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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