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2026-06-12 - 16:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jun 12, 2026 13:02:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2817399221186,26cyclictest0-21swapper/2710:00:1320
2817399221186,26cyclictest0-21swapper/2710:00:1220
2817399221186,26cyclictest0-21swapper/2710:00:1220
2817199206129,55cyclictest171rcu_preempt10:05:0018
2817199206129,55cyclictest171rcu_preempt10:05:0018
2817199206129,55cyclictest171rcu_preempt10:04:5918
2814299203177,17cyclictest0-21swapper/108:10:011
2816999199192,4cyclictest0-21swapper/2310:33:5116
2816999199192,4cyclictest0-21swapper/2310:33:5016
2814299199182,14cyclictest0-21swapper/107:23:041
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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