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2026-07-27 - 07:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Jul 27, 2026 01:01:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2783399212205,4cyclictest0-21swapper/3820:20:1832
2783399212205,4cyclictest0-21swapper/3820:20:1732
2783399212200,10cyclictest0-21swapper/3800:36:2932
2783399212200,10cyclictest0-21swapper/3800:36:2832
2782399209194,12cyclictest0-21swapper/3121:30:3925
2782399209194,12cyclictest0-21swapper/3121:30:3825
2782399208204,3cyclictest0-21swapper/3122:01:3725
2782399208204,3cyclictest0-21swapper/3122:01:3725
2782399207201,4cyclictest0-21swapper/3122:07:5925
2782399207201,4cyclictest0-21swapper/3122:07:5825
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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