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2025-12-19 - 08:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Dec 19, 2025 01:00:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11309992500,247cyclictest0-21swapper/1822:10:1910
11309992500,247cyclictest0-21swapper/1822:10:1910
11309992500,247cyclictest0-21swapper/1800:21:4510
11309992500,247cyclictest0-21swapper/1800:21:4510
11309992500,247cyclictest0-21swapper/1800:21:4410
11309992471,242cyclictest14892-21sshd22:33:4810
11309992471,242cyclictest14892-21sshd22:33:4810
11309992440,236cyclictest0-21swapper/1822:35:2610
11309992440,236cyclictest0-21swapper/1822:35:2510
11309992431,239cyclictest0-21swapper/1823:30:2510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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