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2026-06-04 - 11:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Jun 04, 2026 01:01:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3399299231209,10cyclictest2327-21qemu-system-x8623:20:591
3399299231209,10cyclictest2327-21qemu-system-x8623:20:591
3400099219215,2cyclictest0-21swapper/800:39:2638
3400099219215,2cyclictest0-21swapper/800:39:2638
3400099219215,2cyclictest0-21swapper/800:39:2638
3399299218198,16cyclictest0-21swapper/122:10:121
3399299218198,16cyclictest0-21swapper/122:10:121
3403599217209,4cyclictest3547-21CPU31
3403599217209,4cyclictest3547-21CPU31
3399299217209,6cyclictest0-21swapper/122:20:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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