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2026-06-16 - 13:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Jun 16, 2026 01:01:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3568699225222,2cyclictest0-21swapper/2121:22:5814
3568699225222,2cyclictest0-21swapper/2121:22:5714
3569399202186,7cyclictest0-21swapper/2719:45:3720
3566599199166,27cyclictest0-21swapper/323:03:0623
3566599199166,27cyclictest0-21swapper/323:03:0623
3568899195169,24cyclictest0-21swapper/2321:39:5016
3568899195169,24cyclictest0-21swapper/2321:39:5016
356759919551,134cyclictest0-21swapper/1223:40:114
356759919551,134cyclictest0-21swapper/1223:40:114
3570299194183,10cyclictest0-21swapper/3421:37:5528
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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