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2025-12-25 - 16:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Dec 25, 2025 12:59:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
770299234226,4cyclictest3609-21CPU25
770299234226,4cyclictest3609-21CPU25
767799216211,2cyclictest0-21swapper/910:18:3639
767799216211,2cyclictest0-21swapper/910:18:3639
767799216211,2cyclictest0-21swapper/910:18:3639
768199214209,4cyclictest0-21swapper/1309:47:155
768199214209,4cyclictest0-21swapper/1309:47:155
768199214209,4cyclictest0-21swapper/1309:47:155
770699211204,5cyclictest0-21swapper/3509:15:1229
770699211204,5cyclictest0-21swapper/3509:15:1129
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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