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2022-07-04 - 05:30

x86 Intel Xeon E5-2650Lv2 @1700 MHz, Linux 4.18.7-rt5 (Profile)

Latency plot of system in rack #6, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Up99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jun 03, 2022 02:52:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1406399236232,2cyclictest0-21swapper/1322:29:195
1406399236232,2cyclictest0-21swapper/1322:29:195
1405899221209,5cyclictest4303-21CPU2
1405899221209,5cyclictest4303-21CPU2
1405899213199,11cyclictest35477-21cp21:35:162
1405899213199,11cyclictest35477-21cp21:35:162
1405899212190,13cyclictest0-21swapper/1000:12:122
1405899212190,13cyclictest0-21swapper/1000:12:122
1405899211190,11cyclictest0-21swapper/1000:01:432
1405899211190,11cyclictest0-21swapper/1000:01:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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