You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-04 - 04:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Feb 04, 2026 01:02:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3961799239233,4cyclictest0-21swapper/1421:35:286
3961799239233,4cyclictest0-21swapper/1421:35:286
3961599224211,10cyclictest0-21swapper/1323:52:185
3961599224211,10cyclictest0-21swapper/1323:52:185
3962499222198,20cyclictest0-21swapper/2121:40:1514
3962499222198,20cyclictest0-21swapper/2121:40:1514
3964499219215,2cyclictest0-21swapper/3722:15:1331
3964499219215,2cyclictest0-21swapper/3722:15:1331
3963699213209,2cyclictest0-21swapper/3222:50:1826
3963699213209,2cyclictest0-21swapper/3222:50:1826
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional