You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-07 - 16:41
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Jun 07, 2026 13:03:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
918499217211,4cyclictest0-21swapper/3912:32:1133
918499217211,4cyclictest0-21swapper/3912:32:1133
918399212206,4cyclictest0-21swapper/3808:47:5832
918399212206,4cyclictest0-21swapper/3808:47:5832
918399205188,4cyclictest0-21swapper/3810:46:2232
918399205188,4cyclictest0-21swapper/3810:46:2232
918399205188,4cyclictest0-21swapper/3810:46:2232
918399204198,4cyclictest0-21swapper/3811:06:5732
918399204198,4cyclictest0-21swapper/3811:06:5732
918399204198,4cyclictest0-21swapper/3811:06:5732
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional