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2026-04-27 - 17:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Apr 27, 2026 13:01:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2294699220212,6cyclictest0-21swapper/609:55:4636
2294699220212,6cyclictest0-21swapper/609:55:4636
2294099219212,3cyclictest3541-21CPU1
2294099219212,3cyclictest3541-21CPU1
2294499208202,4cyclictest37346-21qemu-system-x8608:20:0034
2294499208202,4cyclictest37346-21qemu-system-x8608:20:0034
22955992066,20cyclictest0-21swapper/1409:49:396
22955992066,20cyclictest0-21swapper/1409:49:396
2294399205166,22cyclictest0-21swapper/311:15:3823
2294399205166,22cyclictest0-21swapper/311:15:3723
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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