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2026-06-18 - 15:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Jun 18, 2026 13:02:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
310799217173,35cyclictest3609-21CPU1
310799217173,35cyclictest3609-21CPU1
314399212193,16cyclictest0-21swapper/3011:25:4524
314399212193,16cyclictest0-21swapper/3011:25:4524
313099210172,12cyclictest0-21swapper/2112:22:4414
313099210172,12cyclictest0-21swapper/2112:22:4314
313099199170,7cyclictest0-21swapper/2111:41:0814
313099199170,7cyclictest0-21swapper/2111:41:0814
313099199170,7cyclictest0-21swapper/2111:41:0814
311699199185,7cyclictest0-21swapper/809:41:5538
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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