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2026-07-09 - 08:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Jul 09, 2026 01:01:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
915599203194,7cyclictest0-21swapper/3123:12:0325
915599203194,7cyclictest0-21swapper/3123:12:0325
915599203194,7cyclictest0-21swapper/3123:12:0325
915599191184,5cyclictest0-21swapper/3120:15:1025
915599190177,11cyclictest0-21swapper/3123:40:0825
915599190177,11cyclictest0-21swapper/3123:40:0725
914499189129,55cyclictest3547-21CPU15
914499189129,55cyclictest3547-21CPU15
915599188181,5cyclictest0-21swapper/3122:25:2925
915599188181,5cyclictest0-21swapper/3122:25:2925
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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