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2026-09-13 - 06:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Sep 13, 2026 01:02:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
493699216203,6cyclictest0-21swapper/022:41:180
493699216203,6cyclictest0-21swapper/022:41:180
496999209201,7cyclictest0-21swapper/2922:42:5422
496999209201,7cyclictest0-21swapper/2922:42:5422
494599203192,9cyclictest0-21swapper/821:55:4738
494599203192,9cyclictest0-21swapper/821:55:4738
496999198185,12cyclictest0-21swapper/2921:54:4422
496999198185,12cyclictest0-21swapper/2921:54:4422
494099197187,8cyclictest0-21swapper/421:26:3434
494099197187,8cyclictest0-21swapper/421:26:3434
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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