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2026-07-03 - 12:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jul 03, 2026 01:01:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1607599226211,3cyclictest2454-21CPU24
1607599226211,3cyclictest2454-21CPU24
1606399219212,3cyclictest3609-21CPU11
1606399219212,3cyclictest3609-21CPU11
1607399217209,3cyclictest0-21swapper/2819:20:2021
1607399217209,3cyclictest0-21swapper/2819:20:2021
1607599215211,2cyclictest0-21swapper/3021:45:1824
1607599215211,2cyclictest0-21swapper/3021:45:1824
1605599213208,4cyclictest0-21swapper/1321:00:315
1605599213208,4cyclictest0-21swapper/1321:00:305
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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