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2026-09-08 - 19:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Sep 08, 2026 13:02:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3890599222214,6cyclictest0-21swapper/2909:50:2922
3890599222214,6cyclictest0-21swapper/2909:50:2922
3890599220215,3cyclictest4162-21sshd11:21:1722
3890599220215,3cyclictest4162-21sshd11:21:1722
3890599220215,3cyclictest4162-21sshd11:21:1722
3890599209203,4cyclictest0-21swapper/2908:43:1622
3890599208199,7cyclictest0-21swapper/2912:31:3522
3890599208199,7cyclictest0-21swapper/2912:31:3522
3887099208202,4cyclictest0-21swapper/011:33:520
3887099208202,4cyclictest0-21swapper/011:33:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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