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2026-08-16 - 20:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Aug 16, 2026 13:02:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17749921560,151cyclictest0-21swapper/1211:20:184
17749921560,151cyclictest0-21swapper/1211:20:184
17749921560,151cyclictest0-21swapper/1211:20:184
17749921560,151cyclictest0-21swapper/1211:20:184
176599214206,5cyclictest0-21swapper/612:05:2336
176599214206,5cyclictest0-21swapper/612:05:2336
176599207193,12cyclictest0-21swapper/611:55:3436
176599207193,12cyclictest0-21swapper/611:55:3336
176599207191,12cyclictest0-21swapper/610:35:2236
176599207191,12cyclictest0-21swapper/610:35:2136
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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