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2026-02-11 - 23:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Feb 11, 2026 13:02:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1885599230224,4cyclictest0-21swapper/2609:18:1719
1885599230224,4cyclictest0-21swapper/2609:18:1719
1885599230224,4cyclictest0-21swapper/2609:18:1719
1885599224215,7cyclictest28506-21sshd10:38:1719
1885599224215,7cyclictest28506-21sshd10:38:1719
1885599224215,7cyclictest28506-21sshd10:38:1719
1885599216209,4cyclictest2454-21CPU19
1885599216209,4cyclictest2454-21CPU19
1885599216209,4cyclictest2454-21CPU19
1885599214205,7cyclictest0-21swapper/2609:36:4819
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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