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2026-02-21 - 21:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 21, 2026 13:02:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2463899220212,4cyclictest3545-21CPU18
2463899220212,4cyclictest3545-21CPU18
2462799219212,5cyclictest0-21swapper/1509:55:207
2462799219212,5cyclictest0-21swapper/1509:55:207
2462799219212,5cyclictest0-21swapper/1509:55:207
2462799219207,9cyclictest0-21swapper/1511:12:447
2462799219207,9cyclictest0-21swapper/1511:12:437
2462799219207,9cyclictest0-21swapper/1511:12:437
2463899217205,10cyclictest0-21swapper/2511:10:1318
2463899217205,10cyclictest0-21swapper/2511:10:1318
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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