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2026-04-27 - 11:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Apr 27, 2026 01:01:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
106099210201,7cyclictest0-21swapper/3321:11:0427
106099210201,7cyclictest0-21swapper/3321:11:0427
105099206162,41cyclictest37265-21CPU17
105099206162,41cyclictest37265-21CPU17
105099206162,41cyclictest37265-21CPU17
106099205195,7cyclictest0-21swapper/3300:30:2027
106099205195,7cyclictest0-21swapper/3300:30:2027
106099205195,7cyclictest0-21swapper/3300:30:1927
106099203197,4cyclictest0-21swapper/3322:17:4727
106099203197,4cyclictest0-21swapper/3322:17:4627
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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