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2025-12-21 - 08:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Dec 21, 2025 01:00:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
149299923320,14cyclictest0-21swapper/1121:35:083
149299923320,14cyclictest0-21swapper/1121:35:083
1493999212205,5cyclictest0-21swapper/1923:05:2011
1493999212205,5cyclictest0-21swapper/1923:05:1911
1493199212206,5cyclictest0-21swapper/1300:06:575
1493199212206,5cyclictest0-21swapper/1300:06:575
1493199212206,5cyclictest0-21swapper/1300:06:565
1493199210204,4cyclictest0-21swapper/1323:14:045
1493199210204,4cyclictest0-21swapper/1323:14:045
1493199210204,4cyclictest0-21swapper/1323:14:045
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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