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2026-06-20 - 09:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Jun 20, 2026 01:01:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1511199211167,38cyclictest0-21swapper/623:46:1536
1511199211167,38cyclictest0-21swapper/623:46:1436
1511199211167,38cyclictest0-21swapper/623:46:1436
1514199194158,22cyclictest0-21swapper/3100:06:1425
1514199194158,22cyclictest0-21swapper/3100:06:1425
1510799194162,30cyclictest0-21swapper/221:42:1012
1510799194162,30cyclictest0-21swapper/221:42:0912
1510799194162,30cyclictest0-21swapper/221:42:0912
1512699185143,29cyclictest0-21swapper/1700:06:149
1512699185143,29cyclictest0-21swapper/1700:06:149
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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