You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-24 - 13:04
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Dec 24, 2025 00:59:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1884799214203,9cyclictest0-21swapper/1122:57:423
1884799214203,9cyclictest0-21swapper/1122:57:423
1883999214160,22cyclictest0-21swapper/520:20:0335
1886599208200,6cyclictest0-21swapper/2821:10:1921
1886599208200,6cyclictest0-21swapper/2821:10:1921
1886599202166,22cyclictest0-21swapper/2820:05:2221
1886599202166,22cyclictest0-21swapper/2820:05:2221
1887299201167,17cyclictest171rcu_preempt23:24:4626
1887299201167,17cyclictest171rcu_preempt23:24:4626
1886899195141,52cyclictest0-21swapper/3023:27:1224
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional