You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-05-09 - 06:04
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri May 09, 2025 01:01:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
556499268229,16cyclictest0-21swapper/2421:55:1617
556499268229,16cyclictest0-21swapper/2421:55:1617
556499268229,16cyclictest0-21swapper/2421:55:1517
5556992391,62cyclictest0-21swapper/1821:30:1910
5556992391,62cyclictest0-21swapper/1821:30:1910
5556992391,62cyclictest0-21swapper/1821:30:1910
556499227205,4cyclictest0-21swapper/2423:10:1917
556499227205,4cyclictest0-21swapper/2423:10:1917
55799922661,157cyclictest28748-21inotify_reader23:20:2430
55799922661,157cyclictest28748-21inotify_reader23:20:2430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional