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2026-06-06 - 02:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Jun 06, 2026 01:02:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1390799212207,3cyclictest0-21swapper/2123:40:1914
1390799212207,3cyclictest0-21swapper/2123:40:1914
1389999204194,8cyclictest0-21swapper/1522:06:497
1389999204194,8cyclictest0-21swapper/1522:06:497
1389999204194,8cyclictest0-21swapper/1522:06:497
1391499202194,6cyclictest0-21swapper/2721:20:2520
1391499202194,6cyclictest0-21swapper/2721:20:2420
1390399202195,5cyclictest0-21swapper/1722:39:459
1390399202195,5cyclictest0-21swapper/1722:39:459
1390399202195,5cyclictest0-21swapper/1722:39:459
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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