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2025-12-08 - 16:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Dec 08, 2025 13:01:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2613899288248,18cyclictest0-21swapper/510:20:1835
2613899288248,18cyclictest0-21swapper/510:20:1835
2613899288248,18cyclictest0-21swapper/510:20:1835
261859926239,200cyclictest15979-21CPU28
261859926239,200cyclictest15979-21CPU28
261859926239,200cyclictest15979-21CPU28
2613899258218,27cyclictest0-21swapper/512:00:1935
2613899258218,27cyclictest0-21swapper/512:00:1835
2614399244211,21cyclictest9327-21CPU38
2614399244211,21cyclictest9327-21CPU38
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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