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2026-05-27 - 09:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed May 27, 2026 01:01:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2635099216193,20cyclictest0-21swapper/521:12:2935
2635099216193,20cyclictest0-21swapper/521:12:2935
2635099216193,20cyclictest0-21swapper/521:12:2935
2637899211202,6cyclictest0-21swapper/2821:17:4521
2637899211202,6cyclictest0-21swapper/2821:17:4521
2638299206199,5cyclictest0-21swapper/3200:34:2426
2638299206199,5cyclictest0-21swapper/3200:34:2426
2635699206195,8cyclictest13745-21sshd23:11:432
2635699206195,8cyclictest13745-21sshd23:11:432
2638299205195,7cyclictest0-21swapper/3200:35:3226
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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