You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-05 - 18:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Mar 05, 2026 13:03:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2124499243238,2cyclictest0-21swapper/1412:14:116
2124499243238,2cyclictest0-21swapper/1412:14:116
2124499243238,2cyclictest0-21swapper/1412:14:116
2124599239214,15cyclictest0-21swapper/1511:00:017
2124599239214,15cyclictest0-21swapper/1511:00:017
2124599239214,15cyclictest0-21swapper/1511:00:007
2126099228221,5cyclictest0-21swapper/2711:05:2220
2126099228221,5cyclictest0-21swapper/2711:05:2220
2123599221217,2cyclictest0-21swapper/707:10:1937
2123599221217,2cyclictest0-21swapper/707:10:1937
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional