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2026-07-08 - 03:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Jul 08, 2026 01:02:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3199499219208,6cyclictest37352-21CPU18
3199499219208,6cyclictest37352-21CPU18
3200999213205,5cyclictest1384-21rs:main31
3200999213205,5cyclictest1384-21rs:main31
3197799213201,10cyclictest0-21swapper/1023:28:112
3197799213201,10cyclictest0-21swapper/1023:28:112
3200299212207,4cyclictest0-21swapper/3122:32:3325
3200299212207,4cyclictest0-21swapper/3122:32:3325
3200299212207,4cyclictest0-21swapper/3122:32:3325
3199499212201,7cyclictest2456-21CPU18
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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