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2025-12-28 - 10:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Dec 28, 2025 01:00:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
66799202191,9cyclictest0-21swapper/2300:09:0616
66799202191,9cyclictest0-21swapper/2300:09:0616
62699201192,8cyclictest0-21swapper/219:22:0012
62699201192,8cyclictest0-21swapper/219:22:0012
63499199189,9cyclictest0-21swapper/700:09:0537
63499199189,9cyclictest0-21swapper/700:09:0537
70199198193,3cyclictest0-21swapper/3400:20:2028
70199198193,3cyclictest0-21swapper/3400:20:2028
63499196180,14cyclictest0-21swapper/723:56:0537
63499196180,14cyclictest0-21swapper/723:56:0537
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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