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2026-02-08 - 04:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Feb 08, 2026 01:03:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
419099198192,5cyclictest0-21swapper/3819:19:0832
419099198192,5cyclictest0-21swapper/3819:19:0832
417699196188,5cyclictest37346-21qemu-system-x8621:43:2618
417699196188,5cyclictest37346-21qemu-system-x8621:43:2618
417699193178,11cyclictest0-21swapper/2523:40:2018
417699193178,11cyclictest0-21swapper/2523:40:2018
417699193178,11cyclictest0-21swapper/2523:40:1918
419099189174,10cyclictest0-21swapper/3823:32:5132
419099189174,10cyclictest0-21swapper/3823:32:5032
418399187173,8cyclictest0-21swapper/3219:40:0826
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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