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2026-09-22 - 22:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Sep 22, 2026 13:01:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38275992331,229cyclictest0-21swapper/812:35:2338
38275992331,229cyclictest0-21swapper/812:35:2338
38275992331,229cyclictest0-21swapper/812:35:2338
38275992251,212cyclictest0-21swapper/812:31:2638
38275992251,212cyclictest0-21swapper/812:31:2538
3828499224215,6cyclictest0-21swapper/1609:00:178
3828499224215,6cyclictest0-21swapper/1609:00:168
3827699221206,10cyclictest37357-21CPU39
3827699221206,10cyclictest37357-21CPU39
3829999216213,2cyclictest0-21swapper/2908:50:1822
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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