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2026-05-24 - 11:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun May 24, 2026 01:02:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13022992491,244cyclictest0-21swapper/823:50:2038
13022992491,244cyclictest0-21swapper/823:50:1938
13022992491,244cyclictest0-21swapper/823:50:1938
13022992481,242cyclictest0-21swapper/820:00:1438
13022992481,242cyclictest0-21swapper/820:00:1438
13022992441,2cyclictest0-21swapper/819:50:2238
13022992421,238cyclictest0-21swapper/820:40:1338
13022992421,238cyclictest0-21swapper/820:40:1238
13022992411,237cyclictest0-21swapper/821:48:5538
13022992411,237cyclictest0-21swapper/821:48:5538
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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