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2026-07-17 - 06:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jul 17, 2026 01:01:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
76899226212,8cyclictest19562-21cstates21:15:1733
76899226212,8cyclictest19562-21cstates21:15:1733
76899226212,8cyclictest19562-21cstates21:15:1733
73399222209,11cyclictest0-21swapper/921:00:1539
73399222209,11cyclictest0-21swapper/921:00:1539
75499215211,2cyclictest0-21swapper/2722:53:2020
75499215211,2cyclictest0-21swapper/2722:53:2020
76899214195,9cyclictest0-21swapper/3922:50:4433
76899214195,9cyclictest0-21swapper/3922:50:4333
73399214208,4cyclictest0-21swapper/900:00:1839
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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