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2026-08-20 - 14:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Aug 20, 2026 13:02:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
228639921094,109cyclictest0-21swapper/1309:20:395
228639921094,109cyclictest0-21swapper/1309:20:385
228639921094,109cyclictest0-21swapper/1309:20:385
2288599194181,10cyclictest0-21swapper/3209:30:3826
2288599194181,10cyclictest0-21swapper/3209:30:3826
2287299191182,7cyclictest0-21swapper/2012:05:3213
2287299191182,7cyclictest0-21swapper/2012:05:3113
2287299191182,7cyclictest0-21swapper/2012:05:3113
2288599186124,29cyclictest0-21swapper/3212:26:1426
2288599186124,29cyclictest0-21swapper/3212:26:1326
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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