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2026-05-17 - 07:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun May 17, 2026 01:01:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3317599231223,5cyclictest6408-21sshd22:54:0331
3317599231223,5cyclictest6408-21sshd22:54:0331
3317599225216,5cyclictest2454-21CPU31
3317599225216,5cyclictest2454-21CPU31
3317599225216,5cyclictest2454-21CPU31
3317599215209,4cyclictest0-21swapper/3721:12:0931
3317599215209,4cyclictest0-21swapper/3721:12:0831
3317599211197,12cyclictest0-21swapper/3722:24:0631
3317599211197,12cyclictest0-21swapper/3722:24:0631
3317599210205,2cyclictest0-21swapper/3721:45:1531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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