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2026-07-29 - 21:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Jul 29, 2026 13:02:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2292499249108,128cyclictest0-21swapper/3311:10:2027
2292499249108,128cyclictest0-21swapper/3311:10:2027
2292499249108,128cyclictest0-21swapper/3311:10:2027
2289899241215,12cyclictest0-21swapper/1207:20:144
2289899241215,12cyclictest0-21swapper/1207:20:134
2289899226212,5cyclictest0-21swapper/1211:10:214
2289899226212,5cyclictest0-21swapper/1211:10:214
2289899226212,5cyclictest0-21swapper/1211:10:214
2289899226209,7cyclictest3546-21CPU4
2289899226209,7cyclictest3546-21CPU4
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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