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2026-07-10 - 08:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jul 10, 2026 01:02:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1866099222217,3cyclictest0-21swapper/1200:20:234
1866099222217,3cyclictest0-21swapper/1200:20:224
1868899214209,3cyclictest0-21swapper/3500:20:1929
1868899214209,3cyclictest0-21swapper/3500:20:1829
1864899207197,7cyclictest0-21swapper/023:01:290
1864899207197,7cyclictest0-21swapper/023:01:290
1864899206201,4cyclictest0-21swapper/023:37:570
1864899206201,4cyclictest0-21swapper/023:37:560
1867299200193,5cyclictest0-21swapper/2222:22:3615
1867299200193,5cyclictest0-21swapper/2222:22:3515
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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