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2026-04-25 - 13:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Apr 25, 2026 01:01:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3323599211202,7cyclictest0-21swapper/1322:03:255
3323599211202,7cyclictest0-21swapper/1322:03:245
3324799210194,13cyclictest0-21swapper/2322:45:1816
3324799210194,13cyclictest0-21swapper/2322:45:1816
3324599204192,10cyclictest0-21swapper/2123:56:1714
3324599204192,10cyclictest0-21swapper/2123:56:1714
3324599204192,10cyclictest0-21swapper/2123:56:1714
3324799203190,6cyclictest0-21swapper/2323:49:0216
3324799203190,6cyclictest0-21swapper/2323:49:0216
3326099202193,6cyclictest18392-21sshd22:50:0027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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