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2026-05-30 - 18:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat May 30, 2026 13:02:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18357992020,189cyclictest1384-21rs:main27
18357992020,189cyclictest1384-21rs:main27
1834799188178,8cyclictest0-21swapper/2311:20:0916
1834799188178,8cyclictest0-21swapper/2311:20:0916
1834799188178,8cyclictest0-21swapper/2311:20:0916
1832999184176,6cyclictest0-21swapper/810:07:2838
1832999184176,6cyclictest0-21swapper/810:07:2838
1832999184176,6cyclictest0-21swapper/810:07:2838
1832899182152,12cyclictest0-21swapper/710:45:3337
1832899182152,12cyclictest0-21swapper/710:45:3337
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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