You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-13 - 07:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Jan 13, 2026 00:59:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
658399372363,7cyclictest372-21kswapd000:07:5613
658399372363,7cyclictest372-21kswapd000:07:5613
656399372367,3cyclictest372-21kswapd000:07:5836
656399372367,3cyclictest372-21kswapd000:07:5836
659399324319,3cyclictest372-21kswapd023:55:0422
659399324319,3cyclictest372-21kswapd023:55:0422
658899295286,7cyclictest372-21kswapd000:07:5618
658899295286,7cyclictest372-21kswapd000:07:5618
655999278272,4cyclictest372-21kswapd000:07:5612
655999278272,4cyclictest372-21kswapd000:07:5612
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional