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2026-03-03 - 04:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Mar 03, 2026 01:02:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2497699200192,6cyclictest0-21swapper/1223:42:234
2497699200192,6cyclictest0-21swapper/1223:42:234
2497699200192,6cyclictest0-21swapper/1223:42:224
2498899195179,14cyclictest0-21swapper/2200:15:0115
2498899195179,14cyclictest0-21swapper/2200:15:0015
2499499192156,13cyclictest5805-21kworker/u81:3-events_unbound00:05:0720
2499499192156,13cyclictest5805-21kworker/u81:3-events_unbound00:05:0620
2497699192186,4cyclictest0-21swapper/1222:00:414
2497699192186,4cyclictest0-21swapper/1222:00:404
2497699192184,6cyclictest0-21swapper/1222:13:304
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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