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2025-12-13 - 05:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Dec 13, 2025 00:57:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1714599191175,14cyclictest0-21swapper/2619:18:4419
17147991881,103cyclictest0-21swapper/2821:35:2521
17147991881,103cyclictest0-21swapper/2821:35:2521
1712999188131,52cyclictest37263-21CPU2
1712999188131,52cyclictest37263-21CPU2
17147991872,92cyclictest2454-21CPU21
17147991872,92cyclictest2454-21CPU21
17119991840,2cyclictest0-21swapper/022:00:140
17119991840,2cyclictest0-21swapper/022:00:140
1712999183142,39cyclictest0-21swapper/1020:45:032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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