You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-22 - 17:09
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Apr 22, 2026 13:03:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14590992520,248cyclictest0-21swapper/3209:30:2526
14590992520,248cyclictest0-21swapper/3209:30:2426
14590992381,233cyclictest0-21swapper/3212:20:0026
14590992381,233cyclictest0-21swapper/3212:19:5926
14590992301,225cyclictest0-21swapper/3211:15:1826
14590992301,225cyclictest0-21swapper/3211:15:1726
14590992291,223cyclictest0-21swapper/3208:00:1926
14590992291,223cyclictest0-21swapper/3208:00:1926
14590992290,226cyclictest0-21swapper/3208:10:1326
14590992290,226cyclictest0-21swapper/3208:10:1326
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional