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2026-08-11 - 09:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Aug 11, 2026 01:01:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
319699204199,4cyclictest0-21swapper/1821:25:1510
319699204199,4cyclictest0-21swapper/1821:25:1510
319699204193,9cyclictest0-21swapper/1820:10:2310
319699204193,9cyclictest0-21swapper/1820:10:2310
319699199181,14cyclictest0-21swapper/1821:25:0110
319699199181,14cyclictest0-21swapper/1821:25:0110
322299198192,4cyclictest34304-21kworker/u82:0+events_unbound22:42:4133
322299198192,4cyclictest34304-21kworker/u82:0+events_unbound22:42:4133
319699197186,8cyclictest33468-21systemd21:15:2610
319699197186,8cyclictest33468-21systemd21:15:2610
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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