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2025-12-10 - 01:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Dec 09, 2025 13:01:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2584899227221,2cyclictest26592-21inotify_reader12:00:1819
2584899227221,2cyclictest26592-21inotify_reader12:00:1819
2584899227221,2cyclictest26592-21inotify_reader12:00:1819
2584899222208,10cyclictest15980-21CPU19
2584899222208,10cyclictest15980-21CPU19
2584899222208,10cyclictest15980-21CPU19
258199922013,195cyclictest9578-21NetworkChangeNo09:25:191
258199922013,195cyclictest9578-21NetworkChangeNo09:25:191
2584899219197,7cyclictest0-21swapper/2611:35:1819
2584899219197,7cyclictest0-21swapper/2611:35:1819
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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