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2026-08-26 - 12:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Wed Aug 26, 2026 01:01:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
257999207204,2cyclictest0-21swapper/823:11:5138
257999207204,2cyclictest0-21swapper/823:11:5138
257999207204,2cyclictest0-21swapper/823:11:5138
259499202194,6cyclictest16034-21kworker/u81:1+events_unbound21:15:2214
259499202194,6cyclictest16034-21kworker/u81:1+events_unbound21:15:2214
259699201164,34cyclictest0-21swapper/2220:03:0615
259699201164,34cyclictest0-21swapper/2220:03:0615
259399198193,4cyclictest0-21swapper/2020:42:1513
259399198193,4cyclictest0-21swapper/2020:42:1513
261299195186,5cyclictest0-21swapper/3721:29:4231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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