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2026-11-15 - 05:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Nov 15, 2026 01:01:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2383199212147,59cyclictest4796-21CPU29
2383199212147,59cyclictest4796-21CPU29
2383399206174,30cyclictest0-21swapper/3722:23:4631
2383399206174,30cyclictest0-21swapper/3722:23:4631
2379599202133,65cyclictest4630-21CPU35
2379599202133,65cyclictest4630-21CPU35
2383399199140,43cyclictest0-21swapper/3721:30:4831
2383399199140,43cyclictest0-21swapper/3721:30:4831
2379599199194,3cyclictest0-21swapper/521:29:5935
2379599199194,3cyclictest0-21swapper/521:29:5935
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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