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2026-01-24 - 16:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Jan 24, 2026 13:01:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2521999209202,3cyclictest3544-21CPU6
2521999209202,3cyclictest3544-21CPU6
2521999209202,3cyclictest3544-21CPU6
2521999207199,5cyclictest0-21swapper/1412:29:326
2521999207199,5cyclictest0-21swapper/1412:29:326
2521999207199,5cyclictest0-21swapper/1412:29:316
2524099206155,48cyclictest0-21swapper/3112:13:1125
2524099206155,48cyclictest0-21swapper/3112:13:1125
2524099206155,48cyclictest0-21swapper/3112:13:1125
2521999204197,3cyclictest4408-21CPU6
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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