You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-30 - 11:25
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Nov 30, 2025 01:00:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
275999233212,10cyclictest0-21swapper/1022:20:202
275999233212,10cyclictest0-21swapper/1022:20:202
275999230208,10cyclictest34380-21inotify_reader19:55:192
275999230208,10cyclictest34380-21inotify_reader19:55:192
2748992281,81cyclictest0-21swapper/221:20:2012
2748992281,81cyclictest0-21swapper/221:20:1912
278099227200,13cyclictest15978-21CPU10
278099227200,13cyclictest15978-21CPU10
275899226193,23cyclictest27274-21inotify_reader22:00:2139
275899226193,23cyclictest27274-21inotify_reader22:00:2139
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional