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2026-06-05 - 01:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Jun 04, 2026 13:02:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2393999232213,14cyclictest0-21swapper/511:15:0135
2393999232213,14cyclictest0-21swapper/511:15:0135
2395999227215,4cyclictest37355-21CPU15
2395999227215,4cyclictest37355-21CPU15
2396099225214,2cyclictest0-21swapper/2309:55:2716
2396099225214,2cyclictest0-21swapper/2309:55:2716
2396099225214,2cyclictest0-21swapper/2309:55:2616
2394099219211,4cyclictest0-21swapper/611:15:1836
2394099219211,4cyclictest0-21swapper/611:15:1836
2394099219211,4cyclictest0-21swapper/611:15:1836
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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