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2026-02-26 - 08:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Feb 26, 2026 01:02:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1739899251244,4cyclictest0-21swapper/722:25:1237
1739899251244,4cyclictest0-21swapper/722:25:1237
1739299217196,16cyclictest0-21swapper/321:40:0023
1739299217196,16cyclictest0-21swapper/321:39:5923
1739299217196,16cyclictest0-21swapper/321:39:5923
1739599215208,5cyclictest0-21swapper/421:25:5534
1739599215208,5cyclictest0-21swapper/421:25:5534
1743099211205,4cyclictest20744-21cpuspeed_turbos23:55:1330
1743099211205,4cyclictest20744-21cpuspeed_turbos23:55:1230
1743099211205,4cyclictest20744-21cpuspeed_turbos23:55:1230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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