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2026-03-03 - 16:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Mar 03, 2026 13:03:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3397599228217,7cyclictest0-21swapper/1410:13:046
3397599228217,7cyclictest0-21swapper/1410:13:046
3397999207199,5cyclictest2454-21CPU10
3397999207199,5cyclictest2454-21CPU10
3397999207199,5cyclictest2454-21CPU10
3397299203193,6cyclictest37346-21qemu-system-x8611:57:533
3397299203193,6cyclictest37346-21qemu-system-x8611:57:533
3397299203193,6cyclictest37346-21qemu-system-x8611:57:523
3397699199191,6cyclictest0-21swapper/1509:21:347
3397699199191,6cyclictest0-21swapper/1509:21:347
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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