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2025-12-02 - 20:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Dec 02, 2025 13:01:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3642299341325,3cyclictest21722-21NetworkChangeNo11:25:179
3642299341325,3cyclictest21722-21NetworkChangeNo11:25:179
3642299341325,3cyclictest21722-21NetworkChangeNo11:25:179
3642699260232,10cyclictest0-21swapper/2107:15:0514
3642699260232,10cyclictest0-21swapper/2107:15:0514
3641499253229,10cyclictest15984-21CPU2
3641499253229,10cyclictest15984-21CPU2
3644399248229,4cyclictest7811-21TaskSchedulerSi11:20:1928
3644399248229,4cyclictest7811-21TaskSchedulerSi11:20:1928
3644399248229,4cyclictest7811-21TaskSchedulerSi11:20:1928
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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