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2026-05-02 - 21:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat May 02, 2026 13:02:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3979999230200,27cyclictest0-21swapper/1412:00:226
3979999230200,27cyclictest0-21swapper/1412:00:216
3981199225175,21cyclictest0-21swapper/2410:32:3017
3981199225175,21cyclictest0-21swapper/2410:32:3017
3979999223204,10cyclictest0-21swapper/1411:10:016
3979999223204,10cyclictest0-21swapper/1411:10:006
3979999223204,10cyclictest0-21swapper/1411:10:006
3979999222205,10cyclictest3600-21qemu-system-x8611:49:406
3979999222205,10cyclictest3600-21qemu-system-x8611:49:396
3979999222205,10cyclictest3600-21qemu-system-x8611:49:396
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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