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2026-08-02 - 17:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Aug 02, 2026 13:02:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5326992201,4cyclictest3535-21qemu-system-x8608:46:1235
5326992201,4cyclictest3535-21qemu-system-x8608:46:1135
5326992191,8cyclictest3762-21bash11:48:1135
5326992191,8cyclictest3762-21bash11:48:1035
5326992191,8cyclictest3762-21bash11:48:1035
533899200193,5cyclictest0-21swapper/1509:15:117
533899200193,5cyclictest0-21swapper/1509:15:117
536799199194,4cyclictest0-21swapper/3907:30:0333
536799199194,4cyclictest0-21swapper/3907:30:0233
536799197187,8cyclictest1367-21dbus-daemon09:57:0033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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