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2026-06-19 - 18:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Jun 19, 2026 13:02:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3000499210205,4cyclictest0-21swapper/2712:31:3620
3000499210205,4cyclictest0-21swapper/2712:31:3620
3000499202195,3cyclictest3544-21CPU20
3000499202195,3cyclictest3544-21CPU20
3000499199193,4cyclictest0-21swapper/2712:12:4320
3000499199193,4cyclictest0-21swapper/2712:12:4320
3000499199193,4cyclictest0-21swapper/2712:06:0620
3000499199193,4cyclictest0-21swapper/2712:06:0620
3000499197190,5cyclictest0-21swapper/2712:18:5520
3000499197190,5cyclictest0-21swapper/2712:18:5520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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