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2026-06-09 - 18:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Jun 09, 2026 13:02:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3098399213195,9cyclictest0-21swapper/2709:37:1820
3098399213195,9cyclictest0-21swapper/2709:37:1820
3098399201185,14cyclictest0-21swapper/2709:20:1320
3098399201185,14cyclictest0-21swapper/2709:20:1320
3098399198191,5cyclictest0-21swapper/2710:37:3120
3098399198191,5cyclictest0-21swapper/2710:37:3120
3098399198191,5cyclictest0-21swapper/2710:37:3120
3095199197159,28cyclictest0-21swapper/011:27:090
3095199197159,28cyclictest0-21swapper/011:27:090
3095199197159,28cyclictest0-21swapper/011:27:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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