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2026-07-14 - 02:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Jul 14, 2026 01:01:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2837999218213,3cyclictest0-21swapper/2519:45:0118
2837999218213,3cyclictest0-21swapper/2519:45:0018
2835699217213,3cyclictest0-21swapper/620:05:3036
2835699217213,3cyclictest0-21swapper/620:05:3036
2835499213206,5cyclictest0-21swapper/423:46:5434
2835499213206,5cyclictest0-21swapper/423:46:5434
2835199213203,6cyclictest2327-21qemu-system-x8621:20:231
2835199213203,6cyclictest2327-21qemu-system-x8621:20:231
2835199213203,6cyclictest2327-21qemu-system-x8621:20:221
2835899212198,12cyclictest0-21swapper/823:36:5438
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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