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2026-02-21 - 02:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 21, 2026 01:01:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
562699185117,60cyclictest4407-21CPU31
562699185117,60cyclictest4407-21CPU31
562199185150,25cyclictest0-21swapper/3419:51:0328
562199185150,25cyclictest0-21swapper/3419:51:0328
559299185175,4cyclictest37354-21CPU39
559299185175,4cyclictest37354-21CPU39
561399184134,8cyclictest0-21swapper/2823:30:5921
561399184134,8cyclictest0-21swapper/2823:30:5921
558999184143,38cyclictest0-21swapper/723:03:1637
558999184143,38cyclictest0-21swapper/723:03:1637
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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