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2026-02-27 - 11:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Feb 27, 2026 01:02:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3550799594582,10cyclictest373-21kswapd122:47:0724
3550799594582,10cyclictest373-21kswapd122:47:0624
3550799594582,10cyclictest373-21kswapd122:47:0624
3551399422419,2cyclictest373-21kswapd122:47:0730
3551399422419,2cyclictest373-21kswapd122:47:0730
3551399422419,2cyclictest373-21kswapd122:47:0630
3551099383373,8cyclictest373-21kswapd122:47:0927
3551099383373,8cyclictest373-21kswapd122:47:0927
3551099383373,8cyclictest373-21kswapd122:47:0927
3550699366349,13cyclictest7558-21kworker/u81:2+events_unbound22:47:0922
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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