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2025-12-27 - 07:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Dec 27, 2025 01:00:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3164699215200,11cyclictest37354-21CPU33
3164699215200,11cyclictest37354-21CPU33
3164699215200,11cyclictest37354-21CPU33
31618992151,2cyclictest0-21swapper/1522:00:127
31618992151,2cyclictest0-21swapper/1522:00:127
31618992151,2cyclictest0-21swapper/1522:00:127
3160199215203,8cyclictest3545-21CPU1
3160199215203,8cyclictest3545-21CPU1
3160199215203,8cyclictest3545-21CPU1
3160199211198,10cyclictest0-21swapper/100:40:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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