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2025-12-11 - 20:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Dec 11, 2025 13:02:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3812199274239,29cyclictest5046-21inotify_reader09:10:1935
3812199274239,29cyclictest5046-21inotify_reader09:10:1935
3812199261224,27cyclictest37357-21TaskSchedulerSi07:55:2135
3812199261224,27cyclictest37357-21TaskSchedulerSi07:55:2135
3812199250223,14cyclictest0-21swapper/510:10:1835
3812199250223,14cyclictest0-21swapper/510:10:1835
38126992421,91cyclictest0-21swapper/908:20:1939
38126992421,91cyclictest0-21swapper/908:20:1939
3812099239207,16cyclictest0-21swapper/411:35:2334
3812099239207,16cyclictest0-21swapper/411:35:2334
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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