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2026-02-19 - 12:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Feb 19, 2026 01:02:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1109499245180,53cyclictest0-21swapper/3822:17:0632
1109499245180,53cyclictest0-21swapper/3822:17:0632
1107399210200,8cyclictest0-21swapper/2122:10:3114
1107399210200,8cyclictest0-21swapper/2122:10:3114
1107399204198,4cyclictest0-21swapper/2120:35:1214
1107399204198,4cyclictest0-21swapper/2120:35:1214
1106599200157,34cyclictest0-21swapper/1500:12:457
1106599200157,34cyclictest0-21swapper/1500:12:457
1106599200157,34cyclictest0-21swapper/1500:12:447
1106299199117,67cyclictest0-21swapper/1200:15:184
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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