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2026-08-26 - 00:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Aug 25, 2026 13:02:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1484899208200,6cyclictest0-21swapper/1511:10:137
1484899208200,6cyclictest0-21swapper/1511:10:137
1484899207198,5cyclictest1430-21polkitd09:40:197
1484899207198,5cyclictest1430-21polkitd09:40:197
1483699207177,26cyclictest0-21swapper/512:27:1835
1483699207177,26cyclictest0-21swapper/512:27:1835
1483699207177,26cyclictest0-21swapper/512:27:1735
1483299207172,17cyclictest0-21swapper/110:55:461
1483299207172,17cyclictest0-21swapper/110:55:451
1483299207172,17cyclictest0-21swapper/110:55:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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