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2026-07-30 - 10:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Thu Jul 30, 2026 01:01:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2332399220214,5cyclictest0-21swapper/1523:32:427
2332399220214,5cyclictest0-21swapper/1523:32:427
2332399208198,7cyclictest0-21swapper/1523:25:207
2332399208198,7cyclictest0-21swapper/1523:25:207
2334899206197,7cyclictest0-21swapper/3622:30:3130
2334899206197,7cyclictest0-21swapper/3622:30:3030
2334899203194,7cyclictest0-21swapper/3623:14:2130
2334899203194,7cyclictest0-21swapper/3623:14:2030
2334899203194,7cyclictest0-21swapper/3623:14:2030
2332399199190,7cyclictest0-21swapper/1500:15:197
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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