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2025-12-08 - 08:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Dec 08, 2025 01:00:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1943299261225,17cyclictest0-21swapper/821:55:1938
1943299261225,17cyclictest0-21swapper/821:55:1938
19429992561,242cyclictest12788-21sshd22:35:1935
19429992561,242cyclictest12788-21sshd22:35:1935
1943299252222,11cyclictest15978-21CPU38
1943299252222,11cyclictest15978-21CPU38
1945599248240,4cyclictest4624-21qemu-system-x8600:00:2118
1945599248240,4cyclictest4624-21qemu-system-x8600:00:2118
1943299235198,20cyclictest11392-21TaskSchedulerSi21:50:1938
1943299235198,20cyclictest11392-21TaskSchedulerSi21:50:1938
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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