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2025-12-06 - 11:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Dec 06, 2025 01:00:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3605099253212,17cyclictest33424-21TaskSchedulerSi23:30:2024
3605099253212,17cyclictest33424-21TaskSchedulerSi23:30:1924
3600499245228,3cyclictest36795-21nfsd20:05:171
3600499245228,3cyclictest36795-21nfsd20:05:171
3605099244215,12cyclictest137350irq/45-eno1-TxRx-323:55:2124
3605099244215,12cyclictest137350irq/45-eno1-TxRx-323:55:2124
3605099239232,3cyclictest0-21swapper/3020:16:2424
3605099239232,3cyclictest0-21swapper/3020:16:2424
360379923438,176cyclictest16717-21NetworkChangeNo20:20:1918
360379923438,176cyclictest16717-21NetworkChangeNo20:20:1918
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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