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2025-12-07 - 13:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sun Dec 07, 2025 01:00:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4052599274271,2cyclictest0-21swapper/2021:17:4513
4052599274271,2cyclictest0-21swapper/2021:17:4513
4052599274271,2cyclictest0-21swapper/2021:17:4513
40517992231,92cyclictest0-21swapper/1520:40:227
40517992231,92cyclictest0-21swapper/1520:40:227
4052599222161,23cyclictest0-21swapper/2023:45:1913
4052599222161,23cyclictest0-21swapper/2023:45:1913
4052599222161,23cyclictest0-21swapper/2023:45:1913
405139922032,49cyclictest0-21swapper/1122:25:223
405139922032,49cyclictest0-21swapper/1122:25:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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