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2026-06-23 - 13:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Tue Jun 23, 2026 01:01:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2229899205202,2cyclictest0-21swapper/919:15:2639
2229899205202,2cyclictest0-21swapper/919:15:2639
2229699204186,12cyclictest0-21swapper/721:15:2837
2229699204186,12cyclictest0-21swapper/721:15:2837
2229699204186,12cyclictest0-21swapper/721:15:2837
2230799202180,12cyclictest1430-21polkitd22:01:439
2230799202180,12cyclictest1430-21polkitd22:01:439
2230799202180,12cyclictest1430-21polkitd22:01:429
2233299200197,2cyclictest0-21swapper/3919:20:1733
2233299200197,2cyclictest0-21swapper/3919:20:1733
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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