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2025-11-28 - 15:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Fri Nov 28, 2025 13:01:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1146299275240,16cyclictest36511-21TaskSchedulerSi11:30:1823
1146299275240,16cyclictest36511-21TaskSchedulerSi11:30:1823
1146299256229,12cyclictest7399-21sshd10:55:1823
1146299256229,12cyclictest7399-21sshd10:55:1823
11453992411,232cyclictest0-21swapper/010:55:180
11453992411,232cyclictest0-21swapper/010:55:180
1157799238207,15cyclictest21411-21NetworkChangeNo09:25:1829
1157799238207,15cyclictest21411-21NetworkChangeNo09:25:1829
1157799238207,15cyclictest21411-21NetworkChangeNo09:25:1829
1146299232216,5cyclictest9327-21CPU23
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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