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2026-08-31 - 06:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Mon Aug 31, 2026 01:01:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3774999193138,52cyclictest37357-21CPU3
3774999193138,52cyclictest37357-21CPU3
3773899192176,13cyclictest0-21swapper/223:47:2712
3773899192176,13cyclictest0-21swapper/223:47:2712
3773899192163,13cyclictest0-21swapper/223:54:3212
3773899192163,13cyclictest0-21swapper/223:54:3212
3778199184175,7cyclictest0-21swapper/3922:44:1733
3778199184175,7cyclictest0-21swapper/3922:44:1733
3778199184173,9cyclictest0-21swapper/3921:34:0733
3778199184173,9cyclictest0-21swapper/3921:34:0733
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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