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2026-08-01 - 16:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot0.osadl.org (updated Sat Aug 01, 2026 13:02:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3833899223216,3cyclictest3545-21CPU39
3833899223216,3cyclictest3545-21CPU39
3833899221214,5cyclictest0-21swapper/910:01:1239
3833899221214,5cyclictest0-21swapper/910:01:1239
3833899221214,5cyclictest0-21swapper/910:01:1239
3835299217212,3cyclictest0-21swapper/2212:37:2715
3835299217212,3cyclictest0-21swapper/2212:37:2715
3833899217208,6cyclictest0-21swapper/912:17:2339
3833899217208,6cyclictest0-21swapper/912:17:2339
3834099216209,4cyclictest0-21swapper/1108:15:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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