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2026-02-04 - 13:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Feb 04, 2026 01:02:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3961799239233,4cyclictest0-21swapper/1421:35:286
3961799239233,4cyclictest0-21swapper/1421:35:286
3961599224211,10cyclictest0-21swapper/1323:52:185
3961599224211,10cyclictest0-21swapper/1323:52:185
3962499222198,20cyclictest0-21swapper/2121:40:1514
3962499222198,20cyclictest0-21swapper/2121:40:1514
3964499219215,2cyclictest0-21swapper/3722:15:1331
3964499219215,2cyclictest0-21swapper/3722:15:1331
3963699213209,2cyclictest0-21swapper/3222:50:1826
3963699213209,2cyclictest0-21swapper/3222:50:1826
3963699213209,2cyclictest0-21swapper/3222:50:1826
3962599210154,52cyclictest2461-21CPU15
3962599210154,52cyclictest2461-21CPU15
3962599210154,52cyclictest2461-21CPU15
3961599206198,5cyclictest1358-21ModemManager23:20:375
3961599206198,5cyclictest1358-21ModemManager23:20:375
3961599206198,5cyclictest1358-21ModemManager23:20:365
3963299204199,4cyclictest0-21swapper/2800:31:1821
3963299204199,4cyclictest0-21swapper/2800:31:1721
3963299204198,4cyclictest0-21swapper/2800:20:1621
3963299204198,4cyclictest0-21swapper/2800:20:1521
3963299204198,4cyclictest0-21swapper/2800:20:1521
3963399203191,9cyclictest0-21swapper/2920:40:2222
3963399203191,9cyclictest0-21swapper/2920:40:2222
3963299203197,5cyclictest0-21swapper/2823:51:2621
3963299203197,5cyclictest0-21swapper/2823:51:2621
3963299203186,13cyclictest0-21swapper/2800:28:0521
3963299203186,13cyclictest0-21swapper/2800:28:0421
3961099203197,4cyclictest0-21swapper/923:23:1339
3961099203197,4cyclictest0-21swapper/923:23:1339
3961099203197,4cyclictest0-21swapper/923:23:1339
3964599201198,2cyclictest0-21swapper/3821:25:1932
3964599201198,2cyclictest0-21swapper/3821:25:1932
3962499201149,43cyclictest3544-21CPU14
3962499201149,43cyclictest3544-21CPU14
3962499201149,43cyclictest3544-21CPU14
3961599201133,54cyclictest3610-21CPU5
3961599201133,54cyclictest3610-21CPU5
3962499200179,19cyclictest0-21swapper/2121:21:2814
3962499200179,19cyclictest0-21swapper/2121:21:2814
3961599200160,31cyclictest0-21swapper/1321:38:045
3961599200160,31cyclictest0-21swapper/1321:38:045
3963299199193,4cyclictest0-21swapper/2800:12:1521
3963299199193,4cyclictest0-21swapper/2800:12:1421
39625991993,190cyclictest2464-21CPU15
39625991993,190cyclictest2464-21CPU15
39625991991,2cyclictest0-21swapper/2222:50:1515
39625991991,2cyclictest0-21swapper/2222:50:1515
39625991991,2cyclictest0-21swapper/2222:50:1415
3962499199192,5cyclictest0-21swapper/2121:50:0014
3962499199192,5cyclictest0-21swapper/2121:50:0014
3961099199193,4cyclictest0-21swapper/923:26:2939
3961099199193,4cyclictest0-21swapper/923:26:2939
3963299198190,5cyclictest0-21swapper/2800:05:0621
3963299198190,5cyclictest0-21swapper/2800:05:0521
3963299198188,8cyclictest0-21swapper/2822:13:4621
3963299198188,8cyclictest0-21swapper/2822:13:4521
3963299198188,8cyclictest0-21swapper/2822:13:4521
3963299198181,10cyclictest0-21swapper/2820:50:0921
3963299198181,10cyclictest0-21swapper/2820:50:0921
3963399197192,4cyclictest0-21swapper/2922:26:4722
3963399197192,4cyclictest0-21swapper/2922:26:4622
3963399197191,4cyclictest0-21swapper/2922:15:1722
3963399197191,4cyclictest0-21swapper/2922:15:1622
3962499197185,7cyclictest0-21swapper/2122:50:1714
3962499197185,7cyclictest0-21swapper/2122:50:1614
3962499197185,7cyclictest0-21swapper/2122:50:1614
3960999197166,23cyclictest2456-21CPU38
3963399196187,7cyclictest0-21swapper/2923:50:4622
3963399196187,7cyclictest0-21swapper/2923:50:4622
3963299196187,4cyclictest2459-21CPU21
3963299196187,4cyclictest2459-21CPU21
3960799196187,6cyclictest0-21swapper/619:20:2736
3960199196188,6cyclictest0-21swapper/100:39:281
3960199196188,6cyclictest0-21swapper/100:39:271
3963399195188,5cyclictest0-21swapper/2922:30:2522
3963399195188,5cyclictest0-21swapper/2922:30:2422
3963299195191,3cyclictest0-21swapper/2820:00:0321
3963299195187,5cyclictest0-21swapper/2800:17:1421
3963299195187,5cyclictest0-21swapper/2800:17:1321
3961099195184,9cyclictest23277-21kworker/u81:5-events_unbound23:00:5839
3961099195184,9cyclictest23277-21kworker/u81:5-events_unbound23:00:5839
3961099195184,9cyclictest23277-21kworker/u81:5-events_unbound23:00:5839
3964499194189,3cyclictest0-21swapper/3700:05:1931
3964499194189,3cyclictest0-21swapper/3700:05:1931
3964499194189,3cyclictest0-21swapper/3700:05:1831
3962499194186,7cyclictest0-21swapper/2121:51:2314
3962499194186,7cyclictest0-21swapper/2121:51:2314
3963399193188,4cyclictest0-21swapper/2919:45:0422
3963399193188,4cyclictest0-21swapper/2919:45:0322
3963399193183,7cyclictest0-21swapper/2900:33:4322
3963399193183,7cyclictest0-21swapper/2900:33:4322
3963299193178,4cyclictest3542-21CPU21
3963299193178,4cyclictest3542-21CPU21
3963299193178,4cyclictest3542-21CPU21
3962499193183,6cyclictest0-21swapper/2123:40:1214
3962499193183,6cyclictest0-21swapper/2123:40:1114
3962499193178,12cyclictest0-21swapper/2123:35:1614
3962499193178,12cyclictest0-21swapper/2123:35:1614
3961599193187,4cyclictest0-21swapper/1323:19:255
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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