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2026-06-30 - 20:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Jun 30, 2026 13:02:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3590799215192,11cyclictest0-21swapper/1409:14:096
3590799215192,11cyclictest0-21swapper/1409:14:096
3590799197183,12cyclictest0-21swapper/1411:01:276
3590799197183,12cyclictest0-21swapper/1411:01:276
3590799197183,12cyclictest0-21swapper/1411:01:276
3590799194181,11cyclictest0-21swapper/1412:30:396
3590799194181,11cyclictest0-21swapper/1412:30:396
3590799194181,11cyclictest0-21swapper/1412:30:396
3589599191183,3cyclictest0-21swapper/409:37:3234
3589599191183,3cyclictest0-21swapper/409:37:3234
359079918936,143cyclictest0-21swapper/1412:35:156
359079918936,143cyclictest0-21swapper/1412:35:156
3589299189139,46cyclictest0-21swapper/212:28:3012
3589299189139,46cyclictest0-21swapper/212:28:3012
3592799188183,2cyclictest0-21swapper/3311:41:3927
3592799188183,2cyclictest0-21swapper/3311:41:3927
3592799187173,11cyclictest0-21swapper/3312:38:4227
3592799187173,11cyclictest0-21swapper/3312:38:4227
35924991878,88cyclictest0-21swapper/3011:39:1824
35924991878,88cyclictest0-21swapper/3011:39:1824
3592099187159,19cyclictest171rcu_preempt09:31:2920
3592099187159,19cyclictest171rcu_preempt09:31:2920
35902991861,7cyclictest35034-21sshd10:10:163
35902991861,7cyclictest35034-21sshd10:10:163
35902991861,7cyclictest35034-21sshd10:10:163
359249918593,73cyclictest3544-21CPU24
359249918593,73cyclictest3544-21CPU24
3592099185163,15cyclictest171rcu_preempt12:17:5420
3592099185163,15cyclictest171rcu_preempt12:17:5420
3589199184166,11cyclictest0-21swapper/111:00:501
3589199184166,11cyclictest0-21swapper/111:00:501
3589199184166,11cyclictest0-21swapper/111:00:501
3592099183166,8cyclictest171rcu_preempt11:24:3920
3592099183166,8cyclictest171rcu_preempt11:24:3920
3590799183174,6cyclictest0-21swapper/1409:21:216
3590799183174,6cyclictest0-21swapper/1409:21:216
3590799183174,5cyclictest0-21swapper/1410:00:356
3590799183174,5cyclictest0-21swapper/1410:00:356
35902991831,3cyclictest2466-21CPU3
35902991831,3cyclictest2466-21CPU3
35902991831,3cyclictest2466-21CPU3
3589299183146,32cyclictest0-21swapper/209:14:4912
3589299183146,32cyclictest0-21swapper/209:14:4912
3589299183124,57cyclictest0-21swapper/212:08:3412
3589299183124,57cyclictest0-21swapper/212:08:3412
3589299183124,57cyclictest0-21swapper/212:08:3412
35892991830,95cyclictest0-21swapper/210:07:0012
35892991830,95cyclictest0-21swapper/210:07:0012
3589199183144,30cyclictest0-21swapper/111:36:211
3589199183144,30cyclictest0-21swapper/111:36:211
3593699181151,14cyclictest0-21swapper/3910:07:4633
3593699181151,14cyclictest0-21swapper/3910:07:4633
3591899181171,5cyclictest0-21swapper/2512:37:4718
3591899181171,5cyclictest0-21swapper/2512:37:4718
3589299181170,9cyclictest0-21swapper/212:19:2412
3589299181170,9cyclictest0-21swapper/212:19:2412
3589799180169,3cyclictest37263-21CPU36
3589799180169,3cyclictest37263-21CPU36
3592499179128,45cyclictest0-21swapper/3010:39:0324
3592499179128,45cyclictest0-21swapper/3010:39:0324
3592299179169,7cyclictest0-21swapper/2811:45:1421
3592299179169,7cyclictest0-21swapper/2811:45:1421
3592099179173,4cyclictest0-21swapper/2710:51:1120
3592099179173,4cyclictest0-21swapper/2710:51:1120
3592099179173,4cyclictest0-21swapper/2710:51:1020
3592099179172,5cyclictest0-21swapper/2709:59:1320
3592099179172,5cyclictest0-21swapper/2709:59:1320
3592099179167,3cyclictest171rcu_preempt11:30:4320
3592099179167,3cyclictest171rcu_preempt11:30:4320
3592099179149,15cyclictest171rcu_preempt09:28:2420
3592099179149,15cyclictest171rcu_preempt09:28:2420
3592099179149,15cyclictest171rcu_preempt09:28:2420
3592499178112,62cyclictest3542-21CPU24
3592499178112,62cyclictest3542-21CPU24
3590799178153,20cyclictest3548-21CPU6
3590799178153,20cyclictest3548-21CPU6
3589199178167,8cyclictest0-21swapper/110:39:331
3589199178167,8cyclictest0-21swapper/110:39:331
3592999177174,2cyclictest0-21swapper/3410:40:2428
3592999177174,2cyclictest0-21swapper/3410:40:2428
3592099177156,9cyclictest171rcu_preempt09:54:5420
3592099177156,9cyclictest171rcu_preempt09:54:5420
3592099177156,9cyclictest171rcu_preempt09:54:5420
3592099176125,22cyclictest171rcu_preempt11:10:5720
3592099176125,22cyclictest171rcu_preempt11:10:5720
3591699175152,20cyclictest0-21swapper/2309:37:0716
3591699175152,20cyclictest0-21swapper/2309:37:0716
358929917585,79cyclictest0-21swapper/209:32:5312
358929917585,79cyclictest0-21swapper/209:32:5312
3589299175118,51cyclictest4407-21CPU12
3589299175118,51cyclictest4407-21CPU12
3589299175118,51cyclictest4407-21CPU12
35892991750,171cyclictest0-21swapper/209:40:1912
35892991750,171cyclictest0-21swapper/209:40:1812
3592099174159,8cyclictest171rcu_preempt11:48:4320
3592099174159,8cyclictest171rcu_preempt11:48:4320
3592099174133,28cyclictest0-21swapper/2712:38:1620
3592099174133,28cyclictest0-21swapper/2712:38:1620
3589899174163,8cyclictest0-21swapper/711:41:0137
3589899174163,8cyclictest0-21swapper/711:41:0137
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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