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2026-04-20 - 07:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Apr 20, 2026 01:01:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1200799216210,5cyclictest0-21swapper/2223:49:1515
1200799216210,5cyclictest0-21swapper/2223:49:1515
1198499212202,7cyclictest0-21swapper/200:13:2112
1198499212202,7cyclictest0-21swapper/200:13:2112
1198499212202,7cyclictest0-21swapper/200:13:2012
1200799208201,3cyclictest37268-21CPU15
1200799208201,3cyclictest37268-21CPU15
1200799198191,5cyclictest0-21swapper/2219:55:0315
1200799198191,5cyclictest0-21swapper/2219:55:0315
1198399196191,4cyclictest0-21swapper/120:10:301
1198399196191,4cyclictest0-21swapper/120:10:301
1200799195185,7cyclictest755-21systemd-journal22:48:4815
1200799195185,7cyclictest755-21systemd-journal22:48:4815
1200799194189,4cyclictest0-21swapper/2219:50:0415
1200799194189,4cyclictest0-21swapper/2219:50:0415
1198399194186,4cyclictest0-21swapper/123:27:531
1198399194186,4cyclictest0-21swapper/123:27:531
1198399193188,4cyclictest0-21swapper/119:18:431
1198399193188,4cyclictest0-21swapper/119:18:431
1198399193183,8cyclictest3406-21sshd23:34:031
1198399193183,8cyclictest3406-21sshd23:34:031
1200799190186,2cyclictest0-21swapper/2223:50:2015
1200799190186,2cyclictest0-21swapper/2223:50:1915
1200799189180,5cyclictest2459-21CPU15
1200799189180,5cyclictest2459-21CPU15
1200799186179,5cyclictest0-21swapper/2220:05:1215
1200799186179,5cyclictest0-21swapper/2220:05:1215
1200099186179,3cyclictest3609-21CPU8
1198399186170,12cyclictest0-21swapper/119:28:211
1198399186170,12cyclictest0-21swapper/119:28:211
1198399185177,6cyclictest0-21swapper/120:10:001
1198399185177,6cyclictest0-21swapper/120:10:001
1200799181172,6cyclictest0-21swapper/2219:55:2415
1200799181172,6cyclictest0-21swapper/2219:55:2415
1200799179171,5cyclictest0-21swapper/2219:37:0415
1200799179171,5cyclictest0-21swapper/2219:37:0415
1200599178110,52cyclictest38423-21sshd22:14:1113
1200599178110,52cyclictest38423-21sshd22:14:1113
1198399178168,8cyclictest0-21swapper/122:57:231
1198399178168,8cyclictest0-21swapper/122:57:221
1198399178161,13cyclictest0-21swapper/119:33:111
1198399178161,13cyclictest0-21swapper/119:33:111
1201199177172,3cyclictest14910-21kworker/u81:5+events_unbound23:32:4619
1201199177172,3cyclictest14910-21kworker/u81:5+events_unbound23:32:4619
1200799177171,4cyclictest0-21swapper/2219:31:3215
1200799177171,4cyclictest0-21swapper/2219:31:3215
1198399177169,4cyclictest0-21swapper/120:16:311
1198399177165,10cyclictest0-21swapper/121:59:491
1198399177165,10cyclictest0-21swapper/121:59:491
1198399177144,18cyclictest0-21swapper/122:12:121
1198399177144,18cyclictest0-21swapper/122:12:121
1202599175121,38cyclictest0-21swapper/3800:33:2932
1202599175121,38cyclictest0-21swapper/3800:33:2932
1200799175169,4cyclictest0-21swapper/2219:27:0815
1200799175169,4cyclictest0-21swapper/2219:27:0715
1200399175123,49cyclictest0-21swapper/1821:36:3410
1200399175123,49cyclictest0-21swapper/1821:36:3410
1200099175163,8cyclictest0-21swapper/1619:30:448
1200099175163,8cyclictest0-21swapper/1619:30:448
1202299174164,8cyclictest4398-21qemu-system-x8622:03:2730
1202299174164,8cyclictest4398-21qemu-system-x8622:03:2730
1200099174135,15cyclictest171rcu_preempt00:09:278
1200099174135,15cyclictest171rcu_preempt00:09:278
1200099174135,15cyclictest171rcu_preempt00:09:278
119899917415,149cyclictest0-21swapper/723:15:1337
119899917415,149cyclictest0-21swapper/723:15:1337
1202299173168,4cyclictest0-21swapper/3623:24:4330
1202299173168,4cyclictest0-21swapper/3623:24:4330
1202299173168,4cyclictest0-21swapper/3623:24:4330
120009917377,17cyclictest0-21swapper/1622:50:198
120009917377,17cyclictest0-21swapper/1622:50:188
1200099173165,6cyclictest0-21swapper/1620:20:008
1202299172165,5cyclictest0-21swapper/3623:40:0930
1202299172165,5cyclictest0-21swapper/3623:40:0930
1202299172165,5cyclictest0-21swapper/3623:40:0930
1200399172110,48cyclictest0-21swapper/1821:25:5910
1200399172110,48cyclictest0-21swapper/1821:25:5910
1198599172161,8cyclictest3547-21CPU23
1198599172161,8cyclictest3547-21CPU23
1198399172162,8cyclictest0-21swapper/122:26:381
1198399172162,8cyclictest0-21swapper/122:26:381
1198399172102,46cyclictest2454-21CPU1
1198399172102,46cyclictest2454-21CPU1
1200399171119,49cyclictest0-21swapper/1800:31:3410
1200399171119,49cyclictest0-21swapper/1800:31:3410
1202099170128,39cyclictest0-21swapper/3422:20:3928
1202099170128,39cyclictest0-21swapper/3422:20:3828
1200599170111,54cyclictest0-21swapper/2023:59:4513
1200599170111,54cyclictest0-21swapper/2023:59:4513
1200599170111,54cyclictest0-21swapper/2023:59:4513
1200399170115,45cyclictest0-21swapper/1820:26:0010
1200399170115,45cyclictest0-21swapper/1820:26:0010
1198399170143,12cyclictest171rcu_preempt23:15:491
1198399170143,12cyclictest171rcu_preempt23:15:491
1202299169152,14cyclictest0-21swapper/3622:30:2530
1202299169152,14cyclictest0-21swapper/3622:30:2530
120079916851,105cyclictest0-21swapper/2223:15:0115
120079916851,105cyclictest0-21swapper/2223:15:0115
11997991681,3cyclictest0-21swapper/1421:50:156
11997991681,3cyclictest0-21swapper/1421:50:156
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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