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2026-03-08 - 05:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Mar 08, 2026 01:02:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
919999223216,5cyclictest0-21swapper/3820:10:1732
919999223216,5cyclictest0-21swapper/3820:10:1732
918899220209,5cyclictest171rcu_preempt22:29:5524
918899220209,5cyclictest171rcu_preempt22:29:5524
915899213188,23cyclictest0-21swapper/422:04:4134
915899213188,23cyclictest0-21swapper/422:04:4134
917599212204,6cyclictest0-21swapper/2022:34:3513
917599212204,6cyclictest0-21swapper/2022:34:3513
918899209202,5cyclictest1360-21systemd-logind21:53:1024
918899209202,5cyclictest1360-21systemd-logind21:53:1024
918899209202,5cyclictest1360-21systemd-logind21:53:1024
919999206199,5cyclictest0-21swapper/3800:21:4932
919999206199,5cyclictest0-21swapper/3800:21:4932
919999205196,5cyclictest0-21swapper/3800:35:2132
919999205196,5cyclictest0-21swapper/3800:35:2132
915999205182,18cyclictest0-21swapper/521:20:2735
915999205182,18cyclictest0-21swapper/521:20:2635
919999202193,5cyclictest2454-21CPU32
919999202193,5cyclictest2454-21CPU32
919999202193,5cyclictest2454-21CPU32
917299202197,4cyclictest0-21swapper/1722:38:129
917299202197,4cyclictest0-21swapper/1722:38:129
917599201196,4cyclictest0-21swapper/2022:35:2913
917599201196,4cyclictest0-21swapper/2022:35:2913
916799201195,4cyclictest0-21swapper/1321:05:255
916799201195,4cyclictest0-21swapper/1321:05:245
919999200192,6cyclictest0-21swapper/3822:11:5532
919999200192,6cyclictest0-21swapper/3822:11:5532
917599200191,7cyclictest0-21swapper/2000:39:2213
917599200191,7cyclictest0-21swapper/2000:39:2113
916799200194,4cyclictest0-21swapper/1321:49:335
916799200194,4cyclictest0-21swapper/1321:49:335
916799200194,4cyclictest0-21swapper/1321:49:335
919999198193,4cyclictest0-21swapper/3822:19:2532
919999198193,4cyclictest0-21swapper/3822:19:2432
919999198193,4cyclictest0-21swapper/3822:19:2432
918999197188,5cyclictest0-21swapper/3122:17:3425
918999197188,5cyclictest0-21swapper/3122:17:3325
918999197188,5cyclictest0-21swapper/3122:17:3325
919999196190,4cyclictest0-21swapper/3821:54:5232
919999196190,4cyclictest0-21swapper/3821:54:5132
919999196190,4cyclictest0-21swapper/3821:54:5132
919999195188,5cyclictest755-21systemd-journal22:21:3732
919999195188,5cyclictest755-21systemd-journal22:21:3732
919999194186,4cyclictest0-21swapper/3821:55:3632
919999194186,4cyclictest0-21swapper/3821:55:3532
919999194182,8cyclictest0-21swapper/3820:56:4032
919999194182,8cyclictest0-21swapper/3820:56:4032
918999193185,6cyclictest0-21swapper/3122:15:0125
918999193185,6cyclictest0-21swapper/3122:15:0125
918999193185,6cyclictest0-21swapper/3121:45:2125
918999193185,6cyclictest0-21swapper/3121:45:2125
918999193185,6cyclictest0-21swapper/3121:45:2125
919999192186,4cyclictest0-21swapper/3820:02:4232
919999192186,4cyclictest0-21swapper/3820:02:4132
919999192185,5cyclictest0-21swapper/3821:36:5932
919999192185,5cyclictest0-21swapper/3821:36:5932
916199192185,5cyclictest0-21swapper/720:07:0637
916199192185,5cyclictest0-21swapper/720:07:0537
915899192180,10cyclictest0-21swapper/419:17:2334
915899192180,10cyclictest0-21swapper/419:17:2334
919999191184,4cyclictest0-21swapper/3800:25:1032
919999191184,4cyclictest0-21swapper/3800:25:0932
919099191184,3cyclictest0-21swapper/3223:35:2926
919099191184,3cyclictest0-21swapper/3223:35:2926
918999191185,5cyclictest0-21swapper/3120:49:1725
918999191185,5cyclictest0-21swapper/3120:49:1725
915899191182,7cyclictest0-21swapper/423:06:0534
915899191182,7cyclictest0-21swapper/423:06:0534
915899191182,7cyclictest0-21swapper/423:06:0534
915999190183,5cyclictest0-21swapper/521:37:5935
915999190183,5cyclictest0-21swapper/521:37:5935
915999190168,19cyclictest0-21swapper/500:09:5535
915999190168,19cyclictest0-21swapper/500:09:5435
915899190181,6cyclictest0-21swapper/421:15:1234
915899190181,6cyclictest0-21swapper/421:15:1134
915899190181,6cyclictest0-21swapper/421:15:1134
919999189181,6cyclictest0-21swapper/3823:14:2832
919999189181,6cyclictest0-21swapper/3823:14:2832
917599189169,8cyclictest0-21swapper/2023:32:5013
917599189169,8cyclictest0-21swapper/2023:32:4913
917299188181,5cyclictest0-21swapper/1721:57:459
917299188181,5cyclictest0-21swapper/1721:57:459
918899187181,4cyclictest0-21swapper/3020:01:5424
918899187181,4cyclictest0-21swapper/3020:01:5424
915399187174,5cyclictest0-21swapper/123:07:281
915399187174,5cyclictest0-21swapper/123:07:281
915399187174,5cyclictest0-21swapper/123:07:271
919999185179,4cyclictest0-21swapper/3819:40:5132
919999185178,5cyclictest0-21swapper/3822:26:5632
919999185178,5cyclictest0-21swapper/3822:26:5632
918499185175,5cyclictest3610-21CPU19
918499185175,5cyclictest3610-21CPU19
918499185175,5cyclictest3610-21CPU19
9179991851,2cyclictest0-21swapper/2322:30:2416
9179991851,2cyclictest0-21swapper/2322:30:2416
917599184177,5cyclictest0-21swapper/2022:30:0113
917599184177,5cyclictest0-21swapper/2022:30:0113
917299184171,6cyclictest0-21swapper/1722:02:119
917299184171,6cyclictest0-21swapper/1722:02:119
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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