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2026-03-18 - 11:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Mar 18, 2026 01:02:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39852992381,3cyclictest0-21swapper/022:53:240
39852992381,3cyclictest0-21swapper/022:53:240
39852992361,3cyclictest0-21swapper/021:40:210
39852992361,3cyclictest0-21swapper/021:40:200
39852992361,3cyclictest0-21swapper/021:40:200
39852992361,3cyclictest0-21swapper/000:20:220
39852992361,3cyclictest0-21swapper/000:20:210
39852992361,3cyclictest0-21swapper/000:20:210
39852992351,2cyclictest0-21swapper/022:03:030
39852992351,2cyclictest0-21swapper/022:03:030
39852992351,2cyclictest0-21swapper/022:03:030
39852992311,221cyclictest0-21swapper/022:40:210
39852992311,221cyclictest0-21swapper/022:40:210
39852992311,221cyclictest0-21swapper/022:40:210
39852992271,3cyclictest0-21swapper/023:42:270
39852992271,3cyclictest0-21swapper/023:42:270
39852992251,7cyclictest2462-21CPU0
39852992251,7cyclictest2462-21CPU0
39852992251,7cyclictest2462-21CPU0
39852992240,2cyclictest0-21swapper/019:40:010
39852992240,2cyclictest0-21swapper/019:40:010
39852992231,219cyclictest0-21swapper/000:18:120
39852992231,219cyclictest0-21swapper/000:18:120
39852992221,213cyclictest0-21swapper/023:18:260
39852992221,213cyclictest0-21swapper/023:18:260
39852992221,213cyclictest0-21swapper/023:18:250
39852992181,4cyclictest0-21swapper/020:20:040
39852992172,209cyclictest2454-21CPU0
39852992172,209cyclictest2454-21CPU0
39852992170,2cyclictest0-21swapper/023:08:040
39852992170,2cyclictest0-21swapper/023:08:040
39852992161,208cyclictest0-21swapper/020:05:150
39852992161,208cyclictest0-21swapper/020:05:140
39852992161,206cyclictest0-21swapper/000:35:230
39852992161,206cyclictest0-21swapper/000:35:230
39852992161,206cyclictest0-21swapper/000:35:230
39852992160,3cyclictest25112-21sshd22:10:330
39852992160,3cyclictest25112-21sshd22:10:330
39852992160,3cyclictest25112-21sshd22:10:330
39852992151,3cyclictest0-21swapper/023:12:390
39852992151,3cyclictest0-21swapper/023:12:390
39852992151,211cyclictest0-21swapper/020:20:250
39852992151,211cyclictest0-21swapper/020:20:250
39852992141,3cyclictest0-21swapper/021:59:360
39852992141,3cyclictest0-21swapper/021:59:360
39852992132,207cyclictest0-21swapper/023:29:580
39852992132,207cyclictest0-21swapper/023:29:580
39852992131,3cyclictest0-21swapper/000:01:280
39852992131,3cyclictest0-21swapper/000:01:280
39852992131,3cyclictest0-21swapper/000:01:280
39852992121,3cyclictest0-21swapper/021:25:140
39852992121,3cyclictest0-21swapper/021:25:140
39852992121,3cyclictest0-21swapper/021:25:140
39852992111,3cyclictest0-21swapper/023:24:510
39852992111,3cyclictest0-21swapper/023:24:510
39852992111,3cyclictest0-21swapper/021:47:120
39852992111,3cyclictest0-21swapper/021:47:120
39852992110,3cyclictest1367-21dbus-daemon23:55:140
39852992110,3cyclictest1367-21dbus-daemon23:55:140
39852992110,3cyclictest1367-21dbus-daemon23:55:130
39852992102,202cyclictest3546-21CPU0
39852992102,202cyclictest3546-21CPU0
39852992101,205cyclictest0-21swapper/020:40:240
39852992101,205cyclictest0-21swapper/020:40:240
39852992091,3cyclictest0-21swapper/022:28:560
39852992091,3cyclictest0-21swapper/022:28:560
39852992091,3cyclictest0-21swapper/021:20:550
39852992091,3cyclictest0-21swapper/021:20:550
39852992091,205cyclictest0-21swapper/022:55:250
39852992091,205cyclictest0-21swapper/022:55:240
39852992091,205cyclictest0-21swapper/022:55:240
39852992081,3cyclictest0-21swapper/021:31:420
39852992081,3cyclictest0-21swapper/021:31:420
39852992081,2cyclictest0-21swapper/022:45:310
39852992081,2cyclictest0-21swapper/022:45:310
39852992081,2cyclictest0-21swapper/022:18:280
39852992081,2cyclictest0-21swapper/022:18:280
39852992081,2cyclictest0-21swapper/022:18:270
39852992080,2cyclictest0-21swapper/021:35:180
39852992080,2cyclictest0-21swapper/021:35:170
39852992071,2cyclictest0-21swapper/021:51:160
39852992071,2cyclictest0-21swapper/021:51:160
39852992071,201cyclictest0-21swapper/019:55:110
39852992071,201cyclictest0-21swapper/019:55:110
39852992061,3cyclictest0-21swapper/022:33:130
39852992061,3cyclictest0-21swapper/022:33:130
39852992061,2cyclictest0-21swapper/000:10:190
39852992061,2cyclictest0-21swapper/000:10:190
39852992056,196cyclictest0-21swapper/022:20:130
39852992056,196cyclictest0-21swapper/022:20:130
39852992056,196cyclictest0-21swapper/022:20:130
39852992051,2cyclictest0-21swapper/020:30:210
39852992051,2cyclictest0-21swapper/020:30:210
39852992041,194cyclictest0-21swapper/000:05:230
39852992041,194cyclictest0-21swapper/000:05:220
39852992031,3cyclictest0-21swapper/023:03:470
39852992031,3cyclictest0-21swapper/023:03:470
39852992031,2cyclictest0-21swapper/022:36:090
39852992031,2cyclictest0-21swapper/022:36:090
39852992031,2cyclictest0-21swapper/021:12:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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