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2026-02-14 - 09:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 14, 2026 01:02:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3311599239234,3cyclictest0-21swapper/3900:20:1433
3311599239234,3cyclictest0-21swapper/3900:20:1333
3311599239234,3cyclictest0-21swapper/3900:20:1333
3307999225177,42cyclictest4407-21CPU39
3307999225177,42cyclictest4407-21CPU39
3309399215205,8cyclictest0-21swapper/2022:35:2313
3309399215205,8cyclictest0-21swapper/2022:35:2213
3309399215205,8cyclictest0-21swapper/2022:35:2213
3306999212205,3cyclictest3610-21CPU0
3306999212205,3cyclictest3610-21CPU0
3307699201194,2cyclictest0-21swapper/700:11:0137
3307699201194,2cyclictest0-21swapper/700:11:0037
3306999201196,2cyclictest0-21swapper/023:15:230
3306999201196,2cyclictest0-21swapper/023:15:220
3306999201196,2cyclictest0-21swapper/023:15:220
3306999201193,6cyclictest0-21swapper/019:22:260
3306999201193,6cyclictest0-21swapper/019:22:260
3308599197192,4cyclictest0-21swapper/1420:15:206
3308599197192,4cyclictest0-21swapper/1420:15:196
3306999193188,4cyclictest0-21swapper/020:20:200
3306999193188,4cyclictest0-21swapper/020:20:200
3310499192188,2cyclictest0-21swapper/3020:30:0024
3306999192183,7cyclictest0-21swapper/023:26:060
3306999192183,7cyclictest0-21swapper/023:26:050
3306999191186,4cyclictest0-21swapper/023:14:060
3306999191186,4cyclictest0-21swapper/023:14:060
3306999191186,4cyclictest0-21swapper/023:14:060
3306999191186,4cyclictest0-21swapper/019:15:200
3309699189140,38cyclictest37352-21CPU16
3309699189140,38cyclictest37352-21CPU16
3308199189185,2cyclictest0-21swapper/1123:48:553
3308199189185,2cyclictest0-21swapper/1123:48:543
3307699189175,12cyclictest0-21swapper/723:49:5137
3307699189175,12cyclictest0-21swapper/723:49:5037
3306999189181,6cyclictest0-21swapper/020:20:020
3306999189181,6cyclictest0-21swapper/020:20:020
33107991881,184cyclictest0-21swapper/3321:18:3927
33107991881,184cyclictest0-21swapper/3321:18:3927
3307699188179,7cyclictest0-21swapper/723:43:5737
3307699188179,7cyclictest0-21swapper/723:43:5737
3307699188179,7cyclictest0-21swapper/723:43:5637
3307399188180,6cyclictest0-21swapper/423:10:3134
3307399188180,6cyclictest0-21swapper/423:10:3034
3307399188180,6cyclictest0-21swapper/423:10:3034
3307699187180,5cyclictest0-21swapper/700:32:4537
3307699187180,5cyclictest0-21swapper/700:32:4537
3307699187180,5cyclictest0-21swapper/700:32:4437
3307699187150,35cyclictest0-21swapper/721:52:0437
3307699187150,35cyclictest0-21swapper/721:52:0437
3306999187182,4cyclictest0-21swapper/019:10:170
3306999187182,4cyclictest0-21swapper/019:10:170
3307599186165,14cyclictest171rcu_preempt23:02:4436
3307599186165,14cyclictest171rcu_preempt23:02:4436
3307599185136,41cyclictest0-21swapper/622:40:2336
3307599185136,41cyclictest0-21swapper/622:40:2236
33080991831,85cyclictest0-21swapper/1021:30:182
33080991831,85cyclictest0-21swapper/1021:30:172
33080991831,85cyclictest0-21swapper/1021:30:172
3306999183173,8cyclictest0-21swapper/021:37:060
3306999183173,8cyclictest0-21swapper/021:37:060
3306999183173,8cyclictest0-21swapper/021:37:050
3309399182175,5cyclictest0-21swapper/2020:35:3413
3309399182175,5cyclictest0-21swapper/2020:35:3313
3307599182123,41cyclictest37268-21CPU36
3307599182123,41cyclictest37268-21CPU36
3306999182176,4cyclictest0-21swapper/019:10:030
3306999182176,4cyclictest0-21swapper/019:10:020
3306999182172,8cyclictest0-21swapper/020:15:020
3306999182172,8cyclictest0-21swapper/020:15:020
3310799181145,33cyclictest0-21swapper/3323:20:2027
3310799181145,33cyclictest0-21swapper/3323:20:2027
3308899181169,10cyclictest35065-21kworker/u80:0-ext4-rsv-conversion22:45:208
3308899181169,10cyclictest35065-21kworker/u80:0-ext4-rsv-conversion22:45:208
3308899181169,10cyclictest35065-21kworker/u80:0-ext4-rsv-conversion22:45:208
3307999181173,6cyclictest0-21swapper/920:50:3939
3307599181160,10cyclictest171rcu_preempt00:17:4036
3307599181160,10cyclictest171rcu_preempt00:17:3936
330819918092,67cyclictest37354-21CPU3
330819918092,67cyclictest37354-21CPU3
3308899179165,12cyclictest0-21swapper/1623:04:158
3308899179165,12cyclictest0-21swapper/1623:04:158
3307699179168,9cyclictest0-21swapper/722:41:4037
3307699179168,9cyclictest0-21swapper/722:41:4037
3309899178171,4cyclictest0-21swapper/2523:24:1418
3309899178171,4cyclictest0-21swapper/2523:24:1418
3309599178143,22cyclictest3610-21CPU15
3309599178143,22cyclictest3610-21CPU15
3309599178143,22cyclictest3610-21CPU15
330909917858,117cyclictest0-21swapper/1720:25:149
3311599177164,5cyclictest0-21swapper/3900:38:3933
3311599177164,5cyclictest0-21swapper/3900:38:3933
3308199177168,6cyclictest0-21swapper/1123:08:233
3308199177168,6cyclictest0-21swapper/1123:08:233
3307599177147,11cyclictest171rcu_preempt22:02:2036
3307599177147,11cyclictest171rcu_preempt22:02:2036
3307599177140,22cyclictest0-21swapper/621:54:5336
3307599177140,22cyclictest0-21swapper/621:54:5336
3306999177166,7cyclictest0-21swapper/023:33:150
3306999177166,7cyclictest0-21swapper/023:33:150
3306999177166,7cyclictest0-21swapper/023:33:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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