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2026-06-05 - 08:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri Jun 05, 2026 01:01:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2308499230216,10cyclictest0-21swapper/223:55:0012
2308499230216,10cyclictest0-21swapper/223:55:0012
2308499219211,6cyclictest0-21swapper/200:37:2912
2308499219211,6cyclictest0-21swapper/200:37:2812
2308499213206,5cyclictest0-21swapper/200:00:4612
2308499213206,5cyclictest0-21swapper/200:00:4612
230909921117,191cyclictest0-21swapper/721:35:4837
230909921117,191cyclictest0-21swapper/721:35:4837
2309199208200,5cyclictest0-21swapper/822:48:4938
2309199208200,5cyclictest0-21swapper/822:48:4938
2309199208200,5cyclictest0-21swapper/822:48:4938
2309199206201,3cyclictest15406-21sshd23:40:2038
2309199206201,3cyclictest15406-21sshd23:40:2038
23090992063,5cyclictest3543-21CPU37
23090992063,5cyclictest3543-21CPU37
2308499206200,4cyclictest0-21swapper/200:07:4612
2308499206200,4cyclictest0-21swapper/200:07:4612
2309199205197,6cyclictest0-21swapper/821:11:3038
2309199205197,6cyclictest0-21swapper/821:11:3038
2308499205200,4cyclictest0-21swapper/223:57:4012
2308499205200,4cyclictest0-21swapper/223:57:4012
2308499205200,4cyclictest0-21swapper/223:57:3912
2309199204198,4cyclictest0-21swapper/821:15:2938
2309199204198,4cyclictest0-21swapper/821:15:2938
2309199198192,4cyclictest0-21swapper/821:20:1238
2309199198192,4cyclictest0-21swapper/821:20:1238
2309199198192,4cyclictest0-21swapper/821:20:1238
2309199198188,7cyclictest3609-21CPU38
2309199198188,7cyclictest3609-21CPU38
23090991982,5cyclictest37353-21CPU37
23090991982,5cyclictest37353-21CPU37
2309199197191,4cyclictest0-21swapper/800:20:1938
2309199197191,4cyclictest0-21swapper/800:20:1938
2309199197191,4cyclictest0-21swapper/800:20:1938
2309599194111,75cyclictest4407-21CPU2
2309599194111,75cyclictest4407-21CPU2
2308499194164,26cyclictest3609-21CPU12
2308499194164,26cyclictest3609-21CPU12
2309199193187,4cyclictest7826-21idleruntime-cro23:00:0038
2309199193187,4cyclictest7826-21idleruntime-cro23:00:0038
2309199192189,2cyclictest0-21swapper/822:52:1338
2309199192189,2cyclictest0-21swapper/822:52:1338
2309199192183,7cyclictest6964-21cp23:35:2738
2309199192183,7cyclictest6964-21cp23:35:2738
2309199192183,7cyclictest6964-21cp23:35:2738
2312599191184,5cyclictest37257-21qemu-system-x8622:26:1330
2312599191184,5cyclictest37257-21qemu-system-x8622:26:1330
2309199191186,3cyclictest0-21swapper/820:00:1138
2309199191186,3cyclictest0-21swapper/820:00:1138
231089919013,83cyclictest1367-21dbus-daemon23:47:0114
231089919013,83cyclictest1367-21dbus-daemon23:47:0114
231089919013,83cyclictest1367-21dbus-daemon23:47:0114
2309199190186,3cyclictest0-21swapper/820:30:2038
2309199190186,3cyclictest0-21swapper/820:30:2038
2309199190186,2cyclictest0-21swapper/823:02:5538
2309199190186,2cyclictest0-21swapper/823:02:5538
2309199190186,2cyclictest0-21swapper/823:02:5538
2309199190185,4cyclictest0-21swapper/822:37:0938
2309199190185,4cyclictest0-21swapper/822:37:0938
2309199190185,4cyclictest0-21swapper/822:37:0938
2309199189180,4cyclictest37353-21CPU38
2309199189180,4cyclictest37353-21CPU38
2309199189177,7cyclictest0-21swapper/800:30:4838
2309199189177,7cyclictest0-21swapper/800:30:4838
2308799189171,9cyclictest0-21swapper/400:31:5234
2308799189171,9cyclictest0-21swapper/400:31:5234
2308499189183,4cyclictest0-21swapper/200:15:5412
2308499189183,4cyclictest0-21swapper/200:15:5412
2308499189183,4cyclictest0-21swapper/200:15:5412
2309199188183,4cyclictest0-21swapper/821:29:2538
2309199188183,4cyclictest0-21swapper/821:29:2538
2309199188183,4cyclictest0-21swapper/821:29:2538
2309199188180,6cyclictest0-21swapper/823:46:4338
2309199188180,6cyclictest0-21swapper/823:46:4338
2309199188180,6cyclictest0-21swapper/823:46:4338
2309599187122,56cyclictest4407-21CPU2
2309599187122,56cyclictest4407-21CPU2
2309199187181,4cyclictest2461-21CPU38
2309199187181,4cyclictest2461-21CPU38
2308499187171,9cyclictest171rcu_preempt21:22:5212
2308499187171,9cyclictest171rcu_preempt21:22:5212
2308499187171,9cyclictest171rcu_preempt21:22:5212
2309199186181,4cyclictest0-21swapper/820:45:1738
2309199186181,4cyclictest0-21swapper/820:45:1738
2309199186179,4cyclictest0-21swapper/819:47:0338
2309199186179,4cyclictest0-21swapper/819:47:0238
2309199185180,4cyclictest0-21swapper/821:00:2638
2309199185180,4cyclictest0-21swapper/821:00:2638
2309199185177,6cyclictest0-21swapper/820:55:1638
2309199185177,6cyclictest0-21swapper/820:55:1638
2309199185173,9cyclictest37357-21CPU38
2309199185173,9cyclictest37357-21CPU38
2308499185179,3cyclictest0-21swapper/223:08:5812
2308499185179,3cyclictest0-21swapper/223:08:5812
2308299185179,4cyclictest0-21swapper/021:58:340
2308299185179,4cyclictest0-21swapper/021:58:340
2308299185179,4cyclictest0-21swapper/021:58:340
2309199184177,5cyclictest0-21swapper/823:50:1338
2309199184177,5cyclictest0-21swapper/823:50:1338
2308299184175,5cyclictest0-21swapper/000:04:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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