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2026-08-26 - 18:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Aug 26, 2026 13:02:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1480099221129,79cyclictest37266-21CPU36
1480099221129,79cyclictest37266-21CPU36
1480099221129,79cyclictest37266-21CPU36
14800992172,4cyclictest37353-21CPU36
14800992172,4cyclictest37353-21CPU36
14800992172,4cyclictest37353-21CPU36
1480499213210,2cyclictest0-21swapper/1009:40:202
1480499213210,2cyclictest0-21swapper/1009:40:192
1482599212191,15cyclictest2466-21CPU21
1482599212191,15cyclictest2466-21CPU21
1483099202191,9cyclictest0-21swapper/3307:25:0127
1483099202191,9cyclictest0-21swapper/3307:25:0027
1480199199189,5cyclictest37354-21CPU37
1480199199189,5cyclictest37354-21CPU37
1483399198194,2cyclictest0-21swapper/3509:35:0129
1483399198194,2cyclictest0-21swapper/3509:35:0029
1483199197191,5cyclictest0-21swapper/3411:35:2228
1483199197191,5cyclictest0-21swapper/3411:35:2228
1483199197191,5cyclictest0-21swapper/3411:35:2128
14806991962,189cyclictest2464-21CPU4
14806991962,189cyclictest2464-21CPU4
14806991962,189cyclictest2464-21CPU4
1482199193180,2cyclictest0-21swapper/2408:06:1417
1482199193180,2cyclictest0-21swapper/2408:06:1417
148069919387,104cyclictest0-21swapper/1210:40:164
148069919387,104cyclictest0-21swapper/1210:40:154
1483099192174,6cyclictest171rcu_preempt11:17:1427
1483099192174,6cyclictest171rcu_preempt11:17:1427
1483099192174,6cyclictest171rcu_preempt11:17:1427
1480199190183,5cyclictest0-21swapper/709:28:3737
1480199190183,5cyclictest0-21swapper/709:28:3737
1480199190183,5cyclictest0-21swapper/709:28:3637
1480699188153,31cyclictest0-21swapper/1212:35:104
1480699188153,31cyclictest0-21swapper/1212:35:104
1482599187179,6cyclictest0-21swapper/2812:10:1521
1482599187179,6cyclictest0-21swapper/2812:10:1521
1482599187179,6cyclictest0-21swapper/2812:10:1521
1482599187176,9cyclictest0-21swapper/2810:20:1921
1482599187176,9cyclictest0-21swapper/2810:20:1821
1482599187173,9cyclictest0-21swapper/2809:50:1221
1482599187173,9cyclictest0-21swapper/2809:50:1121
1482599187173,9cyclictest0-21swapper/2809:50:1121
1480699185150,21cyclictest0-21swapper/1211:47:404
1480699185150,21cyclictest0-21swapper/1211:47:404
1480199185171,6cyclictest0-21swapper/710:24:5437
1480199185171,6cyclictest0-21swapper/710:24:5437
14819991841,177cyclictest0-21swapper/2211:00:2015
14819991841,177cyclictest0-21swapper/2211:00:2015
14819991841,177cyclictest0-21swapper/2211:00:2015
14819991840,181cyclictest1384-21rs:main15
14819991840,181cyclictest1384-21rs:main15
1483099183170,3cyclictest171rcu_preempt10:36:0627
1483099183170,3cyclictest171rcu_preempt10:36:0527
1483099183170,3cyclictest171rcu_preempt10:36:0527
148199918386,89cyclictest0-21swapper/2211:40:2015
148199918386,89cyclictest0-21swapper/2211:40:1915
1481999183153,26cyclictest0-21swapper/2211:45:2115
1481999183153,26cyclictest0-21swapper/2211:45:2115
14819991821,68cyclictest0-21swapper/2211:35:2115
14819991821,68cyclictest0-21swapper/2211:35:2115
14819991821,68cyclictest0-21swapper/2211:35:2115
1483099181155,15cyclictest0-21swapper/3309:55:4127
1483099181155,15cyclictest0-21swapper/3309:55:4127
1483099181155,15cyclictest0-21swapper/3309:55:4027
1482599181172,7cyclictest0-21swapper/2811:52:4221
1482599181172,7cyclictest0-21swapper/2811:52:4221
1479899181137,37cyclictest3542-21CPU34
1479899181137,37cyclictest3542-21CPU34
1481999180160,17cyclictest0-21swapper/2212:05:2715
1481999180160,17cyclictest0-21swapper/2212:05:2715
1481999180160,17cyclictest0-21swapper/2212:05:2615
14815991802,4cyclictest3543-21CPU13
14815991802,4cyclictest3543-21CPU13
148099918042,129cyclictest2447-21CPU6
148099918042,129cyclictest2447-21CPU6
14827991794,5cyclictest3548-21CPU24
14827991794,5cyclictest3548-21CPU24
14827991794,5cyclictest3548-21CPU24
1482599179143,33cyclictest0-21swapper/2811:05:0421
1482599179143,33cyclictest0-21swapper/2811:05:0421
1482599179143,33cyclictest0-21swapper/2811:05:0421
14815991791,3cyclictest0-21swapper/2010:25:2113
14815991791,3cyclictest0-21swapper/2010:25:2013
148069917958,117cyclictest0-21swapper/1210:15:214
148069917958,117cyclictest0-21swapper/1210:15:204
1480699179154,23cyclictest0-21swapper/1210:04:534
1480699179154,23cyclictest0-21swapper/1210:04:524
148309917839,127cyclictest0-21swapper/3311:35:2227
148309917839,127cyclictest0-21swapper/3311:35:2227
148309917839,127cyclictest0-21swapper/3311:35:2127
1483099178150,19cyclictest171rcu_preempt10:58:3127
1483099178150,19cyclictest171rcu_preempt10:58:3127
1483099178150,19cyclictest171rcu_preempt10:58:3027
1482599178170,5cyclictest0-21swapper/2811:25:1721
1482599178170,5cyclictest0-21swapper/2811:25:1721
1482599178163,11cyclictest0-21swapper/2811:08:2621
1482599178163,11cyclictest0-21swapper/2811:08:2621
148059917898,74cyclictest3547-21CPU3
148059917898,74cyclictest3547-21CPU3
1482599177161,14cyclictest0-21swapper/2812:25:2221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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