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2026-03-03 - 00:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Mar 02, 2026 13:03:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1405799240235,3cyclictest0-21swapper/007:40:220
1405799240235,3cyclictest0-21swapper/007:40:210
1409299238235,2cyclictest0-21swapper/3007:40:2324
1409299238235,2cyclictest0-21swapper/3007:40:2224
1408799236214,12cyclictest0-21swapper/2611:30:2819
1408799236214,12cyclictest0-21swapper/2611:30:2819
1408799236214,12cyclictest0-21swapper/2611:30:2819
1406299229191,24cyclictest0-21swapper/511:08:0935
1406299229191,24cyclictest0-21swapper/511:08:0935
1406299229191,24cyclictest0-21swapper/511:08:0935
1407999223196,12cyclictest0-21swapper/1810:48:3010
1407999223196,12cyclictest0-21swapper/1810:48:3010
1408799219209,6cyclictest8031-21diskstats11:00:2019
1408799219209,6cyclictest8031-21diskstats11:00:2019
1408799219209,6cyclictest8031-21diskstats11:00:1919
1408799219198,15cyclictest3610-21CPU19
1408799219198,15cyclictest3610-21CPU19
1408799216201,6cyclictest0-21swapper/2611:53:0419
1408799216201,6cyclictest0-21swapper/2611:53:0319
1408799216201,6cyclictest0-21swapper/2611:53:0319
1408799216181,21cyclictest0-21swapper/2609:59:1919
1408799216181,21cyclictest0-21swapper/2609:59:1919
1405799215210,3cyclictest0-21swapper/007:30:190
1405799215210,3cyclictest0-21swapper/007:30:190
1408799211198,9cyclictest881-21cstates08:55:1719
1409099210205,3cyclictest0-21swapper/2807:35:2121
1409099210205,3cyclictest0-21swapper/2807:35:2021
1405899210197,3cyclictest0-21swapper/111:39:391
1405899210197,3cyclictest0-21swapper/111:39:391
1405899210197,3cyclictest0-21swapper/111:39:391
1408799208200,4cyclictest3546-21CPU19
1408799208200,4cyclictest3546-21CPU19
1408799207191,14cyclictest0-21swapper/2611:20:2219
1408799207191,14cyclictest0-21swapper/2611:20:2119
1407299207201,2cyclictest0-21swapper/1412:17:496
1407299207201,2cyclictest0-21swapper/1412:17:496
1407299207201,2cyclictest0-21swapper/1412:17:486
1407299207200,4cyclictest2461-21CPU6
1407299207200,4cyclictest2461-21CPU6
1407299207200,4cyclictest2461-21CPU6
1408799205200,4cyclictest0-21swapper/2610:17:2419
1408799205200,4cyclictest0-21swapper/2610:17:2419
1408799205200,4cyclictest0-21swapper/2610:17:2419
1408799205198,4cyclictest3548-21CPU19
1408799205198,4cyclictest3548-21CPU19
1408799205198,4cyclictest3548-21CPU19
1405799205202,2cyclictest0-21swapper/007:45:200
1405799205202,2cyclictest0-21swapper/007:45:200
1407999203191,10cyclictest0-21swapper/1810:58:0610
1407999203191,10cyclictest0-21swapper/1810:58:0610
1407999203191,10cyclictest0-21swapper/1810:58:0610
1406499203190,10cyclictest0-21swapper/712:27:3337
1406499203190,10cyclictest0-21swapper/712:27:3237
1408799201194,4cyclictest142650irq/48-eno1-TxRx-612:35:2019
1408799201194,4cyclictest142650irq/48-eno1-TxRx-612:35:1919
1409099200193,4cyclictest0-21swapper/2811:07:0621
1409099200193,4cyclictest0-21swapper/2811:07:0521
1409099200193,4cyclictest0-21swapper/2811:07:0521
1408799200181,13cyclictest37358-21CPU19
1408799200181,13cyclictest37358-21CPU19
1408799200181,13cyclictest37358-21CPU19
1408199200197,2cyclictest0-21swapper/2007:40:1913
1408199200197,2cyclictest0-21swapper/2007:40:1813
1409099199194,2cyclictest0-21swapper/2807:43:0521
1409099199194,2cyclictest0-21swapper/2807:43:0421
1408799199192,3cyclictest3610-21CPU19
1408799199192,3cyclictest3610-21CPU19
1408799199191,5cyclictest3547-21CPU19
1408799199191,5cyclictest3547-21CPU19
1408799199191,5cyclictest3547-21CPU19
1407799199191,6cyclictest0-21swapper/1708:45:029
1407799199191,6cyclictest0-21swapper/1708:45:029
1408799198190,5cyclictest0-21swapper/2611:35:1619
1408799198190,5cyclictest0-21swapper/2611:35:1519
1408799198190,5cyclictest0-21swapper/2611:35:1519
1408799198176,13cyclictest0-21swapper/2612:15:1719
1408799198176,13cyclictest0-21swapper/2612:15:1619
1408799198176,13cyclictest0-21swapper/2612:15:1619
1407999198153,38cyclictest2461-21CPU10
1407999198153,38cyclictest2461-21CPU10
1407999198153,38cyclictest2461-21CPU10
14066991980,65cyclictest0-21swapper/907:40:1339
14066991980,65cyclictest0-21swapper/907:40:1239
1406299198162,24cyclictest0-21swapper/510:30:0335
1406299198162,24cyclictest0-21swapper/510:30:0335
1406299198162,24cyclictest0-21swapper/510:30:0235
1405899198173,15cyclictest0-21swapper/107:22:011
1405899198173,15cyclictest0-21swapper/107:22:011
1408799197189,6cyclictest0-21swapper/2610:05:1519
1408799197189,6cyclictest0-21swapper/2610:05:1419
1408799197189,6cyclictest0-21swapper/2610:05:1419
1408799197187,8cyclictest0-21swapper/2610:36:3919
1408799197187,8cyclictest0-21swapper/2610:36:3819
1408799197187,8cyclictest0-21swapper/2610:36:3819
1408799197187,5cyclictest37354-21CPU19
1408799197187,5cyclictest37354-21CPU19
1408799197187,5cyclictest37354-21CPU19
1408799197156,36cyclictest37356-21CPU19
1408799197156,36cyclictest37356-21CPU19
1408799196190,4cyclictest1360-21systemd-logind10:54:2419
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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