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2026-08-15 - 20:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Aug 15, 2026 13:02:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2728999257239,5cyclictest37263-21CPU26
2728999257239,5cyclictest37263-21CPU26
2728999257239,5cyclictest37263-21CPU26
2726199229222,4cyclictest2466-21CPU37
2726199229222,4cyclictest2466-21CPU37
2727399224218,3cyclictest0-21swapper/1711:05:129
2727399224218,3cyclictest0-21swapper/1711:05:129
2729799219205,7cyclictest0-21swapper/3709:20:1231
2729799219205,7cyclictest0-21swapper/3709:20:1231
2727299214207,5cyclictest0-21swapper/1607:30:228
2726899208201,5cyclictest0-21swapper/1307:35:305
2726899208201,5cyclictest0-21swapper/1307:35:305
2726899207201,4cyclictest0-21swapper/1308:25:155
2726899207201,4cyclictest0-21swapper/1308:25:155
2726899207195,10cyclictest0-21swapper/1308:00:375
2726899207195,10cyclictest0-21swapper/1308:00:375
2727099206199,4cyclictest2447-21CPU6
2727099206199,4cyclictest2447-21CPU6
2727099206199,4cyclictest2447-21CPU6
2726899206194,9cyclictest0-21swapper/1307:35:005
2729799204198,4cyclictest0-21swapper/3710:41:3831
2729799204198,4cyclictest0-21swapper/3710:41:3831
2727599203198,3cyclictest0-21swapper/1910:25:1411
2727599203198,3cyclictest0-21swapper/1910:25:1411
2729799200189,8cyclictest6552-21systemd11:37:0131
2729799200189,8cyclictest6552-21systemd11:37:0131
2729799199193,4cyclictest0-21swapper/3710:46:0531
2729799199193,4cyclictest0-21swapper/3710:46:0531
2729799199193,4cyclictest0-21swapper/3710:46:0531
2728699199193,4cyclictest0-21swapper/2908:35:2322
2728699199193,4cyclictest0-21swapper/2908:35:2322
2728699199187,7cyclictest37356-21CPU22
2728699199187,7cyclictest37356-21CPU22
2726899199191,7cyclictest0-21swapper/1308:05:475
2726899199191,7cyclictest0-21swapper/1308:05:475
2729799198192,4cyclictest1367-21dbus-daemon10:39:1331
2729799198192,4cyclictest1367-21dbus-daemon10:39:1331
2726899198192,4cyclictest0-21swapper/1308:20:295
2729799197191,4cyclictest0-21swapper/3709:42:1931
2729799197191,4cyclictest0-21swapper/3709:42:1931
2729199196190,4cyclictest0-21swapper/3310:25:2127
2729199196190,4cyclictest0-21swapper/3310:25:2127
2728999195190,3cyclictest0-21swapper/3211:55:2226
2728999195190,3cyclictest0-21swapper/3211:55:2226
2728999195190,3cyclictest0-21swapper/3211:55:2226
2729199194187,5cyclictest0-21swapper/3310:10:1827
2729199194187,5cyclictest0-21swapper/3310:10:1827
2729199194187,5cyclictest0-21swapper/3310:10:1827
2728699194189,4cyclictest0-21swapper/2908:50:1522
2728699194189,4cyclictest0-21swapper/2908:50:1422
2728999191183,4cyclictest4408-21CPU26
2728999191183,4cyclictest4408-21CPU26
2728999191176,11cyclictest0-21swapper/3211:40:1226
2728999191176,11cyclictest0-21swapper/3211:40:1226
2728999191176,11cyclictest0-21swapper/3211:40:1226
2729199190178,9cyclictest0-21swapper/3310:30:4027
2729199190178,9cyclictest0-21swapper/3310:30:4027
2727299190181,7cyclictest16196-21cat07:30:038
2727299190181,7cyclictest16196-21cat07:30:038
2729799189181,5cyclictest1367-21dbus-daemon09:34:5831
2729799189181,5cyclictest1367-21dbus-daemon09:34:5831
2729799189181,5cyclictest1367-21dbus-daemon09:34:5831
2728999189171,16cyclictest0-21swapper/3211:50:1626
2728999189171,16cyclictest0-21swapper/3211:50:1626
2728699189183,4cyclictest0-21swapper/2908:45:2722
2728699189183,4cyclictest0-21swapper/2908:45:2722
2729799188182,4cyclictest0-21swapper/3709:39:1531
2729799188182,4cyclictest0-21swapper/3709:39:1531
2729799188182,4cyclictest0-21swapper/3709:39:1531
2729799188181,5cyclictest0-21swapper/3709:05:1231
2729799188181,5cyclictest0-21swapper/3709:05:1231
2729799188181,5cyclictest0-21swapper/3709:05:1231
2729799188179,6cyclictest0-21swapper/3709:25:1831
2729799188179,6cyclictest0-21swapper/3709:25:1731
2728999188182,4cyclictest40604-21timerwakeupswit12:15:3626
2728999188182,4cyclictest40604-21timerwakeupswit12:15:3526
2728999188179,7cyclictest6866-21cp12:34:2526
2728999188179,7cyclictest6866-21cp12:34:2526
2728999188179,7cyclictest6866-21cp12:34:2526
2728999188172,12cyclictest3546-21CPU26
2728999188172,12cyclictest3546-21CPU26
2729799187181,4cyclictest0-21swapper/3707:10:2031
2729799187181,4cyclictest0-21swapper/3707:10:2031
2729199187180,3cyclictest4408-21CPU27
2729199187180,3cyclictest4408-21CPU27
2728999187183,2cyclictest27077-21sshd11:35:2026
2728999187183,2cyclictest27077-21sshd11:35:2026
2727999187182,2cyclictest0-21swapper/2311:48:2816
2727999187182,2cyclictest0-21swapper/2311:48:2716
2725599187129,52cyclictest0-21swapper/210:30:3712
2725599187129,52cyclictest0-21swapper/210:30:3712
2729199186179,3cyclictest37267-21CPU27
2729199186179,3cyclictest37267-21CPU27
2729199186179,3cyclictest37267-21CPU27
2729199186178,6cyclictest0-21swapper/3309:50:2027
2729199186178,6cyclictest0-21swapper/3309:50:2027
2729199186178,6cyclictest0-21swapper/3309:50:2027
2728999186181,4cyclictest0-21swapper/3211:14:1226
2728999186181,4cyclictest0-21swapper/3211:14:1226
2728999186181,4cyclictest0-21swapper/3211:14:1226
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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