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2026-06-12 - 00:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Jun 11, 2026 13:03:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2968099227207,5cyclictest31410-21sshd09:25:1831
2968099227207,5cyclictest31410-21sshd09:25:1731
2968099227207,5cyclictest31410-21sshd09:25:1731
2964999220180,26cyclictest1392-21gdbus11:40:043
2964999220180,26cyclictest1392-21gdbus11:40:043
2964999220180,26cyclictest1392-21gdbus11:40:033
2968299210193,7cyclictest0-21swapper/3911:06:0233
2968299210193,7cyclictest0-21swapper/3911:06:0233
2968299210193,7cyclictest0-21swapper/3911:06:0133
2964299209202,4cyclictest2454-21CPU35
2964299209202,4cyclictest2454-21CPU35
2964599208203,4cyclictest0-21swapper/812:04:0838
2964599208203,4cyclictest0-21swapper/812:04:0838
2964599208203,4cyclictest0-21swapper/812:04:0838
2966799207143,59cyclictest4408-21CPU18
2966799207143,59cyclictest4408-21CPU18
2966799207143,59cyclictest4408-21CPU18
2964599206193,11cyclictest0-21swapper/811:22:1438
2964599206193,11cyclictest0-21swapper/811:22:1338
2966999205197,4cyclictest1367-21dbus-daemon09:20:1120
2966999205197,4cyclictest1367-21dbus-daemon09:20:1120
296829920398,96cyclictest4408-21CPU33
296829920398,96cyclictest4408-21CPU33
2968299203194,5cyclictest23664-21hddtemp_smartct11:00:2033
2968299203194,5cyclictest23664-21hddtemp_smartct11:00:2033
2968299203194,5cyclictest23664-21hddtemp_smartct11:00:2033
2968099203196,5cyclictest17484-21nfsd08:10:1831
2968099203196,5cyclictest17484-21nfsd08:10:1831
2968099202197,4cyclictest0-21swapper/3710:01:5531
2968099202197,4cyclictest0-21swapper/3710:01:5531
2968099200195,4cyclictest0-21swapper/3709:48:2231
2968099200195,4cyclictest0-21swapper/3709:48:2131
2968099200195,4cyclictest0-21swapper/3709:48:2131
2968099198191,4cyclictest0-21swapper/3709:36:1431
2968099198191,4cyclictest0-21swapper/3709:36:1331
2968299197186,8cyclictest0-21swapper/3907:10:2633
2968299197186,8cyclictest0-21swapper/3907:10:2533
2968099197191,5cyclictest0-21swapper/3709:51:4431
2968099197191,5cyclictest0-21swapper/3709:51:4331
2967099197186,9cyclictest0-21swapper/2811:13:1321
2967099197186,9cyclictest0-21swapper/2811:13:1321
2964599196182,11cyclictest0-21swapper/808:50:3338
2968099195188,5cyclictest0-21swapper/3709:55:1531
2968099195188,5cyclictest0-21swapper/3709:55:1531
2968099195188,5cyclictest0-21swapper/3709:55:1531
2966799195181,12cyclictest0-21swapper/2510:58:4418
2966799195181,12cyclictest0-21swapper/2510:58:4318
2966799195181,12cyclictest0-21swapper/2510:58:4318
2964599195183,10cyclictest0-21swapper/811:16:0138
2964599195183,10cyclictest0-21swapper/811:16:0138
2964599195183,10cyclictest0-21swapper/811:16:0138
2968099194189,4cyclictest0-21swapper/3709:31:0631
2968099194189,4cyclictest0-21swapper/3709:31:0631
2967099194181,6cyclictest0-21swapper/2811:45:1321
2967099194181,6cyclictest0-21swapper/2811:45:1321
2967099194181,6cyclictest0-21swapper/2811:45:1321
2964999194184,7cyclictest0-21swapper/1110:35:153
2964999194184,7cyclictest0-21swapper/1110:35:153
2963999194140,50cyclictest2466-21CPU23
2963999194140,50cyclictest2466-21CPU23
2964599193187,4cyclictest0-21swapper/812:06:0438
2964599193187,4cyclictest0-21swapper/812:06:0438
2964599193187,4cyclictest0-21swapper/812:06:0438
2964599193186,5cyclictest0-21swapper/809:49:0838
2964599193186,5cyclictest0-21swapper/809:49:0838
2964599193186,5cyclictest0-21swapper/809:49:0838
2968099192186,4cyclictest0-21swapper/3708:31:0131
2968099192186,4cyclictest0-21swapper/3708:31:0031
2966999192187,4cyclictest0-21swapper/2712:20:3220
2966999192187,4cyclictest0-21swapper/2712:20:3220
2964999192184,5cyclictest1358-21ModemManager12:32:063
2964999192184,5cyclictest1358-21ModemManager12:32:063
2964999192184,5cyclictest1358-21ModemManager12:32:063
2964999192184,4cyclictest2516-21sshd10:30:263
2964999192184,4cyclictest2516-21sshd10:30:253
2964999192183,6cyclictest37269-21CPU3
2964999192183,6cyclictest37269-21CPU3
2964999192183,6cyclictest37269-21CPU3
2964299192187,4cyclictest0-21swapper/507:50:0735
2964299192183,7cyclictest0-21swapper/507:40:0135
2964299192183,7cyclictest0-21swapper/507:40:0135
2968099191183,6cyclictest0-21swapper/3707:25:0131
2968099191183,6cyclictest0-21swapper/3707:25:0131
2964599191152,34cyclictest3610-21CPU38
2964599191152,34cyclictest3610-21CPU38
2964599191152,34cyclictest3610-21CPU38
2968299190178,10cyclictest0-21swapper/3911:49:2233
2968299190178,10cyclictest0-21swapper/3911:49:2133
2968299190178,10cyclictest0-21swapper/3911:49:2133
2967499190173,9cyclictest171rcu_preempt10:33:3026
2967499190173,9cyclictest171rcu_preempt10:33:3026
2964199190183,5cyclictest0-21swapper/407:20:1634
2964199190183,5cyclictest0-21swapper/407:20:1534
2964999189183,4cyclictest0-21swapper/1107:15:153
2964999189183,4cyclictest0-21swapper/1107:15:153
2964999189182,5cyclictest0-21swapper/1111:11:003
2964999189182,5cyclictest0-21swapper/1111:11:003
2964999189181,4cyclictest3541-21CPU3
2964999189181,4cyclictest3541-21CPU3
2964999189181,4cyclictest3541-21CPU3
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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