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2026-09-21 - 17:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Sep 21, 2026 13:02:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2495899227208,11cyclictest0-21swapper/3311:10:2627
2495899227208,11cyclictest0-21swapper/3311:10:2627
2495899216209,5cyclictest0-21swapper/3312:10:1627
2495899216209,5cyclictest0-21swapper/3312:10:1627
2495899216209,5cyclictest0-21swapper/3312:10:1627
2495899214207,5cyclictest0-21swapper/3312:33:5327
2495899214207,5cyclictest0-21swapper/3312:33:5327
2495899214205,7cyclictest0-21swapper/3309:40:5927
2495899214205,7cyclictest0-21swapper/3309:40:5927
2495899214195,9cyclictest5079-2110-uname10:25:1627
2495899214195,9cyclictest5079-2110-uname10:25:1627
2495899213208,3cyclictest0-21swapper/3312:18:3327
2495899213208,3cyclictest0-21swapper/3312:18:3327
2495899209201,6cyclictest0-21swapper/3309:47:1227
2495899209201,6cyclictest0-21swapper/3309:47:1227
2495899209201,6cyclictest0-21swapper/3309:47:1227
2495899207202,4cyclictest0-21swapper/3309:58:5727
2495899207202,4cyclictest0-21swapper/3309:58:5627
2495899206199,5cyclictest0-21swapper/3310:49:4327
2495899206199,5cyclictest0-21swapper/3310:49:4327
2495899203184,11cyclictest0-21swapper/3312:07:3627
2495899203184,11cyclictest0-21swapper/3312:07:3627
2494599203196,5cyclictest0-21swapper/2308:35:2016
2494599203196,5cyclictest0-21swapper/2308:35:2016
2492299202171,19cyclictest0-21swapper/412:33:2034
2492299202171,19cyclictest0-21swapper/412:33:2034
2495899201195,4cyclictest0-21swapper/3309:12:5227
2495899201195,4cyclictest0-21swapper/3309:12:5227
2495899201194,3cyclictest3543-21CPU27
2495899201194,3cyclictest3543-21CPU27
2495899201194,3cyclictest3543-21CPU27
2495899201192,6cyclictest1-21systemd10:21:1127
2495899201192,6cyclictest1-21systemd10:21:1127
2495899201192,6cyclictest1-21systemd10:21:1127
2495899201190,5cyclictest0-21swapper/3310:50:2927
2495899201190,5cyclictest0-21swapper/3310:50:2927
2495899201190,5cyclictest0-21swapper/3310:50:2927
2494599201195,4cyclictest0-21swapper/2307:40:0316
2494599201195,4cyclictest0-21swapper/2307:40:0316
2495899200192,6cyclictest0-21swapper/3310:00:2227
2495899200192,6cyclictest0-21swapper/3310:00:2227
2495899200192,6cyclictest0-21swapper/3310:00:2227
2495899200180,12cyclictest0-21swapper/3310:11:1127
2495899200180,12cyclictest0-21swapper/3310:11:1127
2495899200180,12cyclictest0-21swapper/3310:11:1127
2494899200182,12cyclictest0-21swapper/2512:33:0518
2494899200182,12cyclictest0-21swapper/2512:33:0518
2495899198192,4cyclictest0-21swapper/3312:02:0627
2495899198192,4cyclictest0-21swapper/3312:02:0627
2495899198190,5cyclictest3548-21CPU27
2495899198190,5cyclictest3548-21CPU27
2495899198190,5cyclictest3548-21CPU27
2495899198188,8cyclictest0-21swapper/3311:40:3227
2495899198188,8cyclictest0-21swapper/3311:40:3127
2495899197190,5cyclictest2327-21qemu-system-x8611:23:0927
2495899197190,5cyclictest2327-21qemu-system-x8611:23:0927
2495899197189,4cyclictest0-21swapper/3309:24:3827
2495899197189,4cyclictest0-21swapper/3309:24:3827
2495899197189,4cyclictest0-21swapper/3309:24:3827
2495899197188,7cyclictest0-21swapper/3312:35:4527
2495899197188,7cyclictest0-21swapper/3312:35:4527
2491899197185,6cyclictest0-21swapper/011:59:440
2491899197185,6cyclictest0-21swapper/011:59:440
2491899197185,6cyclictest0-21swapper/011:59:440
2495399196183,7cyclictest0-21swapper/2912:14:5622
2495399196183,7cyclictest0-21swapper/2912:14:5622
2495399196183,7cyclictest0-21swapper/2912:14:5622
2496399195178,14cyclictest0-21swapper/3711:01:3531
2496399195178,14cyclictest0-21swapper/3711:01:3531
2496399195178,14cyclictest0-21swapper/3711:01:3531
2495899195189,5cyclictest0-21swapper/3310:44:1727
2495899195189,5cyclictest0-21swapper/3310:44:1727
2495899195184,8cyclictest0-21swapper/3308:45:0027
2495899195184,8cyclictest0-21swapper/3308:45:0027
2494599195188,5cyclictest0-21swapper/2311:48:0116
2494599195188,5cyclictest0-21swapper/2311:48:0116
2495899194186,6cyclictest0-21swapper/3311:50:4927
2495899194186,6cyclictest0-21swapper/3311:50:4927
2495899194186,6cyclictest0-21swapper/3311:50:4927
2495899194186,5cyclictest0-21swapper/3307:15:2627
2495899194186,5cyclictest0-21swapper/3307:15:2627
2495899194185,7cyclictest0-21swapper/3309:27:4427
2495899194185,7cyclictest0-21swapper/3309:27:4427
2495899194185,7cyclictest0-21swapper/3309:27:4427
2495899194184,8cyclictest0-21swapper/3311:00:0727
2495899194184,8cyclictest0-21swapper/3311:00:0727
2495899194182,5cyclictest3544-21CPU27
2495899194182,5cyclictest3544-21CPU27
2495899194181,6cyclictest0-21swapper/3310:39:5327
2495899194181,6cyclictest0-21swapper/3310:39:5327
2495899194177,12cyclictest3541-21CPU27
2495899194177,12cyclictest3541-21CPU27
2495899194177,12cyclictest3541-21CPU27
2495899193185,6cyclictest0-21swapper/3311:05:2027
2495899193185,6cyclictest0-21swapper/3311:05:2027
2495899193185,6cyclictest0-21swapper/3311:05:2027
2495899193185,6cyclictest0-21swapper/3311:05:2027
2495899192188,2cyclictest0-21swapper/3308:22:1627
2495899192188,2cyclictest0-21swapper/3308:22:1627
2495899192185,5cyclictest0-21swapper/3311:46:0227
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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