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2026-03-05 - 20:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Mar 05, 2026 13:03:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2124499243238,2cyclictest0-21swapper/1412:14:116
2124499243238,2cyclictest0-21swapper/1412:14:116
2124499243238,2cyclictest0-21swapper/1412:14:116
2124599239214,15cyclictest0-21swapper/1511:00:017
2124599239214,15cyclictest0-21swapper/1511:00:017
2124599239214,15cyclictest0-21swapper/1511:00:007
2126099228221,5cyclictest0-21swapper/2711:05:2220
2126099228221,5cyclictest0-21swapper/2711:05:2220
2123599221217,2cyclictest0-21swapper/707:10:1937
2123599221217,2cyclictest0-21swapper/707:10:1937
2124599218210,6cyclictest0-21swapper/1512:05:207
2124599218210,6cyclictest0-21swapper/1512:05:207
2126799215174,28cyclictest2466-21CPU27
2126799215174,28cyclictest2466-21CPU27
2126799215174,28cyclictest2466-21CPU27
2127299214205,7cyclictest0-21swapper/3811:16:2732
2127299214205,7cyclictest0-21swapper/3811:16:2732
2123999214210,2cyclictest0-21swapper/912:24:2039
2123999214210,2cyclictest0-21swapper/912:24:2039
2123999214210,2cyclictest0-21swapper/912:24:2039
2124599212200,10cyclictest0-21swapper/1511:55:007
2124599212200,10cyclictest0-21swapper/1511:55:007
2124599212200,10cyclictest0-21swapper/1511:55:007
2125499211208,2cyclictest0-21swapper/2209:51:1315
2125499211208,2cyclictest0-21swapper/2209:51:1315
2125499211208,2cyclictest0-21swapper/2209:51:1315
2124599210204,4cyclictest0-21swapper/1509:15:197
2124599210204,4cyclictest0-21swapper/1509:15:197
2124599210204,4cyclictest0-21swapper/1509:15:197
2124099210195,11cyclictest0-21swapper/1007:30:252
2124099210195,11cyclictest0-21swapper/1007:30:252
2124599209203,4cyclictest0-21swapper/1511:03:377
2124599209203,4cyclictest0-21swapper/1511:03:377
2124599209203,4cyclictest0-21swapper/1511:03:377
2124599208197,9cyclictest0-21swapper/1509:56:407
2124599208197,9cyclictest0-21swapper/1509:56:407
2124599208197,9cyclictest0-21swapper/1509:56:407
2125599207204,1cyclictest0-21swapper/2310:55:5016
2125599207204,1cyclictest0-21swapper/2310:55:5016
2125599207204,1cyclictest0-21swapper/2310:55:4916
2124599207201,4cyclictest0-21swapper/1512:30:347
2124599207201,4cyclictest0-21swapper/1512:30:347
2124599207201,4cyclictest0-21swapper/1510:53:117
2124599207201,4cyclictest0-21swapper/1510:53:117
2124599206199,5cyclictest0-21swapper/1510:16:207
2124599206199,5cyclictest0-21swapper/1510:16:207
2124599205198,5cyclictest0-21swapper/1509:05:207
2124599205198,5cyclictest0-21swapper/1509:05:207
2124599205198,5cyclictest0-21swapper/1509:05:207
2124599205197,6cyclictest0-21swapper/1510:31:447
2124599205197,6cyclictest0-21swapper/1510:31:447
2124599205196,5cyclictest37270-21CPU7
2124599205196,5cyclictest37270-21CPU7
2124599205196,5cyclictest37270-21CPU7
2124599205186,11cyclictest0-21swapper/1511:47:147
2124599205186,11cyclictest0-21swapper/1511:47:147
2124599205186,11cyclictest0-21swapper/1511:47:147
2124599205182,16cyclictest0-21swapper/1511:23:417
2124599205182,16cyclictest0-21swapper/1511:23:417
2124599205182,16cyclictest0-21swapper/1511:23:407
2124599204199,4cyclictest0-21swapper/1510:00:417
2124599204199,4cyclictest0-21swapper/1510:00:407
2124599204197,6cyclictest0-21swapper/1511:36:317
2124599204197,6cyclictest0-21swapper/1511:36:317
2124599204197,6cyclictest0-21swapper/1511:36:307
2124599203199,3cyclictest0-21swapper/1509:47:597
2124599203199,3cyclictest0-21swapper/1509:47:597
2124599203198,4cyclictest0-21swapper/1512:24:217
2124599203198,4cyclictest0-21swapper/1512:24:217
2124599203198,4cyclictest0-21swapper/1512:24:217
2122699203197,4cyclictest0-21swapper/008:25:300
2122699203197,4cyclictest0-21swapper/008:25:300
2122699203197,4cyclictest0-21swapper/008:25:300
2124599202195,5cyclictest0-21swapper/1510:45:197
2124599202195,5cyclictest0-21swapper/1510:45:197
2124599202195,5cyclictest0-21swapper/1510:45:197
2124799201189,11cyclictest0-21swapper/1612:04:078
2124799201189,11cyclictest0-21swapper/1612:04:078
2124599201196,4cyclictest0-21swapper/1512:26:027
2124599201196,4cyclictest0-21swapper/1512:26:027
2124599201196,4cyclictest0-21swapper/1510:39:057
2124599201196,4cyclictest0-21swapper/1510:39:057
2124599201196,4cyclictest0-21swapper/1510:39:057
2124599201194,5cyclictest0-21swapper/1509:26:477
2124599201194,5cyclictest0-21swapper/1509:26:477
2124599201194,5cyclictest0-21swapper/1509:26:467
2124599201194,5cyclictest0-21swapper/1508:45:017
2124599201194,5cyclictest0-21swapper/1508:45:017
2124599201193,4cyclictest3542-21CPU7
2124599201193,4cyclictest3542-21CPU7
2124599201193,4cyclictest3542-21CPU7
2124599201192,5cyclictest2454-21CPU7
2124599201192,5cyclictest2454-21CPU7
2124599201192,5cyclictest2454-21CPU7
2125599200159,38cyclictest2454-21CPU16
2125599200159,38cyclictest2454-21CPU16
2124599200192,7cyclictest21976-21diskstats09:20:177
2124599200192,7cyclictest21976-21diskstats09:20:177
2124599200192,6cyclictest0-21swapper/1511:57:067
2124599200192,6cyclictest0-21swapper/1511:57:067
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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