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2026-02-10 - 13:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Feb 10, 2026 01:02:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4027999209201,6cyclictest0-21swapper/3019:15:2424
4027999209201,6cyclictest0-21swapper/3019:15:2424
4028899198189,7cyclictest0-21swapper/3600:13:0030
4028899198189,7cyclictest0-21swapper/3600:13:0030
4028899198189,7cyclictest0-21swapper/3600:12:5930
4027299198142,40cyclictest0-21swapper/2419:30:2117
4027299198142,40cyclictest0-21swapper/2419:30:2117
4027999194179,12cyclictest0-21swapper/3019:20:0524
4027999194179,12cyclictest0-21swapper/3019:20:0424
4024699186174,9cyclictest1442-21gdbus23:06:081
4024699186174,9cyclictest1442-21gdbus23:06:081
4027299185161,7cyclictest0-21swapper/2419:44:5417
4027299185161,7cyclictest0-21swapper/2419:44:5317
40274991821,4cyclictest1358-21ModemManager22:05:1619
40274991821,4cyclictest1358-21ModemManager22:05:1619
4024699181175,4cyclictest0-21swapper/100:19:091
4024699181175,4cyclictest0-21swapper/100:19:091
4028699179141,24cyclictest0-21swapper/3522:39:5129
4028699179141,24cyclictest0-21swapper/3522:39:5129
4027999177151,15cyclictest0-21swapper/3000:03:0924
4027999177151,15cyclictest0-21swapper/3000:03:0924
4024699176164,8cyclictest3542-21CPU1
4024699176164,8cyclictest3542-21CPU1
40286991751,169cyclictest0-21swapper/3500:25:2229
40286991751,169cyclictest0-21swapper/3500:25:2229
40286991751,169cyclictest0-21swapper/3500:25:2229
4027999175164,7cyclictest37352-21CPU24
4027999175164,7cyclictest37352-21CPU24
4024699175168,5cyclictest0-21swapper/122:30:461
4024699175168,5cyclictest0-21swapper/122:30:461
4026499174152,15cyclictest0-21swapper/1600:13:008
4026499174152,15cyclictest0-21swapper/1600:13:008
4026499174152,15cyclictest0-21swapper/1600:12:598
4025499174169,3cyclictest0-21swapper/822:16:1138
4025499174169,3cyclictest0-21swapper/822:16:1138
4025499174169,3cyclictest0-21swapper/822:16:1038
4027899173114,55cyclictest3545-21CPU22
4027899173114,55cyclictest3545-21CPU22
4027299173155,10cyclictest0-21swapper/2420:21:1217
4027299173155,10cyclictest0-21swapper/2420:21:1217
4025899171163,5cyclictest2454-21CPU4
4025899171163,5cyclictest2454-21CPU4
4025899171163,5cyclictest2454-21CPU4
4024699171168,2cyclictest0-21swapper/122:29:581
4024699171168,2cyclictest0-21swapper/122:29:581
4027199169159,6cyclictest0-21swapper/2321:32:4616
4027199169159,6cyclictest0-21swapper/2321:32:4616
4026999169157,8cyclictest0-21swapper/2100:36:3314
4026999169157,8cyclictest0-21swapper/2100:36:3214
4024899169163,4cyclictest0-21swapper/319:35:0623
4024899169163,4cyclictest0-21swapper/319:35:0523
4025599168161,4cyclictest0-21swapper/921:27:5739
4025599168161,4cyclictest0-21swapper/921:27:5739
4025599168161,4cyclictest0-21swapper/921:27:5739
4027299167157,8cyclictest0-21swapper/2420:36:0217
4027299167157,8cyclictest0-21swapper/2420:36:0217
4027299167140,8cyclictest171rcu_preempt23:53:0017
4027299167140,8cyclictest171rcu_preempt23:52:5917
4027299167140,8cyclictest171rcu_preempt23:52:5917
40253991671,156cyclictest0-21swapper/700:20:2337
40253991671,156cyclictest0-21swapper/700:20:2237
4024699167162,4cyclictest0-21swapper/123:33:251
4024699167162,4cyclictest0-21swapper/123:33:251
4027199166150,12cyclictest0-21swapper/2322:45:5616
4027199166150,12cyclictest0-21swapper/2322:45:5616
4027199166150,12cyclictest0-21swapper/2322:45:5616
4026499164144,8cyclictest0-21swapper/1623:23:388
4026499164144,8cyclictest0-21swapper/1623:23:388
4026499164144,8cyclictest0-21swapper/1623:23:388
4027199163152,6cyclictest0-21swapper/2323:36:3816
4027199163152,6cyclictest0-21swapper/2323:36:3816
4027199163152,6cyclictest0-21swapper/2323:36:3716
4025399163118,38cyclictest0-21swapper/700:09:4237
4025399163118,38cyclictest0-21swapper/700:09:4237
4027999162128,18cyclictest0-21swapper/3022:51:4124
4027999162128,18cyclictest0-21swapper/3022:51:4124
4027299162139,9cyclictest171rcu_preempt23:48:3517
4027299162139,9cyclictest171rcu_preempt23:48:3517
4025599162143,6cyclictest0-21swapper/922:38:2239
4025599162143,6cyclictest0-21swapper/922:38:2239
4025399162123,29cyclictest0-21swapper/722:52:0937
4025399162123,29cyclictest0-21swapper/722:52:0837
4024699162150,10cyclictest755-21systemd-journal22:38:371
4024699162150,10cyclictest755-21systemd-journal22:38:361
4024699162149,10cyclictest0-21swapper/100:06:381
4024699162149,10cyclictest0-21swapper/100:06:381
4028699161138,20cyclictest0-21swapper/3523:33:1429
4028699161138,20cyclictest0-21swapper/3523:33:1429
4027999161152,6cyclictest0-21swapper/3019:25:2224
4027999161152,6cyclictest0-21swapper/3019:25:2224
4027299161140,8cyclictest0-21swapper/2423:25:5217
4027299161140,8cyclictest0-21swapper/2423:25:5117
4024699161150,6cyclictest37354-21CPU1
4024699161150,6cyclictest37354-21CPU1
4024699161150,6cyclictest37354-21CPU1
4024699161147,6cyclictest0-21swapper/123:35:421
4024699161147,6cyclictest0-21swapper/123:35:411
4024699161147,6cyclictest0-21swapper/123:35:411
4024699161146,12cyclictest0-21swapper/121:10:261
4024699161146,12cyclictest0-21swapper/121:10:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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