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2024-04-17 - 23:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Apr 17, 2024 13:01:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2197299227222,3cyclictest0-21swapper/610:48:0636
2197299227222,3cyclictest0-21swapper/610:48:0636
2197299227222,3cyclictest0-21swapper/610:48:0636
2200699220157,50cyclictest4908-21CPU30
2200699220157,50cyclictest4908-21CPU30
2197299220184,33cyclictest11901-21CPU36
2197299220184,33cyclictest11901-21CPU36
2197299220184,33cyclictest11901-21CPU36
2196699218207,9cyclictest0-21swapper/011:15:260
2196699218207,9cyclictest0-21swapper/011:15:260
2199299215211,2cyclictest0-21swapper/2309:22:2216
2199299215211,2cyclictest0-21swapper/2309:22:2216
2196699214206,5cyclictest2564-21kworker/0:3-cgroup_destroy10:59:200
2196699214206,5cyclictest2564-21kworker/0:3-cgroup_destroy10:59:200
2196699214206,5cyclictest2564-21kworker/0:3-cgroup_destroy10:59:190
2196699212194,7cyclictest0-21swapper/011:53:470
2196699212194,7cyclictest0-21swapper/011:53:470
2196699212194,7cyclictest0-21swapper/011:53:470
2197399210200,7cyclictest0-21swapper/711:28:2537
2197399210200,7cyclictest0-21swapper/711:28:2537
2196699209186,9cyclictest0-21swapper/012:39:570
2196699209186,9cyclictest0-21swapper/012:39:570
2196699209186,9cyclictest0-21swapper/012:39:570
2196799208199,7cyclictest22264-21sh09:50:371
2196799208199,7cyclictest22264-21sh09:50:371
2196699205200,4cyclictest0-21swapper/010:33:220
2196699205200,4cyclictest0-21swapper/010:33:220
2196699205200,4cyclictest0-21swapper/010:33:220
2199499204164,36cyclictest4631-21CPU18
2199499204164,36cyclictest4631-21CPU18
2199499204164,36cyclictest4631-21CPU18
2196799203198,3cyclictest0-21swapper/109:20:221
2196799203198,3cyclictest0-21swapper/109:20:221
2198499202114,84cyclictest11900-21CPU9
2198499202114,84cyclictest11900-21CPU9
2197999202179,20cyclictest11905-21CPU4
2197999202179,20cyclictest11905-21CPU4
2200599200197,2cyclictest0-21swapper/3512:18:1629
2200599200197,2cyclictest0-21swapper/3512:18:1629
2200599200197,2cyclictest0-21swapper/3512:18:1529
2197299200186,11cyclictest0-21swapper/611:03:1036
2197299200186,11cyclictest0-21swapper/611:03:1036
2201099199187,6cyclictest0-21swapper/3909:14:1233
2201099199187,6cyclictest0-21swapper/3909:14:1233
2197399199187,11cyclictest0-21swapper/710:15:3437
2197399199187,11cyclictest0-21swapper/710:15:3437
2196699199176,13cyclictest11900-21CPU0
2196699199176,13cyclictest11900-21CPU0
2197099198192,3cyclictest1930-21gdbus11:00:4534
2197099198192,3cyclictest1930-21gdbus11:00:4534
2196799198194,2cyclictest0-21swapper/110:53:391
2196799198194,2cyclictest0-21swapper/110:53:391
2196799198194,2cyclictest0-21swapper/110:53:391
2196699198188,8cyclictest0-21swapper/012:32:350
2196699198188,8cyclictest0-21swapper/012:32:350
2199999197191,5cyclictest0-21swapper/3009:01:3424
2199999197191,5cyclictest0-21swapper/3009:01:3424
2199999197186,7cyclictest9334-21CPU24
2199999197186,7cyclictest9334-21CPU24
2198699197174,18cyclictest4636-21CPU11
2198699197174,18cyclictest4636-21CPU11
2198699197174,18cyclictest4636-21CPU11
2196699197190,5cyclictest0-21swapper/011:26:350
2196699197190,5cyclictest0-21swapper/011:26:350
2197299196177,12cyclictest1977-21kworker/u81:3+events_unbound12:32:2436
2197299196177,12cyclictest1977-21kworker/u81:3+events_unbound12:32:2436
2197099196146,47cyclictest4908-21CPU34
2197099196146,47cyclictest4908-21CPU34
2197099196146,47cyclictest4908-21CPU34
2196699196164,22cyclictest11899-21CPU0
2196699196164,22cyclictest11899-21CPU0
2196699196164,22cyclictest11899-21CPU0
2198699195159,31cyclictest11901-21CPU11
2198699195159,31cyclictest11901-21CPU11
2198699195159,31cyclictest11901-21CPU11
2196799195191,2cyclictest0-21swapper/108:59:371
2196799195191,2cyclictest0-21swapper/108:59:371
2196699195146,46cyclictest0-21swapper/011:12:320
2196699195146,46cyclictest0-21swapper/011:12:320
2196699195146,46cyclictest0-21swapper/011:12:320
2199999194165,13cyclictest0-21swapper/3009:59:0624
2199999194165,13cyclictest0-21swapper/3009:59:0624
2199999194165,13cyclictest0-21swapper/3009:59:0524
2199499194171,11cyclictest0-21swapper/2508:55:5218
2199499194171,11cyclictest0-21swapper/2508:55:5218
2197999194182,9cyclictest11901-21CPU4
2197999194182,9cyclictest11901-21CPU4
2197999194179,9cyclictest171rcu_preempt08:50:464
2197999194179,9cyclictest171rcu_preempt08:50:464
2196699194186,6cyclictest0-21swapper/009:31:150
2196699194186,6cyclictest0-21swapper/009:31:150
2197999193177,12cyclictest4909-21CPU4
2197999193177,12cyclictest4909-21CPU4
2197299193177,14cyclictest0-21swapper/611:05:3636
2197299193177,14cyclictest0-21swapper/611:05:3636
2200199192189,2cyclictest0-21swapper/3210:34:5326
2200199192189,2cyclictest0-21swapper/3210:34:5326
2200199192189,2cyclictest0-21swapper/3210:34:5326
2198199191182,7cyclictest0-21swapper/1410:21:556
2198199191182,7cyclictest0-21swapper/1410:21:556
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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