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2026-01-19 - 18:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Jan 19, 2026 13:02:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3578399226220,4cyclictest0-21swapper/1308:20:145
3578399226220,4cyclictest0-21swapper/1308:20:145
3577799222213,6cyclictest0-21swapper/712:29:0837
3577799222213,6cyclictest0-21swapper/712:29:0837
3577799222213,6cyclictest0-21swapper/712:29:0837
3579799214207,3cyclictest13569-21cp10:55:2016
3579799214207,3cyclictest13569-21cp10:55:1916
3580599213205,5cyclictest0-21swapper/3111:14:0625
3580599213205,5cyclictest0-21swapper/3111:14:0625
3577799212206,4cyclictest0-21swapper/709:21:0837
3577799212206,4cyclictest0-21swapper/709:21:0837
3577799212206,4cyclictest0-21swapper/709:21:0837
3577799210203,5cyclictest17715-21/usr/sbin/munin11:40:1737
3577799210203,5cyclictest17715-21/usr/sbin/munin11:40:1737
3577799210203,5cyclictest17715-21/usr/sbin/munin11:40:1737
3577799210203,5cyclictest0-21swapper/712:05:2137
3577799210203,5cyclictest0-21swapper/712:05:2137
3577799210203,5cyclictest0-21swapper/712:05:2137
3577799209193,11cyclictest0-21swapper/712:20:4437
3577799209193,11cyclictest0-21swapper/712:20:4437
3577799209193,11cyclictest0-21swapper/712:20:4437
3580599208192,12cyclictest0-21swapper/3108:40:1425
3580599208192,12cyclictest0-21swapper/3108:40:1425
3579799208202,4cyclictest17483-21nfsd10:30:2116
3579799208202,4cyclictest17483-21nfsd10:30:2116
3579799208202,4cyclictest17483-21nfsd10:30:2116
3579799208200,6cyclictest0-21swapper/2311:06:3016
3579799208200,6cyclictest0-21swapper/2311:06:3016
3578599208205,2cyclictest0-21swapper/1408:10:206
3576999208104,90cyclictest3543-21CPU0
3576999208104,90cyclictest3543-21CPU0
3576999207203,3cyclictest0-21swapper/009:13:470
3576999207203,3cyclictest0-21swapper/009:13:470
3576999207203,3cyclictest0-21swapper/009:13:470
3579799206198,6cyclictest0-21swapper/2312:23:5916
3579799206198,6cyclictest0-21swapper/2312:23:5916
3579799206198,6cyclictest0-21swapper/2312:23:5916
3577799206198,6cyclictest0-21swapper/710:10:1237
3577799206198,6cyclictest0-21swapper/710:10:1237
3577799206198,6cyclictest0-21swapper/710:10:1237
3577799206195,6cyclictest0-21swapper/707:25:1337
3577799206195,6cyclictest0-21swapper/707:25:1337
3580599205197,4cyclictest3548-21CPU25
3580599205197,4cyclictest3548-21CPU25
3580599205197,4cyclictest3548-21CPU25
3579799205200,4cyclictest0-21swapper/2308:10:1216
3577799205199,4cyclictest0-21swapper/711:20:2337
3577799205199,4cyclictest0-21swapper/711:20:2337
3577799205199,4cyclictest0-21swapper/711:20:2237
3580399204195,6cyclictest3600-21qemu-system-x8612:23:0522
3580399204195,6cyclictest3600-21qemu-system-x8612:23:0522
3580399204195,6cyclictest3600-21qemu-system-x8612:23:0522
3577199203199,2cyclictest0-21swapper/112:21:171
3577199203199,2cyclictest0-21swapper/112:21:171
3577199203199,2cyclictest0-21swapper/112:21:161
3577799202194,5cyclictest0-21swapper/707:21:4337
3577799202194,5cyclictest0-21swapper/707:21:4337
3577799202194,4cyclictest2447-21CPU37
3577799202194,4cyclictest2447-21CPU37
3577799202191,9cyclictest0-21swapper/711:35:1337
3577799202191,9cyclictest0-21swapper/711:35:1337
3577799202191,9cyclictest0-21swapper/711:35:1337
3576999202198,2cyclictest6667-21sshd11:39:210
3576999202198,2cyclictest6667-21sshd11:39:210
3576999202198,2cyclictest6667-21sshd11:39:210
3579799201194,3cyclictest3547-21CPU16
3579799201194,3cyclictest3547-21CPU16
3579799201194,3cyclictest3547-21CPU16
3577799201196,4cyclictest0-21swapper/712:31:1637
3577799201196,4cyclictest0-21swapper/712:31:1637
3577799201195,4cyclictest0-21swapper/710:08:5137
3577799201195,4cyclictest0-21swapper/710:08:5137
3577799201195,4cyclictest0-21swapper/710:08:5137
3577299201181,19cyclictest0-21swapper/209:06:3012
3577299201181,19cyclictest0-21swapper/209:06:3012
3577299201181,19cyclictest0-21swapper/209:06:3012
35814992003,5cyclictest2456-21CPU33
35814992003,5cyclictest2456-21CPU33
35814992003,5cyclictest2456-21CPU33
3579799200193,5cyclictest0-21swapper/2310:20:1116
3579799200193,5cyclictest0-21swapper/2310:20:1116
3579799200193,5cyclictest0-21swapper/2310:20:1116
3579799200190,8cyclictest0-21swapper/2311:38:4716
3579799200190,8cyclictest0-21swapper/2311:38:4716
3579799200190,8cyclictest0-21swapper/2311:38:4716
3578899200197,2cyclictest0-21swapper/1709:30:199
3578899200197,2cyclictest0-21swapper/1709:30:199
3577899200197,2cyclictest0-21swapper/811:00:1938
3577899200197,2cyclictest0-21swapper/811:00:1938
3577799200195,4cyclictest0-21swapper/708:35:1637
3577799200195,4cyclictest0-21swapper/708:35:1637
3577799200194,4cyclictest0-21swapper/711:29:1337
3577799200194,4cyclictest0-21swapper/711:29:1337
3577799200194,4cyclictest0-21swapper/711:29:1237
3577799200192,6cyclictest0-21swapper/709:55:2137
3577799200192,6cyclictest0-21swapper/709:55:2137
3577799200192,6cyclictest0-21swapper/709:55:2137
3576999200194,4cyclictest0-21swapper/009:15:130
3576999200194,4cyclictest0-21swapper/009:15:130
3576999200194,4cyclictest0-21swapper/009:15:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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