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2026-01-20 - 14:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Jan 20, 2026 13:01:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1488699210203,5cyclictest0-21swapper/2010:09:1013
1488699210203,5cyclictest0-21swapper/2010:09:1013
1488699193184,7cyclictest0-21swapper/2011:48:0613
1488699193184,7cyclictest0-21swapper/2011:48:0613
149029918962,113cyclictest0-21swapper/3411:13:0828
149029918962,113cyclictest0-21swapper/3411:13:0828
149029918962,113cyclictest0-21swapper/3411:13:0828
1490299184151,24cyclictest0-21swapper/3410:39:0628
1490299184151,24cyclictest0-21swapper/3410:39:0628
1488699184175,7cyclictest0-21swapper/2010:22:2913
1488699184175,7cyclictest0-21swapper/2010:22:2813
1488699184175,7cyclictest0-21swapper/2010:22:2813
1490299183159,18cyclictest0-21swapper/3409:25:3928
1490299183159,18cyclictest0-21swapper/3409:25:3928
1490299183159,18cyclictest0-21swapper/3409:25:3928
1487299179173,4cyclictest0-21swapper/809:52:3638
1487299179173,4cyclictest0-21swapper/809:52:3638
1488699178167,9cyclictest0-21swapper/2011:58:4513
1488699178167,9cyclictest0-21swapper/2011:58:4513
143132178169,5sleep230-21swapper/2307:09:5116
143132178169,5sleep230-21swapper/2307:09:5016
1489699177157,15cyclictest0-21swapper/2809:34:3121
1489699177157,15cyclictest0-21swapper/2809:34:3121
1489699177157,15cyclictest0-21swapper/2809:34:3121
1489699176167,6cyclictest0-21swapper/2811:14:2321
1489699176167,6cyclictest0-21swapper/2811:14:2321
1489699176167,6cyclictest0-21swapper/2811:14:2321
1486199176142,31cyclictest0-21swapper/012:25:560
1486199176142,31cyclictest0-21swapper/012:25:560
1486199176132,34cyclictest0-21swapper/011:52:290
1486199176132,34cyclictest0-21swapper/011:52:290
1486199176132,34cyclictest0-21swapper/011:52:290
1490799175131,40cyclictest0-21swapper/3910:23:3533
1490799175131,40cyclictest0-21swapper/3910:23:3533
1490799175131,40cyclictest0-21swapper/3910:23:3533
1489699175170,4cyclictest0-21swapper/2809:52:3621
1489699175170,4cyclictest0-21swapper/2809:52:3621
1488199175157,13cyclictest0-21swapper/1610:55:258
1488199175157,13cyclictest0-21swapper/1610:55:258
1488199175157,13cyclictest0-21swapper/1610:55:258
14907991741,17cyclictest0-21swapper/3912:35:1533
14907991741,17cyclictest0-21swapper/3912:35:1533
14907991741,17cyclictest0-21swapper/3912:35:1533
1487999174140,31cyclictest0-21swapper/1412:32:566
1487999174140,31cyclictest0-21swapper/1412:32:566
1487999174140,31cyclictest0-21swapper/1412:32:566
1486799174159,12cyclictest0-21swapper/507:10:5735
1489699173161,8cyclictest0-21swapper/2809:21:0121
1489699173161,8cyclictest0-21swapper/2809:21:0121
1488699173166,6cyclictest0-21swapper/2009:59:2413
1488699173166,6cyclictest0-21swapper/2009:59:2313
1488699173166,6cyclictest0-21swapper/2009:59:2313
1490799172135,29cyclictest0-21swapper/3911:02:2933
1490799172135,29cyclictest0-21swapper/3911:02:2933
1490799172135,29cyclictest0-21swapper/3911:02:2933
1488699172160,10cyclictest0-21swapper/2009:18:4313
1488699172160,10cyclictest0-21swapper/2009:18:4313
1486199172131,38cyclictest0-21swapper/010:34:040
1486199172131,38cyclictest0-21swapper/010:34:040
1486199172131,38cyclictest0-21swapper/010:34:040
1490799171123,45cyclictest0-21swapper/3912:30:0933
1490799171123,45cyclictest0-21swapper/3912:30:0933
1490799171123,45cyclictest0-21swapper/3912:30:0933
1489499170158,10cyclictest0-21swapper/2712:27:3320
1489499170158,10cyclictest0-21swapper/2712:27:3320
1489299170162,4cyclictest3609-21CPU19
1489299170162,4cyclictest3609-21CPU19
1489299170162,4cyclictest3609-21CPU19
1488699170163,6cyclictest0-21swapper/2012:18:4513
1488699170163,6cyclictest0-21swapper/2012:18:4413
1486699170162,6cyclictest0-21swapper/409:51:3834
1486699170162,6cyclictest0-21swapper/409:51:3834
14902991691,3cyclictest0-21swapper/3408:00:1928
14902991691,3cyclictest0-21swapper/3408:00:1928
1489499169158,8cyclictest0-21swapper/2712:03:2120
1489499169158,8cyclictest0-21swapper/2712:03:2120
1489499169158,8cyclictest0-21swapper/2712:03:2120
1488699169153,7cyclictest2327-21qemu-system-x8611:20:5213
1488699169153,7cyclictest2327-21qemu-system-x8611:20:5213
1486799169158,6cyclictest2461-21CPU35
1486799169158,6cyclictest2461-21CPU35
1486699169162,5cyclictest0-21swapper/409:50:0734
148619916986,79cyclictest0-21swapper/009:10:460
148619916986,79cyclictest0-21swapper/009:10:460
148619916986,79cyclictest0-21swapper/009:10:460
14907991681,162cyclictest3544-21CPU33
14907991681,162cyclictest3544-21CPU33
1490299168139,25cyclictest0-21swapper/3411:29:2428
1490299168139,25cyclictest0-21swapper/3411:29:2428
1489499168137,17cyclictest171rcu_preempt10:06:2120
1489499168137,17cyclictest171rcu_preempt10:06:2120
1488699168159,7cyclictest0-21swapper/2008:00:2713
1488699168159,7cyclictest0-21swapper/2008:00:2713
1486599168155,11cyclictest0-21swapper/309:42:1223
1486599168155,11cyclictest0-21swapper/309:42:1223
1486599168155,11cyclictest0-21swapper/309:42:1223
1486599168153,10cyclictest0-21swapper/311:38:0323
1486599168153,10cyclictest0-21swapper/311:38:0323
1486599168153,10cyclictest0-21swapper/311:38:0223
1486599168153,10cyclictest0-21swapper/311:38:0223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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