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2026-04-06 - 16:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Apr 06, 2026 13:03:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3885699226222,2cyclictest0-21swapper/3307:45:2027
3885699226222,2cyclictest0-21swapper/3307:45:1927
3881999205193,7cyclictest25005-21gdbus12:04:5512
3881999205193,7cyclictest25005-21gdbus12:04:5412
3881999205193,7cyclictest25005-21gdbus12:04:5412
3883499203197,4cyclictest0-21swapper/1509:23:597
3883499203197,4cyclictest0-21swapper/1509:23:597
3883099199174,21cyclictest3609-21CPU3
3883099199174,21cyclictest3609-21CPU3
3883099199174,21cyclictest3609-21CPU3
3883499198195,2cyclictest0-21swapper/1508:50:007
3883499198195,2cyclictest0-21swapper/1508:50:007
3881999198186,10cyclictest9935-21sshd09:45:1312
3881999198186,10cyclictest9935-21sshd09:45:1312
3883499197191,4cyclictest0-21swapper/1509:15:187
3883499197191,4cyclictest0-21swapper/1509:15:177
3883499197191,4cyclictest0-21swapper/1509:15:177
3883499197187,8cyclictest0-21swapper/1507:35:007
3883499197187,8cyclictest0-21swapper/1507:35:007
3883499196191,3cyclictest39678-21systemd09:12:567
3883499196191,3cyclictest39678-21systemd09:12:567
3883499196191,3cyclictest0-21swapper/1507:35:137
3883499196191,3cyclictest0-21swapper/1507:35:137
3883499196188,6cyclictest0-21swapper/1509:06:347
3883499196188,6cyclictest0-21swapper/1509:06:337
3881999196190,5cyclictest0-21swapper/211:00:1912
3881999196190,5cyclictest0-21swapper/211:00:1812
3881999196190,5cyclictest0-21swapper/211:00:1812
3881999196190,4cyclictest37257-21qemu-system-x8611:16:5412
3881999196190,4cyclictest37257-21qemu-system-x8611:16:5412
3881999195189,3cyclictest24952-21packagekitd09:55:2112
3881999195189,3cyclictest24952-21packagekitd09:55:2112
3881999195189,3cyclictest24952-21packagekitd09:55:2112
3881999195185,5cyclictest3543-21CPU12
3881999195185,5cyclictest3543-21CPU12
3881999195185,5cyclictest3543-21CPU12
3881999195176,13cyclictest0-21swapper/210:07:2512
3881999195176,13cyclictest0-21swapper/210:07:2512
3881999195176,13cyclictest0-21swapper/210:07:2512
388179919498,83cyclictest3609-21CPU1
388179919498,83cyclictest3609-21CPU1
3883499193187,4cyclictest0-21swapper/1509:29:007
3883499193187,4cyclictest0-21swapper/1509:28:597
3881999193183,8cyclictest0-21swapper/210:36:1912
3881999193183,8cyclictest0-21swapper/210:36:1812
3881999193183,8cyclictest0-21swapper/210:36:1812
3884099192187,3cyclictest0-21swapper/2110:00:1914
3884099192187,3cyclictest0-21swapper/2110:00:1914
3884099192187,3cyclictest0-21swapper/2110:00:1914
3881999192183,7cyclictest1382-21in:imuxsock11:48:5412
3881999192183,7cyclictest1382-21in:imuxsock11:48:5412
3881999192183,7cyclictest1382-21in:imuxsock11:48:5412
3884699191136,51cyclictest37358-21CPU19
3884699191136,51cyclictest37358-21CPU19
3884699191136,51cyclictest37358-21CPU19
3883499191186,4cyclictest0-21swapper/1508:00:007
3883499191186,4cyclictest0-21swapper/1507:59:597
3883499191183,5cyclictest29358-21latency_hist08:30:037
3883499191183,5cyclictest29358-21latency_hist08:30:037
3883199191144,13cyclictest171rcu_preempt10:30:464
3883199191144,13cyclictest171rcu_preempt10:30:464
3883199191144,13cyclictest171rcu_preempt10:30:464
3881999191179,9cyclictest0-21swapper/212:32:3112
3881999191179,9cyclictest0-21swapper/212:32:3012
3881799190107,74cyclictest2456-21CPU1
3881799190107,74cyclictest2456-21CPU1
3881799190107,74cyclictest2456-21CPU1
3886099189135,46cyclictest0-21swapper/3709:52:2931
3886099189135,46cyclictest0-21swapper/3709:52:2931
3886099189135,46cyclictest0-21swapper/3709:52:2931
3886099188149,37cyclictest0-21swapper/3712:31:3031
3886099188149,37cyclictest0-21swapper/3712:31:2931
3881999188182,4cyclictest0-21swapper/209:50:2812
3881999188182,4cyclictest0-21swapper/209:50:2812
3881999188182,4cyclictest0-21swapper/209:50:2812
3881999188181,4cyclictest30755-21sshd10:25:2812
3881999188181,4cyclictest30755-21sshd10:25:2812
3881999188181,4cyclictest30755-21sshd10:25:2712
3883499187178,7cyclictest0-21swapper/1509:42:447
3883499187178,7cyclictest0-21swapper/1509:42:437
38860991861,181cyclictest0-21swapper/3709:45:1531
38860991861,181cyclictest0-21swapper/3709:45:1531
38817991861,134cyclictest0-21swapper/111:40:141
38817991861,134cyclictest0-21swapper/111:40:131
38817991861,134cyclictest0-21swapper/111:40:131
3883499185169,14cyclictest0-21swapper/1509:35:007
3883499185169,14cyclictest0-21swapper/1509:35:007
3883499185169,14cyclictest0-21swapper/1509:35:007
3881999185179,4cyclictest0-21swapper/210:57:1712
3881999185179,4cyclictest0-21swapper/210:57:1712
3881999185179,4cyclictest0-21swapper/210:57:1612
3881999185179,4cyclictest0-21swapper/210:20:0112
3881999185179,4cyclictest0-21swapper/210:20:0112
3881999185178,4cyclictest0-21swapper/210:45:5912
3881999185178,4cyclictest0-21swapper/210:45:5812
3881999185177,6cyclictest0-21swapper/210:10:2112
3881999185177,6cyclictest0-21swapper/210:10:2112
3881999185177,6cyclictest0-21swapper/210:10:2112
3883199184175,7cyclictest0-21swapper/1210:37:574
3883199184175,7cyclictest0-21swapper/1210:37:574
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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