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2026-07-23 - 01:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Jul 22, 2026 13:01:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31116992620,3cyclictest17482-21nfsd11:11:1524
31116992620,3cyclictest17482-21nfsd11:11:1524
31116992620,3cyclictest17482-21nfsd11:11:1424
31116992491,3cyclictest35963-21grep10:10:1224
31116992491,3cyclictest35963-21grep10:10:1124
31116992421,2cyclictest0-21swapper/3010:52:2324
31116992421,2cyclictest0-21swapper/3010:52:2324
31116992421,2cyclictest0-21swapper/3010:52:2224
31116992381,233cyclictest0-21swapper/3011:20:0324
31116992381,233cyclictest0-21swapper/3011:20:0324
31116992381,233cyclictest0-21swapper/3011:20:0224
31116992370,2cyclictest0-21swapper/3012:15:2724
31116992370,2cyclictest0-21swapper/3012:15:2624
31116992351,4cyclictest37263-21CPU24
31116992351,4cyclictest37263-21CPU24
31116992331,228cyclictest0-21swapper/3011:43:3524
31116992331,228cyclictest0-21swapper/3011:43:3524
31116992311,2cyclictest0-21swapper/3011:05:2024
31116992311,2cyclictest0-21swapper/3011:05:2024
31116992311,2cyclictest0-21swapper/3011:05:1924
31116992301,226cyclictest0-21swapper/3010:40:2824
31116992301,226cyclictest0-21swapper/3010:40:2824
31116992272,220cyclictest4407-21CPU24
31116992272,220cyclictest4407-21CPU24
31116992271,223cyclictest0-21swapper/3011:39:5324
31116992271,223cyclictest0-21swapper/3011:39:5224
31116992261,3cyclictest0-21swapper/3011:20:2324
31116992261,3cyclictest0-21swapper/3011:20:2324
31116992261,3cyclictest0-21swapper/3011:20:2224
31116992260,2cyclictest0-21swapper/3010:15:2624
31116992260,2cyclictest0-21swapper/3010:15:2524
31116992251,5cyclictest18646-21systemd11:47:2524
31116992251,5cyclictest18646-21systemd11:47:2424
31116992251,2cyclictest0-21swapper/3010:09:5824
31116992251,2cyclictest0-21swapper/3010:09:5824
31116992242,216cyclictest3542-21CPU24
31116992242,216cyclictest3542-21CPU24
31116992241,220cyclictest0-21swapper/3010:45:1524
31116992241,220cyclictest0-21swapper/3010:45:1524
31116992221,218cyclictest0-21swapper/3010:25:0124
31116992221,218cyclictest0-21swapper/3010:25:0124
31116992201,215cyclictest1358-21ModemManager12:03:3324
31116992201,215cyclictest1358-21ModemManager12:03:3324
31116992201,214cyclictest29073-21sshd11:31:4824
31116992201,214cyclictest29073-21sshd11:31:4824
31116992201,214cyclictest29073-21sshd11:31:4724
31116992200,2cyclictest0-21swapper/3010:39:2124
31116992200,2cyclictest0-21swapper/3010:39:2024
31116992200,2cyclictest0-21swapper/3010:39:2024
31116992200,2cyclictest0-21swapper/3010:25:5424
31116992200,2cyclictest0-21swapper/3010:25:5324
31116992191,3cyclictest1367-21dbus-daemon11:25:4424
31116992191,3cyclictest1367-21dbus-daemon11:25:4324
31116992191,214cyclictest0-21swapper/3011:50:1524
31116992191,214cyclictest0-21swapper/3011:50:1524
31116992181,212cyclictest0-21swapper/3012:36:4424
31116992181,212cyclictest0-21swapper/3012:36:4424
31116992171,2cyclictest0-21swapper/3010:33:4424
31116992171,2cyclictest0-21swapper/3010:33:4424
31116992171,2cyclictest0-21swapper/3010:33:4424
31116992171,213cyclictest0-21swapper/3012:10:1524
31116992171,213cyclictest0-21swapper/3012:10:1524
31116992171,213cyclictest0-21swapper/3012:10:1524
31116992160,2cyclictest0-21swapper/3010:58:3624
31116992160,2cyclictest0-21swapper/3010:58:3624
31116992151,211cyclictest0-21swapper/3012:08:5624
31116992151,211cyclictest0-21swapper/3012:08:5624
31116992150,2cyclictest0-21swapper/3012:25:2824
31116992150,2cyclictest0-21swapper/3012:25:2824
31116992150,2cyclictest0-21swapper/3012:25:2824
31116992141,2cyclictest0-21swapper/3011:59:3924
31116992141,2cyclictest0-21swapper/3011:59:3924
3109999207202,4cyclictest0-21swapper/1607:20:308
3109999207202,4cyclictest0-21swapper/1607:20:308
3109999206198,6cyclictest0-21swapper/1609:56:038
3109999206198,6cyclictest0-21swapper/1609:56:038
3110699200196,2cyclictest0-21swapper/2108:55:1714
3109999200194,4cyclictest0-21swapper/1608:20:598
3109999200194,4cyclictest0-21swapper/1608:20:588
3109299200193,2cyclictest0-21swapper/1010:35:062
3109299200193,2cyclictest0-21swapper/1010:35:062
3111599197142,50cyclictest0-21swapper/2911:17:2422
3111599197142,50cyclictest0-21swapper/2911:17:2422
3111599197142,50cyclictest0-21swapper/2911:17:2322
3111899196184,10cyclictest0-21swapper/3208:20:2726
3111899196184,10cyclictest0-21swapper/3208:20:2726
3109999196184,10cyclictest0-21swapper/1607:42:198
3109999196184,10cyclictest0-21swapper/1607:42:188
3109699195133,50cyclictest3610-21CPU5
3109699195133,50cyclictest3610-21CPU5
3111899194189,4cyclictest0-21swapper/3207:54:4026
3111899194189,4cyclictest0-21swapper/3207:54:3926
3111899194177,9cyclictest0-21swapper/3209:42:0326
3111899194177,9cyclictest0-21swapper/3209:42:0326
3111899194177,9cyclictest0-21swapper/3209:42:0226
3108599194180,9cyclictest0-21swapper/308:20:4723
3108599194180,9cyclictest0-21swapper/308:20:4623
3109999193187,4cyclictest0-21swapper/1609:50:588
3109999193187,4cyclictest0-21swapper/1609:50:578
3109999193183,6cyclictest2466-21CPU8
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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