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2026-02-13 - 20:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri Feb 13, 2026 13:03:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
608399221204,12cyclictest0-21swapper/2212:29:4115
608399221204,12cyclictest0-21swapper/2212:29:4115
608399221204,12cyclictest0-21swapper/2212:29:4015
608399213195,16cyclictest0-21swapper/2210:30:1915
608399213195,16cyclictest0-21swapper/2210:30:1815
609099212189,13cyclictest0-21swapper/2710:40:0820
609099212189,13cyclictest0-21swapper/2710:40:0820
608399212200,10cyclictest0-21swapper/2209:36:2115
608399212200,10cyclictest0-21swapper/2209:36:2115
606199207201,4cyclictest0-21swapper/307:17:0523
606199207201,4cyclictest0-21swapper/307:17:0523
608399201188,11cyclictest0-21swapper/2209:45:1815
608399201188,11cyclictest0-21swapper/2209:45:1715
608399201188,11cyclictest0-21swapper/2209:45:1715
608199201190,7cyclictest0-21swapper/2011:10:4313
608199201190,7cyclictest0-21swapper/2011:10:4213
608199201190,7cyclictest0-21swapper/2011:10:4213
609399199190,5cyclictest3547-21CPU24
609399199190,5cyclictest3547-21CPU24
610299198187,9cyclictest0-21swapper/3612:07:0030
610299198187,9cyclictest0-21swapper/3612:06:5930
610299198187,9cyclictest0-21swapper/3612:06:5930
610199197190,5cyclictest0-21swapper/3511:05:4129
610199197190,5cyclictest0-21swapper/3511:05:4129
610199197190,5cyclictest0-21swapper/3511:05:4029
610199195181,12cyclictest0-21swapper/3511:56:5429
610199195181,12cyclictest0-21swapper/3511:56:5329
610199195181,12cyclictest0-21swapper/3511:56:5329
609399194175,13cyclictest0-21swapper/3009:26:3324
609399194175,13cyclictest0-21swapper/3009:26:3324
609399194175,13cyclictest0-21swapper/3009:26:3224
608399194179,13cyclictest0-21swapper/2212:30:2815
608399194179,13cyclictest0-21swapper/2212:30:2715
608399194179,13cyclictest0-21swapper/2212:30:2715
608399193185,6cyclictest3535-21qemu-system-x8612:37:4615
608399193185,6cyclictest3535-21qemu-system-x8612:37:4515
608399193182,9cyclictest17484-21nfsd11:43:1015
608399193182,9cyclictest17484-21nfsd11:43:0915
608399193182,9cyclictest17484-21nfsd11:43:0915
608399192186,4cyclictest0-21swapper/2209:52:2015
608399192186,4cyclictest0-21swapper/2209:52:1915
608399192186,4cyclictest0-21swapper/2209:52:1915
61019919193,87cyclictest37354-21CPU29
61019919193,87cyclictest37354-21CPU29
61019919193,87cyclictest37354-21CPU29
608399191184,5cyclictest37257-21qemu-system-x8609:32:4015
608399191184,5cyclictest37257-21qemu-system-x8609:32:3915
606199191180,8cyclictest0-21swapper/307:22:3623
606199191180,8cyclictest0-21swapper/307:22:3523
609399190178,11cyclictest0-21swapper/3010:55:3424
609399190178,11cyclictest0-21swapper/3010:55:3424
609399190159,25cyclictest0-21swapper/3009:13:5224
609399190159,25cyclictest0-21swapper/3009:13:5124
609399190159,25cyclictest0-21swapper/3009:13:5124
608399190178,10cyclictest0-21swapper/2211:52:0015
608399190178,10cyclictest0-21swapper/2211:51:5915
608399190178,10cyclictest0-21swapper/2211:51:5915
608399189181,5cyclictest3543-21CPU15
608399189181,5cyclictest3543-21CPU15
608399189179,8cyclictest0-21swapper/2210:10:3915
608399189179,8cyclictest0-21swapper/2210:10:3915
608399189179,8cyclictest0-21swapper/2210:10:3915
608399189179,5cyclictest37356-21CPU15
608399189179,5cyclictest37356-21CPU15
608399188177,8cyclictest2456-21CPU15
608399188177,8cyclictest2456-21CPU15
608199188180,6cyclictest0-21swapper/2009:29:5313
608199188180,6cyclictest0-21swapper/2009:29:5313
608199188180,6cyclictest0-21swapper/2009:29:5213
606199188156,22cyclictest0-21swapper/311:15:5823
606199188156,22cyclictest0-21swapper/311:15:5723
606199188156,22cyclictest0-21swapper/311:15:5723
610299187182,4cyclictest0-21swapper/3612:03:0130
610299187182,4cyclictest0-21swapper/3612:03:0130
608399187181,4cyclictest0-21swapper/2209:07:3315
608399187181,4cyclictest0-21swapper/2209:07:3215
608399187168,15cyclictest0-21swapper/2207:27:4015
608399187168,15cyclictest0-21swapper/2207:27:3915
608399187164,13cyclictest0-21swapper/2209:11:4015
608399187164,13cyclictest0-21swapper/2209:11:3915
608399187164,13cyclictest0-21swapper/2209:11:3915
610299186120,48cyclictest37352-21CPU30
610299186120,48cyclictest37352-21CPU30
610299186120,48cyclictest37352-21CPU30
608399186179,3cyclictest3541-21CPU15
608399186179,3cyclictest3541-21CPU15
608399186179,3cyclictest3541-21CPU15
606199186153,31cyclictest0-21swapper/308:10:5823
606199186153,31cyclictest0-21swapper/308:10:5823
610299185177,6cyclictest0-21swapper/3610:46:2530
610299185177,6cyclictest0-21swapper/3610:46:2530
610299185177,6cyclictest0-21swapper/3610:46:2430
608399185171,11cyclictest0-21swapper/2210:01:2415
608399185171,11cyclictest0-21swapper/2210:01:2415
60739918583,99cyclictest36384-21sshd11:45:165
60739918583,99cyclictest36384-21sshd11:45:155
60739918583,99cyclictest36384-21sshd11:45:155
610199184176,6cyclictest0-21swapper/3511:32:1429
610199184176,6cyclictest0-21swapper/3511:32:1429
610199184176,6cyclictest0-21swapper/3511:32:1429
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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