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2026-02-02 - 19:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Feb 02, 2026 13:00:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1233499232225,2cyclictest0-21swapper/712:15:2737
1233499232225,2cyclictest0-21swapper/712:15:2737
1236299204195,7cyclictest24785-21missed_timers07:15:2725
1236299204195,7cyclictest24785-21missed_timers07:15:2725
1234199203197,4cyclictest0-21swapper/1411:10:196
1234199203197,4cyclictest0-21swapper/1411:10:196
1234199203197,4cyclictest0-21swapper/1411:10:196
1234199199191,6cyclictest0-21swapper/1407:20:176
1236899198179,16cyclictest0-21swapper/3509:05:2229
1236899198179,16cyclictest0-21swapper/3509:05:2129
1236299198193,3cyclictest0-21swapper/3107:15:0025
1236299198193,3cyclictest0-21swapper/3107:15:0025
1234199196140,46cyclictest0-21swapper/1412:25:216
1234199196140,46cyclictest0-21swapper/1412:25:206
1233199196187,2cyclictest0-21swapper/411:08:1334
1233199196187,2cyclictest0-21swapper/411:08:1334
1235199195137,46cyclictest3548-21CPU15
1235199195137,46cyclictest3548-21CPU15
1234499194180,12cyclictest0-21swapper/1609:21:598
1234499194180,12cyclictest0-21swapper/1609:21:588
1234499194180,12cyclictest0-21swapper/1609:21:588
1235599193187,3cyclictest2466-21CPU17
1235599193187,3cyclictest2466-21CPU17
1236899192187,4cyclictest0-21swapper/3509:12:2829
1236899192187,4cyclictest0-21swapper/3509:12:2729
1236899192187,4cyclictest0-21swapper/3509:12:2729
1236899192186,3cyclictest32665-21cat09:15:1529
1236899192186,3cyclictest32665-21cat09:15:1529
1234199191185,4cyclictest0-21swapper/1409:10:196
1234199191185,4cyclictest0-21swapper/1409:10:196
1234199191185,4cyclictest0-21swapper/1409:10:186
1234199191184,5cyclictest0-21swapper/1411:09:126
1234199191184,5cyclictest0-21swapper/1411:09:126
1237099190176,8cyclictest1367-21dbus-daemon12:25:1731
1237099190176,8cyclictest1367-21dbus-daemon12:25:1731
1236899190184,4cyclictest0-21swapper/3509:02:2729
1236899190184,4cyclictest0-21swapper/3509:02:2729
1232999190182,6cyclictest0-21swapper/312:26:2823
1232999190182,6cyclictest0-21swapper/312:26:2823
1235699189184,4cyclictest0-21swapper/2512:35:2218
1235699189184,4cyclictest0-21swapper/2512:35:2218
1236899188179,7cyclictest0-21swapper/3512:06:5529
1236899188179,7cyclictest0-21swapper/3512:06:5529
1236899188179,7cyclictest0-21swapper/3512:06:5529
123389918774,110cyclictest0-21swapper/1112:20:273
123389918774,110cyclictest0-21swapper/1112:20:273
1236899186170,14cyclictest0-21swapper/3512:17:4829
1236899186170,14cyclictest0-21swapper/3512:17:4829
1234199186184,1cyclictest0-21swapper/1412:34:086
1234199186184,1cyclictest0-21swapper/1412:34:086
1234199186180,4cyclictest0-21swapper/1407:12:376
1234199186180,4cyclictest0-21swapper/1407:12:376
1234199186179,5cyclictest0-21swapper/1409:20:126
1234199186179,5cyclictest0-21swapper/1409:20:126
1234199186179,5cyclictest0-21swapper/1409:20:126
1234199186178,6cyclictest0-21swapper/1409:17:166
1234199186178,6cyclictest0-21swapper/1409:17:166
1235199185175,8cyclictest0-21swapper/2212:29:3115
1235199185175,8cyclictest0-21swapper/2212:29:3115
1235199185157,12cyclictest171rcu_preempt10:19:0315
1235199185157,12cyclictest171rcu_preempt10:19:0315
1234199185179,4cyclictest0-21swapper/1409:06:076
1234199185179,4cyclictest0-21swapper/1409:06:076
1237099184131,26cyclictest0-21swapper/3710:36:0731
1237099184131,26cyclictest0-21swapper/3710:36:0731
1237099184131,26cyclictest0-21swapper/3710:36:0631
1234199184177,5cyclictest0-21swapper/1407:18:006
1234199184177,5cyclictest0-21swapper/1407:18:006
1235199183163,11cyclictest171rcu_preempt07:34:3915
1235199183163,11cyclictest171rcu_preempt07:34:3915
1234199183178,4cyclictest0-21swapper/1408:53:056
1234199183178,4cyclictest0-21swapper/1408:53:056
1232999183174,7cyclictest0-21swapper/309:34:5623
1232999183174,7cyclictest0-21swapper/309:34:5523
1232999183174,6cyclictest0-21swapper/309:50:1323
1232999183174,6cyclictest0-21swapper/309:50:1323
1232999183174,6cyclictest0-21swapper/309:50:1323
1237099182147,23cyclictest0-21swapper/3708:20:3731
1232999182168,10cyclictest0-21swapper/310:31:3623
1232999182168,10cyclictest0-21swapper/310:31:3623
1232699182178,2cyclictest0-21swapper/107:20:251
1236899181103,61cyclictest0-21swapper/3512:25:1229
1236899181103,61cyclictest0-21swapper/3512:25:1229
1235199181168,6cyclictest171rcu_preempt11:02:5415
1235199181168,6cyclictest171rcu_preempt11:02:5315
1235199181168,6cyclictest171rcu_preempt11:02:5315
1234199181176,4cyclictest0-21swapper/1408:57:416
1234199181176,4cyclictest0-21swapper/1408:57:416
1237099180159,13cyclictest171rcu_preempt09:06:1331
1237099180159,13cyclictest171rcu_preempt09:06:1331
1235199180173,4cyclictest3535-21qemu-system-x8608:00:2915
1235199180173,4cyclictest3535-21qemu-system-x8608:00:2915
1235199180118,28cyclictest0-21swapper/2212:36:3215
1235199180118,28cyclictest0-21swapper/2212:36:3115
1234199180173,3cyclictest37358-21CPU6
1237099179167,4cyclictest0-21swapper/3712:18:0431
1237099179167,4cyclictest0-21swapper/3712:18:0431
1237099179153,11cyclictest171rcu_preempt10:34:1631
1237099179153,11cyclictest171rcu_preempt10:34:1631
1236899179174,4cyclictest0-21swapper/3509:22:1029
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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