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2025-12-18 - 17:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Dec 18, 2025 12:59:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3426499229190,17cyclictest0-21swapper/2312:01:2616
3426499229190,17cyclictest0-21swapper/2312:01:2616
3424299226180,43cyclictest3544-21CPU35
3424299226180,43cyclictest3544-21CPU35
3425799204188,10cyclictest0-21swapper/1712:07:179
3425799204188,10cyclictest0-21swapper/1712:07:179
3425499204193,9cyclictest4410-21qemu-system-x8610:02:156
3425499204193,9cyclictest4410-21qemu-system-x8610:02:146
3424299198193,2cyclictest0-21swapper/511:20:0735
3424299198193,2cyclictest0-21swapper/511:20:0635
3424299198187,9cyclictest0-21swapper/511:26:2335
3424299198187,9cyclictest0-21swapper/511:26:2335
3424299197193,2cyclictest0-21swapper/510:30:5635
3424299197193,2cyclictest0-21swapper/510:30:5635
3424299197193,2cyclictest0-21swapper/510:30:5535
3425699193177,12cyclictest0-21swapper/1610:03:028
3425699193177,12cyclictest0-21swapper/1610:03:028
3425399193179,8cyclictest171rcu_preempt09:14:575
3425399193179,8cyclictest171rcu_preempt09:14:575
3425399193179,8cyclictest171rcu_preempt09:14:565
3424299191181,8cyclictest0-21swapper/509:20:5835
3424299191181,8cyclictest0-21swapper/509:20:5735
3424299189176,11cyclictest0-21swapper/511:03:2835
3424299189176,11cyclictest0-21swapper/511:03:2735
3424299189171,8cyclictest0-21swapper/510:16:5935
3424299189171,8cyclictest0-21swapper/510:16:5935
3424299189171,8cyclictest0-21swapper/510:16:5835
3424499187173,12cyclictest0-21swapper/710:28:4837
3424499187173,12cyclictest0-21swapper/710:28:4837
3424499187173,12cyclictest0-21swapper/710:28:4837
3424399187178,7cyclictest0-21swapper/612:18:5236
3424399187178,7cyclictest0-21swapper/612:18:5236
3426499186113,68cyclictest3548-21CPU16
3426499186113,68cyclictest3548-21CPU16
3426499185128,27cyclictest0-21swapper/2309:16:3416
3426499185128,27cyclictest0-21swapper/2309:16:3416
3424399183158,15cyclictest37958-21kworker/u81:1-events_unbound09:00:0136
3424399183158,15cyclictest37958-21kworker/u81:1-events_unbound09:00:0136
3425199182177,3cyclictest0-21swapper/1109:55:213
3425199182177,3cyclictest0-21swapper/1109:55:213
3425799181170,4cyclictest0-21swapper/1712:27:589
3425799181170,4cyclictest0-21swapper/1712:27:579
3425799181170,4cyclictest0-21swapper/1712:27:579
342529918144,132cyclictest15893-21expr09:35:154
342529918144,132cyclictest15893-21expr09:35:144
3424299181156,8cyclictest171rcu_preempt11:12:1935
3424299181156,8cyclictest171rcu_preempt11:12:1935
3427199180174,4cyclictest0-21swapper/2909:55:1122
3427199180174,4cyclictest0-21swapper/2909:55:1022
3425799180126,23cyclictest0-21swapper/1709:14:179
3425799180126,23cyclictest0-21swapper/1709:14:179
3425799180126,23cyclictest0-21swapper/1709:14:179
3424399180173,4cyclictest0-21swapper/609:19:1736
3424399180173,4cyclictest0-21swapper/609:19:1636
3424299180143,27cyclictest2454-21CPU35
3424299180143,27cyclictest2454-21CPU35
3424299180143,27cyclictest2454-21CPU35
3423699180116,57cyclictest36640-21sshd09:44:000
3423699180116,57cyclictest36640-21sshd09:44:000
3426499178155,8cyclictest171rcu_preempt11:11:5916
3426499178155,8cyclictest171rcu_preempt11:11:5816
3425799178127,27cyclictest0-21swapper/1707:23:189
3424399178167,9cyclictest0-21swapper/607:30:0236
3424299178165,11cyclictest0-21swapper/510:04:4535
3424299178165,11cyclictest0-21swapper/510:04:4435
3423799178175,2cyclictest0-21swapper/111:55:191
3423799178175,2cyclictest0-21swapper/111:55:191
3426499177124,22cyclictest0-21swapper/2309:28:2116
3426499177124,22cyclictest0-21swapper/2309:28:2116
3426899176156,18cyclictest0-21swapper/2710:25:4120
3426899176156,18cyclictest0-21swapper/2710:25:4020
3426899176156,18cyclictest0-21swapper/2710:25:4020
3426499176158,11cyclictest0-21swapper/2311:52:0316
3426499176158,11cyclictest0-21swapper/2311:52:0316
3426499176158,11cyclictest0-21swapper/2311:52:0316
3425799176156,11cyclictest171rcu_preempt11:26:259
3425799176156,11cyclictest171rcu_preempt11:26:259
3424399176165,9cyclictest0-21swapper/610:22:1236
3424399176165,9cyclictest0-21swapper/610:22:1236
3424399176165,9cyclictest0-21swapper/610:22:1136
3424399175163,9cyclictest0-21swapper/610:40:4636
3424399175163,9cyclictest0-21swapper/610:40:4536
3426899174150,18cyclictest0-21swapper/2708:20:4020
3426499174123,29cyclictest0-21swapper/2310:43:5916
3426499174123,29cyclictest0-21swapper/2310:43:5816
3425799174133,22cyclictest0-21swapper/1707:17:319
3425799174133,22cyclictest0-21swapper/1707:17:319
3423999174157,15cyclictest0-21swapper/309:34:4023
3423999174157,15cyclictest0-21swapper/309:34:4023
3423999174157,15cyclictest0-21swapper/309:34:4023
3426499173148,18cyclictest0-21swapper/2310:49:4716
3426499173148,18cyclictest0-21swapper/2310:49:4716
3426499173110,51cyclictest0-21swapper/2311:31:5216
3426499173110,51cyclictest0-21swapper/2311:31:5116
3425299173105,41cyclictest3609-21CPU4
3425299173105,41cyclictest3609-21CPU4
3425299173105,41cyclictest3609-21CPU4
3424399173167,5cyclictest0-21swapper/609:28:5036
3424399173167,5cyclictest0-21swapper/609:28:5036
3424399173120,25cyclictest0-21swapper/612:23:2236
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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