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2026-06-22 - 07:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Jun 22, 2026 01:02:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4060992632,255cyclictest3610-21CPU1
4060992632,255cyclictest3610-21CPU1
4060992542,247cyclictest2456-21CPU1
4060992542,247cyclictest2456-21CPU1
4060992541,249cyclictest0-21swapper/122:40:071
4060992541,249cyclictest0-21swapper/122:40:071
4060992541,249cyclictest0-21swapper/122:40:061
4060992530,2cyclictest0-21swapper/123:18:131
4060992530,2cyclictest0-21swapper/123:18:131
4060992521,246cyclictest37257-21qemu-system-x8600:00:551
4060992521,246cyclictest37257-21qemu-system-x8600:00:541
4060992521,246cyclictest37257-21qemu-system-x8600:00:541
4060992501,245cyclictest0-21swapper/121:00:131
4060992501,245cyclictest0-21swapper/121:00:131
4060992451,241cyclictest0-21swapper/123:14:351
4060992451,241cyclictest0-21swapper/123:14:341
4060992441,240cyclictest0-21swapper/121:11:131
4060992441,240cyclictest0-21swapper/121:11:131
4060992441,240cyclictest0-21swapper/119:47:511
4060992441,240cyclictest0-21swapper/119:47:511
4060992422,235cyclictest4407-21CPU1
4060992422,235cyclictest4407-21CPU1
4060992420,239cyclictest20914-21sshd00:21:511
4060992420,239cyclictest20914-21sshd00:21:501
4060992392,231cyclictest3609-21CPU1
4060992392,231cyclictest3609-21CPU1
4060992381,234cyclictest0-21swapper/100:05:181
4060992381,234cyclictest0-21swapper/100:05:181
4060992381,234cyclictest0-21swapper/100:05:171
4060992370,3cyclictest3600-21qemu-system-x8622:31:471
4060992370,3cyclictest3600-21qemu-system-x8622:31:461
4060992361,232cyclictest1-21systemd23:54:001
4060992361,232cyclictest1-21systemd23:54:001
4060992341,228cyclictest0-21swapper/123:48:371
4060992341,228cyclictest0-21swapper/123:48:361
4060992340,2cyclictest0-21swapper/122:10:251
4060992340,2cyclictest0-21swapper/122:10:251
4060992331,229cyclictest1367-21dbus-daemon21:37:071
4060992331,229cyclictest1367-21dbus-daemon21:37:071
4060992330,230cyclictest0-21swapper/100:11:321
4060992330,230cyclictest0-21swapper/100:11:321
4060992330,230cyclictest0-21swapper/100:11:321
4060992330,224cyclictest0-21swapper/123:28:221
4060992330,224cyclictest0-21swapper/123:28:221
4060992330,224cyclictest0-21swapper/123:28:211
4060992322,225cyclictest3546-21CPU1
4060992322,225cyclictest3546-21CPU1
4060992322,225cyclictest3546-21CPU1
4060992321,228cyclictest0-21swapper/122:28:101
4060992321,228cyclictest0-21swapper/122:28:101
4060992321,228cyclictest0-21swapper/122:28:101
4060992321,223cyclictest0-21swapper/122:15:171
4060992321,223cyclictest0-21swapper/122:15:171
4060992321,223cyclictest0-21swapper/122:15:161
4060992320,2cyclictest0-21swapper/121:30:091
4060992320,2cyclictest0-21swapper/121:30:091
4060992320,2cyclictest0-21swapper/121:30:091
4060992311,227cyclictest24952-21packagekitd00:15:461
4060992311,227cyclictest24952-21packagekitd00:15:451
4060992311,227cyclictest24952-21packagekitd00:15:451
4060992311,226cyclictest12683-21sshd00:35:201
4060992311,226cyclictest12683-21sshd00:35:191
4060992303,221cyclictest3548-21CPU1
4060992303,221cyclictest3548-21CPU1
4060992301,2cyclictest0-21swapper/122:05:491
4060992301,2cyclictest0-21swapper/122:05:491
4060992301,226cyclictest0-21swapper/123:38:251
4060992301,226cyclictest0-21swapper/123:38:251
4060992301,226cyclictest0-21swapper/121:15:131
4060992301,226cyclictest0-21swapper/121:15:121
4060992301,223cyclictest0-21swapper/121:58:121
4060992301,223cyclictest0-21swapper/121:58:111
4060992301,223cyclictest0-21swapper/121:58:111
4060992281,224cyclictest0-21swapper/120:32:481
4060992281,224cyclictest0-21swapper/120:32:481
4060992281,214cyclictest0-21swapper/123:55:191
4060992281,214cyclictest0-21swapper/123:55:191
4060992281,214cyclictest0-21swapper/123:55:181
4060992261,222cyclictest0-21swapper/123:20:421
4060992261,222cyclictest0-21swapper/123:20:411
4060992261,222cyclictest0-21swapper/123:20:411
4060992250,221cyclictest0-21swapper/122:54:421
4060992250,221cyclictest0-21swapper/122:54:411
4060992240,2cyclictest0-21swapper/123:07:091
4060992240,2cyclictest0-21swapper/123:07:091
4060992240,2cyclictest0-21swapper/123:07:081
4060992240,2cyclictest0-21swapper/121:23:311
4060992240,2cyclictest0-21swapper/121:23:311
4060992231,219cyclictest0-21swapper/119:30:131
4060992231,219cyclictest0-21swapper/119:30:131
4060992230,2cyclictest0-21swapper/119:43:241
4060992230,2cyclictest0-21swapper/119:43:241
4060992220,2cyclictest0-21swapper/121:48:101
4060992220,2cyclictest0-21swapper/121:48:101
4060992210,214cyclictest0-21swapper/120:50:461
4060992210,214cyclictest0-21swapper/120:50:461
4060992210,214cyclictest0-21swapper/120:50:451
4060992202,213cyclictest3545-21CPU1
4060992202,213cyclictest3545-21CPU1
4060992201,216cyclictest0-21swapper/121:28:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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