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2026-06-28 - 15:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Jun 28, 2026 13:03:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1408699231224,5cyclictest0-21swapper/3907:22:2633
1408699231224,5cyclictest0-21swapper/3907:22:2633
14048992231,69cyclictest0-21swapper/609:40:1236
14048992231,69cyclictest0-21swapper/609:40:1236
14048992231,69cyclictest0-21swapper/609:40:1236
14056992040,196cyclictest0-21swapper/1209:50:214
14056992040,196cyclictest0-21swapper/1209:50:204
14056992040,196cyclictest0-21swapper/1209:50:204
1407899203172,12cyclictest171rcu_preempt12:32:5525
1407899203172,12cyclictest171rcu_preempt12:32:5525
1408699202194,6cyclictest0-21swapper/3907:25:1433
1408699202194,6cyclictest0-21swapper/3907:25:1333
1408199201151,38cyclictest37354-21CPU28
1408199201151,38cyclictest37354-21CPU28
14083992002,3cyclictest2456-21CPU30
14083992002,3cyclictest2456-21CPU30
14083992002,3cyclictest2456-21CPU30
1405299197177,15cyclictest0-21swapper/812:10:1338
1405299197177,15cyclictest0-21swapper/812:10:1238
1408699196190,4cyclictest0-21swapper/3907:10:1933
1408699196190,4cyclictest0-21swapper/3907:10:1933
1405299196183,11cyclictest0-21swapper/812:35:2438
1405299196183,11cyclictest0-21swapper/812:35:2438
1408699195189,4cyclictest0-21swapper/3907:18:4633
1408699195189,4cyclictest0-21swapper/3907:18:4533
1408699195184,6cyclictest37357-21CPU33
1408699195184,6cyclictest37357-21CPU33
1405699195146,43cyclictest0-21swapper/1212:20:014
1405699195146,43cyclictest0-21swapper/1212:20:014
1404099195183,7cyclictest0-21swapper/010:08:210
1404099195183,7cyclictest0-21swapper/010:08:210
1404099195183,7cyclictest0-21swapper/010:08:210
1408099194174,17cyclictest2454-21CPU27
1408099194174,17cyclictest2454-21CPU27
1408099194174,17cyclictest2454-21CPU27
1406299194184,8cyclictest0-21swapper/1809:10:0410
1406299194184,8cyclictest0-21swapper/1809:10:0410
1405299194179,10cyclictest1367-21dbus-daemon11:56:2438
1405299194179,10cyclictest1367-21dbus-daemon11:56:2438
14056991931,95cyclictest0-21swapper/1208:55:214
14056991931,95cyclictest0-21swapper/1208:55:204
1405299193176,7cyclictest4408-21CPU38
1405299193176,7cyclictest4408-21CPU38
1406199190187,2cyclictest0-21swapper/1708:51:099
1406199190187,2cyclictest0-21swapper/1708:51:099
1405299190167,15cyclictest0-21swapper/807:55:0138
1405299190167,15cyclictest0-21swapper/807:55:0038
1407799189158,14cyclictest0-21swapper/3012:37:0824
1407799189158,14cyclictest0-21swapper/3012:37:0724
1406699189184,3cyclictest0-21swapper/2110:35:2014
1406699189184,3cyclictest0-21swapper/2110:35:2014
1405299189182,5cyclictest0-21swapper/812:05:2438
1405299189182,5cyclictest0-21swapper/812:05:2338
1405299189182,5cyclictest0-21swapper/812:05:2338
1405299188176,10cyclictest0-21swapper/810:48:0738
1405299188176,10cyclictest0-21swapper/810:48:0638
1405299188173,13cyclictest0-21swapper/812:32:2838
1405299188173,13cyclictest0-21swapper/812:32:2838
1404299188122,16cyclictest0-21swapper/110:50:151
1404299188122,16cyclictest0-21swapper/110:50:151
1405299187174,11cyclictest25005-21gdbus12:27:4338
1405299187174,11cyclictest25005-21gdbus12:27:4238
1404399187152,8cyclictest171rcu_preempt10:47:5112
1404399187152,8cyclictest171rcu_preempt10:47:5112
1405299186179,5cyclictest755-21systemd-journal12:16:5238
1405299186179,5cyclictest755-21systemd-journal12:16:5138
1405299186179,5cyclictest17484-21nfsd12:00:3638
1405299186179,5cyclictest17484-21nfsd12:00:3538
1408099185145,30cyclictest3543-21CPU27
1408099185145,30cyclictest3543-21CPU27
1408099185145,30cyclictest3543-21CPU27
1407899185168,9cyclictest171rcu_preempt09:43:5425
1407899185168,9cyclictest171rcu_preempt09:43:5425
1407899185168,9cyclictest171rcu_preempt09:43:5425
1408299184179,4cyclictest14038-21cyclictest09:20:0429
1408299184179,4cyclictest14038-21cyclictest09:20:0329
1408299184179,4cyclictest14038-21cyclictest09:20:0329
1405299184177,5cyclictest1367-21dbus-daemon12:20:3138
1405299184177,5cyclictest1367-21dbus-daemon12:20:3138
1405299184177,5cyclictest1367-21dbus-daemon12:20:3038
1408499183177,3cyclictest0-21swapper/3709:13:4931
1408499183177,3cyclictest0-21swapper/3709:13:4931
1408499183177,3cyclictest0-21swapper/3709:13:4931
1408299183153,17cyclictest0-21swapper/3510:42:1529
1408299183153,17cyclictest0-21swapper/3510:42:1429
1407799183148,18cyclictest0-21swapper/3010:10:4224
1407799183148,18cyclictest0-21swapper/3010:10:4124
1405299183178,4cyclictest0-21swapper/808:20:1638
1408299182154,11cyclictest0-21swapper/3510:12:3829
1408299182154,11cyclictest0-21swapper/3510:12:3729
1408099181143,35cyclictest2454-21CPU27
1408099181143,35cyclictest2454-21CPU27
1407799181165,9cyclictest171rcu_preempt07:37:1524
1407799181165,9cyclictest171rcu_preempt07:37:1524
1405399181146,30cyclictest0-21swapper/910:43:4839
1405399181146,30cyclictest0-21swapper/910:43:4839
14048991811,126cyclictest0-21swapper/608:55:1736
14048991811,126cyclictest0-21swapper/608:55:1736
1408699180177,2cyclictest0-21swapper/3907:10:0233
1405699180143,34cyclictest0-21swapper/1211:15:334
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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