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2026-02-28 - 17:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 28, 2026 13:04:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3423299214206,6cyclictest0-21swapper/710:25:0437
3423299214206,6cyclictest0-21swapper/710:25:0437
3423299214206,6cyclictest0-21swapper/710:25:0437
3422599211203,6cyclictest0-21swapper/011:11:550
3422599211203,6cyclictest0-21swapper/011:11:550
3423299210201,5cyclictest0-21swapper/710:25:1537
3423299210201,5cyclictest0-21swapper/710:25:1537
3423299210201,5cyclictest0-21swapper/710:25:1537
3422799210203,5cyclictest0-21swapper/211:39:1312
3422799210203,5cyclictest0-21swapper/211:39:1312
3422799210203,5cyclictest0-21swapper/211:39:1312
3422799210203,5cyclictest0-21swapper/211:39:1312
3426899207201,4cyclictest0-21swapper/3609:39:0430
3426899207201,4cyclictest0-21swapper/3609:39:0430
3426899205198,3cyclictest37263-21CPU30
3426899205198,3cyclictest37263-21CPU30
3426899204197,5cyclictest17483-21nfsd09:46:5230
3426899204197,5cyclictest17483-21nfsd09:46:5230
3426899204197,4cyclictest0-21swapper/3610:55:5530
3426899204197,4cyclictest0-21swapper/3610:55:5530
3426899203194,7cyclictest0-21swapper/3610:10:2030
3426899203194,7cyclictest0-21swapper/3610:10:2030
3426899203189,12cyclictest0-21swapper/3611:37:2230
3426899203189,12cyclictest0-21swapper/3611:37:2230
3426899203189,12cyclictest0-21swapper/3611:37:2230
3426899203189,12cyclictest0-21swapper/3611:37:2230
3426899203185,8cyclictest20527-21sshd12:20:3830
3426899203185,8cyclictest20527-21sshd12:20:3830
3426899203185,8cyclictest20527-21sshd12:20:3830
3422599202191,6cyclictest3609-21CPU0
3422599202191,6cyclictest3609-21CPU0
3422599202191,6cyclictest3609-21CPU0
3422799200192,6cyclictest0-21swapper/209:43:3912
3422799200192,6cyclictest0-21swapper/209:43:3912
3422799200192,6cyclictest0-21swapper/209:43:3912
3422599200194,3cyclictest2466-21CPU0
3422599200194,3cyclictest2466-21CPU0
3422599200194,3cyclictest2466-21CPU0
3426899199193,3cyclictest1344-21sshd09:10:0830
3426899199193,3cyclictest1344-21sshd09:10:0830
3426899199193,3cyclictest1344-21sshd09:10:0830
3426899199192,5cyclictest0-21swapper/3612:18:2030
3426899199192,5cyclictest0-21swapper/3612:18:2030
3426899199189,8cyclictest0-21swapper/3607:22:0030
3422799199187,11cyclictest0-21swapper/207:18:2212
3426899198189,5cyclictest2456-21CPU30
3426899198189,5cyclictest2456-21CPU30
3426899198189,5cyclictest2456-21CPU30
3426199198193,4cyclictest0-21swapper/3109:02:2225
3426199198193,4cyclictest0-21swapper/3109:02:2225
3426899197190,5cyclictest17484-21nfsd08:20:1230
3426899197190,5cyclictest17484-21nfsd08:20:1230
3426899197188,6cyclictest26700-21ystemctl11:20:0930
3426899197188,6cyclictest26700-21ystemctl11:20:0930
3426899197188,6cyclictest26700-21ystemctl11:20:0930
3426199197192,4cyclictest0-21swapper/3109:12:0025
3426199197192,4cyclictest0-21swapper/3109:12:0025
3426199197192,4cyclictest0-21swapper/3109:12:0025
3422799197192,3cyclictest0-21swapper/209:47:0612
3422799197192,3cyclictest0-21swapper/209:47:0612
3422799197191,4cyclictest0-21swapper/212:30:0212
3422799197191,4cyclictest0-21swapper/212:30:0112
3422799197191,4cyclictest0-21swapper/212:30:0112
3422599197136,48cyclictest37264-21CPU0
3426899196190,4cyclictest0-21swapper/3611:52:4330
3426899196190,4cyclictest0-21swapper/3611:52:4330
3426899196187,6cyclictest0-21swapper/3610:48:1130
3426899196187,6cyclictest0-21swapper/3610:48:1130
3426899196187,6cyclictest0-21swapper/3610:48:1130
3422799196185,6cyclictest0-21swapper/207:10:1612
3422799196185,6cyclictest0-21swapper/207:10:1612
3422599196190,4cyclictest0-21swapper/011:06:580
3422599196190,4cyclictest0-21swapper/011:06:580
3422599196190,4cyclictest0-21swapper/011:06:580
3426899195190,4cyclictest0-21swapper/3609:51:5530
3426899195190,4cyclictest0-21swapper/3609:51:5530
3426899195188,4cyclictest0-21swapper/3610:07:1830
3426899195188,4cyclictest0-21swapper/3610:07:1830
3426899195187,4cyclictest0-21swapper/3609:34:2230
3426899195187,4cyclictest0-21swapper/3609:34:2230
3426899195173,19cyclictest37355-21CPU30
3426899195173,19cyclictest37355-21CPU30
3426899195173,19cyclictest37355-21CPU30
3426899195173,14cyclictest0-21swapper/3612:35:0430
3426899195173,14cyclictest0-21swapper/3612:35:0430
3426899195173,14cyclictest0-21swapper/3612:35:0430
3422799194189,4cyclictest0-21swapper/210:18:0812
3422799194189,4cyclictest0-21swapper/210:18:0812
3422799194189,4cyclictest0-21swapper/210:18:0812
3422799194184,7cyclictest0-21swapper/210:53:2512
3422799194184,7cyclictest0-21swapper/210:53:2512
3426899193184,6cyclictest0-21swapper/3607:20:0130
3426899193183,6cyclictest2459-21CPU30
3426899193183,6cyclictest2459-21CPU30
3426899193183,6cyclictest2459-21CPU30
3426899192183,5cyclictest0-21swapper/3610:00:2430
3426899192183,5cyclictest0-21swapper/3610:00:2430
3426899192183,5cyclictest0-21swapper/3610:00:2430
3422799192186,4cyclictest0-21swapper/211:16:4612
3422799192186,4cyclictest0-21swapper/211:16:4612
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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