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2026-03-20 - 14:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri Mar 20, 2026 13:02:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1864399218203,10cyclictest0-21swapper/3710:40:1131
1864399218203,10cyclictest0-21swapper/3710:40:1131
1864399218203,10cyclictest0-21swapper/3710:40:1131
1864599216210,4cyclictest0-21swapper/3908:15:0133
1864599216210,4cyclictest0-21swapper/3908:15:0033
1864599216210,4cyclictest0-21swapper/3908:15:0033
1864599205199,4cyclictest17483-21nfsd09:15:5733
1864599205199,4cyclictest17483-21nfsd09:15:5633
1864599204198,4cyclictest0-21swapper/3911:25:2933
1864599204198,4cyclictest0-21swapper/3911:25:2933
1863299204190,12cyclictest0-21swapper/2709:53:3120
1863299204190,12cyclictest0-21swapper/2709:53:3120
1863299204190,12cyclictest0-21swapper/2709:53:3020
1864599203198,4cyclictest0-21swapper/3911:23:2333
1864599203198,4cyclictest0-21swapper/3911:23:2333
1864599203198,4cyclictest0-21swapper/3911:23:2333
1864599203194,5cyclictest3547-21CPU33
1864599203194,5cyclictest3547-21CPU33
1864599202195,5cyclictest0-21swapper/3907:21:1533
1864599202195,5cyclictest0-21swapper/3907:21:1533
1863599202198,2cyclictest0-21swapper/2907:10:2122
1863599202198,2cyclictest0-21swapper/2907:10:2122
1864599201196,4cyclictest0-21swapper/3912:18:0133
1864599201196,4cyclictest0-21swapper/3912:18:0133
1864599201196,4cyclictest0-21swapper/3912:18:0033
1864599201191,8cyclictest27945-21cstates09:10:1433
1864599201191,8cyclictest27945-21cstates09:10:1433
1864599201191,8cyclictest27945-21cstates09:10:1433
1864599201191,7cyclictest37257-21qemu-system-x8611:30:2333
1864599201191,7cyclictest37257-21qemu-system-x8611:30:2333
1864599201191,6cyclictest37352-21CPU33
1864599201191,6cyclictest37352-21CPU33
1863999201185,8cyclictest171rcu_preempt09:57:2027
1863999201185,8cyclictest171rcu_preempt09:57:1927
1860999201195,4cyclictest0-21swapper/811:43:3638
1860999201195,4cyclictest0-21swapper/811:43:3538
1860999201195,4cyclictest0-21swapper/811:43:3538
1864599200194,4cyclictest0-21swapper/3912:25:2233
1864599200194,4cyclictest0-21swapper/3912:25:2233
1864599200194,3cyclictest3548-21CPU33
1864599200194,3cyclictest3548-21CPU33
1864599198191,3cyclictest37269-21CPU33
1864599198191,3cyclictest37269-21CPU33
1864599198187,9cyclictest35130-21sshd12:11:1433
1864599198187,9cyclictest35130-21sshd12:11:1433
1864599198187,9cyclictest35130-21sshd12:11:1333
1863999198194,2cyclictest0-21swapper/3312:13:0627
1863999198194,2cyclictest0-21swapper/3312:13:0627
1863999198194,2cyclictest0-21swapper/3312:13:0527
1860699198183,8cyclictest0-21swapper/612:26:3636
1860699198183,8cyclictest0-21swapper/612:26:3536
1864599197191,5cyclictest0-21swapper/3912:09:4033
1864599197191,5cyclictest0-21swapper/3912:09:4033
1864599197190,5cyclictest0-21swapper/3908:44:3233
1864599197190,4cyclictest755-21systemd-journal11:59:0433
1864599197190,4cyclictest755-21systemd-journal11:59:0333
1864599197188,6cyclictest15002-21sshd09:30:1433
1864599197188,6cyclictest15002-21sshd09:30:1433
1863299197190,3cyclictest3541-21CPU20
1864599196189,5cyclictest0-21swapper/3909:20:1233
1864599196189,5cyclictest0-21swapper/3909:20:1133
1864599196189,3cyclictest0-21swapper/3912:01:1033
1864599196189,3cyclictest0-21swapper/3912:01:1033
1863999196188,6cyclictest0-21swapper/3309:24:1127
1863999196188,6cyclictest0-21swapper/3309:24:1127
1864599195188,5cyclictest0-21swapper/3912:20:2333
1864599195188,5cyclictest0-21swapper/3912:20:2233
1864599195188,5cyclictest0-21swapper/3912:20:2233
1863299195188,5cyclictest0-21swapper/2707:12:5220
1863299195188,5cyclictest0-21swapper/2707:12:5220
1860399195191,2cyclictest0-21swapper/310:00:1323
1860399195191,2cyclictest0-21swapper/310:00:1223
1860399195191,2cyclictest0-21swapper/310:00:1223
1864599194189,3cyclictest0-21swapper/3907:33:4033
1864599194189,3cyclictest0-21swapper/3907:33:4033
1864599194189,3cyclictest0-21swapper/3907:33:3933
1864599194188,4cyclictest2456-21CPU33
1864599194188,4cyclictest2456-21CPU33
1864599194188,4cyclictest0-21swapper/3909:25:1333
1864599194188,4cyclictest0-21swapper/3909:25:1333
1864599194188,4cyclictest0-21swapper/3909:25:1233
1860499194189,3cyclictest0-21swapper/407:10:1534
1860499194189,3cyclictest0-21swapper/407:10:1534
1862999193189,2cyclictest0-21swapper/2511:50:2318
1862999193189,2cyclictest0-21swapper/2511:50:2318
1862999193189,2cyclictest0-21swapper/2511:50:2318
1864599192186,4cyclictest0-21swapper/3907:16:1233
1864599192186,4cyclictest0-21swapper/3907:16:1233
1864599192185,5cyclictest26108-21grep07:40:2633
1863299192134,27cyclictest0-21swapper/2710:07:3420
1863299192134,27cyclictest0-21swapper/2710:07:3420
1863299192134,27cyclictest0-21swapper/2710:07:3320
1862899192158,31cyclictest3542-21CPU17
1862899192158,31cyclictest3542-21CPU17
1860599192188,2cyclictest0-21swapper/509:15:0835
1860599192188,2cyclictest0-21swapper/509:15:0735
1860599192188,2cyclictest0-21swapper/509:15:0735
1860199192167,16cyclictest0-21swapper/209:47:0012
1860199192167,16cyclictest0-21swapper/209:46:5912
1864599191184,5cyclictest0-21swapper/3911:17:5433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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