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2026-02-25 - 07:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Feb 25, 2026 01:02:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31493991951,97cyclictest0-21swapper/523:25:1235
31493991951,97cyclictest0-21swapper/523:25:1235
3152499193157,27cyclictest0-21swapper/3121:07:1525
3152499193157,27cyclictest0-21swapper/3121:07:1525
3152499193157,27cyclictest0-21swapper/3121:07:1525
3152699191187,2cyclictest0-21swapper/3222:35:2026
3152699191187,2cyclictest0-21swapper/3222:35:1926
3152699191187,2cyclictest0-21swapper/3222:35:1926
3151999189166,20cyclictest0-21swapper/2721:38:2720
3151999189166,20cyclictest0-21swapper/2721:38:2720
3150099188162,8cyclictest171rcu_preempt00:02:082
3150099188162,8cyclictest171rcu_preempt00:02:082
3150299186176,8cyclictest0-21swapper/1122:35:223
3150299186176,8cyclictest0-21swapper/1122:35:213
3150299186176,8cyclictest0-21swapper/1122:35:213
3149499184175,7cyclictest0-21swapper/622:47:2136
3149499184175,7cyclictest0-21swapper/622:47:2136
3150299183163,13cyclictest0-21swapper/1123:25:443
3150299183163,13cyclictest0-21swapper/1123:25:433
3150899182163,12cyclictest3610-21CPU9
3150899182163,12cyclictest3610-21CPU9
3150899182163,12cyclictest3610-21CPU9
3150899180163,14cyclictest0-21swapper/1721:13:569
3150899180163,14cyclictest0-21swapper/1721:13:569
3150899180161,11cyclictest0-21swapper/1721:17:539
3150899180161,11cyclictest0-21swapper/1721:17:539
3149799180161,13cyclictest0-21swapper/821:28:3238
3149799180161,13cyclictest0-21swapper/821:28:3238
3149799180161,13cyclictest0-21swapper/821:28:3138
3148899179143,4cyclictest0-21swapper/122:32:291
3148899179143,4cyclictest0-21swapper/122:32:291
3150299176160,11cyclictest0-21swapper/1122:01:203
3150299176160,11cyclictest0-21swapper/1122:01:203
3150299175167,6cyclictest0-21swapper/1123:33:413
3150299175167,6cyclictest0-21swapper/1123:33:403
315039917470,101cyclictest37351-21CPU4
315039917470,101cyclictest37351-21CPU4
315039917470,101cyclictest37351-21CPU4
3150299174165,6cyclictest37257-21qemu-system-x8623:17:033
3150299174165,6cyclictest37257-21qemu-system-x8623:17:033
3149499174163,5cyclictest0-21swapper/623:48:3936
3149499174163,5cyclictest0-21swapper/623:48:3936
3149499174163,5cyclictest0-21swapper/623:48:3936
3152499173140,25cyclictest0-21swapper/3122:52:0725
3152499173140,25cyclictest0-21swapper/3122:52:0625
3150299173165,6cyclictest0-21swapper/1122:26:463
3150299173165,6cyclictest0-21swapper/1122:26:453
3149499173166,5cyclictest0-21swapper/600:28:2636
3149499173166,5cyclictest0-21swapper/600:28:2636
3149499173166,5cyclictest0-21swapper/600:28:2536
3151299172158,4cyclictest0-21swapper/2100:09:0314
3151299172158,4cyclictest0-21swapper/2100:09:0214
3148799172152,10cyclictest0-21swapper/022:19:580
3148799172152,10cyclictest0-21swapper/022:19:580
3148799172152,10cyclictest0-21swapper/022:19:580
31509991711,144cyclictest0-21swapper/1821:50:1510
31509991711,144cyclictest0-21swapper/1821:50:1510
31509991711,144cyclictest0-21swapper/1821:50:1510
3149499171160,8cyclictest28765-21kworker/u80:1-ext4-rsv-conversion23:03:4036
3149499171160,8cyclictest28765-21kworker/u80:1-ext4-rsv-conversion23:03:4036
3148899171161,8cyclictest0-21swapper/123:28:511
3148899171161,8cyclictest0-21swapper/123:28:501
3148799171158,12cyclictest0-21swapper/023:19:030
3148799171158,12cyclictest0-21swapper/023:19:030
3153199170139,22cyclictest0-21swapper/3621:00:3030
3153199170139,22cyclictest0-21swapper/3621:00:3030
3152099170135,32cyclictest32271-21sshd21:12:5521
3152099170135,32cyclictest32271-21sshd21:12:5521
3152099170135,28cyclictest0-21swapper/2822:21:5721
3152099170135,28cyclictest0-21swapper/2822:21:5721
3152099170135,28cyclictest0-21swapper/2822:21:5621
3151299170139,24cyclictest1-21systemd22:50:2914
3151299170139,24cyclictest1-21systemd22:50:2914
3150299170162,4cyclictest0-21swapper/1123:20:363
3150299170162,4cyclictest0-21swapper/1123:20:363
3150299170157,9cyclictest19458-2110-uname21:56:433
3150299170157,9cyclictest19458-2110-uname21:56:433
3149899170152,16cyclictest0-21swapper/923:37:1339
3149899170152,16cyclictest0-21swapper/923:37:1339
3150299169159,8cyclictest0-21swapper/1122:54:493
3150299169159,8cyclictest0-21swapper/1122:54:483
3149499169162,5cyclictest0-21swapper/621:12:5536
3149499169162,5cyclictest0-21swapper/621:12:5536
3153499168140,21cyclictest0-21swapper/3921:45:0533
3153499168140,21cyclictest0-21swapper/3921:45:0433
31520991681,71cyclictest0-21swapper/2820:30:2121
31520991681,71cyclictest0-21swapper/2820:30:2021
3148799168162,4cyclictest3535-21qemu-system-x8600:15:160
3148799168162,4cyclictest3535-21qemu-system-x8600:15:150
315249916718,137cyclictest0-21swapper/3100:15:1625
315249916718,137cyclictest0-21swapper/3100:15:1525
3152499167150,10cyclictest0-21swapper/3119:27:2425
3152499167150,10cyclictest0-21swapper/3119:27:2425
3152099167128,35cyclictest0-21swapper/2822:43:5021
3152099167128,35cyclictest0-21swapper/2822:43:5021
3152099167128,35cyclictest0-21swapper/2822:43:5021
3151299167135,13cyclictest171rcu_preempt22:18:3914
3151299167135,13cyclictest171rcu_preempt22:18:3814
3151299167135,13cyclictest171rcu_preempt22:18:3814
314889916791,38cyclictest2466-21CPU1
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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