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2026-09-07 - 09:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Sep 07, 2026 01:02:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38822992641,256cyclictest0-21swapper/3600:25:2230
38822992641,256cyclictest0-21swapper/3600:25:2230
38822992641,256cyclictest0-21swapper/3600:25:2230
38822992601,4cyclictest17483-21nfsd23:35:2230
38822992601,4cyclictest17483-21nfsd23:35:2230
38822992590,4cyclictest17723-21sshd22:10:2330
38822992590,4cyclictest17723-21sshd22:10:2330
38822992561,241cyclictest0-21swapper/3622:30:2130
38822992561,241cyclictest0-21swapper/3622:30:2130
38822992531,246cyclictest0-21swapper/3621:45:2030
38822992531,246cyclictest0-21swapper/3621:45:1930
38822992521,241cyclictest0-21swapper/3622:55:1830
38822992521,241cyclictest0-21swapper/3622:55:1830
38822992502,235cyclictest3544-21CPU30
38822992502,235cyclictest3544-21CPU30
38822992502,235cyclictest3544-21CPU30
38822992480,3cyclictest40897-21sshd23:40:2230
38822992480,3cyclictest40897-21sshd23:40:2230
38822992461,235cyclictest0-21swapper/3623:51:4430
38822992461,235cyclictest0-21swapper/3623:51:4330
38822992452,235cyclictest3546-21CPU30
38822992452,235cyclictest3546-21CPU30
38822992421,236cyclictest17980-21sshd22:35:1430
38822992421,236cyclictest17980-21sshd22:35:1430
38822992411,237cyclictest0-21swapper/3623:15:2130
38822992411,237cyclictest0-21swapper/3623:15:2130
38822992411,237cyclictest0-21swapper/3623:15:2130
38822992391,2cyclictest0-21swapper/3623:00:1730
38822992391,2cyclictest0-21swapper/3623:00:1730
38822992381,2cyclictest0-21swapper/3622:21:1730
38822992381,2cyclictest0-21swapper/3622:21:1730
38822992381,2cyclictest0-21swapper/3622:21:1730
38822992381,2cyclictest0-21swapper/3621:55:1530
38822992381,2cyclictest0-21swapper/3621:55:1530
38822992361,2cyclictest0-21swapper/3622:44:0430
38822992361,2cyclictest0-21swapper/3622:44:0330
38822992361,231cyclictest0-21swapper/3623:05:1630
38822992361,231cyclictest0-21swapper/3623:05:1530
38822992361,230cyclictest0-21swapper/3600:40:0130
38822992361,230cyclictest0-21swapper/3600:40:0030
38822992353,228cyclictest0-21swapper/3623:55:2330
38822992353,228cyclictest0-21swapper/3623:55:2330
38822992353,228cyclictest0-21swapper/3623:55:2230
38822992353,228cyclictest0-21swapper/3623:55:2230
38822992351,2cyclictest0-21swapper/3621:25:0230
38822992351,2cyclictest0-21swapper/3621:25:0130
38822992351,2cyclictest0-21swapper/3600:17:2630
38822992351,2cyclictest0-21swapper/3600:17:2530
38822992351,230cyclictest0-21swapper/3621:33:3230
38822992351,230cyclictest0-21swapper/3621:33:3230
38822992331,225cyclictest0-21swapper/3600:30:1530
38822992331,225cyclictest0-21swapper/3600:30:1530
38822992321,223cyclictest0-21swapper/3623:45:1530
38822992321,223cyclictest0-21swapper/3623:45:1530
38822992320,2cyclictest0-21swapper/3600:21:2930
38822992320,2cyclictest0-21swapper/3600:21:2830
3881299231224,4cyclictest2456-21CPU20
3881299231224,4cyclictest2456-21CPU20
3878599231226,3cyclictest0-21swapper/320:20:2323
3878599231226,3cyclictest0-21swapper/320:20:2323
38822992301,226cyclictest0-21swapper/3621:25:2930
38822992301,226cyclictest0-21swapper/3621:25:2930
38822992301,226cyclictest0-21swapper/3621:25:2930
3878299230224,3cyclictest18628-21kworker/u81:1+events_unbound22:40:100
3878299230224,3cyclictest18628-21kworker/u81:1+events_unbound22:40:100
38822992292,222cyclictest0-21swapper/3619:40:4130
38822992292,222cyclictest0-21swapper/3619:40:4030
38822992291,225cyclictest0-21swapper/3622:01:5730
38822992291,225cyclictest0-21swapper/3622:01:5730
38822992291,225cyclictest0-21swapper/3622:01:5730
38822992281,224cyclictest0-21swapper/3623:25:1230
38822992281,224cyclictest0-21swapper/3623:25:1230
38822992271,223cyclictest0-21swapper/3621:41:0930
38822992271,223cyclictest0-21swapper/3621:41:0930
38822992262,219cyclictest37267-21CPU30
38822992262,219cyclictest37267-21CPU30
38822992261,2cyclictest0-21swapper/3623:10:2230
38822992261,2cyclictest0-21swapper/3623:10:2130
38822992261,2cyclictest0-21swapper/3623:10:2130
38822992251,2cyclictest0-21swapper/3622:26:2930
38822992251,2cyclictest0-21swapper/3622:26:2930
38822992250,2cyclictest0-21swapper/3620:02:2230
38822992241,3cyclictest0-21swapper/3622:16:3630
38822992241,3cyclictest0-21swapper/3622:16:3630
38822992241,2cyclictest0-21swapper/3623:34:1630
38822992241,2cyclictest0-21swapper/3623:34:1530
38822992241,220cyclictest0-21swapper/3600:12:1730
38822992241,220cyclictest0-21swapper/3600:12:1630
38822992231,2cyclictest0-21swapper/3619:59:0530
38822992231,2cyclictest0-21swapper/3619:59:0530
38822992231,219cyclictest0-21swapper/3622:55:0430
38822992231,219cyclictest0-21swapper/3622:55:0430
38822992231,219cyclictest0-21swapper/3621:18:4730
38822992231,219cyclictest0-21swapper/3621:18:4730
38822992231,219cyclictest0-21swapper/3621:00:1230
38822992231,219cyclictest0-21swapper/3621:00:1130
38822992221,218cyclictest0-21swapper/3600:07:0430
38822992221,218cyclictest0-21swapper/3600:07:0430
38822992221,218cyclictest0-21swapper/3600:07:0330
38822992202,214cyclictest2459-21CPU30
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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