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2026-04-06 - 06:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Apr 06, 2026 01:01:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
67309925523,226cyclictest0-21swapper/2322:45:1716
67309925523,226cyclictest0-21swapper/2322:45:1716
67309921617,2cyclictest0-21swapper/2323:32:5316
67309921617,2cyclictest0-21swapper/2323:32:5216
67309921617,2cyclictest0-21swapper/2323:32:5216
672699209185,14cyclictest0-21swapper/2000:07:4013
672699209185,14cyclictest0-21swapper/2000:07:4013
672699209185,14cyclictest0-21swapper/2000:07:3913
671299209195,12cyclictest0-21swapper/921:39:3439
671299209195,12cyclictest0-21swapper/921:39:3439
673999208198,8cyclictest0-21swapper/3022:32:1124
673999208198,8cyclictest0-21swapper/3022:32:1124
673199207156,22cyclictest0-21swapper/2422:51:3417
673199207156,22cyclictest0-21swapper/2422:51:3417
672999207172,12cyclictest0-21swapper/2222:55:3015
672999207172,12cyclictest0-21swapper/2222:55:3015
674399205144,26cyclictest0-21swapper/3421:55:0728
674399205144,26cyclictest0-21swapper/3421:55:0728
671299203176,15cyclictest0-21swapper/922:55:3839
671299203176,15cyclictest0-21swapper/922:55:3839
673399200164,14cyclictest0-21swapper/2623:30:5919
673399200164,14cyclictest0-21swapper/2623:30:5919
673399200164,14cyclictest0-21swapper/2623:30:5919
673199200177,9cyclictest0-21swapper/2419:20:2517
673199200177,9cyclictest0-21swapper/2419:20:2517
672999199175,15cyclictest2461-21CPU15
672999199175,15cyclictest2461-21CPU15
673799198167,17cyclictest37346-21qemu-system-x8621:21:0222
673799198167,17cyclictest37346-21qemu-system-x8621:21:0122
673599198189,7cyclictest0-21swapper/2823:02:2221
673599198189,7cyclictest0-21swapper/2823:02:2221
673599198189,7cyclictest0-21swapper/2823:02:2221
670999197175,17cyclictest3543-21CPU37
670999197175,17cyclictest3543-21CPU37
670999197171,13cyclictest0-21swapper/700:26:5837
670999197171,13cyclictest0-21swapper/700:26:5737
670799197188,7cyclictest27714-21kworker/u81:3+events_unbound19:35:0635
670799197188,7cyclictest27714-21kworker/u81:3+events_unbound19:35:0635
673599196181,12cyclictest0-21swapper/2800:39:5821
673599196181,12cyclictest0-21swapper/2800:39:5721
670799195123,46cyclictest0-21swapper/500:06:3135
670799195123,46cyclictest0-21swapper/500:06:3135
670799195123,46cyclictest0-21swapper/500:06:3135
672999194170,7cyclictest171rcu_preempt19:44:5915
672999194170,7cyclictest171rcu_preempt19:44:5915
672599194146,27cyclictest3543-21CPU11
672599194146,27cyclictest3543-21CPU11
672599194146,27cyclictest3543-21CPU11
6711991941,190cyclictest0-21swapper/822:00:2438
6711991941,190cyclictest0-21swapper/822:00:2438
673999191151,21cyclictest0-21swapper/3000:00:3024
673999191151,21cyclictest0-21swapper/3000:00:3024
672599191151,18cyclictest0-21swapper/1921:58:3411
672599191151,18cyclictest0-21swapper/1921:58:3411
672999189136,42cyclictest0-21swapper/2223:51:3415
672999189136,42cyclictest0-21swapper/2223:51:3415
674399188177,9cyclictest0-21swapper/3420:25:0028
674399188177,9cyclictest0-21swapper/3420:25:0028
674899185153,28cyclictest0-21swapper/3923:00:3133
674899185153,28cyclictest0-21swapper/3923:00:3133
674899185153,28cyclictest0-21swapper/3923:00:3133
672299184181,2cyclictest0-21swapper/1623:38:178
672299184181,2cyclictest0-21swapper/1623:38:178
671599184135,44cyclictest3609-21CPU2
671599184135,44cyclictest3609-21CPU2
67479918382,92cyclictest0-21swapper/3822:50:2032
67479918382,92cyclictest0-21swapper/3822:50:1932
674799183144,35cyclictest3543-21CPU32
674799183144,35cyclictest3543-21CPU32
673399183177,4cyclictest0-21swapper/2622:59:5319
673399183177,4cyclictest0-21swapper/2622:59:5219
671899183174,7cyclictest0-21swapper/1321:33:165
671899183174,7cyclictest0-21swapper/1321:33:165
670999183165,6cyclictest171rcu_preempt22:20:2937
670999183165,6cyclictest171rcu_preempt22:20:2937
674899182153,26cyclictest0-21swapper/3923:15:3133
674899182153,26cyclictest0-21swapper/3923:15:3133
673299182176,1cyclictest0-21swapper/2522:09:1918
673299182176,1cyclictest0-21swapper/2522:09:1918
673199182167,7cyclictest171rcu_preempt23:43:1417
673199182167,7cyclictest171rcu_preempt23:43:1417
673199182167,7cyclictest171rcu_preempt23:43:1417
672999182135,19cyclictest0-21swapper/2220:55:0615
671899182173,8cyclictest0-21swapper/1300:01:225
671899182173,8cyclictest0-21swapper/1300:01:225
671799182172,8cyclictest0-21swapper/1221:13:514
671799182172,8cyclictest0-21swapper/1221:13:514
6711991821,5cyclictest2464-21CPU38
6711991821,5cyclictest2464-21CPU38
670199182166,4cyclictest0-21swapper/123:30:171
670199182166,4cyclictest0-21swapper/123:30:171
670199182166,4cyclictest0-21swapper/123:30:171
673199181141,22cyclictest0-21swapper/2420:26:4117
673199181141,22cyclictest0-21swapper/2420:26:4117
672999181169,6cyclictest171rcu_preempt21:00:3515
670999181169,6cyclictest171rcu_preempt21:32:2937
670999181169,6cyclictest171rcu_preempt21:32:2937
674199180157,15cyclictest0-21swapper/3200:00:2926
674199180157,15cyclictest0-21swapper/3200:00:2926
672999180164,10cyclictest171rcu_preempt21:27:3715
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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