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2026-03-04 - 15:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Mar 04, 2026 13:03:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3775299221213,5cyclictest0-21swapper/1708:10:149
3775299209199,7cyclictest0-21swapper/1712:39:419
3775299209199,7cyclictest0-21swapper/1712:39:419
3775399208201,4cyclictest1360-21systemd-logind09:25:5510
3775399208201,4cyclictest1360-21systemd-logind09:25:5410
3774099206197,5cyclictest0-21swapper/711:34:3437
3774099206197,5cyclictest0-21swapper/711:34:3437
3774099206197,5cyclictest0-21swapper/711:34:3337
3775399203173,21cyclictest0-21swapper/1811:17:4910
3775399203173,21cyclictest0-21swapper/1811:17:4910
3775399203173,21cyclictest0-21swapper/1811:17:4810
3775399199192,4cyclictest0-21swapper/1809:35:1910
3775399199192,4cyclictest0-21swapper/1809:35:1910
3775399199192,4cyclictest0-21swapper/1809:35:1910
3774399199192,2cyclictest0-21swapper/1009:00:272
3774399199192,2cyclictest0-21swapper/1009:00:272
3775299195189,4cyclictest0-21swapper/1712:06:579
3775299195189,4cyclictest0-21swapper/1712:06:579
3775299195189,4cyclictest0-21swapper/1712:06:569
3775299195189,4cyclictest0-21swapper/1711:09:399
3775299195189,4cyclictest0-21swapper/1711:09:399
3775299194187,5cyclictest0-21swapper/1712:20:349
3775299194187,5cyclictest0-21swapper/1712:20:349
3775299194187,5cyclictest0-21swapper/1710:22:489
3775299194187,5cyclictest0-21swapper/1710:22:489
3775299194187,5cyclictest0-21swapper/1710:22:479
3775899193181,8cyclictest11295-2110-uname10:11:2516
3775899193181,8cyclictest11295-2110-uname10:11:2516
3775899193181,8cyclictest11295-2110-uname10:11:2516
3775399193186,5cyclictest0-21swapper/1809:10:1710
3775399193186,5cyclictest0-21swapper/1809:10:1710
3775299192185,5cyclictest0-21swapper/1712:27:219
3775299192185,5cyclictest0-21swapper/1712:27:219
3775299192185,5cyclictest0-21swapper/1712:27:219
3775399191185,4cyclictest0-21swapper/1811:38:3410
3775399191185,4cyclictest0-21swapper/1811:38:3310
3775299191186,4cyclictest0-21swapper/1710:28:569
3775299191186,4cyclictest0-21swapper/1710:28:569
3775299191186,4cyclictest0-21swapper/1710:28:559
3775299191184,4cyclictest1-21systemd10:50:199
3775299191184,4cyclictest1-21systemd10:50:199
3775299191184,4cyclictest1-21systemd10:50:199
3774199191187,2cyclictest0-21swapper/810:12:5638
3774199191187,2cyclictest0-21swapper/810:12:5638
3774199191187,2cyclictest0-21swapper/810:12:5638
3775299190182,6cyclictest0-21swapper/1712:02:169
3775299190182,6cyclictest0-21swapper/1712:02:159
3775299190181,7cyclictest0-21swapper/1711:53:099
3775299190181,7cyclictest0-21swapper/1711:53:099
3774099190179,9cyclictest0-21swapper/711:11:1937
3774099190179,9cyclictest0-21swapper/711:11:1937
3774099190179,9cyclictest0-21swapper/711:11:1937
3773899190126,56cyclictest0-21swapper/509:44:4835
3773899190126,56cyclictest0-21swapper/509:44:4835
3775399189184,3cyclictest0-21swapper/1811:30:1410
3775399189184,3cyclictest0-21swapper/1811:30:1410
3775399189184,3cyclictest0-21swapper/1811:30:1410
3775299189182,5cyclictest0-21swapper/1708:00:119
3775299189182,5cyclictest0-21swapper/1708:00:109
3775299189181,6cyclictest1367-21dbus-daemon12:18:109
3775299189181,6cyclictest1367-21dbus-daemon12:18:109
3775299189181,6cyclictest1367-21dbus-daemon12:18:099
3775399188182,4cyclictest0-21swapper/1811:29:3410
3775399188182,4cyclictest0-21swapper/1811:29:3310
3775399188176,10cyclictest0-21swapper/1809:33:5910
3775399188176,10cyclictest0-21swapper/1809:33:5910
3775299188182,4cyclictest0-21swapper/1710:40:209
3775299188182,4cyclictest0-21swapper/1710:40:209
3775299188182,4cyclictest0-21swapper/1710:40:209
3775299188182,4cyclictest0-21swapper/1710:19:179
3775299188182,4cyclictest0-21swapper/1710:19:179
3775299187180,5cyclictest0-21swapper/1710:46:139
3775299187180,5cyclictest0-21swapper/1710:46:139
3775299187180,5cyclictest0-21swapper/1710:46:129
3775299187177,5cyclictest37355-21CPU9
3775299187177,5cyclictest37355-21CPU9
3775399186181,4cyclictest0-21swapper/1811:42:0910
3775399186181,4cyclictest0-21swapper/1811:42:0810
3775399186104,78cyclictest3544-21CPU10
3775399186104,78cyclictest3544-21CPU10
3775299186177,7cyclictest0-21swapper/1710:55:599
3775299186177,7cyclictest0-21swapper/1710:55:599
3775299186177,7cyclictest0-21swapper/1710:55:599
3775299186176,7cyclictest0-21swapper/1711:39:599
3775299186176,7cyclictest0-21swapper/1711:39:589
3775299185174,9cyclictest0-21swapper/1708:45:279
3775299185174,9cyclictest0-21swapper/1708:45:279
3775399184174,6cyclictest2464-21CPU10
3775399184174,6cyclictest2464-21CPU10
3775399184174,6cyclictest2464-21CPU10
3775299184177,5cyclictest0-21swapper/1710:30:429
3775299184177,5cyclictest0-21swapper/1710:30:429
3775299184171,11cyclictest0-21swapper/1711:43:589
3775299184171,11cyclictest0-21swapper/1711:43:589
3775399183177,4cyclictest0-21swapper/1809:21:0310
3775399183177,4cyclictest0-21swapper/1809:21:0310
3777899182157,11cyclictest0-21swapper/3909:00:3233
3777899182157,11cyclictest0-21swapper/3909:00:3233
377569918260,34cyclictest0-21swapper/2108:20:2114
377569918260,34cyclictest0-21swapper/2108:20:2114
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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