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2026-02-16 - 11:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Feb 16, 2026 01:01:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1947799214209,3cyclictest0-21swapper/2622:41:1519
1947799214209,3cyclictest0-21swapper/2622:41:1519
1947799213206,5cyclictest19400-21sshd00:19:3719
1947799213206,5cyclictest19400-21sshd00:19:3719
1947299213193,15cyclictest0-21swapper/2120:40:0114
1947299213193,15cyclictest0-21swapper/2120:40:0114
1947799212203,5cyclictest3610-21CPU19
1947799212203,5cyclictest3610-21CPU19
1947799210203,5cyclictest0-21swapper/2622:50:1519
1947799210203,5cyclictest0-21swapper/2622:50:1419
1945999209199,5cyclictest17028-21fschecks_time23:30:193
1945999209199,5cyclictest17028-21fschecks_time23:30:193
1945999209184,13cyclictest0-21swapper/1123:28:223
1945999209184,13cyclictest0-21swapper/1123:28:213
1945899209152,19cyclictest0-21swapper/1000:22:272
1945899209152,19cyclictest0-21swapper/1000:22:272
1945899209152,19cyclictest0-21swapper/1000:22:272
1947799207201,4cyclictest0-21swapper/2622:58:1719
1947799207201,4cyclictest0-21swapper/2622:58:1719
1947799207199,5cyclictest0-21swapper/2600:32:5719
1947799207199,5cyclictest0-21swapper/2600:32:5719
1947799207199,5cyclictest0-21swapper/2600:32:5719
1946699207201,4cyclictest0-21swapper/1619:35:148
1946699207201,4cyclictest0-21swapper/1619:35:148
1947799206200,4cyclictest17481-21nfsd22:38:0319
1947799206200,4cyclictest17481-21nfsd22:38:0319
1947799203198,4cyclictest0-21swapper/2623:41:1719
1947799203198,4cyclictest0-21swapper/2623:41:1719
1947799203198,4cyclictest0-21swapper/2623:41:1619
1946699203196,6cyclictest0-21swapper/1620:23:118
1946699203196,6cyclictest0-21swapper/1620:23:118
1945499203195,6cyclictest0-21swapper/722:11:1337
1945499203195,6cyclictest0-21swapper/722:11:1237
1947799202193,7cyclictest0-21swapper/2600:20:1119
1947799202193,7cyclictest0-21swapper/2600:20:1119
1947799202193,7cyclictest0-21swapper/2600:20:1119
1947799201194,5cyclictest0-21swapper/2600:37:0919
1947799201194,5cyclictest0-21swapper/2600:37:0819
1947799201194,5cyclictest0-21swapper/2600:05:1419
1947799201194,5cyclictest0-21swapper/2600:05:1419
1947799201187,9cyclictest4407-21CPU19
1947799201187,9cyclictest4407-21CPU19
1946699201193,6cyclictest0-21swapper/1620:00:188
1946699201193,6cyclictest0-21swapper/1620:00:188
1947799199194,4cyclictest0-21swapper/2623:13:4919
1947799199194,4cyclictest0-21swapper/2623:13:4919
1946699199193,4cyclictest0-21swapper/1619:20:118
1947799198193,3cyclictest25169-21systemd-cgroups00:02:1519
1947799198193,3cyclictest25169-21systemd-cgroups00:02:1519
1947799198192,4cyclictest0-21swapper/2622:45:3519
1947799198192,4cyclictest0-21swapper/2622:45:3519
1947799198192,4cyclictest0-21swapper/2622:45:3419
1947799196191,3cyclictest0-21swapper/2623:01:1719
1947799196191,3cyclictest0-21swapper/2623:01:1719
1947799196188,5cyclictest1430-21polkitd23:57:4019
1947799196188,5cyclictest1430-21polkitd23:57:4019
1947799196188,5cyclictest1430-21polkitd23:57:3919
1947299196190,4cyclictest0-21swapper/2120:40:1114
1947299196190,4cyclictest0-21swapper/2120:40:1014
1947799195189,4cyclictest0-21swapper/2600:26:0619
1947799195189,4cyclictest0-21swapper/2600:26:0519
1947899194189,3cyclictest0-21swapper/2722:45:1720
1947899194189,3cyclictest0-21swapper/2722:45:1720
1947899194189,3cyclictest0-21swapper/2722:45:1620
1947799194187,5cyclictest3406-21sshd23:15:4619
1947799194187,5cyclictest3406-21sshd23:15:4619
1947799193187,4cyclictest0-21swapper/2621:03:5019
1947799193187,4cyclictest0-21swapper/2621:03:5019
1946699193188,4cyclictest0-21swapper/1620:14:428
1946699193188,4cyclictest0-21swapper/1620:14:428
1947799192187,4cyclictest0-21swapper/2620:54:1519
1947799192187,4cyclictest0-21swapper/2620:54:1519
1947299192187,4cyclictest0-21swapper/2120:58:3214
1947299192187,4cyclictest0-21swapper/2120:58:3114
1946699192184,6cyclictest0-21swapper/1619:16:568
1945999192185,5cyclictest0-21swapper/1123:22:333
1945999192185,5cyclictest0-21swapper/1123:22:333
1947799191184,3cyclictest3546-21CPU19
1947799191184,3cyclictest3546-21CPU19
1944699191184,5cyclictest0-21swapper/021:19:420
1944699191184,5cyclictest0-21swapper/021:19:420
1947799190184,2cyclictest3547-21CPU19
1947799190184,2cyclictest3547-21CPU19
1947799190183,5cyclictest0-21swapper/2623:50:1419
1947799190183,5cyclictest0-21swapper/2623:50:1419
1947799190183,5cyclictest0-21swapper/2623:50:1419
1947799190178,10cyclictest0-21swapper/2620:55:0919
1947799190178,10cyclictest0-21swapper/2620:55:0819
1946699190182,6cyclictest0-21swapper/1619:50:258
1946699190182,6cyclictest0-21swapper/1619:50:248
1948199189174,10cyclictest0-21swapper/2900:33:4422
1948199189174,10cyclictest0-21swapper/2900:33:4422
1948199189174,10cyclictest0-21swapper/2900:33:4422
1946699189184,4cyclictest0-21swapper/1620:17:198
1947799188182,4cyclictest0-21swapper/2621:10:1819
1947799188182,4cyclictest0-21swapper/2621:10:1819
1947799188182,4cyclictest0-21swapper/2621:10:1719
1947799187184,2cyclictest0-21swapper/2620:43:1319
1947799187184,2cyclictest0-21swapper/2620:43:1219
1947299187181,4cyclictest0-21swapper/2120:45:2514
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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