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2026-01-14 - 18:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Jan 14, 2026 13:01:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3448399213205,5cyclictest0-21swapper/2609:45:1219
3448399213205,5cyclictest0-21swapper/2609:45:1219
3448399213205,5cyclictest0-21swapper/2609:45:1219
3447299213189,19cyclictest2454-21CPU7
3447299213189,19cyclictest2454-21CPU7
3448199208192,13cyclictest0-21swapper/2411:09:0017
3448199208192,13cyclictest0-21swapper/2411:09:0017
3448199208192,13cyclictest0-21swapper/2411:09:0017
3448399205199,4cyclictest0-21swapper/2612:38:1519
3448399205199,4cyclictest0-21swapper/2612:38:1419
3448399205199,4cyclictest0-21swapper/2612:38:1419
3448399205198,5cyclictest0-21swapper/2611:00:4519
3448399205198,5cyclictest0-21swapper/2611:00:4519
3448399205198,5cyclictest0-21swapper/2611:00:4419
3448399200182,10cyclictest0-21swapper/2611:11:4919
3448399200182,10cyclictest0-21swapper/2611:11:4919
3448399200182,10cyclictest0-21swapper/2611:11:4919
3448399198193,3cyclictest0-21swapper/2611:58:3219
3448399198193,3cyclictest0-21swapper/2611:58:3119
3448399198193,3cyclictest0-21swapper/2611:58:3119
3448399198192,4cyclictest0-21swapper/2611:30:4419
3448399198192,4cyclictest0-21swapper/2611:30:4419
3448399198192,4cyclictest0-21swapper/2611:30:4419
3448299198193,3cyclictest0-21swapper/2508:10:2018
3448299198193,3cyclictest0-21swapper/2508:10:2018
3448399196191,2cyclictest0-21swapper/2611:24:2219
3448399196191,2cyclictest0-21swapper/2611:24:2219
3448399196191,2cyclictest0-21swapper/2611:24:2219
3448999194173,8cyclictest0-21swapper/3211:35:3726
3448999194173,8cyclictest0-21swapper/3211:35:3626
3448999194173,8cyclictest0-21swapper/3211:35:3626
3448399194188,4cyclictest9455-21systemd-cgroups09:38:5819
3448399194188,4cyclictest9455-21systemd-cgroups09:38:5819
3448399194188,4cyclictest9455-21systemd-cgroups09:38:5819
3448399194188,4cyclictest0-21swapper/2610:45:1919
3448399194188,4cyclictest0-21swapper/2610:45:1919
3448399194187,5cyclictest0-21swapper/2610:13:1819
3448399194187,5cyclictest0-21swapper/2610:13:1719
3448399194183,7cyclictest37265-21CPU19
3448399194183,7cyclictest37265-21CPU19
3448399194181,11cyclictest0-21swapper/2610:29:1819
3448399194181,11cyclictest0-21swapper/2610:29:1819
3448399194181,11cyclictest0-21swapper/2610:29:1819
3448399193187,5cyclictest0-21swapper/2610:17:0219
3448399193187,5cyclictest0-21swapper/2610:17:0119
3448399193187,5cyclictest0-21swapper/2610:17:0119
3448399193187,4cyclictest0-21swapper/2611:06:2219
3448399193187,4cyclictest0-21swapper/2611:06:2119
3448399193187,4cyclictest0-21swapper/2611:06:2119
3445799193183,9cyclictest0-21swapper/010:12:080
3445799193183,9cyclictest0-21swapper/010:12:080
3448399192187,3cyclictest24952-21packagekitd12:01:3719
3448399192187,3cyclictest24952-21packagekitd12:01:3719
3448399192186,4cyclictest0-21swapper/2611:45:0219
3448399192186,4cyclictest0-21swapper/2611:45:0219
3448399192186,4cyclictest0-21swapper/2611:45:0219
3448399192186,3cyclictest20827-21systemd-cgroups12:07:0719
3448399192186,3cyclictest20827-21systemd-cgroups12:07:0719
3448399192186,3cyclictest20827-21systemd-cgroups12:07:0719
3448399192185,5cyclictest0-21swapper/2612:21:3719
3448399192185,5cyclictest0-21swapper/2612:21:3719
3448399192184,3cyclictest3544-21CPU19
3448399192184,3cyclictest3544-21CPU19
3448399192184,3cyclictest3544-21CPU19
3448399192182,7cyclictest0-21swapper/2610:37:5819
3448399192182,7cyclictest0-21swapper/2610:37:5819
3448399192182,7cyclictest0-21swapper/2610:37:5819
3448399192180,9cyclictest3535-21qemu-system-x8612:17:1619
3448399192180,9cyclictest3535-21qemu-system-x8612:17:1619
3445799192182,8cyclictest0-21swapper/012:06:190
3445799192182,8cyclictest0-21swapper/012:06:190
3445799192182,8cyclictest0-21swapper/012:06:190
3445799192181,5cyclictest0-21swapper/010:08:000
3445799192181,5cyclictest0-21swapper/010:07:590
3445799192181,5cyclictest0-21swapper/010:07:590
3448399191185,4cyclictest0-21swapper/2611:00:0719
3448399191185,4cyclictest0-21swapper/2611:00:0719
3448399191179,10cyclictest0-21swapper/2609:54:4819
3448399191179,10cyclictest0-21swapper/2609:54:4819
3448399191179,10cyclictest0-21swapper/2609:54:4819
3446199191184,5cyclictest0-21swapper/411:49:3234
3446199191184,5cyclictest0-21swapper/411:49:3134
3448399190185,4cyclictest0-21swapper/2609:24:3919
3448399190185,4cyclictest0-21swapper/2609:24:3919
3448399190184,4cyclictest0-21swapper/2611:35:1719
3448399190184,4cyclictest0-21swapper/2611:35:1619
3448399190184,4cyclictest0-21swapper/2611:35:1619
3448399190183,5cyclictest0-21swapper/2609:26:1119
3448399190183,5cyclictest0-21swapper/2609:26:1019
3447799190185,2cyclictest0-21swapper/2011:25:4913
3447799190185,2cyclictest0-21swapper/2011:25:4913
3447799190185,2cyclictest0-21swapper/2011:25:4913
3448399189184,4cyclictest0-21swapper/2611:48:5219
3448399189184,4cyclictest0-21swapper/2611:48:5219
3448399189183,4cyclictest3535-21qemu-system-x8612:14:0119
3448399189183,4cyclictest3535-21qemu-system-x8612:14:0119
3448399189183,4cyclictest0-21swapper/2609:57:2419
3448399189183,4cyclictest0-21swapper/2609:57:2419
3448399188183,4cyclictest0-21swapper/2610:24:4519
3448399188183,4cyclictest0-21swapper/2610:24:4519
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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