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2026-06-21 - 04:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Jun 21, 2026 01:01:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2639992401,234cyclictest0-21swapper/1900:14:5711
2639992401,234cyclictest0-21swapper/1900:14:5611
2639992351,230cyclictest0-21swapper/1921:00:1411
2639992351,224cyclictest0-21swapper/1923:48:0511
2639992351,224cyclictest0-21swapper/1923:48:0411
2639992351,224cyclictest0-21swapper/1923:48:0411
2639992341,2cyclictest0-21swapper/1922:02:4011
2639992341,2cyclictest0-21swapper/1922:02:4011
2639992323,224cyclictest2454-21CPU11
2639992323,224cyclictest2454-21CPU11
2639992323,224cyclictest2454-21CPU11
2639992321,3cyclictest4398-21qemu-system-x8623:19:5811
2639992321,3cyclictest4398-21qemu-system-x8623:19:5811
2639992321,3cyclictest4398-21qemu-system-x8623:19:5811
2639992321,228cyclictest0-21swapper/1922:22:3611
2639992321,228cyclictest0-21swapper/1922:22:3511
2639992311,5cyclictest4317-21sshd00:26:2311
2639992311,5cyclictest4317-21sshd00:26:2311
2639992293,221cyclictest3610-21CPU11
2639992293,221cyclictest3610-21CPU11
2639992291,4cyclictest1360-21systemd-logind23:20:2011
2639992291,4cyclictest1360-21systemd-logind23:20:2011
2639992291,2cyclictest0-21swapper/1923:30:2811
2639992291,2cyclictest0-21swapper/1923:30:2711
2639992291,2cyclictest0-21swapper/1923:30:2711
2639992291,2cyclictest0-21swapper/1922:30:4211
2639992291,2cyclictest0-21swapper/1922:30:4211
2639992291,2cyclictest0-21swapper/1922:25:2911
2639992291,2cyclictest0-21swapper/1922:25:2811
2639992291,222cyclictest0-21swapper/1921:44:2711
2639992291,222cyclictest0-21swapper/1921:44:2611
2639992283,222cyclictest1367-21dbus-daemon00:09:3511
2639992283,222cyclictest1367-21dbus-daemon00:09:3511
2639992280,2cyclictest0-21swapper/1923:12:4511
2639992280,2cyclictest0-21swapper/1923:12:4511
2639992280,2cyclictest0-21swapper/1923:12:4511
2639992280,2cyclictest0-21swapper/1922:59:1311
2639992280,2cyclictest0-21swapper/1922:59:1311
2639992271,2cyclictest0-21swapper/1923:37:2211
2639992271,2cyclictest0-21swapper/1923:37:2211
2639992271,2cyclictest0-21swapper/1921:20:1311
2639992271,2cyclictest0-21swapper/1921:20:1311
2639992270,2cyclictest0-21swapper/1923:40:1711
2639992270,2cyclictest0-21swapper/1923:40:1711
2639992262,219cyclictest3545-21CPU11
2639992262,219cyclictest3545-21CPU11
2639992261,2cyclictest0-21swapper/1922:15:3311
2639992261,2cyclictest0-21swapper/1922:15:3311
2639992260,7cyclictest4342-21sshd22:50:5511
2639992260,7cyclictest4342-21sshd22:50:5411
2639992260,2cyclictest0-21swapper/1923:51:1011
2639992260,2cyclictest0-21swapper/1923:51:0911
2639992260,2cyclictest0-21swapper/1921:58:0911
2639992260,2cyclictest0-21swapper/1921:58:0811
2639992260,2cyclictest0-21swapper/1921:58:0811
2639992251,2cyclictest0-21swapper/1923:25:1311
2639992251,2cyclictest0-21swapper/1923:25:1311
2639992250,2cyclictest0-21swapper/1900:40:0311
2639992250,2cyclictest0-21swapper/1900:40:0211
2639992242,217cyclictest2454-21CPU11
2639992242,217cyclictest2454-21CPU11
2639992242,217cyclictest2454-21CPU11
2639992241,214cyclictest0-21swapper/1921:38:0511
2639992241,214cyclictest0-21swapper/1921:38:0511
2639992241,214cyclictest0-21swapper/1921:38:0511
2639992231,216cyclictest0-21swapper/1923:04:2511
2639992231,216cyclictest0-21swapper/1923:04:2411
2639992221,2cyclictest0-21swapper/1900:24:3011
2639992221,2cyclictest0-21swapper/1900:24:2911
2639992211,3cyclictest0-21swapper/1923:05:4811
2639992211,3cyclictest0-21swapper/1923:05:4811
2639992211,2cyclictest0-21swapper/1922:44:0411
2639992211,2cyclictest0-21swapper/1922:44:0311
2639992211,2cyclictest0-21swapper/1922:36:4011
2639992211,2cyclictest0-21swapper/1922:36:3911
2639992211,2cyclictest0-21swapper/1922:36:3911
2639992211,2cyclictest0-21swapper/1900:04:5511
2639992211,2cyclictest0-21swapper/1900:04:5511
2639992211,10cyclictest32970-21uname21:50:3111
2639992211,10cyclictest32970-21uname21:50:3011
2639992210,11cyclictest2121-21sshd22:05:2211
2639992210,11cyclictest2121-21sshd22:05:2211
2639992201,2cyclictest0-21swapper/1922:12:0011
2639992201,2cyclictest0-21swapper/1922:11:5911
2639992201,2cyclictest0-21swapper/1921:29:3111
2639992201,2cyclictest0-21swapper/1921:29:3111
2639992201,215cyclictest0-21swapper/1921:11:2111
2639992201,215cyclictest0-21swapper/1921:11:2011
2639992200,2cyclictest0-21swapper/1900:34:2111
2639992200,2cyclictest0-21swapper/1900:34:2011
2639992200,2cyclictest0-21swapper/1900:15:2411
2639992200,2cyclictest0-21swapper/1900:15:2311
2639992200,2cyclictest0-21swapper/1900:15:2311
2639992161,5cyclictest3535-21qemu-system-x8621:45:4411
2639992161,5cyclictest3535-21qemu-system-x8621:45:4411
2639992090,2cyclictest0-21swapper/1920:55:1411
2639992080,2cyclictest0-21swapper/1921:05:1911
2639992080,2cyclictest0-21swapper/1921:05:1911
2639992080,2cyclictest0-21swapper/1921:05:1811
262799201190,8cyclictest0-21swapper/822:55:0438
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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