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2026-06-17 - 01:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Jun 16, 2026 13:03:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
163199237222,11cyclictest0-21swapper/2211:20:1715
163199237222,11cyclictest0-21swapper/2211:20:1615
164699222215,4cyclictest28873-21sshd11:46:5729
164699222215,4cyclictest28873-21sshd11:46:5629
164699222215,4cyclictest28873-21sshd11:46:5629
164999221206,12cyclictest0-21swapper/3812:36:1132
164999221206,12cyclictest0-21swapper/3812:36:1032
164999221206,12cyclictest0-21swapper/3812:36:1032
1633992198,103cyclictest0-21swapper/2409:10:1617
1633992198,103cyclictest0-21swapper/2409:10:1517
1633992198,103cyclictest0-21swapper/2409:10:1517
161599216203,10cyclictest3610-21CPU37
161599216203,10cyclictest3610-21CPU37
162999211208,2cyclictest0-21swapper/2008:20:1513
162999211208,2cyclictest0-21swapper/2008:20:1513
161999205173,25cyclictest0-21swapper/1110:02:413
161999205173,25cyclictest0-21swapper/1110:02:413
161999205173,25cyclictest0-21swapper/1110:02:413
164399203191,10cyclictest0-21swapper/3209:29:0926
164399203191,10cyclictest0-21swapper/3209:29:0926
164199203198,3cyclictest0-21swapper/3008:25:1424
164999202192,8cyclictest0-21swapper/3809:34:2432
164999202192,8cyclictest0-21swapper/3809:34:2332
163199201186,11cyclictest0-21swapper/2211:58:1315
163199201186,11cyclictest0-21swapper/2211:58:1315
163199200186,10cyclictest0-21swapper/2212:10:1315
163199200186,10cyclictest0-21swapper/2212:10:1315
1619992007,188cyclictest2454-21CPU3
1619992007,188cyclictest2454-21CPU3
163199199191,5cyclictest0-21swapper/2211:52:5615
163199199191,5cyclictest0-21swapper/2211:52:5615
163199199191,5cyclictest0-21swapper/2211:52:5615
163199199188,7cyclictest0-21swapper/2212:18:1515
163199199188,7cyclictest0-21swapper/2212:18:1415
163199199187,8cyclictest1358-21ModemManager12:05:5715
163199199187,8cyclictest1358-21ModemManager12:05:5715
163199199186,11cyclictest0-21swapper/2211:17:0015
163199199186,11cyclictest0-21swapper/2211:17:0015
162299199187,5cyclictest0-21swapper/1411:08:156
162299199187,5cyclictest0-21swapper/1411:08:146
162299199187,5cyclictest0-21swapper/1411:08:146
161499199194,3cyclictest0-21swapper/607:16:0736
161499199194,3cyclictest0-21swapper/607:16:0736
164999197191,4cyclictest0-21swapper/3812:30:5032
164999197191,4cyclictest0-21swapper/3812:30:4932
164999197188,7cyclictest0-21swapper/3807:11:2232
164999197188,7cyclictest0-21swapper/3807:11:2232
163199197184,6cyclictest1-21systemd11:48:1015
163199197184,6cyclictest1-21systemd11:48:1015
163199197184,6cyclictest1-21systemd11:48:1015
163199197162,9cyclictest171rcu_preempt12:39:0715
163199197162,9cyclictest171rcu_preempt12:39:0615
163199197162,9cyclictest171rcu_preempt12:39:0615
1619991971,63cyclictest0-21swapper/1111:30:203
1619991971,63cyclictest0-21swapper/1111:30:203
1619991971,63cyclictest0-21swapper/1111:30:193
163199196178,15cyclictest0-21swapper/2209:32:3715
163199196178,15cyclictest0-21swapper/2209:32:3615
163199195184,8cyclictest0-21swapper/2211:05:1815
163199195184,8cyclictest0-21swapper/2211:05:1815
163199195184,8cyclictest0-21swapper/2211:05:1815
163199195182,7cyclictest0-21swapper/2212:03:4915
163199195182,7cyclictest0-21swapper/2212:03:4915
163199195182,7cyclictest0-21swapper/2212:03:4915
163199195171,19cyclictest0-21swapper/2211:03:0315
163199195171,19cyclictest0-21swapper/2211:03:0215
163199195171,19cyclictest0-21swapper/2211:03:0215
1619991951,2cyclictest0-21swapper/1108:00:183
1619991951,2cyclictest0-21swapper/1108:00:173
161599195190,3cyclictest0-21swapper/711:37:4137
161599195190,3cyclictest0-21swapper/711:37:4137
164999194187,5cyclictest0-21swapper/3809:00:1932
164999194187,5cyclictest0-21swapper/3809:00:1932
163199194172,19cyclictest37265-21CPU15
163199194172,19cyclictest37265-21CPU15
161699194179,8cyclictest37354-21CPU38
161699194179,8cyclictest37354-21CPU38
161699194179,8cyclictest37354-21CPU38
161699194174,13cyclictest0-21swapper/809:25:0238
161699194174,13cyclictest0-21swapper/809:25:0138
161699194174,13cyclictest0-21swapper/809:25:0138
163199193180,9cyclictest19953-21kill11:10:3415
163199193180,9cyclictest19953-21kill11:10:3315
163199193180,9cyclictest19953-21kill11:10:3315
163199193173,13cyclictest0-21swapper/2210:47:1115
163199193173,13cyclictest0-21swapper/2210:47:1015
162999192189,2cyclictest0-21swapper/2010:25:2613
162999192189,2cyclictest0-21swapper/2010:25:2513
161699192178,11cyclictest0-21swapper/809:35:2238
161699192178,11cyclictest0-21swapper/809:35:2138
164499191185,4cyclictest0-21swapper/3311:08:2827
164499191185,4cyclictest0-21swapper/3311:08:2727
164499191185,4cyclictest0-21swapper/3311:08:2727
164299191161,16cyclictest0-21swapper/3112:15:4125
164299191161,16cyclictest0-21swapper/3112:15:4025
163899191188,2cyclictest0-21swapper/2707:20:3920
163899191188,2cyclictest0-21swapper/2707:20:3820
163199191157,20cyclictest171rcu_preempt11:25:2715
163199191157,20cyclictest171rcu_preempt11:25:2715
1620991911,126cyclictest0-21swapper/1209:43:014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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