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2026-05-19 - 11:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue May 19, 2026 01:02:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3691999200176,15cyclictest0-21swapper/300:35:1523
3691999200176,15cyclictest0-21swapper/300:35:1423
3696099195147,40cyclictest0-21swapper/3821:30:0332
3696099195147,40cyclictest0-21swapper/3821:30:0332
3696099195147,40cyclictest0-21swapper/3821:30:0232
3693899189168,7cyclictest4408-21CPU11
3693899189168,7cyclictest4408-21CPU11
3691999188168,9cyclictest0-21swapper/300:27:0023
3691999188168,9cyclictest0-21swapper/300:26:5923
3691999188168,9cyclictest0-21swapper/300:26:5923
3691999187159,14cyclictest0-21swapper/321:56:0823
3691999187159,14cyclictest0-21swapper/321:56:0723
3691999186169,12cyclictest0-21swapper/300:33:1723
3691999186169,12cyclictest0-21swapper/300:33:1623
3694999185180,3cyclictest38856-21kworker/u81:5+events_unbound23:07:4121
3694999185180,3cyclictest38856-21kworker/u81:5+events_unbound23:07:4121
3692399185161,8cyclictest0-21swapper/721:55:0037
3692399185161,8cyclictest0-21swapper/721:55:0037
3693899184173,9cyclictest0-21swapper/1921:56:1911
3693899184173,9cyclictest0-21swapper/1921:56:1811
3693899184157,18cyclictest3541-21CPU11
3693899184157,18cyclictest3541-21CPU11
3693899184157,18cyclictest3541-21CPU11
3695199183110,35cyclictest3609-21CPU24
3695199183110,35cyclictest3609-21CPU24
3691999183168,13cyclictest0-21swapper/300:22:5123
3691999183168,13cyclictest0-21swapper/300:22:5123
3692699182162,11cyclictest0-21swapper/1021:57:212
3692699182162,11cyclictest0-21swapper/1021:57:202
3695899181128,25cyclictest0-21swapper/3623:12:1030
3695899181128,25cyclictest0-21swapper/3623:12:1030
3692399181153,22cyclictest0-21swapper/722:48:3937
3692399181153,22cyclictest0-21swapper/722:48:3937
3691999181169,9cyclictest1367-21dbus-daemon00:19:3323
3691999181169,9cyclictest1367-21dbus-daemon00:19:3323
3695899180109,41cyclictest3609-21CPU30
3695899180109,41cyclictest3609-21CPU30
3693899180172,6cyclictest0-21swapper/1921:45:2611
3693899180172,6cyclictest0-21swapper/1921:45:2511
3692399180154,15cyclictest0-21swapper/721:20:4237
3692399180154,15cyclictest0-21swapper/721:20:4237
3695699179147,23cyclictest0-21swapper/3421:58:5828
3695699179147,23cyclictest0-21swapper/3421:58:5728
3695699179138,35cyclictest0-21swapper/3422:44:4228
3695699179138,35cyclictest0-21swapper/3422:44:4228
3691999179144,18cyclictest0-21swapper/321:21:4523
3691999179144,18cyclictest0-21swapper/321:21:4423
3696099178101,72cyclictest0-21swapper/3821:37:3232
3696099178101,72cyclictest0-21swapper/3821:37:3232
3695699178160,15cyclictest0-21swapper/3422:17:3828
3695699178160,15cyclictest0-21swapper/3422:17:3828
3693899178165,7cyclictest6456-21systemd23:11:1811
3693899178165,7cyclictest6456-21systemd23:11:1711
3694999177152,14cyclictest2454-21CPU21
3694999177152,14cyclictest2454-21CPU21
3693799177134,34cyclictest0-21swapper/1800:26:4110
3693799177134,34cyclictest0-21swapper/1800:26:4010
3693799177134,34cyclictest0-21swapper/1800:26:4010
3691899177152,7cyclictest0-21swapper/221:59:3012
3691899177152,7cyclictest0-21swapper/221:59:3012
3695899176116,43cyclictest0-21swapper/3623:41:4230
3695899176116,43cyclictest0-21swapper/3623:41:4230
3692999176120,26cyclictest0-21swapper/1222:32:584
3692999176120,26cyclictest0-21swapper/1222:32:584
3695699175144,26cyclictest3150-21sshd22:55:4128
3695699175144,26cyclictest3150-21sshd22:55:4128
3695099175134,23cyclictest0-21swapper/2919:21:0422
3695099175134,23cyclictest0-21swapper/2919:21:0422
3693899175146,12cyclictest0-21swapper/1922:40:1711
3693899175146,12cyclictest0-21swapper/1922:40:1611
3691899175164,3cyclictest0-21swapper/200:21:2912
3691899175164,3cyclictest0-21swapper/200:21:2912
369609917492,72cyclictest3541-21CPU32
369609917492,72cyclictest3541-21CPU32
3696099174142,27cyclictest0-21swapper/3823:05:3032
3696099174142,27cyclictest0-21swapper/3823:05:3032
3695099174112,44cyclictest37354-21CPU22
3695099174112,44cyclictest37354-21CPU22
369379917490,77cyclictest0-21swapper/1800:39:2410
369379917490,77cyclictest0-21swapper/1800:39:2310
3693799174133,32cyclictest0-21swapper/1823:24:3410
3693799174133,32cyclictest0-21swapper/1823:24:3410
369359917434,111cyclictest3542-21CPU9
369359917434,111cyclictest3542-21CPU9
3695899173163,8cyclictest0-21swapper/3622:48:4030
3695899173163,8cyclictest0-21swapper/3622:48:3930
3695099173164,2cyclictest0-21swapper/2900:12:5722
3695099173164,2cyclictest0-21swapper/2900:12:5622
3695099173164,2cyclictest0-21swapper/2900:12:5622
3694699173142,14cyclictest0-21swapper/2523:46:1718
3694699173142,14cyclictest0-21swapper/2523:46:1618
3696099172123,31cyclictest0-21swapper/3821:46:4632
3696099172123,31cyclictest0-21swapper/3821:46:4632
3695899172114,46cyclictest3609-21CPU30
3695899172114,46cyclictest3609-21CPU30
3695899172114,46cyclictest3609-21CPU30
3695899172103,58cyclictest37264-21CPU30
3695899172103,58cyclictest37264-21CPU30
3695099172154,13cyclictest2461-21CPU22
3695099172154,13cyclictest2461-21CPU22
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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