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2026-03-07 - 07:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri Mar 06, 2026 13:03:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3611799209204,4cyclictest0-21swapper/3111:14:3725
3611799209204,4cyclictest0-21swapper/3111:14:3725
3608199204190,11cyclictest0-21swapper/007:45:140
3608199204190,11cyclictest0-21swapper/007:45:140
3608199202193,7cyclictest0-21swapper/008:00:200
3608199202193,7cyclictest0-21swapper/008:00:200
3611799201196,4cyclictest0-21swapper/3108:17:3025
3611799201196,4cyclictest0-21swapper/3108:17:2925
3608199200194,4cyclictest0-21swapper/009:28:130
3608199200194,4cyclictest0-21swapper/009:28:130
3608199200194,4cyclictest0-21swapper/009:28:130
3608199200192,6cyclictest0-21swapper/009:11:230
3608199200192,6cyclictest0-21swapper/009:11:230
3608199200192,6cyclictest0-21swapper/009:11:230
3612099198188,8cyclictest0-21swapper/3412:36:5328
3612099198188,8cyclictest0-21swapper/3412:36:5328
3608199198189,7cyclictest0-21swapper/010:41:070
3608199198189,7cyclictest0-21swapper/010:41:070
3608199198189,7cyclictest0-21swapper/010:15:010
3608199198189,7cyclictest0-21swapper/010:15:010
3608199198189,7cyclictest0-21swapper/010:15:010
3608199198184,11cyclictest0-21swapper/008:40:010
3608199198184,11cyclictest0-21swapper/008:40:010
3608199197191,4cyclictest0-21swapper/010:47:220
3608199197191,4cyclictest0-21swapper/010:47:210
3612399196137,52cyclictest4407-21CPU31
3612399196137,52cyclictest4407-21CPU31
3608199196185,8cyclictest0-21swapper/010:51:570
3608199196185,8cyclictest0-21swapper/010:51:570
3608199196185,8cyclictest0-21swapper/010:51:570
3611799195180,12cyclictest0-21swapper/3111:05:5025
3611799195180,12cyclictest0-21swapper/3111:05:5025
3608199194185,6cyclictest3535-21qemu-system-x8610:20:110
3608199194185,6cyclictest3535-21qemu-system-x8610:20:110
3608199194185,6cyclictest3535-21qemu-system-x8610:20:110
3608199194184,8cyclictest0-21swapper/012:39:560
3608199194184,8cyclictest0-21swapper/012:39:560
3611799193186,5cyclictest0-21swapper/3111:00:3125
3611799193186,5cyclictest0-21swapper/3111:00:3125
3608199193185,5cyclictest37257-21qemu-system-x8610:31:570
3608199193185,5cyclictest37257-21qemu-system-x8610:31:570
3608199193184,7cyclictest0-21swapper/010:36:410
3608199193184,7cyclictest0-21swapper/010:36:410
3608199193184,7cyclictest0-21swapper/010:36:410
3608199192184,6cyclictest0-21swapper/009:18:180
3608199192184,6cyclictest0-21swapper/009:18:180
3612699190126,60cyclictest28534-21lxd08:35:1833
3612699190126,60cyclictest28534-21lxd08:35:1833
3608199190183,5cyclictest0-21swapper/010:19:150
3608199190183,5cyclictest0-21swapper/010:19:150
3608199190182,5cyclictest0-21swapper/009:55:330
3608199190182,5cyclictest0-21swapper/009:55:330
3608199190182,5cyclictest0-21swapper/009:55:330
3608199190178,10cyclictest17026-21run-parts12:23:050
3608199190178,10cyclictest17026-21run-parts12:23:050
3608199190178,10cyclictest17026-21run-parts12:23:050
3610199189178,9cyclictest0-21swapper/1711:48:319
3610199189178,9cyclictest0-21swapper/1711:48:319
3608199189183,4cyclictest0-21swapper/007:30:010
3608199189183,4cyclictest0-21swapper/007:30:010
3608199189183,4cyclictest0-21swapper/007:30:010
3608199189182,5cyclictest0-21swapper/009:23:240
3608199189182,5cyclictest0-21swapper/009:23:230
3608199189182,5cyclictest0-21swapper/009:23:230
3608199189181,5cyclictest0-21swapper/012:29:120
3608199189181,5cyclictest0-21swapper/012:29:120
3608199189181,5cyclictest0-21swapper/012:29:120
3608199189157,26cyclictest0-21swapper/009:36:030
3608199189157,26cyclictest0-21swapper/009:36:030
3608199189157,26cyclictest0-21swapper/009:36:030
3612099188182,5cyclictest0-21swapper/3410:06:1028
3612099188182,5cyclictest0-21swapper/3410:06:1028
3608199188182,4cyclictest0-21swapper/010:26:570
3608199188182,4cyclictest0-21swapper/010:26:570
3611799187182,4cyclictest0-21swapper/3110:56:0225
3611799187182,4cyclictest0-21swapper/3110:56:0225
3610199187174,11cyclictest0-21swapper/1710:22:059
3610199187174,11cyclictest0-21swapper/1710:22:059
3610199187174,11cyclictest0-21swapper/1710:22:059
3611999186175,5cyclictest0-21swapper/3312:22:0627
3611999186175,5cyclictest0-21swapper/3312:22:0627
3611999186175,5cyclictest0-21swapper/3312:22:0627
3608199186121,35cyclictest2447-21CPU0
3608199186121,35cyclictest2447-21CPU0
3608199186121,35cyclictest2447-21CPU0
3611799184179,3cyclictest0-21swapper/3111:21:3225
3611799184179,3cyclictest0-21swapper/3111:21:3225
3611799184156,6cyclictest171rcu_preempt11:18:2225
3611799184156,6cyclictest171rcu_preempt11:18:2225
3611799184156,6cyclictest171rcu_preempt11:18:2225
3608199184178,5cyclictest0-21swapper/007:32:110
3608199184178,5cyclictest0-21swapper/007:32:110
3608199184177,5cyclictest0-21swapper/007:17:020
3608199184177,5cyclictest0-21swapper/007:17:020
3608199184175,7cyclictest0-21swapper/007:21:250
3608199184175,7cyclictest0-21swapper/007:21:250
3611899183139,32cyclictest3535-21qemu-system-x8610:42:3226
3611899183139,32cyclictest3535-21qemu-system-x8610:42:3226
3611799183174,4cyclictest3546-21CPU25
3611799183174,4cyclictest3546-21CPU25
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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