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2026-01-24 - 06:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Jan 24, 2026 01:00:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3120599226221,3cyclictest0-21swapper/3521:05:1729
3120599226221,3cyclictest0-21swapper/3521:05:1729
3117299226216,8cyclictest25684-21cat23:40:0238
3117299226216,8cyclictest25684-21cat23:40:0238
3117299226216,8cyclictest25684-21cat23:40:0238
3117299221206,11cyclictest0-21swapper/822:04:4438
3117299221206,11cyclictest0-21swapper/822:04:4438
3119699220205,11cyclictest1367-21dbus-daemon23:37:0422
3119699220205,11cyclictest1367-21dbus-daemon23:37:0422
3119699220205,11cyclictest1367-21dbus-daemon23:37:0422
3117399215208,5cyclictest0-21swapper/900:26:2639
3117399215208,5cyclictest0-21swapper/900:26:2639
3117399215208,5cyclictest0-21swapper/900:26:2639
3119699214208,4cyclictest0-21swapper/2920:54:4522
3119699213205,6cyclictest21515-21systemctl00:03:2522
3119699213205,6cyclictest21515-21systemctl00:03:2522
3116499213204,7cyclictest0-21swapper/100:00:161
3116499213204,7cyclictest0-21swapper/100:00:161
3119699211206,4cyclictest0-21swapper/2922:18:2622
3119699211206,4cyclictest0-21swapper/2922:18:2522
3116799211178,14cyclictest0-21swapper/422:43:3534
3116799211178,14cyclictest0-21swapper/422:43:3534
3116499211204,6cyclictest0-21swapper/121:28:271
3116499211204,6cyclictest0-21swapper/121:28:261
3116499211204,6cyclictest0-21swapper/121:28:261
3117299210204,4cyclictest17482-21nfsd22:00:0838
3117299210185,7cyclictest0-21swapper/822:17:0638
3117299210185,7cyclictest0-21swapper/822:17:0638
3120899209199,5cyclictest37268-21CPU32
3120899209199,5cyclictest37268-21CPU32
3117399209202,5cyclictest0-21swapper/900:01:0239
3117399209202,5cyclictest0-21swapper/900:01:0239
3117099209182,11cyclictest0-21swapper/622:12:0536
3117099209182,11cyclictest0-21swapper/622:12:0536
3116499209200,7cyclictest0-21swapper/100:10:181
3116499209200,7cyclictest0-21swapper/100:10:181
3116499208204,2cyclictest3848-21sshd00:09:471
3116499208204,2cyclictest3848-21sshd00:09:471
3116499207199,7cyclictest0-21swapper/122:34:511
3116499207199,7cyclictest0-21swapper/122:34:511
3116499207197,8cyclictest0-21swapper/121:30:561
3116499207197,8cyclictest0-21swapper/121:30:561
3116499207197,8cyclictest0-21swapper/121:30:561
3116499207195,9cyclictest0-21swapper/122:16:061
3116499207195,9cyclictest0-21swapper/122:16:051
3116499207195,10cyclictest0-21swapper/122:12:451
3116499207195,10cyclictest0-21swapper/122:12:451
3119699206197,5cyclictest4407-21CPU22
3119699206197,5cyclictest4407-21CPU22
3117299206198,3cyclictest3544-21CPU38
3117299206198,3cyclictest3544-21CPU38
3117299206192,12cyclictest0-21swapper/819:40:2038
3117299206192,12cyclictest0-21swapper/819:40:2038
3116799206196,4cyclictest0-21swapper/422:39:5634
3116799206196,4cyclictest0-21swapper/422:39:5634
3116499206198,6cyclictest0-21swapper/121:36:271
3116499206198,6cyclictest0-21swapper/121:36:271
3119599205196,7cyclictest0-21swapper/2800:22:1721
3119599205196,7cyclictest0-21swapper/2800:22:1721
3117299205198,5cyclictest0-21swapper/800:13:4738
3117299205198,5cyclictest0-21swapper/800:13:4738
3116499205199,5cyclictest0-21swapper/123:59:491
3116499205199,5cyclictest0-21swapper/123:59:491
3119699204199,4cyclictest0-21swapper/2922:20:2722
3119699204199,4cyclictest0-21swapper/2922:20:2722
3117699204197,5cyclictest0-21swapper/1221:05:134
3117699204197,5cyclictest0-21swapper/1221:05:134
3117399204199,4cyclictest0-21swapper/919:29:2739
3117399204199,4cyclictest0-21swapper/919:29:2739
3116499204199,4cyclictest0-21swapper/123:48:581
3116499204199,4cyclictest0-21swapper/123:48:581
3119699203196,3cyclictest37270-21CPU22
3119699203196,3cyclictest37270-21CPU22
3119699202196,4cyclictest0-21swapper/2920:40:1022
3119699202196,4cyclictest0-21swapper/2920:40:1022
3116799202193,8cyclictest0-21swapper/423:38:5134
3116799202193,8cyclictest0-21swapper/423:38:5134
3116799202193,8cyclictest0-21swapper/423:38:5134
3119699201193,5cyclictest0-21swapper/2922:27:0722
3119699201193,5cyclictest0-21swapper/2922:27:0722
3117299201195,4cyclictest0-21swapper/821:58:5338
3117099201195,4cyclictest0-21swapper/619:25:1536
3117099201195,4cyclictest0-21swapper/619:25:1536
3117099201190,9cyclictest0-21swapper/620:51:3336
3119699200195,4cyclictest0-21swapper/2923:32:4422
3119699200195,4cyclictest0-21swapper/2923:32:4422
3116499200195,4cyclictest0-21swapper/120:30:241
3116499200195,4cyclictest0-21swapper/120:30:241
3119699199193,4cyclictest0-21swapper/2921:48:4622
3119699199193,4cyclictest0-21swapper/2921:48:4622
3119699199193,4cyclictest0-21swapper/2921:48:4522
3119699199193,4cyclictest0-21swapper/2919:26:2522
3119699199193,4cyclictest0-21swapper/2919:26:2522
3119699199190,5cyclictest2462-21CPU22
3119699199190,5cyclictest2462-21CPU22
3119699199190,5cyclictest2462-21CPU22
3119299199190,7cyclictest0-21swapper/2622:37:2919
3119299199190,7cyclictest0-21swapper/2622:37:2919
3116399199193,4cyclictest2454-21CPU0
3116399199193,4cyclictest2454-21CPU0
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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