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2026-01-14 - 11:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Jan 14, 2026 01:01:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2865199200192,5cyclictest37257-21qemu-system-x8621:13:0413
2865199200192,5cyclictest37257-21qemu-system-x8621:13:0413
2863299199193,4cyclictest0-21swapper/421:49:2434
2863299199193,4cyclictest0-21swapper/421:49:2434
2864199198151,34cyclictest0-21swapper/1222:17:524
2864199198151,34cyclictest0-21swapper/1222:17:524
2864199198151,34cyclictest0-21swapper/1222:17:524
2863299194178,7cyclictest0-21swapper/421:50:2034
2863299194178,7cyclictest0-21swapper/421:50:2034
2863299194178,7cyclictest0-21swapper/421:50:2034
2865899192171,12cyclictest0-21swapper/2723:25:0820
2865099191176,6cyclictest171rcu_preempt23:54:5911
2865099191176,6cyclictest171rcu_preempt23:54:5911
2865099191176,6cyclictest171rcu_preempt23:54:5911
2863299191154,6cyclictest171rcu_preempt22:29:1434
2863299191154,6cyclictest171rcu_preempt22:29:1434
2863299191154,6cyclictest171rcu_preempt22:29:1434
2865199190183,4cyclictest0-21swapper/2021:15:4213
2865199190183,4cyclictest0-21swapper/2021:15:4213
2865199190183,4cyclictest0-21swapper/2021:15:4213
2863099190166,13cyclictest0-21swapper/221:30:5512
2863099190166,13cyclictest0-21swapper/221:30:5512
2863099190166,13cyclictest0-21swapper/221:30:5512
2863399189182,5cyclictest0-21swapper/523:08:3435
2863399189182,5cyclictest0-21swapper/523:08:3435
2863399189182,5cyclictest0-21swapper/523:08:3435
2865199188179,7cyclictest10465-21sshd23:43:1313
2865199188179,7cyclictest10465-21sshd23:43:1313
2865199185157,9cyclictest171rcu_preempt00:07:0713
2865199185157,9cyclictest171rcu_preempt00:07:0713
2865899182169,10cyclictest0-21swapper/2721:56:1420
2865899182169,10cyclictest0-21swapper/2721:56:1420
2865799182154,24cyclictest0-21swapper/2621:17:4119
2865799182154,24cyclictest0-21swapper/2621:17:4119
2865799182154,24cyclictest0-21swapper/2621:17:4119
2866599181173,6cyclictest1367-21dbus-daemon23:38:0127
2866599181173,6cyclictest1367-21dbus-daemon23:38:0127
2863399181166,14cyclictest0-21swapper/523:14:2635
2863399181166,14cyclictest0-21swapper/523:14:2635
2863399181166,14cyclictest0-21swapper/523:14:2635
2865899180172,4cyclictest0-21swapper/2719:45:1620
2865899180172,4cyclictest0-21swapper/2719:45:1620
286739917817,155cyclictest0-21swapper/3821:49:4232
286739917817,155cyclictest0-21swapper/3821:49:4232
2864199178121,54cyclictest0-21swapper/1222:24:144
2864199178121,54cyclictest0-21swapper/1222:24:144
2863299178162,10cyclictest0-21swapper/422:16:0634
2863299178162,10cyclictest0-21swapper/422:16:0634
2863299178162,10cyclictest0-21swapper/422:16:0634
2865199177158,8cyclictest0-21swapper/2019:40:2613
2865199177158,8cyclictest0-21swapper/2019:40:2613
2865099177112,52cyclictest37267-21CPU11
2865099177112,52cyclictest37267-21CPU11
2865099177112,52cyclictest37267-21CPU11
2865199176162,8cyclictest0-21swapper/2022:38:5113
2865199176162,8cyclictest0-21swapper/2022:38:5113
2865199176162,8cyclictest0-21swapper/2022:38:5113
2865099175140,18cyclictest0-21swapper/1922:39:5511
2865099175140,18cyclictest0-21swapper/1922:39:5511
2865099175140,18cyclictest0-21swapper/1922:39:5511
2864199174134,37cyclictest0-21swapper/1223:31:154
2864199174134,37cyclictest0-21swapper/1223:31:154
2865899172141,16cyclictest0-21swapper/2700:31:1320
2865899172141,16cyclictest0-21swapper/2700:31:1320
2865199172160,10cyclictest0-21swapper/2023:48:3113
2865199172160,10cyclictest0-21swapper/2023:48:3113
2863399172156,4cyclictest0-21swapper/519:50:2935
2863399172156,4cyclictest0-21swapper/519:50:2935
2865199171147,10cyclictest171rcu_preempt21:32:3913
2865199171147,10cyclictest171rcu_preempt21:32:3913
2865199171147,10cyclictest171rcu_preempt21:32:3913
2865199171121,22cyclictest0-21swapper/2022:51:3513
2865199171121,22cyclictest0-21swapper/2022:51:3513
2863299171133,20cyclictest0-21swapper/421:16:2034
2863299171133,20cyclictest0-21swapper/421:16:2034
2863299171133,20cyclictest0-21swapper/421:16:2034
2863299171120,26cyclictest0-21swapper/400:08:4734
2863299171120,26cyclictest0-21swapper/400:08:4734
2865899170152,7cyclictest0-21swapper/2722:57:5820
2865899170152,7cyclictest0-21swapper/2722:57:5820
2865199170155,7cyclictest0-21swapper/2021:53:2913
2865199170155,7cyclictest0-21swapper/2021:53:2913
2865199170155,7cyclictest0-21swapper/2021:53:2913
2864199170147,21cyclictest0-21swapper/1200:03:534
2864199170147,21cyclictest0-21swapper/1200:03:534
2864199170146,20cyclictest0-21swapper/1221:53:194
2864199170146,20cyclictest0-21swapper/1221:53:184
2864199170146,20cyclictest0-21swapper/1221:53:184
2863299170130,19cyclictest0-21swapper/423:03:5634
2863299170130,19cyclictest0-21swapper/423:03:5634
2863299170130,19cyclictest0-21swapper/423:03:5634
2863399169142,14cyclictest171rcu_preempt22:53:0635
2863399169142,14cyclictest171rcu_preempt22:53:0635
2863299169159,9cyclictest0-21swapper/400:33:2834
2863299169159,9cyclictest0-21swapper/400:33:2734
2864199168135,26cyclictest0-21swapper/1221:57:254
2864199168135,26cyclictest0-21swapper/1221:57:244
2864199168130,31cyclictest0-21swapper/1223:15:304
2864199168130,31cyclictest0-21swapper/1223:15:304
2865199167162,4cyclictest0-21swapper/2019:21:4013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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