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2026-02-01 - 07:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Feb 01, 2026 01:00:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3069799242229,8cyclictest1382-21in:imuxsock23:29:1834
3069799242229,8cyclictest1382-21in:imuxsock23:29:1834
3069799242229,8cyclictest1382-21in:imuxsock23:29:1834
3069799241230,9cyclictest0-21swapper/421:16:3234
3069799241230,9cyclictest0-21swapper/421:16:3234
3069799241230,9cyclictest0-21swapper/421:16:3234
3069799241230,6cyclictest0-21swapper/423:01:4434
3069799241230,6cyclictest0-21swapper/423:01:4434
3069799240226,12cyclictest0-21swapper/422:26:2534
3069799240226,12cyclictest0-21swapper/422:26:2534
3069799239227,8cyclictest0-21swapper/421:25:1534
3069799239227,8cyclictest0-21swapper/421:25:1534
3069799237211,24cyclictest0-21swapper/422:50:1934
3069799237211,24cyclictest0-21swapper/422:50:1934
3069799237211,24cyclictest0-21swapper/422:50:1934
3069799231223,4cyclictest4408-21CPU34
3069799231223,4cyclictest4408-21CPU34
3069799231223,4cyclictest4408-21CPU34
3069799226220,4cyclictest0-21swapper/422:30:5434
3069799226220,4cyclictest0-21swapper/422:30:5434
3069799226217,7cyclictest0-21swapper/421:43:5534
3069799226217,7cyclictest0-21swapper/421:43:5534
3069799224219,4cyclictest0-21swapper/419:15:2334
3069799224219,4cyclictest0-21swapper/419:15:2234
3069799222216,4cyclictest0-21swapper/421:11:3734
3069799222216,4cyclictest0-21swapper/421:11:3734
3069799222216,4cyclictest0-21swapper/421:11:3734
3069799221205,9cyclictest0-21swapper/423:46:0834
3069799221205,9cyclictest0-21swapper/423:46:0834
3069799220211,7cyclictest0-21swapper/423:07:0834
3069799220211,7cyclictest0-21swapper/423:07:0834
3069799219212,4cyclictest0-21swapper/423:44:3034
3069799219212,4cyclictest0-21swapper/423:44:3034
3069799219212,4cyclictest0-21swapper/423:44:3034
3069799218202,14cyclictest0-21swapper/421:33:1834
3069799218202,14cyclictest0-21swapper/421:33:1834
3069799218202,14cyclictest0-21swapper/421:33:1834
3069799217196,15cyclictest37270-21CPU34
3069799217196,15cyclictest37270-21CPU34
3069799217174,30cyclictest0-21swapper/400:34:2534
3069799217174,30cyclictest0-21swapper/400:34:2534
3069799216194,19cyclictest0-21swapper/422:10:1434
3069799216194,19cyclictest0-21swapper/422:10:1434
3069799215201,12cyclictest22898-21sshd21:35:5134
3069799215201,12cyclictest22898-21sshd21:35:5134
3069799215201,12cyclictest22898-21sshd21:35:5134
3069799215200,10cyclictest0-21swapper/422:00:1534
3069799215200,10cyclictest0-21swapper/422:00:1534
3069799215200,10cyclictest0-21swapper/422:00:1534
3069799215191,15cyclictest0-21swapper/423:38:0034
3069799215191,15cyclictest0-21swapper/423:38:0034
3069799215191,15cyclictest0-21swapper/423:38:0034
3069799214208,4cyclictest0-21swapper/421:45:1634
3069799214208,4cyclictest0-21swapper/421:45:1634
3069799214203,7cyclictest0-21swapper/400:37:1034
3069799214203,7cyclictest0-21swapper/400:37:0934
3069799212195,10cyclictest0-21swapper/422:37:0034
3069799212195,10cyclictest0-21swapper/422:37:0034
3069799211198,9cyclictest0-21swapper/421:05:1434
3069799211198,9cyclictest0-21swapper/421:05:1434
3069799211198,9cyclictest0-21swapper/421:05:1434
3069799210201,7cyclictest0-21swapper/422:46:3934
3069799210201,7cyclictest0-21swapper/422:46:3934
3069799210198,8cyclictest0-21swapper/423:15:1934
3069799210198,8cyclictest0-21swapper/423:15:1934
3069799210192,11cyclictest3535-21qemu-system-x8600:23:5134
3069799210192,11cyclictest3535-21qemu-system-x8600:23:5134
3069799210187,13cyclictest4398-21qemu-system-x8622:23:5534
3069799210187,13cyclictest4398-21qemu-system-x8622:23:5534
3069799210187,13cyclictest4398-21qemu-system-x8622:23:5534
3069799209189,18cyclictest0-21swapper/422:18:1434
3069799209189,18cyclictest0-21swapper/422:18:1434
3069799209189,18cyclictest0-21swapper/422:18:1434
3069799208196,7cyclictest0-21swapper/422:58:3234
3069799208196,7cyclictest0-21swapper/422:58:3134
3069799208196,7cyclictest0-21swapper/422:58:3134
3069799207196,9cyclictest0-21swapper/420:51:1434
3069799207196,9cyclictest0-21swapper/420:51:1434
3073099206174,24cyclictest0-21swapper/3223:32:4026
3073099206174,24cyclictest0-21swapper/3223:32:4026
3069799206196,8cyclictest0-21swapper/423:32:4134
3069799206196,8cyclictest0-21swapper/423:32:4134
3069799206194,8cyclictest0-21swapper/400:26:0434
3069799206194,8cyclictest0-21swapper/400:26:0434
3069799206194,8cyclictest0-21swapper/400:26:0434
3069799206193,10cyclictest0-21swapper/422:09:0034
3069799206193,10cyclictest0-21swapper/422:09:0034
3069799206190,14cyclictest0-21swapper/419:45:1634
3069799206190,14cyclictest0-21swapper/419:45:1634
3069799206183,13cyclictest0-21swapper/422:42:2334
3069799206183,13cyclictest0-21swapper/422:42:2334
3069799205192,10cyclictest0-21swapper/400:04:1634
3069799205192,10cyclictest0-21swapper/400:04:1634
3069799205192,10cyclictest0-21swapper/400:04:1634
3069799203193,8cyclictest0-21swapper/419:30:1634
3069799203193,8cyclictest0-21swapper/419:30:1534
3069799203190,11cyclictest0-21swapper/421:53:3634
3069799203190,11cyclictest0-21swapper/421:53:3634
3069799203190,11cyclictest0-21swapper/421:53:3634
3069799202196,4cyclictest0-21swapper/423:20:3034
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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