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2026-08-04 - 19:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Aug 04, 2026 13:02:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1026199250235,11cyclictest0-21swapper/3108:40:2525
1026199250235,11cyclictest0-21swapper/3108:40:2525
1026699239236,2cyclictest0-21swapper/3610:55:1930
1026699239236,2cyclictest0-21swapper/3610:55:1830
1026699239236,2cyclictest0-21swapper/3610:55:1830
1026199229226,2cyclictest0-21swapper/3109:12:4625
1026199229226,2cyclictest0-21swapper/3109:12:4525
1026299223209,6cyclictest0-21swapper/3212:04:1926
1026299223209,6cyclictest0-21swapper/3212:04:1926
1026299223209,6cyclictest0-21swapper/3212:04:1926
1022799211200,7cyclictest0-21swapper/409:15:0234
1022799211200,7cyclictest0-21swapper/409:15:0234
1026299209202,5cyclictest0-21swapper/3208:08:0326
1026299209202,5cyclictest0-21swapper/3208:08:0326
1025099207196,6cyclictest0-21swapper/2209:20:3615
1025099207196,6cyclictest0-21swapper/2209:20:3515
1025099207196,6cyclictest0-21swapper/2209:20:3515
1022699205195,8cyclictest0-21swapper/311:41:1423
1022699205195,8cyclictest0-21swapper/311:41:1423
1022699205195,8cyclictest0-21swapper/311:41:1423
1025799203192,8cyclictest0-21swapper/2808:40:1421
1025799203192,8cyclictest0-21swapper/2808:40:1421
1025499203186,7cyclictest171rcu_preempt10:50:5019
1025499203186,7cyclictest171rcu_preempt10:50:5019
1025099203197,4cyclictest0-21swapper/2209:33:2415
1025099203197,4cyclictest0-21swapper/2209:33:2315
1025499201189,10cyclictest0-21swapper/2612:28:3319
1025499201189,10cyclictest0-21swapper/2612:28:3219
1025499201183,8cyclictest0-21swapper/2609:53:5419
1025499201183,8cyclictest0-21swapper/2609:53:5419
1026199200127,62cyclictest37265-21CPU25
1026199200127,62cyclictest37265-21CPU25
1025799200185,8cyclictest3600-21qemu-system-x8611:00:4021
1025799200185,8cyclictest3600-21qemu-system-x8611:00:4021
1023199200181,7cyclictest0-21swapper/710:19:5337
1023199200181,7cyclictest0-21swapper/710:19:5337
1025099199188,8cyclictest0-21swapper/2209:40:0115
1025099199188,8cyclictest0-21swapper/2209:40:0115
1025099199187,10cyclictest0-21swapper/2210:41:5815
1025099199187,10cyclictest0-21swapper/2210:41:5815
1026199198186,5cyclictest0-21swapper/3109:49:4025
1026199198186,5cyclictest0-21swapper/3109:49:3925
1026199198186,5cyclictest0-21swapper/3109:49:3925
1025999197185,10cyclictest0-21swapper/2910:05:2022
1025999197185,10cyclictest0-21swapper/2910:05:2022
1025999197185,10cyclictest0-21swapper/2910:05:2022
1023199197181,6cyclictest0-21swapper/710:49:2737
1023199197181,6cyclictest0-21swapper/710:49:2737
1025999196187,7cyclictest0-21swapper/2910:47:0022
1025999196187,7cyclictest0-21swapper/2910:47:0022
1025099195180,12cyclictest0-21swapper/2209:40:1715
1025099195180,12cyclictest0-21swapper/2209:40:1715
1022399195187,2cyclictest2851-21sshd11:29:091
1022399195187,2cyclictest2851-21sshd11:29:091
1022399195187,2cyclictest2851-21sshd11:29:091
1025999194189,4cyclictest0-21swapper/2909:49:1322
1025999194189,4cyclictest0-21swapper/2909:49:1222
1025999194189,4cyclictest0-21swapper/2909:49:1222
1025799194187,4cyclictest0-21swapper/2808:50:1221
1025799194187,4cyclictest0-21swapper/2808:50:1221
1025099194187,4cyclictest0-21swapper/2209:25:2315
1025099194187,4cyclictest0-21swapper/2209:25:2215
1025099194187,4cyclictest0-21swapper/2209:25:2215
1025099194183,9cyclictest0-21swapper/2209:49:2115
1025099194183,9cyclictest0-21swapper/2209:49:2015
1025099194183,9cyclictest0-21swapper/2209:49:2015
1026299193181,6cyclictest171rcu_preempt11:54:3526
1026299193181,6cyclictest171rcu_preempt11:54:3526
1025999193186,5cyclictest0-21swapper/2910:10:1922
1025999193186,5cyclictest0-21swapper/2910:10:1822
1025999193182,9cyclictest0-21swapper/2911:56:0622
1025999193182,9cyclictest0-21swapper/2911:56:0622
1025999193177,8cyclictest0-21swapper/2909:50:3422
1025999193177,8cyclictest0-21swapper/2909:50:3422
1025299193186,5cyclictest372-21kswapd007:20:0417
1025299193186,5cyclictest372-21kswapd007:20:0317
1025999192185,3cyclictest3542-21CPU22
1025999192185,3cyclictest3542-21CPU22
1025099192186,5cyclictest0-21swapper/2209:10:3915
1025099192186,5cyclictest0-21swapper/2209:10:3815
1025999191182,5cyclictest3546-21CPU22
1025999191182,5cyclictest3546-21CPU22
1025799191185,4cyclictest0-21swapper/2808:47:2521
1025799191185,4cyclictest0-21swapper/2808:47:2521
1023199191151,28cyclictest0-21swapper/711:22:2937
1023199191151,28cyclictest0-21swapper/711:22:2837
1026699190186,2cyclictest0-21swapper/3611:00:5130
1026699190186,2cyclictest0-21swapper/3611:00:5130
1026199190175,8cyclictest171rcu_preempt10:05:3025
1026199190175,8cyclictest171rcu_preempt10:05:2925
1026199190175,8cyclictest171rcu_preempt10:05:2925
1025999190183,5cyclictest0-21swapper/2908:10:0322
1025999190183,5cyclictest0-21swapper/2908:10:0322
1025799190185,4cyclictest0-21swapper/2808:34:5021
1025099190178,9cyclictest0-21swapper/2209:15:2915
1025099190178,9cyclictest0-21swapper/2209:15:2915
1025099190178,9cyclictest0-21swapper/2209:15:2915
1026999189179,6cyclictest0-21swapper/3910:33:4133
1026999189179,6cyclictest0-21swapper/3910:33:4033
1026999189179,6cyclictest0-21swapper/3910:33:4033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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