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2026-05-08 - 15:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri May 08, 2026 13:02:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3624499224216,5cyclictest0-21swapper/2910:00:0022
3624499224216,5cyclictest0-21swapper/2910:00:0022
3623599216212,2cyclictest0-21swapper/2009:35:2813
3623599216212,2cyclictest0-21swapper/2009:35:2813
3621499206193,9cyclictest0-21swapper/310:53:2223
3621499206193,9cyclictest0-21swapper/310:53:2123
3621499206193,9cyclictest0-21swapper/310:53:2123
3621499205189,10cyclictest0-21swapper/310:24:5223
3621499205189,10cyclictest0-21swapper/310:24:5223
3623199204148,53cyclictest37270-21CPU10
3623199204148,53cyclictest37270-21CPU10
3623199204148,53cyclictest37270-21CPU10
3624499203197,2cyclictest0-21swapper/2912:20:1622
3624499203197,2cyclictest0-21swapper/2912:20:1522
3621499203165,9cyclictest0-21swapper/310:41:4123
3621499203165,9cyclictest0-21swapper/310:41:4123
3621499202175,22cyclictest0-21swapper/310:13:0823
3621499202175,22cyclictest0-21swapper/310:13:0723
36258992011,193cyclictest0-21swapper/3909:35:0133
36258992011,193cyclictest0-21swapper/3909:35:0133
3624399200167,18cyclictest0-21swapper/2809:00:0521
3624399200167,18cyclictest0-21swapper/2809:00:0521
3624199200193,5cyclictest0-21swapper/2608:00:1819
3624199200193,5cyclictest0-21swapper/2608:00:1719
3624199200193,5cyclictest0-21swapper/2608:00:1719
3621499198186,10cyclictest0-21swapper/311:21:0123
3621499198186,10cyclictest0-21swapper/311:21:0123
3624099197192,3cyclictest0-21swapper/2509:48:3318
3624099197192,3cyclictest0-21swapper/2509:48:3318
3624399196186,7cyclictest0-21swapper/2812:04:0821
3624399196186,7cyclictest0-21swapper/2812:04:0821
3624199195187,4cyclictest37269-21CPU19
3624199195187,4cyclictest37269-21CPU19
3624399194181,11cyclictest0-21swapper/2810:50:5721
3624399194181,11cyclictest0-21swapper/2810:50:5721
3624399194181,11cyclictest0-21swapper/2810:50:5621
3621699194173,16cyclictest0-21swapper/511:32:2235
3621699194173,16cyclictest0-21swapper/511:32:2135
3621699194173,16cyclictest0-21swapper/511:32:2135
3621499194179,13cyclictest0-21swapper/311:56:4423
3621499194179,13cyclictest0-21swapper/311:56:4423
3621499194179,13cyclictest0-21swapper/311:56:4323
3622199193156,35cyclictest2462-21CPU2
3622199193156,35cyclictest2462-21CPU2
3625199192177,5cyclictest171rcu_preempt10:35:3028
3625199192177,5cyclictest171rcu_preempt10:35:3028
3625199192177,5cyclictest171rcu_preempt10:35:2928
3624399192182,8cyclictest0-21swapper/2812:25:3421
3624399192182,8cyclictest0-21swapper/2812:25:3421
3624399192182,8cyclictest0-21swapper/2812:25:3321
362569919135,106cyclictest0-21swapper/3812:25:1832
362569919135,106cyclictest0-21swapper/3812:25:1832
362569919135,106cyclictest0-21swapper/3812:25:1732
3624499191183,6cyclictest2327-21qemu-system-x8611:44:2922
3624499191183,6cyclictest2327-21qemu-system-x8611:44:2922
3624499191183,6cyclictest2327-21qemu-system-x8611:44:2822
3624399191153,29cyclictest2464-21CPU21
3624399191153,29cyclictest2464-21CPU21
3624399191153,29cyclictest2464-21CPU21
3624199191176,11cyclictest142650irq/48-eno1-TxRx-607:50:1819
3624199191176,11cyclictest142650irq/48-eno1-TxRx-607:50:1819
3621499191174,6cyclictest171rcu_preempt12:32:4623
3621499191174,6cyclictest171rcu_preempt12:32:4523
3621399191186,2cyclictest0-21swapper/212:10:1312
3621399191186,2cyclictest0-21swapper/212:10:1212
3624399190176,12cyclictest0-21swapper/2807:20:3021
3624399190176,11cyclictest0-21swapper/2811:34:5321
3624399190176,11cyclictest0-21swapper/2811:34:5321
3624399190176,11cyclictest0-21swapper/2811:34:5321
36221991891,2cyclictest0-21swapper/1008:50:132
36221991891,2cyclictest0-21swapper/1008:50:132
3621499189183,3cyclictest0-21swapper/311:29:3523
3621499189183,3cyclictest0-21swapper/311:29:3523
3621499189183,3cyclictest0-21swapper/311:29:3523
362529918890,90cyclictest2459-21CPU29
362529918890,90cyclictest2459-21CPU29
3623399188133,50cyclictest3609-21CPU11
3623399188133,50cyclictest3609-21CPU11
3621599188169,15cyclictest0-21swapper/411:42:5934
3621599188169,15cyclictest0-21swapper/411:42:5834
3621599188169,15cyclictest0-21swapper/411:42:5834
3624499187179,5cyclictest30038-21sshd12:19:3922
3624499187179,5cyclictest30038-21sshd12:19:3822
3624499187179,5cyclictest30038-21sshd12:19:3822
3624499187177,7cyclictest0-21swapper/2910:05:1222
3624499187177,7cyclictest0-21swapper/2910:05:1222
3624499187177,7cyclictest0-21swapper/2910:05:1222
3624499187177,5cyclictest0-21swapper/2907:20:0422
3624499187177,5cyclictest0-21swapper/2907:20:0322
3622099187177,8cyclictest0-21swapper/912:08:0539
3622099187177,8cyclictest0-21swapper/912:08:0439
3621699187159,24cyclictest0-21swapper/509:25:0035
3621699187159,24cyclictest0-21swapper/509:25:0035
3621699187159,24cyclictest0-21swapper/509:25:0035
3625199186165,9cyclictest171rcu_preempt12:22:5228
3625199186165,9cyclictest171rcu_preempt12:22:5128
3625199186159,23cyclictest3545-21CPU28
3625199186159,23cyclictest3545-21CPU28
36258991851,94cyclictest0-21swapper/3912:15:1533
36258991851,94cyclictest0-21swapper/3912:15:1433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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