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2025-12-18 - 00:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Dec 17, 2025 13:01:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
366199921518,175cyclictest0-21swapper/710:55:1537
366199921518,175cyclictest0-21swapper/710:55:1437
3661399213161,41cyclictest0-21swapper/110:58:181
3661399213161,41cyclictest0-21swapper/110:58:181
3663999207203,2cyclictest0-21swapper/2311:05:1216
3663999207203,2cyclictest0-21swapper/2311:05:1216
3663999207203,2cyclictest0-21swapper/2311:05:1216
3664099201178,21cyclictest0-21swapper/2407:22:5817
3664099195182,6cyclictest2462-21CPU17
3664099195182,6cyclictest2462-21CPU17
3664099194186,5cyclictest0-21swapper/2407:18:4617
3664099194186,5cyclictest0-21swapper/2407:18:4617
3664099190178,6cyclictest0-21swapper/2407:40:1617
3664099190178,6cyclictest0-21swapper/2407:40:1517
3664099184175,5cyclictest3610-21CPU17
3664099184175,5cyclictest3610-21CPU17
3661399181165,12cyclictest0-21swapper/111:06:041
3661399181165,12cyclictest0-21swapper/111:06:031
3661399181165,12cyclictest0-21swapper/111:06:031
3663499179166,10cyclictest0-21swapper/1810:30:4910
3663499179166,10cyclictest0-21swapper/1810:30:4910
3663499179166,10cyclictest0-21swapper/1810:30:4910
3665699178153,9cyclictest0-21swapper/3709:54:0431
3665699178153,9cyclictest0-21swapper/3709:54:0331
3665499178143,24cyclictest0-21swapper/3609:20:1130
3665499178143,24cyclictest0-21swapper/3609:20:1030
3665499178143,24cyclictest0-21swapper/3609:20:1030
36614991789,153cyclictest2447-21CPU12
36614991789,153cyclictest2447-21CPU12
3664099177170,5cyclictest0-21swapper/2407:10:0417
36645991761,77cyclictest0-21swapper/2809:55:1621
36645991761,77cyclictest0-21swapper/2809:55:1621
36645991761,77cyclictest0-21swapper/2809:55:1621
3664799175143,24cyclictest4407-21CPU24
3664799175143,24cyclictest4407-21CPU24
3664799175143,24cyclictest4407-21CPU24
3661999175104,63cyclictest2464-21CPU37
3661999175104,63cyclictest2464-21CPU37
3661999175104,63cyclictest2464-21CPU37
3665699173147,12cyclictest0-21swapper/3707:15:3731
3665699173147,12cyclictest0-21swapper/3707:15:3631
366459917216,141cyclictest1430-21polkitd12:15:1921
366459917216,141cyclictest1430-21polkitd12:15:1921
366459917216,141cyclictest1430-21polkitd12:15:1821
3664099172167,4cyclictest0-21swapper/2407:30:4317
3664099172167,4cyclictest0-21swapper/2407:30:4317
3665899171144,20cyclictest0-21swapper/3911:45:1733
3665899171144,20cyclictest0-21swapper/3911:45:1733
3663399171168,2cyclictest0-21swapper/1709:55:139
3663399171168,2cyclictest0-21swapper/1709:55:139
3663399171168,2cyclictest0-21swapper/1709:55:139
3663499170147,9cyclictest0-21swapper/1809:29:2010
3663499170147,9cyclictest0-21swapper/1809:29:1910
3664099169163,4cyclictest0-21swapper/2407:30:0517
3664099169163,4cyclictest0-21swapper/2407:30:0417
3664099169161,6cyclictest0-21swapper/2407:45:4417
3664099169161,6cyclictest0-21swapper/2407:45:4317
3663999169164,3cyclictest0-21swapper/2310:35:1516
3663999169164,3cyclictest0-21swapper/2310:35:1516
3663999169164,3cyclictest0-21swapper/2310:35:1516
366589916883,80cyclictest0-21swapper/3910:40:2233
366589916883,80cyclictest0-21swapper/3910:40:2133
366589916883,80cyclictest0-21swapper/3910:40:2133
3665699168148,8cyclictest3609-21CPU31
3665699168148,8cyclictest3609-21CPU31
3665699168148,8cyclictest3609-21CPU31
3665699167148,9cyclictest0-21swapper/3709:05:1431
3665699167148,9cyclictest0-21swapper/3709:05:1431
36654991671,71cyclictest0-21swapper/3609:55:1430
36654991671,71cyclictest0-21swapper/3609:55:1430
36654991671,71cyclictest0-21swapper/3609:55:1430
3664299167135,18cyclictest0-21swapper/2609:23:4819
3664299167135,18cyclictest0-21swapper/2609:23:4719
3664299167135,18cyclictest0-21swapper/2609:23:4719
3663699167151,10cyclictest171rcu_preempt07:17:2613
3663699167151,10cyclictest171rcu_preempt07:17:2613
3663499167160,5cyclictest0-21swapper/1810:56:5710
3663499167160,5cyclictest0-21swapper/1810:56:5710
3663499167152,2cyclictest0-21swapper/1812:15:5410
3663499167152,2cyclictest0-21swapper/1812:15:5410
3663499167152,2cyclictest0-21swapper/1812:15:5310
36642991661,160cyclictest0-21swapper/2610:55:1519
36642991661,160cyclictest0-21swapper/2610:55:1519
36617991661,4cyclictest1367-21dbus-daemon09:10:3735
36617991661,4cyclictest1367-21dbus-daemon09:10:3735
3664199165121,40cyclictest0-21swapper/2511:12:0618
3664199165121,40cyclictest0-21swapper/2511:12:0618
3661799165114,41cyclictest2461-21CPU35
3661799165114,41cyclictest2461-21CPU35
3661799165114,41cyclictest2461-21CPU35
3665699164151,7cyclictest0-21swapper/3709:17:2431
3665699164151,7cyclictest0-21swapper/3709:17:2431
3665699164151,7cyclictest0-21swapper/3709:17:2431
3665699164143,19cyclictest0-21swapper/3709:26:0231
3665699164143,19cyclictest0-21swapper/3709:26:0231
366529916494,66cyclictest37354-21CPU29
366529916494,66cyclictest37354-21CPU29
366529916494,66cyclictest37354-21CPU29
3664199164130,30cyclictest0-21swapper/2512:14:3318
3664199164130,30cyclictest0-21swapper/2512:14:3218
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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