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2026-02-24 - 11:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Feb 24, 2026 01:01:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2483799213173,23cyclictest2464-21CPU35
2483799213173,23cyclictest2464-21CPU35
2483199199168,28cyclictest0-21swapper/021:31:570
2483199199168,28cyclictest0-21swapper/021:31:560
2483199199168,28cyclictest0-21swapper/021:31:560
2483799191169,10cyclictest0-21swapper/519:22:5135
2483799191169,10cyclictest0-21swapper/519:22:5135
2483799187166,12cyclictest0-21swapper/521:20:2635
2483799187166,12cyclictest0-21swapper/521:20:2635
2485399186143,40cyclictest0-21swapper/1823:19:0910
2485399186143,40cyclictest0-21swapper/1823:19:0910
24842991861,113cyclictest0-21swapper/921:25:2039
24842991861,113cyclictest0-21swapper/921:25:1939
248589918472,36cyclictest0-21swapper/2221:35:2015
248589918472,36cyclictest0-21swapper/2221:35:2015
2487299183156,9cyclictest0-21swapper/3400:11:1428
2487299183156,9cyclictest0-21swapper/3400:11:1428
2484299182145,29cyclictest0-21swapper/923:16:1939
2484299182145,29cyclictest0-21swapper/923:16:1939
2484299180150,24cyclictest0-21swapper/922:28:3739
2484299180150,24cyclictest0-21swapper/922:28:3739
2485899179142,19cyclictest0-21swapper/2221:17:0715
2485899179142,19cyclictest0-21swapper/2221:17:0715
2486799178157,11cyclictest0-21swapper/3023:38:5924
2486799178157,11cyclictest0-21swapper/3023:38:5924
2486799178157,11cyclictest0-21swapper/3023:38:5924
2486799178100,62cyclictest3544-21CPU24
2486799178100,62cyclictest3544-21CPU24
248539917899,64cyclictest0-21swapper/1821:59:4910
248539917899,64cyclictest0-21swapper/1821:59:4910
2485099178152,10cyclictest0-21swapper/1522:42:287
2485099178152,10cyclictest0-21swapper/1522:42:287
2486799177163,9cyclictest0-21swapper/3022:47:4724
2486799177163,9cyclictest0-21swapper/3022:47:4724
2483799177165,10cyclictest0-21swapper/521:15:5235
2483799177165,10cyclictest0-21swapper/521:15:5235
2487399176151,21cyclictest2464-21CPU29
2487399176151,21cyclictest2464-21CPU29
2487399176151,21cyclictest2464-21CPU29
2485099176161,12cyclictest0-21swapper/1521:48:387
2485099176161,12cyclictest0-21swapper/1521:48:377
2484299174115,50cyclictest3609-21CPU39
2484299174115,50cyclictest3609-21CPU39
2484299174115,50cyclictest3609-21CPU39
2484299173132,37cyclictest0-21swapper/921:13:1039
2484299173132,37cyclictest0-21swapper/921:13:1039
24842991731,114cyclictest0-21swapper/921:30:1439
24842991731,114cyclictest0-21swapper/921:30:1439
24842991731,114cyclictest0-21swapper/921:30:1439
2486799172152,11cyclictest0-21swapper/3021:51:2624
2486799172152,11cyclictest0-21swapper/3021:51:2624
2484999172121,47cyclictest3541-21CPU6
2484999172121,47cyclictest3541-21CPU6
248659917191,70cyclictest20879-21lxd21:59:4922
248659917191,70cyclictest20879-21lxd21:59:4922
2485399171133,23cyclictest0-21swapper/1822:30:0110
2485399171133,23cyclictest0-21swapper/1822:30:0010
2486799170152,9cyclictest0-21swapper/3021:01:1824
2486799170152,9cyclictest0-21swapper/3021:01:1824
2484999170153,4cyclictest36129-21sshd21:27:316
2484999170153,4cyclictest36129-21sshd21:27:306
2483199170136,13cyclictest0-21swapper/021:15:520
2483199170136,13cyclictest0-21swapper/021:15:520
2486999169148,12cyclictest0-21swapper/3122:53:5025
2486999169148,12cyclictest0-21swapper/3122:53:4925
2484299169141,22cyclictest0-21swapper/922:49:4239
2484299169141,22cyclictest0-21swapper/922:49:4239
2487299168133,16cyclictest171rcu_preempt23:40:2928
2487299168133,16cyclictest171rcu_preempt23:40:2828
2487299168133,16cyclictest171rcu_preempt23:40:2828
2483399168154,11cyclictest0-21swapper/221:17:1712
2483399168154,11cyclictest0-21swapper/221:17:1612
2486799167150,8cyclictest0-21swapper/3000:16:2224
2486799167150,8cyclictest0-21swapper/3000:16:2124
2483799167108,56cyclictest3542-21CPU35
2483799167108,56cyclictest3542-21CPU35
2483799167105,38cyclictest37263-21CPU35
2483799167105,38cyclictest37263-21CPU35
2483799167105,38cyclictest37263-21CPU35
248539916641,123cyclictest0-21swapper/1823:27:4910
248539916641,123cyclictest0-21swapper/1823:27:4910
248539916641,123cyclictest0-21swapper/1823:27:4910
2486799165151,9cyclictest0-21swapper/3022:40:4824
2486799165151,9cyclictest0-21swapper/3022:40:4824
2485599165104,42cyclictest0-21swapper/2000:39:0013
2485599165104,42cyclictest0-21swapper/2000:38:5913
2485599165104,42cyclictest0-21swapper/2000:38:5913
2485499165154,2cyclictest0-21swapper/1919:17:4011
2485499165154,2cyclictest0-21swapper/1919:17:4011
2486799164110,42cyclictest2454-21CPU24
2486799164110,42cyclictest2454-21CPU24
2485499164157,5cyclictest0-21swapper/1921:42:0411
2485499164157,5cyclictest0-21swapper/1921:42:0411
2486799163149,2cyclictest0-21swapper/3021:42:5724
2486799163149,2cyclictest0-21swapper/3021:42:5624
2486799163136,10cyclictest171rcu_preempt23:08:0824
2486799163136,10cyclictest171rcu_preempt23:08:0824
2486799163112,26cyclictest0-21swapper/3021:32:5624
2486799163112,26cyclictest0-21swapper/3021:32:5624
2486799163112,26cyclictest0-21swapper/3021:32:5624
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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