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2026-01-26 - 09:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Jan 26, 2026 00:59:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25897991991,195cyclictest0-21swapper/2523:00:1918
25897991991,195cyclictest0-21swapper/2523:00:1918
2589799194141,50cyclictest0-21swapper/2521:44:4618
2589799194141,50cyclictest0-21swapper/2521:44:4618
2589399192177,13cyclictest0-21swapper/2200:28:2815
2589399192177,13cyclictest0-21swapper/2200:28:2815
2590299187184,2cyclictest0-21swapper/2923:53:3022
2590299187184,2cyclictest0-21swapper/2923:53:3022
2589299183132,32cyclictest0-21swapper/2121:38:2014
2589299183132,32cyclictest0-21swapper/2121:38:2014
2590599181176,4cyclictest0-21swapper/3223:11:5726
2590599181176,4cyclictest0-21swapper/3223:11:5726
2589299181129,43cyclictest37358-21CPU14
2589299181129,43cyclictest37358-21CPU14
2590599180176,2cyclictest0-21swapper/3221:12:2426
2590599180176,2cyclictest0-21swapper/3221:12:2426
25872991803,97cyclictest0-21swapper/523:05:4035
25872991803,97cyclictest0-21swapper/523:05:4035
2589399179164,12cyclictest0-21swapper/2200:21:0115
2589399179164,12cyclictest0-21swapper/2200:21:0115
2588499179173,4cyclictest0-21swapper/1421:11:006
2588499179173,4cyclictest0-21swapper/1421:11:006
2590699178160,14cyclictest0-21swapper/3323:19:4827
2590699178160,14cyclictest0-21swapper/3323:19:4727
2590699178116,16cyclictest171rcu_preempt00:36:4827
2590699178116,16cyclictest171rcu_preempt00:36:4827
2589799178149,24cyclictest0-21swapper/2522:48:5018
2589799178149,24cyclictest0-21swapper/2522:48:5018
25897991781,160cyclictest0-21swapper/2521:38:0718
25897991781,160cyclictest0-21swapper/2521:38:0718
2590699177156,11cyclictest0-21swapper/3321:17:1327
2590699177156,11cyclictest0-21swapper/3321:17:1327
2589299176130,22cyclictest0-21swapper/2121:14:1514
2589299176130,22cyclictest0-21swapper/2121:14:1414
2589299176101,55cyclictest4407-21CPU14
2589299176101,55cyclictest4407-21CPU14
2589399175110,57cyclictest0-21swapper/2221:29:4515
2589399175110,57cyclictest0-21swapper/2221:29:4515
2589299175119,41cyclictest2466-21CPU14
2589299175119,41cyclictest2466-21CPU14
2589299174125,32cyclictest0-21swapper/2119:17:4714
2589299174125,32cyclictest0-21swapper/2119:17:4714
2588499174162,10cyclictest0-21swapper/1400:24:286
2588499174162,10cyclictest0-21swapper/1400:24:286
2588299174162,6cyclictest2327-21qemu-system-x8623:38:254
2588299174162,6cyclictest2327-21qemu-system-x8623:38:254
2590699173159,6cyclictest0-21swapper/3323:56:5127
2590699173159,6cyclictest0-21swapper/3323:56:5127
2590699173159,6cyclictest0-21swapper/3323:56:5127
2590399173160,11cyclictest0-21swapper/3022:26:3924
2590399173160,11cyclictest0-21swapper/3022:26:3924
2589299173145,23cyclictest0-21swapper/2123:08:4514
2589299173145,23cyclictest0-21swapper/2123:08:4514
2589299173118,27cyclictest0-21swapper/2122:52:4514
2589299173118,27cyclictest0-21swapper/2122:52:4514
2588499173161,8cyclictest0-21swapper/1422:13:096
2588499173161,8cyclictest0-21swapper/1422:13:096
2588499173161,8cyclictest0-21swapper/1422:13:096
2590699172160,11cyclictest0-21swapper/3300:02:1727
2590699172160,11cyclictest0-21swapper/3300:02:1727
2590699172160,11cyclictest0-21swapper/3300:02:1727
2590699172125,27cyclictest0-21swapper/3321:40:3527
2590699172125,27cyclictest0-21swapper/3321:40:3527
2590399172164,4cyclictest0-21swapper/3000:31:2324
2590399172164,4cyclictest0-21swapper/3000:31:2324
2589299172125,29cyclictest0-21swapper/2123:55:3914
2589299172125,29cyclictest0-21swapper/2123:55:3914
2589299172125,29cyclictest0-21swapper/2123:55:3914
2589299172124,22cyclictest0-21swapper/2100:28:2114
2589299172124,22cyclictest0-21swapper/2100:28:2114
2589299172105,53cyclictest3543-21CPU14
2589299172105,53cyclictest3543-21CPU14
2590699171149,13cyclictest171rcu_preempt23:06:0227
2590699171149,13cyclictest171rcu_preempt23:06:0227
2589399171162,5cyclictest0-21swapper/2200:11:4315
2589399171162,5cyclictest0-21swapper/2200:11:4315
258929917193,64cyclictest3546-21CPU14
258929917193,64cyclictest3546-21CPU14
2589299171120,28cyclictest0-21swapper/2119:21:4614
2589299171120,28cyclictest0-21swapper/2119:21:4614
2589299171116,10cyclictest0-21swapper/2123:10:2914
2589299171116,10cyclictest0-21swapper/2123:10:2914
258729917185,80cyclictest2456-21CPU35
258729917185,80cyclictest2456-21CPU35
258729917185,80cyclictest2456-21CPU35
2591099170162,6cyclictest0-21swapper/3721:00:3731
2591099170162,6cyclictest0-21swapper/3721:00:3731
2590699170145,9cyclictest171rcu_preempt21:11:1827
2590699170145,9cyclictest171rcu_preempt21:11:1827
2590699170129,20cyclictest0-21swapper/3323:04:4327
2590699170129,20cyclictest0-21swapper/3323:04:4327
2589399170166,2cyclictest0-21swapper/2200:19:3315
2589399170166,2cyclictest0-21swapper/2200:19:3315
2589399170166,2cyclictest0-21swapper/2200:19:3315
2589399170157,9cyclictest0-21swapper/2200:32:0515
2589399170157,9cyclictest0-21swapper/2200:32:0515
2589299170154,14cyclictest0-21swapper/2123:43:2814
2589299170154,14cyclictest0-21swapper/2123:43:2814
2589299170149,11cyclictest171rcu_preempt20:15:3014
2589299170149,11cyclictest171rcu_preempt20:15:3014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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