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2026-03-06 - 03:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri Mar 06, 2026 01:02:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2307399234224,8cyclictest0-21swapper/622:20:1836
2307399234224,8cyclictest0-21swapper/622:20:1836
2307399234224,8cyclictest0-21swapper/622:20:1836
2309099225221,2cyclictest0-21swapper/2219:25:1815
2309299215208,4cyclictest2454-21CPU16
2309299215208,4cyclictest2454-21CPU16
2309299214210,2cyclictest0-21swapper/2322:19:0316
2309299214210,2cyclictest0-21swapper/2322:19:0316
2310999212198,6cyclictest0-21swapper/3821:49:1832
2310999212198,6cyclictest0-21swapper/3821:49:1832
2307399210205,3cyclictest0-21swapper/622:15:1436
2307399210205,3cyclictest0-21swapper/622:15:1436
2306999210187,18cyclictest0-21swapper/221:42:4312
2306999210187,18cyclictest0-21swapper/221:42:4312
2310999208185,17cyclictest0-21swapper/3822:04:5132
2310999208185,17cyclictest0-21swapper/3822:04:5132
2310999208185,17cyclictest0-21swapper/3822:04:5132
2310399204181,17cyclictest373-21kswapd100:08:5927
2310399204181,17cyclictest373-21kswapd100:08:5927
2310399204181,17cyclictest373-21kswapd100:08:5927
2307399204194,5cyclictest24789-21systemd22:13:0536
2307399204194,5cyclictest24789-21systemd22:13:0536
2307399204194,5cyclictest24789-21systemd22:13:0536
2308199203193,3cyclictest2462-21CPU5
2308199203193,3cyclictest2462-21CPU5
2308199203193,3cyclictest2462-21CPU5
2306999203190,11cyclictest0-21swapper/221:36:4012
2306999203190,11cyclictest0-21swapper/221:36:4012
2310999202194,4cyclictest2456-21CPU32
2310999202194,4cyclictest2456-21CPU32
2308999202180,19cyclictest2459-21CPU14
2308999202180,19cyclictest2459-21CPU14
2307399202194,5cyclictest0-21swapper/622:25:5936
2307399202194,5cyclictest0-21swapper/622:25:5936
2307399202194,5cyclictest0-21swapper/622:25:5936
2307299202171,24cyclictest0-21swapper/500:10:2135
2307299202171,24cyclictest0-21swapper/500:10:2135
2307299202171,24cyclictest0-21swapper/500:10:2135
2306999201189,8cyclictest0-21swapper/221:33:0712
2306999201189,8cyclictest0-21swapper/221:33:0712
2306999201189,8cyclictest0-21swapper/221:33:0712
2309099199196,2cyclictest0-21swapper/2222:55:1315
2309099199196,2cyclictest0-21swapper/2222:55:1315
2308399199186,6cyclictest3406-21sshd23:00:017
2308399199186,6cyclictest3406-21sshd23:00:017
2307399199193,4cyclictest0-21swapper/622:55:0236
2307399199193,4cyclictest0-21swapper/622:55:0236
2307399199193,4cyclictest0-21swapper/622:55:0236
2307399199187,10cyclictest0-21swapper/620:22:4236
2309699198159,37cyclictest0-21swapper/2623:28:4219
2309699198159,37cyclictest0-21swapper/2623:28:4219
2308399198191,5cyclictest0-21swapper/1523:00:237
2308399198191,5cyclictest0-21swapper/1523:00:237
2306999198137,46cyclictest0-21swapper/221:25:0512
2306999198137,46cyclictest0-21swapper/221:25:0512
2307199197194,2cyclictest0-21swapper/422:00:1734
2307199197194,2cyclictest0-21swapper/422:00:1734
2307199197194,2cyclictest0-21swapper/422:00:1734
2306999197187,8cyclictest0-21swapper/221:29:0412
2306999197187,8cyclictest0-21swapper/221:29:0412
2306999197187,8cyclictest0-21swapper/221:29:0412
2310599196158,36cyclictest0-21swapper/3523:20:0329
2310599196158,36cyclictest0-21swapper/3523:20:0329
2310999195188,5cyclictest0-21swapper/3821:56:2332
2310999195188,5cyclictest0-21swapper/3821:56:2332
2308399195185,6cyclictest0-21swapper/1523:25:137
2308399195185,6cyclictest0-21swapper/1523:25:137
2308399195183,6cyclictest0-21swapper/1500:30:277
2308399195183,6cyclictest0-21swapper/1500:30:277
2308399195181,11cyclictest1367-21dbus-daemon00:11:517
2308399195181,11cyclictest1367-21dbus-daemon00:11:517
2308399195181,11cyclictest1367-21dbus-daemon00:11:517
2308399195173,15cyclictest0-21swapper/1523:30:567
2308399195173,15cyclictest0-21swapper/1523:30:567
2308999193181,10cyclictest0-21swapper/2120:30:2214
2308999193181,10cyclictest0-21swapper/2120:30:2214
2306999193187,5cyclictest0-21swapper/221:15:3112
2306999193187,5cyclictest0-21swapper/221:15:3112
2307399192186,4cyclictest0-21swapper/622:07:3136
2307399192186,4cyclictest0-21swapper/622:07:3136
2310599190140,40cyclictest0-21swapper/3523:03:5329
2310599190140,40cyclictest0-21swapper/3523:03:5329
2310199189157,21cyclictest0-21swapper/3119:21:1025
2310199189157,21cyclictest0-21swapper/3119:21:1025
2310199189157,21cyclictest0-21swapper/3119:21:1025
2308399189178,9cyclictest0-21swapper/1500:38:037
2308399189178,9cyclictest0-21swapper/1500:38:037
2308199189183,4cyclictest0-21swapper/1322:55:185
2308199189183,4cyclictest0-21swapper/1322:55:185
2307399189183,4cyclictest0-21swapper/620:13:4136
2307399189183,4cyclictest0-21swapper/620:13:4136
2310599188156,30cyclictest0-21swapper/3522:39:4129
2310599188156,30cyclictest0-21swapper/3522:39:4129
2308299188185,2cyclictest0-21swapper/1422:25:236
2308299188185,2cyclictest0-21swapper/1422:25:236
2308299188185,2cyclictest0-21swapper/1422:25:236
2307399188183,4cyclictest0-21swapper/620:19:4636
2307299188126,53cyclictest3548-21CPU35
2307299188126,53cyclictest3548-21CPU35
2308999187181,4cyclictest0-21swapper/2121:12:4014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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