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2026-05-01 - 16:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri May 01, 2026 13:02:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
149499212202,7cyclictest0-21swapper/309:28:4223
149499212202,7cyclictest0-21swapper/309:28:4223
149499212202,7cyclictest0-21swapper/309:28:4223
150499200194,5cyclictest0-21swapper/1309:23:535
150499200194,5cyclictest0-21swapper/1309:23:535
150499200194,5cyclictest0-21swapper/1309:23:535
149499198188,8cyclictest0-21swapper/311:56:1323
149499198188,8cyclictest0-21swapper/311:56:1323
149399196153,39cyclictest2454-21CPU12
149399196153,39cyclictest2454-21CPU12
152199191173,7cyclictest0-21swapper/2611:23:4819
152199191173,7cyclictest0-21swapper/2611:23:4819
152199191173,7cyclictest0-21swapper/2611:23:4819
150499191177,10cyclictest3546-21CPU5
150499191177,10cyclictest3546-21CPU5
149399191171,17cyclictest0-21swapper/210:20:1712
149399191171,17cyclictest0-21swapper/210:20:1712
152599188106,64cyclictest3543-21CPU24
152599188106,64cyclictest3543-21CPU24
150499188178,8cyclictest0-21swapper/1311:41:195
150499188178,8cyclictest0-21swapper/1311:41:185
149499188179,7cyclictest0-21swapper/310:03:0923
149499188179,7cyclictest0-21swapper/310:03:0923
152199187172,11cyclictest0-21swapper/2609:54:3119
152199187172,11cyclictest0-21swapper/2609:54:3119
152199187172,11cyclictest0-21swapper/2609:54:3119
149399187179,6cyclictest0-21swapper/210:05:1512
149399187179,6cyclictest0-21swapper/210:05:1512
149399187179,6cyclictest0-21swapper/210:05:1512
149399187176,9cyclictest0-21swapper/211:34:1812
149399187176,9cyclictest0-21swapper/211:34:1812
151799185168,7cyclictest0-21swapper/2211:41:1215
151799185168,7cyclictest0-21swapper/2211:41:1215
14949918496,63cyclictest2464-21CPU23
14949918496,63cyclictest2464-21CPU23
149399183175,4cyclictest3547-21CPU12
149399183175,4cyclictest3547-21CPU12
149399183175,4cyclictest3547-21CPU12
149399181174,5cyclictest0-21swapper/209:32:4412
149399181174,5cyclictest0-21swapper/209:32:4412
149399181171,8cyclictest0-21swapper/209:51:5212
149399181171,8cyclictest0-21swapper/209:51:5212
149399181171,8cyclictest0-21swapper/209:51:5212
150499180172,6cyclictest0-21swapper/1310:35:025
150499180172,6cyclictest0-21swapper/1310:35:025
150499180170,3cyclictest0-21swapper/1311:15:205
150499180170,3cyclictest0-21swapper/1311:15:205
149499179164,12cyclictest0-21swapper/312:27:2323
149499179164,12cyclictest0-21swapper/312:27:2323
149399179170,6cyclictest0-21swapper/208:45:2412
149399179170,6cyclictest0-21swapper/208:45:2312
149399179101,66cyclictest37353-21CPU12
149399179101,66cyclictest37353-21CPU12
15259917897,58cyclictest37267-21CPU24
15259917897,58cyclictest37267-21CPU24
152199178169,6cyclictest0-21swapper/2610:38:3219
152199178169,6cyclictest0-21swapper/2610:38:3219
149899178161,11cyclictest0-21swapper/712:08:0737
149899178161,11cyclictest0-21swapper/712:08:0737
149399178163,10cyclictest37355-21CPU12
149399178163,10cyclictest37355-21CPU12
149799177117,49cyclictest0-21swapper/610:52:5836
149799177117,49cyclictest0-21swapper/610:52:5836
149399177169,6cyclictest0-21swapper/209:41:0712
149399177169,6cyclictest0-21swapper/209:41:0712
153299176162,11cyclictest0-21swapper/3609:35:2230
153299176162,11cyclictest0-21swapper/3609:35:2230
153299176162,11cyclictest0-21swapper/3609:35:2230
151799176164,10cyclictest0-21swapper/2209:54:0515
151799176164,10cyclictest0-21swapper/2209:54:0515
151799176164,10cyclictest0-21swapper/2209:54:0515
150499176171,4cyclictest0-21swapper/1311:02:135
150499176171,4cyclictest0-21swapper/1311:02:135
150499176171,4cyclictest0-21swapper/1311:02:135
150499176149,19cyclictest0-21swapper/1312:12:445
150499176149,19cyclictest0-21swapper/1312:12:445
150499175163,3cyclictest3546-21CPU5
150499175163,3cyclictest3546-21CPU5
150499175163,3cyclictest3546-21CPU5
149899175140,7cyclictest171rcu_preempt12:23:1637
149899175140,7cyclictest171rcu_preempt12:23:1637
149499175165,7cyclictest0-21swapper/311:02:3623
149499175165,7cyclictest0-21swapper/311:02:3523
149499175165,7cyclictest0-21swapper/311:02:3523
149499175145,9cyclictest0-21swapper/309:20:5023
149499175145,9cyclictest0-21swapper/309:20:4923
149499175145,9cyclictest0-21swapper/309:20:4923
153299174159,5cyclictest0-21swapper/3610:32:0530
153299174159,5cyclictest0-21swapper/3610:32:0530
152199174156,16cyclictest0-21swapper/2611:31:3619
152199174156,16cyclictest0-21swapper/2611:31:3619
149499174153,8cyclictest0-21swapper/312:08:2223
149499174153,8cyclictest0-21swapper/312:08:2223
149399174168,4cyclictest0-21swapper/210:14:0812
149399174168,4cyclictest0-21swapper/210:14:0812
149399174164,7cyclictest0-21swapper/209:35:1812
149399174164,7cyclictest0-21swapper/209:35:1812
149399174164,7cyclictest0-21swapper/209:35:1812
149399174159,5cyclictest0-21swapper/211:58:5512
149399174159,5cyclictest0-21swapper/211:58:5512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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