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2026-04-18 - 20:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Apr 18, 2026 13:02:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3576899201191,8cyclictest0-21swapper/011:07:110
3576899201191,8cyclictest0-21swapper/011:07:100
3578899198189,5cyclictest3548-21CPU9
3578899198189,5cyclictest3548-21CPU9
3576899197189,6cyclictest0-21swapper/009:20:010
3576899197189,6cyclictest0-21swapper/009:20:000
3578899195186,4cyclictest2454-21CPU9
3578899195186,4cyclictest2454-21CPU9
3576899194187,5cyclictest0-21swapper/012:25:400
3576899194187,5cyclictest0-21swapper/012:25:390
3576899191186,3cyclictest0-21swapper/010:13:540
3576899191186,3cyclictest0-21swapper/010:13:540
3576899191184,4cyclictest0-21swapper/007:30:160
3576899189183,4cyclictest4398-21qemu-system-x8607:37:110
35791991881,87cyclictest0-21swapper/2010:35:1513
35791991881,87cyclictest0-21swapper/2010:35:1513
35791991881,87cyclictest0-21swapper/2010:35:1513
35791991881,183cyclictest4398-21qemu-system-x8608:00:2213
35791991881,183cyclictest4398-21qemu-system-x8608:00:2213
3580299187167,17cyclictest0-21swapper/3008:10:1024
3580299187167,17cyclictest0-21swapper/3008:10:1024
3576899187181,4cyclictest4398-21qemu-system-x8610:23:570
3576899187181,4cyclictest4398-21qemu-system-x8610:23:560
3576899187175,8cyclictest0-21swapper/011:40:580
3576899187175,8cyclictest0-21swapper/011:40:580
3576899187175,8cyclictest0-21swapper/011:40:580
3580899186171,9cyclictest0-21swapper/3511:03:2029
3580899186171,9cyclictest0-21swapper/3511:03:2029
3580899186171,9cyclictest0-21swapper/3511:03:1929
3579199186157,27cyclictest0-21swapper/2011:50:4313
3579199186157,27cyclictest0-21swapper/2011:50:4313
3576899186174,9cyclictest0-21swapper/008:00:400
3576899186174,9cyclictest0-21swapper/008:00:400
3576899185179,4cyclictest0-21swapper/011:02:510
3576899185179,4cyclictest0-21swapper/011:02:510
3576899185179,4cyclictest0-21swapper/011:02:510
3576899185178,4cyclictest0-21swapper/011:10:160
3576899185178,4cyclictest0-21swapper/011:10:160
3576899185178,4cyclictest0-21swapper/011:10:160
3576899184178,4cyclictest17484-21nfsd11:27:320
3576899184178,4cyclictest17484-21nfsd11:27:320
3576899184176,6cyclictest0-21swapper/009:26:040
3576899184176,6cyclictest0-21swapper/009:26:040
3576899184176,6cyclictest0-21swapper/009:26:030
3576899184174,6cyclictest37353-21CPU0
3576899184174,6cyclictest37353-21CPU0
3576899183176,4cyclictest37346-21qemu-system-x8612:19:520
3576899183176,4cyclictest37346-21qemu-system-x8612:19:510
3578899182166,6cyclictest171rcu_preempt12:28:339
3578899182166,6cyclictest171rcu_preempt12:28:339
3576899182175,5cyclictest0-21swapper/011:58:560
3576899182175,5cyclictest0-21swapper/011:58:560
3576899182175,5cyclictest0-21swapper/011:58:550
3576899182171,9cyclictest0-21swapper/010:26:320
3576899182171,9cyclictest0-21swapper/010:26:310
3580299181168,9cyclictest0-21swapper/3012:19:4924
3580299181168,9cyclictest0-21swapper/3012:19:4824
3576899181174,5cyclictest0-21swapper/010:38:340
3576899181174,5cyclictest0-21swapper/010:38:330
3576899181174,5cyclictest0-21swapper/010:38:330
3580399180165,7cyclictest0-21swapper/3109:35:1925
3580399180165,7cyclictest0-21swapper/3109:35:1925
3580399180165,7cyclictest0-21swapper/3109:35:1925
3577799180145,32cyclictest0-21swapper/808:35:3338
3577799180145,32cyclictest0-21swapper/808:35:3338
3577799180139,34cyclictest0-21swapper/809:15:0738
3577799180139,34cyclictest0-21swapper/809:15:0738
3579999179140,34cyclictest3547-21CPU21
3579999179140,34cyclictest3547-21CPU21
3579999179140,34cyclictest3547-21CPU21
3576899179163,13cyclictest0-21swapper/009:35:140
3576899179163,13cyclictest0-21swapper/009:35:140
3576899179163,13cyclictest0-21swapper/009:35:130
3579199178144,24cyclictest0-21swapper/2009:58:3513
3579199178144,24cyclictest0-21swapper/2009:58:3513
3578899178127,44cyclictest0-21swapper/1710:05:599
3578899178127,44cyclictest0-21swapper/1710:05:589
3578899178127,44cyclictest0-21swapper/1710:05:589
3576899178173,4cyclictest0-21swapper/012:04:220
3576899178173,4cyclictest0-21swapper/012:04:220
3576899178173,4cyclictest0-21swapper/012:04:220
3576899178172,5cyclictest0-21swapper/010:41:470
3576899178172,5cyclictest0-21swapper/010:41:470
3576899178169,7cyclictest0-21swapper/012:20:240
3576899178169,7cyclictest0-21swapper/012:20:240
3576899178169,7cyclictest0-21swapper/012:20:230
3576899178162,14cyclictest3535-21qemu-system-x8612:39:390
3576899178162,14cyclictest3535-21qemu-system-x8612:39:390
3576899178162,14cyclictest3535-21qemu-system-x8612:39:390
3576899177171,4cyclictest1384-21rs:main0
3576899177171,4cyclictest1384-21rs:main0
3576899177170,5cyclictest0-21swapper/012:30:320
3576899177170,5cyclictest0-21swapper/012:30:320
3576899177170,5cyclictest0-21swapper/012:30:310
3576899177166,7cyclictest3543-21CPU0
3576899177166,7cyclictest3543-21CPU0
3577099176171,3cyclictest0-21swapper/209:33:4712
3577099176171,3cyclictest0-21swapper/209:33:4712
3577099176168,7cyclictest0-21swapper/210:17:3612
3577099176168,7cyclictest0-21swapper/210:17:3512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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