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2026-02-17 - 09:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Feb 17, 2026 01:03:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
197799200186,13cyclictest0-21swapper/3422:25:0128
197799200186,13cyclictest0-21swapper/3422:25:0128
195799199158,35cyclictest0-21swapper/1823:20:4110
195799199158,35cyclictest0-21swapper/1823:20:4110
195799199158,35cyclictest0-21swapper/1823:20:4110
194499195171,15cyclictest0-21swapper/721:39:1337
194499195171,15cyclictest0-21swapper/721:39:1337
194499195171,15cyclictest0-21swapper/721:39:1337
194999192184,6cyclictest0-21swapper/1000:25:342
194999192184,6cyclictest0-21swapper/1000:25:342
197099191172,17cyclictest19779-21kworker/u81:5-events_unbound00:27:2221
197099191172,17cyclictest19779-21kworker/u81:5-events_unbound00:27:2221
1957991911,178cyclictest0-21swapper/1822:25:1810
1957991911,178cyclictest0-21swapper/1822:25:1810
194999188138,46cyclictest37264-21CPU2
194999188138,46cyclictest37264-21CPU2
194499188164,22cyclictest0-21swapper/722:58:0837
194499188164,22cyclictest0-21swapper/722:58:0837
197799187182,4cyclictest0-21swapper/3423:57:3528
197799187182,4cyclictest0-21swapper/3423:57:3528
197799187182,4cyclictest0-21swapper/3423:57:3528
197799187181,4cyclictest30098-21kworker/u82:4-events_unbound22:17:5328
197799187181,4cyclictest30098-21kworker/u82:4-events_unbound22:17:5328
197799187181,4cyclictest30098-21kworker/u82:4-events_unbound22:17:5328
197799187181,3cyclictest27077-21updatedb.mlocat00:07:4928
197799187181,3cyclictest27077-21updatedb.mlocat00:07:4928
197799187181,3cyclictest27077-21updatedb.mlocat00:07:4928
196499186151,24cyclictest3545-21CPU17
196499186151,24cyclictest3545-21CPU17
196899185177,7cyclictest0-21swapper/2722:57:4720
196899185177,7cyclictest0-21swapper/2722:57:4720
196899185173,10cyclictest0-21swapper/2723:58:1420
196899185173,10cyclictest0-21swapper/2723:58:1420
196899185173,10cyclictest0-21swapper/2723:58:1420
194999185130,28cyclictest0-21swapper/1000:31:122
194999185130,28cyclictest0-21swapper/1000:31:122
197799184178,5cyclictest0-21swapper/3423:50:4728
197799184178,5cyclictest0-21swapper/3423:50:4728
197799183171,10cyclictest0-21swapper/3422:26:2828
197799183171,10cyclictest0-21swapper/3422:26:2828
197799182175,5cyclictest142450irq/46-eno1-TxRx-422:40:1528
197799182175,5cyclictest142450irq/46-eno1-TxRx-422:40:1528
19579918289,81cyclictest0-21swapper/1822:00:1910
19579918289,81cyclictest0-21swapper/1822:00:1910
197799181164,13cyclictest0-21swapper/3422:40:0528
197799181164,13cyclictest0-21swapper/3422:40:0528
197799181164,13cyclictest0-21swapper/3422:40:0528
195799181136,38cyclictest0-21swapper/1821:37:4810
195799181136,38cyclictest0-21swapper/1821:37:4810
195799181136,38cyclictest0-21swapper/1821:37:4810
195799181136,36cyclictest0-21swapper/1822:58:5110
195799181136,36cyclictest0-21swapper/1822:58:5110
195799181129,37cyclictest0-21swapper/1823:29:3610
195799181129,37cyclictest0-21swapper/1823:29:3610
194999181168,11cyclictest0-21swapper/1021:46:192
194999181168,11cyclictest0-21swapper/1021:46:192
194999181168,11cyclictest0-21swapper/1021:46:192
194999181164,11cyclictest0-21swapper/1020:09:242
194999181164,11cyclictest0-21swapper/1020:09:242
197799180174,4cyclictest0-21swapper/3422:56:5328
197799180174,4cyclictest0-21swapper/3422:56:5328
197799180172,6cyclictest0-21swapper/3423:40:0128
197799180172,6cyclictest0-21swapper/3423:40:0128
197799180172,6cyclictest0-21swapper/3423:40:0128
197799180172,6cyclictest0-21swapper/3423:12:2328
197799180172,6cyclictest0-21swapper/3423:12:2328
197799180172,6cyclictest0-21swapper/3422:50:2128
197799180172,6cyclictest0-21swapper/3422:50:2128
197799180169,10cyclictest0-21swapper/3400:20:1428
197799180169,10cyclictest0-21swapper/3400:20:1428
197799180169,10cyclictest0-21swapper/3400:20:1428
195799180140,38cyclictest0-21swapper/1822:54:0410
195799180140,38cyclictest0-21swapper/1822:54:0410
197799179174,4cyclictest0-21swapper/3422:48:0028
197799179174,4cyclictest0-21swapper/3422:48:0028
197799179173,5cyclictest0-21swapper/3422:32:0228
197799179173,5cyclictest0-21swapper/3422:32:0228
196499179160,6cyclictest0-21swapper/2421:44:5817
196499179160,6cyclictest0-21swapper/2421:44:5817
196499179160,6cyclictest0-21swapper/2421:44:5817
195799179144,28cyclictest0-21swapper/1821:49:0710
195799179144,28cyclictest0-21swapper/1821:49:0710
195799179144,28cyclictest0-21swapper/1821:49:0710
19449917973,103cyclictest0-21swapper/700:20:1237
19449917973,103cyclictest0-21swapper/700:20:1237
19449917973,103cyclictest0-21swapper/700:20:1237
196899178170,7cyclictest0-21swapper/2723:01:0620
196899178170,7cyclictest0-21swapper/2723:01:0620
196899178158,11cyclictest0-21swapper/2721:23:1020
196899178158,11cyclictest0-21swapper/2721:23:1020
196899178158,11cyclictest0-21swapper/2721:23:1020
196499178162,8cyclictest0-21swapper/2423:37:0817
196499178162,8cyclictest0-21swapper/2423:37:0817
196499178162,8cyclictest0-21swapper/2423:37:0817
194999178170,6cyclictest0-21swapper/1023:29:092
194999178170,6cyclictest0-21swapper/1023:29:092
194999178127,18cyclictest0-21swapper/1023:35:562
194999178127,18cyclictest0-21swapper/1023:35:562
194999178127,18cyclictest0-21swapper/1023:35:562
197099177171,2cyclictest0-21swapper/2823:20:4821
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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