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2026-02-25 - 00:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Feb 24, 2026 13:03:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1350599219200,17cyclictest0-21swapper/712:25:0037
1350599219200,17cyclictest0-21swapper/712:24:5937
13509992183,81cyclictest37354-21CPU2
13509992183,81cyclictest37354-21CPU2
1350399215202,7cyclictest3548-21CPU36
1350399215202,7cyclictest3548-21CPU36
1350399215202,7cyclictest3548-21CPU36
1350399213193,14cyclictest3548-21CPU36
1350399213193,14cyclictest3548-21CPU36
1350399213193,14cyclictest3548-21CPU36
1350999210118,88cyclictest3543-21CPU2
1350999210118,88cyclictest3543-21CPU2
1350999210118,88cyclictest3543-21CPU2
1350399209202,4cyclictest0-21swapper/611:27:2136
1350399209202,4cyclictest0-21swapper/611:27:2136
1350399209202,4cyclictest0-21swapper/611:27:2136
1350399209201,4cyclictest2459-21CPU36
1350399209201,4cyclictest2459-21CPU36
1350399208198,8cyclictest0-21swapper/611:12:2236
1350399208198,8cyclictest0-21swapper/611:12:2236
1350399208198,8cyclictest0-21swapper/611:12:2136
1350399208192,12cyclictest0-21swapper/611:38:0936
1350399208192,12cyclictest0-21swapper/611:38:0936
1350399208192,12cyclictest0-21swapper/611:38:0936
1350399207201,4cyclictest0-21swapper/609:25:3736
1350399207201,4cyclictest0-21swapper/609:25:3636
1350399207200,2cyclictest0-21swapper/610:20:2136
1350399207200,2cyclictest0-21swapper/610:20:2136
1350399207189,9cyclictest0-21swapper/611:59:2336
1350399207189,9cyclictest0-21swapper/611:59:2336
1350399207189,9cyclictest0-21swapper/611:59:2236
1350399206185,12cyclictest0-21swapper/611:43:0936
1350399206185,12cyclictest0-21swapper/611:43:0936
1350399206185,12cyclictest0-21swapper/611:43:0836
1350399203194,7cyclictest0-21swapper/611:55:0536
1350399203194,7cyclictest0-21swapper/611:55:0436
13509992022,131cyclictest37264-21CPU2
13509992022,131cyclictest37264-21CPU2
13509992022,131cyclictest37264-21CPU2
1353299201132,62cyclictest2461-21CPU22
1353299201132,62cyclictest2461-21CPU22
1350399201194,5cyclictest28233-21systemd12:30:1536
1350399201194,5cyclictest28233-21systemd12:30:1436
1350399201191,7cyclictest0-21swapper/611:45:1736
1350399201191,7cyclictest0-21swapper/611:45:1736
1350399201191,7cyclictest0-21swapper/611:45:1736
1350599200177,18cyclictest2447-21CPU37
1350599200177,18cyclictest2447-21CPU37
1350599200177,18cyclictest2447-21CPU37
1350399200189,8cyclictest3535-21qemu-system-x8612:14:1836
1350399200189,8cyclictest3535-21qemu-system-x8612:14:1836
1350399200189,8cyclictest3535-21qemu-system-x8612:14:1836
1352699199193,3cyclictest0-21swapper/2411:05:0117
1352699199193,3cyclictest0-21swapper/2411:05:0117
1352699199193,3cyclictest0-21swapper/2411:05:0017
1350799199184,11cyclictest0-21swapper/909:21:5239
1350799199184,11cyclictest0-21swapper/909:21:5139
1350799199184,11cyclictest0-21swapper/909:21:5139
1350399199194,3cyclictest0-21swapper/612:28:0936
1350399199194,3cyclictest0-21swapper/612:28:0936
1350399199194,3cyclictest0-21swapper/609:30:2736
1350399199194,3cyclictest0-21swapper/609:30:2736
1350399199194,3cyclictest0-21swapper/609:30:2736
1350399199192,3cyclictest37355-21CPU36
1350399199192,3cyclictest37355-21CPU36
1350399199192,3cyclictest37355-21CPU36
1350399198190,6cyclictest0-21swapper/610:30:2236
1350399198190,6cyclictest0-21swapper/610:30:2136
1350399198190,6cyclictest0-21swapper/610:30:2136
1350399197191,4cyclictest0-21swapper/609:14:0536
1350399197191,4cyclictest0-21swapper/609:14:0536
1350399197190,4cyclictest0-21swapper/610:48:3536
1350399197190,4cyclictest0-21swapper/610:48:3436
1350399197190,4cyclictest0-21swapper/610:48:3436
1350399197188,5cyclictest3545-21CPU36
1350399197188,5cyclictest3545-21CPU36
1350399196188,6cyclictest0-21swapper/612:23:3136
1350399196188,6cyclictest0-21swapper/612:23:3036
1350399196188,6cyclictest0-21swapper/610:25:1736
1350399196188,6cyclictest0-21swapper/610:25:1736
1350399196186,6cyclictest4408-21CPU36
1350399196186,6cyclictest4408-21CPU36
1350399196180,14cyclictest0-21swapper/610:50:2036
1350399196180,14cyclictest0-21swapper/610:50:2036
1352499195185,8cyclictest0-21swapper/2209:50:5915
1352499195185,8cyclictest0-21swapper/2209:50:5915
1352499195185,8cyclictest0-21swapper/2209:50:5915
1350399195187,5cyclictest0-21swapper/611:02:5336
1350399195187,5cyclictest0-21swapper/611:02:5236
1350399195187,5cyclictest0-21swapper/611:02:5236
1350399194188,4cyclictest0-21swapper/611:31:1936
1350399194188,4cyclictest0-21swapper/611:31:1936
1350399194188,4cyclictest0-21swapper/611:31:1836
1350399194188,4cyclictest0-21swapper/609:51:2136
1350399194188,4cyclictest0-21swapper/609:51:2036
1350399194188,4cyclictest0-21swapper/609:51:2036
1350399194188,4cyclictest0-21swapper/609:47:3736
1350399194188,4cyclictest0-21swapper/609:47:3736
1350399194188,4cyclictest0-21swapper/607:19:2536
1350399194188,4cyclictest0-21swapper/607:19:2436
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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