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2026-02-07 - 10:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 07, 2026 01:01:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1415499238231,5cyclictest3535-21qemu-system-x8600:29:2433
1415499238231,5cyclictest3535-21qemu-system-x8600:29:2433
1415499238222,11cyclictest0-21swapper/3923:04:5233
1415499238222,11cyclictest0-21swapper/3923:04:5233
1415499238221,10cyclictest0-21swapper/3923:30:1533
1415499238221,10cyclictest0-21swapper/3923:30:1533
1415499236211,15cyclictest0-21swapper/3900:20:1933
1415499236211,15cyclictest0-21swapper/3900:20:1933
1415499236211,15cyclictest0-21swapper/3900:20:1933
1415499233221,5cyclictest3610-21CPU33
1415499233221,5cyclictest3610-21CPU33
1415499227220,5cyclictest2454-21CPU33
1415499227220,5cyclictest2454-21CPU33
1412499225221,2cyclictest0-21swapper/920:55:0539
14143992243,5cyclictest4408-21CPU21
14143992243,5cyclictest4408-21CPU21
1415499222206,14cyclictest0-21swapper/3900:35:2033
1415499222206,14cyclictest0-21swapper/3900:35:2033
1415499221215,4cyclictest0-21swapper/3922:26:3733
1415499221215,4cyclictest0-21swapper/3922:26:3733
14143992217,4cyclictest3548-21CPU21
14143992217,4cyclictest3548-21CPU21
1411999221215,3cyclictest0-21swapper/422:41:0134
1411999221215,3cyclictest0-21swapper/422:41:0034
14143992192,4cyclictest4408-21CPU21
14143992192,4cyclictest4408-21CPU21
1411999219212,5cyclictest0-21swapper/420:55:0534
1415499216208,5cyclictest0-21swapper/3922:45:1533
1415499216208,5cyclictest0-21swapper/3922:45:1533
1415499214207,5cyclictest0-21swapper/3923:05:1933
1415499214207,5cyclictest0-21swapper/3923:05:1933
1415499214207,5cyclictest0-21swapper/3923:05:1933
1414999214158,53cyclictest3543-21CPU28
1414999214158,53cyclictest3543-21CPU28
14143992143,5cyclictest37270-21CPU21
14143992143,5cyclictest37270-21CPU21
1415499212207,4cyclictest0-21swapper/3921:40:0233
1415499212207,4cyclictest0-21swapper/3921:40:0233
1415499212206,4cyclictest0-21swapper/3922:23:4933
1415499212206,4cyclictest0-21swapper/3922:23:4933
1415499212202,8cyclictest0-21swapper/3900:04:5433
1415499212202,8cyclictest0-21swapper/3900:04:5333
1415499212202,8cyclictest0-21swapper/3900:04:5333
1415499211205,4cyclictest0-21swapper/3923:25:1633
1415499211205,4cyclictest0-21swapper/3923:25:1633
1415499210204,4cyclictest0-21swapper/3921:32:1033
1415499210204,4cyclictest0-21swapper/3921:32:0933
14143992103,4cyclictest3610-21CPU21
14143992103,4cyclictest3610-21CPU21
14143992102,6cyclictest3546-21CPU21
14143992102,6cyclictest3546-21CPU21
1412199210202,5cyclictest0-21swapper/622:33:0536
1412199210202,5cyclictest0-21swapper/622:33:0536
1415499208202,4cyclictest0-21swapper/3923:11:3633
1415499208202,4cyclictest0-21swapper/3923:11:3533
1415499208201,5cyclictest0-21swapper/3921:46:2833
1415499208201,5cyclictest0-21swapper/3921:46:2733
1415499208201,5cyclictest0-21swapper/3921:46:2733
14143992082,4cyclictest4407-21CPU21
14143992082,4cyclictest4407-21CPU21
1415499207202,3cyclictest0-21swapper/3922:12:5833
1415499207202,3cyclictest0-21swapper/3922:12:5833
1415499207201,4cyclictest0-21swapper/3923:46:5533
1415499207201,4cyclictest0-21swapper/3923:46:5533
1415499207201,4cyclictest0-21swapper/3923:41:1033
1415499207201,4cyclictest0-21swapper/3923:41:1033
1415499207201,4cyclictest0-21swapper/3922:40:2033
1415499207201,4cyclictest0-21swapper/3922:40:2033
1415499207200,4cyclictest0-21swapper/3921:52:5033
1415499207200,4cyclictest0-21swapper/3921:52:4933
1415499207187,16cyclictest0-21swapper/3923:15:2333
1415499207187,16cyclictest0-21swapper/3923:15:2333
1415499207187,16cyclictest0-21swapper/3923:15:2333
1415499205200,3cyclictest29914-21kill22:52:4833
1415499205200,3cyclictest29914-21kill22:52:4833
1415499205200,3cyclictest29914-21kill22:52:4833
1412899204190,12cyclictest0-21swapper/1300:15:035
1412899204190,12cyclictest0-21swapper/1300:15:035
1415499203196,4cyclictest0-21swapper/3923:20:4633
1415499203196,4cyclictest0-21swapper/3923:20:4533
1415499203196,4cyclictest0-21swapper/3923:20:4533
1415499203189,10cyclictest3543-21CPU33
1415499203189,10cyclictest3543-21CPU33
1415499202198,3cyclictest0-21swapper/3920:28:2133
1415499202197,4cyclictest0-21swapper/3923:35:5333
1415499202197,4cyclictest0-21swapper/3923:35:5233
1415499202194,6cyclictest0-21swapper/3900:06:0133
1415499202194,6cyclictest0-21swapper/3900:06:0133
1415499202194,6cyclictest0-21swapper/3900:06:0133
1415499202193,6cyclictest1360-21systemd-logind00:32:5133
1415499202193,6cyclictest1360-21systemd-logind00:32:5033
1415499202193,6cyclictest1360-21systemd-logind00:32:5033
1415499202191,8cyclictest0-21swapper/3920:15:1833
1415499202191,8cyclictest0-21swapper/3920:15:1833
1415299202199,2cyclictest0-21swapper/3723:28:4331
1415299202199,2cyclictest0-21swapper/3723:28:4331
1414699202189,11cyclictest0-21swapper/3100:38:4525
1414699202189,11cyclictest0-21swapper/3100:38:4525
1411999201170,7cyclictest171rcu_preempt21:29:4534
1411999201170,7cyclictest171rcu_preempt21:29:4534
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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