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2026-03-01 - 07:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Mar 01, 2026 01:02:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1780899330240,88cyclictest373-21kswapd100:07:1826
1780899330240,88cyclictest373-21kswapd100:07:1726
1779099302262,37cyclictest373-21kswapd100:06:448
1779099302262,37cyclictest373-21kswapd100:06:448
17772992381,233cyclictest2454-21CPU1
17772992381,233cyclictest2454-21CPU1
17772992371,2cyclictest0-21swapper/121:41:491
17772992371,2cyclictest0-21swapper/121:41:481
17772992371,233cyclictest0-21swapper/123:40:201
17772992371,233cyclictest0-21swapper/123:40:201
17772992371,233cyclictest0-21swapper/123:40:201
17772992371,233cyclictest0-21swapper/123:11:101
17772992371,233cyclictest0-21swapper/123:11:091
17772992331,229cyclictest28507-21bash21:30:241
17772992331,229cyclictest28507-21bash21:30:241
17772992321,227cyclictest0-21swapper/119:55:011
17772992321,227cyclictest0-21swapper/119:55:011
17772992311,227cyclictest0-21swapper/122:49:571
17772992311,227cyclictest0-21swapper/122:49:571
17772992311,227cyclictest0-21swapper/122:49:571
17772992303,221cyclictest37269-21CPU1
17772992303,221cyclictest37269-21CPU1
17772992291,222cyclictest0-21swapper/120:50:021
17772992291,222cyclictest0-21swapper/120:50:011
17772992290,2cyclictest0-21swapper/122:02:251
17772992290,2cyclictest0-21swapper/122:02:251
17772992290,2cyclictest0-21swapper/122:02:251
17772992281,221cyclictest0-21swapper/100:05:121
17772992281,221cyclictest0-21swapper/100:05:121
17772992280,2cyclictest0-21swapper/121:25:211
17772992280,2cyclictest0-21swapper/121:25:201
17772992280,2cyclictest0-21swapper/121:25:201
17772992262,2cyclictest1-21systemd00:28:551
17772992262,2cyclictest1-21systemd00:28:551
17772992262,2cyclictest1-21systemd00:28:551
17772992261,221cyclictest0-21swapper/123:28:111
17772992261,221cyclictest0-21swapper/123:28:111
17772992241,219cyclictest0-21swapper/122:55:171
17772992241,219cyclictest0-21swapper/122:55:161
17772992241,219cyclictest0-21swapper/122:55:161
17772992240,3cyclictest38672-21sshd00:21:051
17772992240,3cyclictest38672-21sshd00:21:041
17772992240,3cyclictest38672-21sshd00:21:041
17772992240,2cyclictest0-21swapper/122:41:371
17772992240,2cyclictest0-21swapper/122:41:361
17772992231,219cyclictest0-21swapper/123:20:181
17772992231,219cyclictest0-21swapper/123:20:181
17772992231,218cyclictest0-21swapper/122:29:411
17772992231,218cyclictest0-21swapper/122:29:411
17772992231,217cyclictest0-21swapper/100:35:181
17772992231,217cyclictest0-21swapper/100:35:181
17772992221,2cyclictest0-21swapper/121:17:021
17772992221,2cyclictest0-21swapper/121:17:021
17772992211,2cyclictest0-21swapper/123:40:011
17772992211,2cyclictest0-21swapper/123:40:011
17772992211,2cyclictest0-21swapper/122:11:471
17772992211,2cyclictest0-21swapper/122:11:471
17772992211,2cyclictest0-21swapper/122:11:471
17772992211,217cyclictest0-21swapper/121:49:101
17772992211,217cyclictest0-21swapper/121:49:101
17772992211,217cyclictest0-21swapper/121:35:151
17772992211,217cyclictest0-21swapper/121:35:151
17772992211,215cyclictest0-21swapper/123:01:321
17772992211,215cyclictest0-21swapper/123:01:321
17772992211,215cyclictest0-21swapper/123:01:321
17772992211,214cyclictest2447-21CPU1
17772992211,214cyclictest2447-21CPU1
17772992211,214cyclictest0-21swapper/120:15:171
17772992211,214cyclictest0-21swapper/120:15:171
17772992210,2cyclictest0-21swapper/123:05:431
17772992210,2cyclictest0-21swapper/123:05:431
17772992210,2cyclictest0-21swapper/123:05:431
17772992210,2cyclictest0-21swapper/120:23:131
17772992210,2cyclictest0-21swapper/120:23:121
17772992201,2cyclictest0-21swapper/123:59:021
17772992201,2cyclictest0-21swapper/123:59:011
17772992201,2cyclictest0-21swapper/123:59:011
17772992201,2cyclictest0-21swapper/121:21:531
17772992201,2cyclictest0-21swapper/121:21:521
17772992201,2cyclictest0-21swapper/121:21:521
17772992201,216cyclictest0-21swapper/100:34:331
17772992201,216cyclictest0-21swapper/100:34:331
17772992201,215cyclictest0-21swapper/100:03:371
17772992201,215cyclictest0-21swapper/100:03:361
17772992201,215cyclictest0-21swapper/100:03:361
17772992191,215cyclictest0-21swapper/122:39:301
17772992191,215cyclictest0-21swapper/122:39:301
17772992180,2cyclictest0-21swapper/122:07:451
17772992180,2cyclictest0-21swapper/122:07:451
17772992180,2cyclictest0-21swapper/122:07:451
17772992171,2cyclictest0-21swapper/121:00:451
17772992171,2cyclictest0-21swapper/121:00:441
17772992171,2cyclictest0-21swapper/100:19:371
17772992171,2cyclictest0-21swapper/100:19:371
17772992171,213cyclictest0-21swapper/122:20:191
17772992171,213cyclictest0-21swapper/122:20:191
17772992171,208cyclictest1367-21dbus-daemon22:50:141
17772992171,208cyclictest1367-21dbus-daemon22:50:141
17772992171,208cyclictest1367-21dbus-daemon22:50:141
17772992170,2cyclictest0-21swapper/119:17:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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