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2026-01-15 - 07:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Jan 15, 2026 01:00:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
881999227222,3cyclictest0-21swapper/822:00:1138
881999227222,3cyclictest0-21swapper/822:00:1138
885199226206,17cyclictest0-21swapper/3600:20:1930
885199226206,17cyclictest0-21swapper/3600:20:1930
885199226206,17cyclictest0-21swapper/3600:20:1930
885199215209,3cyclictest23194-21systemd-cgroups00:35:2230
885199215209,3cyclictest23194-21systemd-cgroups00:35:2230
885199214207,5cyclictest0-21swapper/3600:05:1930
885199214207,5cyclictest0-21swapper/3600:05:1930
885199211203,4cyclictest1392-21gdbus00:27:1430
885199211203,4cyclictest1392-21gdbus00:27:1330
883199211193,15cyclictest0-21swapper/1922:15:2311
883199211193,15cyclictest0-21swapper/1922:15:2311
885199210202,5cyclictest0-21swapper/3620:15:1430
885199210202,5cyclictest0-21swapper/3620:15:1330
883199209203,4cyclictest0-21swapper/1922:56:3011
883199209203,4cyclictest0-21swapper/1922:56:3011
883199209203,4cyclictest0-21swapper/1922:56:3011
883199208197,7cyclictest3547-21CPU11
883199208197,7cyclictest3547-21CPU11
885199206201,4cyclictest0-21swapper/3600:11:3130
885199206201,4cyclictest0-21swapper/3600:11:3130
885199206201,4cyclictest0-21swapper/3600:11:3130
883199206198,5cyclictest0-21swapper/1922:10:1811
883199206198,5cyclictest0-21swapper/1922:10:1811
883199206198,5cyclictest0-21swapper/1922:10:1811
885199205197,5cyclictest0-21swapper/3621:26:5030
885199205197,5cyclictest0-21swapper/3621:26:5030
883199205197,5cyclictest0-21swapper/1922:00:1011
883199205197,5cyclictest0-21swapper/1922:00:1011
885199203197,4cyclictest0-21swapper/3620:02:2030
885199203197,4cyclictest0-21swapper/3620:02:2030
885199202196,4cyclictest0-21swapper/3620:40:0130
885199202194,4cyclictest3543-21CPU30
885199202194,4cyclictest3543-21CPU30
885199202191,9cyclictest0-21swapper/3620:07:0430
885199202191,9cyclictest0-21swapper/3620:07:0430
883199202194,6cyclictest0-21swapper/1923:30:1311
883199202194,6cyclictest0-21swapper/1923:30:1311
883199202192,7cyclictest0-21swapper/1923:10:1311
883199202192,7cyclictest0-21swapper/1923:10:1311
883199202192,7cyclictest0-21swapper/1923:10:1211
883199201191,5cyclictest2462-21CPU11
883199201191,5cyclictest2462-21CPU11
883199200195,4cyclictest0-21swapper/1923:17:5211
883199200195,4cyclictest0-21swapper/1923:17:5211
883199200195,4cyclictest0-21swapper/1923:04:3411
883199200195,4cyclictest0-21swapper/1923:04:3411
883199200195,4cyclictest0-21swapper/1923:04:3411
883199200194,5cyclictest0-21swapper/1923:52:4411
883199200194,5cyclictest0-21swapper/1923:52:4411
883199200194,5cyclictest0-21swapper/1923:52:4411
883199200194,4cyclictest0-21swapper/1923:38:4911
883199200194,4cyclictest0-21swapper/1923:38:4911
883199200194,3cyclictest0-21swapper/1922:53:3511
883199200194,3cyclictest0-21swapper/1922:53:3511
883199200194,3cyclictest0-21swapper/1922:53:3511
885199199193,4cyclictest1367-21dbus-daemon21:21:5830
885199199193,4cyclictest1367-21dbus-daemon21:21:5830
883199199194,4cyclictest0-21swapper/1921:47:2811
883199199194,4cyclictest0-21swapper/1921:47:2711
883199199194,4cyclictest0-21swapper/1921:47:2711
883199199192,5cyclictest0-21swapper/1919:45:2211
883199199192,5cyclictest0-21swapper/1919:45:2211
883199199188,8cyclictest0-21swapper/1900:04:5611
883199199188,8cyclictest0-21swapper/1900:04:5611
883199199188,8cyclictest0-21swapper/1900:04:5611
885199198194,2cyclictest1948-21sshd21:33:0330
885199198194,2cyclictest1948-21sshd21:33:0330
885199198194,2cyclictest1948-21sshd21:33:0330
885199198189,5cyclictest37269-21CPU30
885199198189,5cyclictest37269-21CPU30
883199198192,4cyclictest0-21swapper/1922:34:3611
883199198192,4cyclictest0-21swapper/1922:34:3611
885199197192,4cyclictest0-21swapper/3620:10:1230
885199197192,4cyclictest0-21swapper/3620:10:1230
885199197192,4cyclictest0-21swapper/3619:19:5430
885199197192,4cyclictest0-21swapper/3619:19:5430
883199197192,4cyclictest0-21swapper/1919:40:1911
885199196190,5cyclictest0-21swapper/3621:15:1330
885199196190,5cyclictest0-21swapper/3621:15:1330
885199196188,6cyclictest0-21swapper/3600:32:4630
885199196188,6cyclictest0-21swapper/3600:32:4630
883199196190,5cyclictest0-21swapper/1922:06:4011
883199196190,5cyclictest0-21swapper/1922:06:4011
883199196187,5cyclictest37351-21CPU11
883199196187,5cyclictest37351-21CPU11
882899196187,7cyclictest0-21swapper/1620:15:358
882899196187,7cyclictest0-21swapper/1620:15:358
885199195187,5cyclictest0-21swapper/3621:11:3830
885199195187,5cyclictest0-21swapper/3621:11:3830
885199195185,8cyclictest0-21swapper/3621:39:0330
885199195185,8cyclictest0-21swapper/3621:39:0330
883199195187,6cyclictest0-21swapper/1919:23:2011
883199195187,6cyclictest0-21swapper/1919:23:2011
884599194184,7cyclictest0-21swapper/3100:20:1625
884599194184,7cyclictest0-21swapper/3100:20:1625
884599194184,7cyclictest0-21swapper/3100:20:1625
883699194177,3cyclictest171rcu_preempt22:26:1915
883699194177,3cyclictest171rcu_preempt22:26:1815
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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