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2026-01-20 - 08:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Jan 20, 2026 01:00:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
928999249240,7cyclictest0-21swapper/800:00:1338
928999249240,7cyclictest0-21swapper/800:00:1338
928999249240,7cyclictest0-21swapper/800:00:1338
932299224214,5cyclictest2464-21CPU30
932299224214,5cyclictest2464-21CPU30
932299221215,4cyclictest0-21swapper/3621:35:2130
932299221215,4cyclictest0-21swapper/3621:35:2130
932299221215,4cyclictest0-21swapper/3621:35:2130
932299220213,5cyclictest0-21swapper/3623:49:2130
932299220213,5cyclictest0-21swapper/3623:49:2130
932299220211,6cyclictest0-21swapper/3622:48:1030
932299220211,6cyclictest0-21swapper/3622:48:1030
932299219211,6cyclictest0-21swapper/3621:28:5030
932299219211,6cyclictest0-21swapper/3621:28:5030
932299219210,4cyclictest2459-21CPU30
932299219210,4cyclictest2459-21CPU30
932299216210,4cyclictest0-21swapper/3600:35:4930
932299216210,4cyclictest0-21swapper/3600:35:4930
932299215207,6cyclictest0-21swapper/3623:40:1930
932299215207,6cyclictest0-21swapper/3623:40:1930
931199214207,5cyclictest0-21swapper/2620:45:2119
931199214207,5cyclictest0-21swapper/2620:45:2119
932299213207,4cyclictest0-21swapper/3621:03:1830
932299213207,4cyclictest0-21swapper/3621:03:1830
932299213195,9cyclictest0-21swapper/3623:10:0430
932299213195,9cyclictest0-21swapper/3623:10:0430
932299212205,5cyclictest0-21swapper/3622:11:5230
932299212205,5cyclictest0-21swapper/3622:11:5230
932299212205,5cyclictest0-21swapper/3622:11:5230
932299210204,4cyclictest0-21swapper/3622:41:2030
932299210204,4cyclictest0-21swapper/3622:41:2030
932299210201,6cyclictest0-21swapper/3621:53:3730
932299210201,6cyclictest0-21swapper/3621:53:3730
932299210201,6cyclictest0-21swapper/3621:53:3730
932299209198,8cyclictest0-21swapper/3623:10:1130
932299209198,8cyclictest0-21swapper/3623:10:1130
932299209198,8cyclictest0-21swapper/3623:10:1130
932299209189,14cyclictest0-21swapper/3622:55:1430
932299209189,14cyclictest0-21swapper/3622:55:1430
932299207202,3cyclictest0-21swapper/3623:50:1830
932299207202,3cyclictest0-21swapper/3623:50:1830
932299207202,3cyclictest0-21swapper/3623:50:1830
932299207201,4cyclictest0-21swapper/3623:02:2730
932299207201,4cyclictest0-21swapper/3623:02:2730
932299207201,4cyclictest0-21swapper/3623:02:2730
932299207197,8cyclictest0-21swapper/3623:57:3430
932299207197,8cyclictest0-21swapper/3623:57:3330
932299207197,8cyclictest0-21swapper/3623:57:3330
932299205197,6cyclictest0-21swapper/3600:34:1430
932299205197,6cyclictest0-21swapper/3600:34:1430
932299205192,7cyclictest0-21swapper/3620:15:2230
932299205192,7cyclictest0-21swapper/3620:15:2230
931999205195,8cyclictest0-21swapper/3323:22:2227
931999205195,8cyclictest0-21swapper/3323:22:2227
931999205195,8cyclictest0-21swapper/3323:22:2227
932299204198,5cyclictest0-21swapper/3620:50:1430
932299204198,5cyclictest0-21swapper/3620:50:1430
9312992043,194cyclictest4408-21CPU20
9312992043,194cyclictest4408-21CPU20
928999204188,10cyclictest0-21swapper/800:15:2638
928999204188,10cyclictest0-21swapper/800:15:2638
932299203192,8cyclictest24359-21bash21:30:2030
932299203192,8cyclictest24359-21bash21:30:2030
932299202196,4cyclictest0-21swapper/3623:27:5830
932299202196,4cyclictest0-21swapper/3623:27:5830
932299202196,4cyclictest0-21swapper/3623:27:5830
932299202194,6cyclictest0-21swapper/3622:05:1830
932299202194,6cyclictest0-21swapper/3622:05:1830
932299202194,6cyclictest0-21swapper/3622:05:1830
932299202192,3cyclictest0-21swapper/3621:25:0130
932299202192,3cyclictest0-21swapper/3621:25:0130
932299202192,3cyclictest0-21swapper/3621:25:0130
931199202188,11cyclictest0-21swapper/2621:57:1219
931199202188,11cyclictest0-21swapper/2621:57:1219
932299199193,3cyclictest37269-21CPU30
928999199188,6cyclictest0-21swapper/800:10:2238
928999199188,6cyclictest0-21swapper/800:10:2238
928999199188,6cyclictest0-21swapper/800:10:2238
928799199146,45cyclictest0-21swapper/623:10:1436
928799199146,45cyclictest0-21swapper/623:10:1436
928799199146,45cyclictest0-21swapper/623:10:1436
932299198193,4cyclictest0-21swapper/3621:14:2830
932299198193,4cyclictest0-21swapper/3621:14:2830
932299198193,4cyclictest0-21swapper/3621:14:2830
931199198174,15cyclictest0-21swapper/2619:37:4419
932299197188,5cyclictest0-21swapper/3620:20:1730
932299197188,5cyclictest0-21swapper/3620:20:1730
932299196190,4cyclictest0-21swapper/3622:39:3230
932299196190,4cyclictest0-21swapper/3622:39:3230
932299195191,2cyclictest0-21swapper/3619:17:0930
932299195191,2cyclictest0-21swapper/3619:17:0930
932299195183,8cyclictest0-21swapper/3623:31:1430
932299195183,8cyclictest0-21swapper/3623:31:1430
932299195183,8cyclictest0-21swapper/3619:20:3630
932299195183,8cyclictest0-21swapper/3619:20:3630
932099195191,2cyclictest0-21swapper/3419:10:1428
932099195191,2cyclictest0-21swapper/3419:10:1428
928999195186,6cyclictest0-21swapper/822:22:5038
928999195186,6cyclictest0-21swapper/822:22:5038
928999195186,6cyclictest0-21swapper/822:22:5038
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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