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2026-01-17 - 09:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Jan 17, 2026 00:59:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2003899198147,35cyclictest0-21swapper/822:55:2138
2003899198147,35cyclictest0-21swapper/822:55:2138
2003899198147,35cyclictest0-21swapper/822:55:2138
2005699195168,26cyclictest0-21swapper/2400:17:4817
2005699195168,26cyclictest0-21swapper/2400:17:4817
2003599187138,41cyclictest4408-21CPU35
2003599187138,41cyclictest4408-21CPU35
2003599187138,41cyclictest4408-21CPU35
2003599185170,12cyclictest0-21swapper/523:21:4935
2003599185170,12cyclictest0-21swapper/523:21:4935
2003599184150,29cyclictest0-21swapper/523:44:2635
2003599184150,29cyclictest0-21swapper/523:44:2635
2003599184146,34cyclictest0-21swapper/522:03:3035
2003599184146,34cyclictest0-21swapper/522:03:3035
20042991821,88cyclictest0-21swapper/1200:10:184
20042991821,88cyclictest0-21swapper/1200:10:184
20038991820,121cyclictest0-21swapper/820:20:0038
20038991820,121cyclictest0-21swapper/820:20:0038
2003299181151,11cyclictest0-21swapper/321:14:5523
2003299181151,11cyclictest0-21swapper/321:14:5523
20050991804,99cyclictest37356-21CPU10
20050991804,99cyclictest37356-21CPU10
20043991801,174cyclictest0-21swapper/1300:05:015
20043991801,174cyclictest0-21swapper/1300:05:015
20072991791,4cyclictest37346-21qemu-system-x8622:35:1130
20072991791,4cyclictest37346-21qemu-system-x8622:35:1130
2005699179164,12cyclictest17483-21nfsd21:17:2017
2005699179164,12cyclictest17483-21nfsd21:17:2017
20050991791,157cyclictest0-21swapper/1821:07:1810
20050991791,157cyclictest0-21swapper/1821:07:1710
2004799177172,3cyclictest0-21swapper/1523:00:217
2004799177172,3cyclictest0-21swapper/1523:00:217
2006699176149,11cyclictest0-21swapper/3321:14:5527
2006699176149,11cyclictest0-21swapper/3321:14:5427
200659917675,88cyclictest3541-21CPU26
200659917675,88cyclictest3541-21CPU26
200659917675,88cyclictest3541-21CPU26
20062991761,6cyclictest1367-21dbus-daemon00:10:1822
20062991761,6cyclictest1367-21dbus-daemon00:10:1822
2003899176148,22cyclictest0-21swapper/823:27:5638
2003899176148,22cyclictest0-21swapper/823:27:5538
2003899176148,22cyclictest0-21swapper/823:27:5538
20035991762,126cyclictest3545-21CPU35
20035991762,126cyclictest3545-21CPU35
20072991751,92cyclictest0-21swapper/3620:15:2130
20072991751,92cyclictest0-21swapper/3620:15:2130
2006699175166,7cyclictest0-21swapper/3319:19:0427
2006699175166,7cyclictest0-21swapper/3319:19:0427
200589917514,108cyclictest37351-21CPU19
200589917514,108cyclictest37351-21CPU19
2003599175125,35cyclictest0-21swapper/523:26:1435
2003599175125,35cyclictest0-21swapper/523:26:1435
2003599175125,35cyclictest0-21swapper/523:26:1435
200759917470,92cyclictest2447-21CPU33
200759917470,92cyclictest2447-21CPU33
2006699174142,13cyclictest0-21swapper/3322:45:3927
2006699174142,13cyclictest0-21swapper/3322:45:3927
2006699174108,61cyclictest3545-21CPU27
2006699174108,61cyclictest3545-21CPU27
2006699174108,61cyclictest3545-21CPU27
200389917485,79cyclictest0-21swapper/800:05:1438
200389917485,79cyclictest0-21swapper/800:05:1438
2003799174163,6cyclictest0-21swapper/700:39:4437
2003799174163,6cyclictest0-21swapper/700:39:4437
2003599174163,9cyclictest0-21swapper/523:00:1135
2003599174163,9cyclictest0-21swapper/523:00:1135
20035991741,161cyclictest0-21swapper/522:52:2335
20035991741,161cyclictest0-21swapper/522:52:2335
2006699173149,5cyclictest0-21swapper/3319:26:5127
2006699173149,5cyclictest0-21swapper/3319:26:5127
2005299173166,4cyclictest2466-21CPU13
2005299173166,4cyclictest2466-21CPU13
2005199173165,4cyclictest0-21swapper/1921:33:2911
2005199173165,4cyclictest0-21swapper/1921:33:2911
2005199173165,4cyclictest0-21swapper/1921:33:2811
2003099173164,6cyclictest0-21swapper/122:37:271
2003099173164,6cyclictest0-21swapper/122:37:271
20041991721,3cyclictest0-21swapper/1100:05:203
20041991721,3cyclictest0-21swapper/1100:05:203
2003599172144,26cyclictest0-21swapper/523:48:3635
2003599172144,26cyclictest0-21swapper/523:48:3635
20035991720,165cyclictest26631-21sshd00:10:0135
20035991720,165cyclictest26631-21sshd00:10:0035
2003299172159,9cyclictest24952-21packagekitd23:16:1423
2003299172159,9cyclictest24952-21packagekitd23:16:1423
2007499171160,7cyclictest17484-21nfsd19:19:5932
2007499171160,7cyclictest17484-21nfsd19:19:5932
20072991711,5cyclictest0-21swapper/3600:00:2230
20072991711,5cyclictest0-21swapper/3600:00:2230
2006499171157,11cyclictest0-21swapper/3119:17:5825
2006499171157,11cyclictest0-21swapper/3119:17:5825
2004299171113,54cyclictest0-21swapper/1222:44:114
2004299171113,54cyclictest0-21swapper/1222:44:114
2003899171132,35cyclictest0-21swapper/823:13:0738
2003899171132,35cyclictest0-21swapper/823:13:0738
2003899171132,35cyclictest0-21swapper/823:13:0738
2006599170158,10cyclictest0-21swapper/3222:56:3426
2006599170158,10cyclictest0-21swapper/3222:56:3426
2006599170158,10cyclictest0-21swapper/3222:56:3426
2005699170154,8cyclictest0-21swapper/2422:06:0117
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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