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2026-03-30 - 08:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Mar 30, 2026 01:02:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1753599219210,7cyclictest4410-21qemu-system-x8621:12:3936
1753599219210,7cyclictest4410-21qemu-system-x8621:12:3936
1757199215204,8cyclictest35270-21sshd21:59:2731
1757199215204,8cyclictest35270-21sshd21:59:2731
1757199214208,5cyclictest0-21swapper/3700:24:2531
1757199214208,5cyclictest0-21swapper/3700:24:2531
1757199214208,5cyclictest0-21swapper/3700:24:2531
1754299211204,5cyclictest0-21swapper/1321:17:025
1754299211204,5cyclictest0-21swapper/1321:17:015
1753899211171,37cyclictest0-21swapper/923:25:3839
1753899211171,37cyclictest0-21swapper/923:25:3739
1753899211171,37cyclictest0-21swapper/923:25:3739
1757199210202,5cyclictest0-21swapper/3721:52:5031
1757199210202,5cyclictest0-21swapper/3721:52:5031
1757199210199,6cyclictest3543-21CPU31
1757199210199,6cyclictest3543-21CPU31
1757199208201,5cyclictest0-21swapper/3700:29:1131
1757199208201,5cyclictest0-21swapper/3700:29:1031
1757199208201,5cyclictest0-21swapper/3700:29:1031
1757199207200,5cyclictest0-21swapper/3722:07:0031
1757199207200,5cyclictest0-21swapper/3722:07:0031
1757199207200,5cyclictest0-21swapper/3722:07:0031
1757199207200,5cyclictest0-21swapper/3700:33:5731
1757199207200,5cyclictest0-21swapper/3700:33:5631
1757199207200,5cyclictest0-21swapper/3700:33:5631
1755099206203,2cyclictest0-21swapper/1919:40:1911
1753599206114,89cyclictest3610-21CPU36
1753599206114,89cyclictest3610-21CPU36
1753599206114,89cyclictest3610-21CPU36
1757199204196,6cyclictest0-21swapper/3700:37:2531
1757199204196,6cyclictest0-21swapper/3700:37:2531
1757199204196,6cyclictest0-21swapper/3700:37:2531
1753599204193,9cyclictest0-21swapper/622:48:1636
1753599204193,9cyclictest0-21swapper/622:48:1536
1757199203198,3cyclictest1-21systemd21:37:3631
1757199203198,3cyclictest1-21systemd21:37:3631
1757199203194,7cyclictest0-21swapper/3722:50:1631
1757199203194,7cyclictest0-21swapper/3722:50:1531
1757199202197,4cyclictest0-21swapper/3722:32:1631
1757199202197,4cyclictest0-21swapper/3722:32:1631
1757199202197,4cyclictest0-21swapper/3722:32:1631
1757199202196,4cyclictest0-21swapper/3721:05:1531
1757199202196,4cyclictest0-21swapper/3721:05:1531
1757199202194,6cyclictest0-21swapper/3722:35:1731
1757199202194,6cyclictest0-21swapper/3722:35:1731
1757199202192,7cyclictest1367-21dbus-daemon21:30:1831
1757199202192,7cyclictest1367-21dbus-daemon21:30:1831
1757199202177,23cyclictest0-21swapper/3722:40:2231
1757199202177,23cyclictest0-21swapper/3722:40:2131
1757199201196,4cyclictest0-21swapper/3721:18:0131
1757199201196,4cyclictest0-21swapper/3721:18:0131
1753599201194,6cyclictest0-21swapper/621:37:4236
1753599201194,6cyclictest0-21swapper/621:37:4236
1757199200194,4cyclictest0-21swapper/3722:18:0031
1757199200194,4cyclictest0-21swapper/3722:18:0031
1757199200194,4cyclictest0-21swapper/3721:49:0931
1757199200194,4cyclictest0-21swapper/3721:49:0831
1757199200192,4cyclictest2464-21CPU31
1757199200192,4cyclictest2464-21CPU31
1757199199195,2cyclictest0-21swapper/3722:20:1331
1757199199195,2cyclictest0-21swapper/3722:20:1331
1757199199195,2cyclictest0-21swapper/3722:20:1231
1754799199191,5cyclictest3541-21CPU9
1754799199191,5cyclictest3541-21CPU9
1754799199191,5cyclictest3541-21CPU9
1754299199186,9cyclictest37352-21CPU5
1754299199186,9cyclictest37352-21CPU5
1753599199190,8cyclictest0-21swapper/600:22:1236
1753599199190,8cyclictest0-21swapper/600:22:1236
1753599199190,8cyclictest0-21swapper/600:22:1236
1756199198181,13cyclictest0-21swapper/2821:49:5621
1756199198181,13cyclictest0-21swapper/2821:49:5621
1755699198193,3cyclictest0-21swapper/2323:10:1716
1755699198193,3cyclictest0-21swapper/2323:10:1716
1755699198193,3cyclictest0-21swapper/2323:10:1716
1753599198190,6cyclictest0-21swapper/622:03:0136
1753599198190,6cyclictest0-21swapper/622:03:0036
1757199197192,4cyclictest0-21swapper/3721:22:1331
1757199197192,4cyclictest0-21swapper/3721:22:1331
1757199197174,14cyclictest0-21swapper/3722:29:5831
1757199197174,14cyclictest0-21swapper/3722:29:5731
1753599197188,8cyclictest0-21swapper/600:09:3436
1753599197188,8cyclictest0-21swapper/600:09:3436
1757199196185,8cyclictest21921-21latency_hist00:15:0231
1757199196185,8cyclictest21921-21latency_hist00:15:0231
1755999196138,53cyclictest2447-21CPU19
1755999196138,53cyclictest2447-21CPU19
1753599196131,62cyclictest37355-21CPU36
1753599196131,62cyclictest37355-21CPU36
1753599196131,62cyclictest37355-21CPU36
1757199195182,4cyclictest3610-21CPU31
1757199195182,4cyclictest3610-21CPU31
1757199195182,4cyclictest3610-21CPU31
17559991951,86cyclictest0-21swapper/2600:30:1519
17559991951,86cyclictest0-21swapper/2600:30:1419
17559991951,86cyclictest0-21swapper/2600:30:1419
1753199195192,2cyclictest0-21swapper/222:16:3712
1753199195192,2cyclictest0-21swapper/222:16:3712
1757199194188,5cyclictest0-21swapper/3721:12:0631
1757199194188,5cyclictest0-21swapper/3721:12:0631
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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