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2026-09-02 - 12:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Sep 02, 2026 01:01:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26255992331,228cyclictest0-21swapper/2122:59:2614
26255992331,228cyclictest0-21swapper/2122:59:2614
26255992311,221cyclictest0-21swapper/2123:05:2914
26255992311,221cyclictest0-21swapper/2123:05:2814
26255992291,220cyclictest0-21swapper/2100:35:1914
26255992291,220cyclictest0-21swapper/2100:35:1814
26255992291,220cyclictest0-21swapper/2100:35:1814
26255992272,220cyclictest2466-21CPU14
26255992272,220cyclictest2466-21CPU14
26255992271,214cyclictest0-21swapper/2100:32:2514
26255992271,214cyclictest0-21swapper/2100:32:2514
26255992271,212cyclictest0-21swapper/2100:22:0214
26255992271,212cyclictest0-21swapper/2100:22:0114
26255992271,212cyclictest0-21swapper/2100:22:0114
26255992261,218cyclictest0-21swapper/2123:24:5814
26255992261,218cyclictest0-21swapper/2123:24:5814
26255992240,2cyclictest0-21swapper/2100:02:5314
26255992240,2cyclictest0-21swapper/2100:02:5314
26255992240,219cyclictest2466-21CPU14
26255992240,219cyclictest2466-21CPU14
26255992211,216cyclictest1-21systemd22:19:5414
26255992211,216cyclictest1-21systemd22:19:5414
26255992211,206cyclictest0-21swapper/2123:25:2814
26255992211,206cyclictest0-21swapper/2123:25:2714
26255992211,205cyclictest0-21swapper/2123:33:0614
26255992211,205cyclictest0-21swapper/2123:33:0614
26255992192,207cyclictest3544-21CPU14
26255992192,207cyclictest3544-21CPU14
26255992190,2cyclictest0-21swapper/2121:55:1614
26255992190,2cyclictest0-21swapper/2121:55:1514
26255992180,2cyclictest0-21swapper/2123:20:0114
26255992180,2cyclictest0-21swapper/2123:20:0114
26255992180,215cyclictest0-21swapper/2123:36:1114
26255992180,215cyclictest0-21swapper/2123:36:1114
26255992171,210cyclictest37257-21qemu-system-x8622:45:3314
26255992171,210cyclictest37257-21qemu-system-x8622:45:3214
26255992171,210cyclictest37257-21qemu-system-x8622:45:3214
26255992170,2cyclictest0-21swapper/2100:25:5814
26255992170,2cyclictest0-21swapper/2100:25:5814
26255992170,2cyclictest0-21swapper/2100:25:5714
26255992162,210cyclictest0-21swapper/2123:51:2014
26255992162,210cyclictest0-21swapper/2123:51:1914
26255992160,2cyclictest0-21swapper/2122:30:1814
26255992160,2cyclictest0-21swapper/2122:30:1714
26255992152,200cyclictest37354-21CPU14
26255992152,200cyclictest37354-21CPU14
26255992141,209cyclictest37346-21qemu-system-x8623:41:2514
26255992141,209cyclictest37346-21qemu-system-x8623:41:2514
26255992140,2cyclictest0-21swapper/2122:22:3414
26255992140,2cyclictest0-21swapper/2122:22:3414
26255992140,193cyclictest0-21swapper/2122:00:3714
26255992140,193cyclictest0-21swapper/2122:00:3714
26255992131,209cyclictest29244-21sed00:00:0514
26255992131,209cyclictest29244-21sed00:00:0514
26255992101,203cyclictest0-21swapper/2123:48:3714
26255992101,203cyclictest0-21swapper/2123:48:3614
26255992101,197cyclictest0-21swapper/2100:05:0814
26255992101,197cyclictest0-21swapper/2100:05:0814
26255992100,2cyclictest0-21swapper/2122:53:5214
26255992100,2cyclictest0-21swapper/2122:53:5214
26255992070,203cyclictest0-21swapper/2123:00:3114
26255992070,203cyclictest0-21swapper/2123:00:3114
26255992061,201cyclictest0-21swapper/2122:40:1214
26255992061,201cyclictest0-21swapper/2122:40:1214
26255992031,197cyclictest17484-21nfsd22:27:1214
26255992031,197cyclictest17484-21nfsd22:27:1214
26255992021,189cyclictest0-21swapper/2122:39:5214
26255992021,189cyclictest0-21swapper/2122:39:5214
2627499201189,10cyclictest0-21swapper/3622:10:1630
2627499201189,10cyclictest0-21swapper/3622:10:1630
26255991991,195cyclictest1-21systemd22:14:1614
26255991991,195cyclictest1-21systemd22:14:1614
2625299197113,62cyclictest4408-21CPU10
2625299197113,62cyclictest4408-21CPU10
26255991870,179cyclictest0-21swapper/2121:53:4214
26255991870,179cyclictest0-21swapper/2121:53:4214
2625299184146,33cyclictest0-21swapper/1800:21:0910
2625299184146,33cyclictest0-21swapper/1800:21:0810
2625299184146,33cyclictest0-21swapper/1800:21:0810
2623299184174,8cyclictest0-21swapper/119:40:371
2623299184174,8cyclictest0-21swapper/119:40:361
2627699183168,13cyclictest0-21swapper/3819:30:1232
2627699183168,13cyclictest0-21swapper/3819:30:1232
2623299182170,4cyclictest0-21swapper/123:44:091
2623299182170,4cyclictest0-21swapper/123:44:081
2625299181100,60cyclictest2447-21CPU10
2625299181100,60cyclictest2447-21CPU10
2627699179164,11cyclictest0-21swapper/3822:14:0132
2627699179164,11cyclictest0-21swapper/3822:14:0132
2627499178165,10cyclictest4407-21CPU30
2627499178165,10cyclictest4407-21CPU30
2627499178165,10cyclictest4407-21CPU30
2627699177170,6cyclictest0-21swapper/3800:14:5032
2627699177170,6cyclictest0-21swapper/3800:14:5032
2623299177159,16cyclictest0-21swapper/121:42:421
2623299177159,16cyclictest0-21swapper/121:42:421
2627699176156,15cyclictest0-21swapper/3821:10:2432
2627699176156,15cyclictest0-21swapper/3821:10:2432
2627699175165,7cyclictest0-21swapper/3800:27:1632
2627699175165,7cyclictest0-21swapper/3800:27:1532
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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