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2026-02-05 - 20:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Feb 05, 2026 01:02:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205389920015,178cyclictest0-21swapper/820:20:5938
205389920015,178cyclictest0-21swapper/820:20:5938
2056199198167,15cyclictest171rcu_preempt00:27:5821
2056199198167,15cyclictest171rcu_preempt00:27:5821
2056199198167,15cyclictest171rcu_preempt00:27:5821
2056199196189,5cyclictest0-21swapper/2823:46:1721
2056199196189,5cyclictest0-21swapper/2823:46:1721
20537991961,188cyclictest0-21swapper/722:15:0137
20537991961,188cyclictest0-21swapper/722:15:0137
20537991961,188cyclictest0-21swapper/722:15:0037
2057699189165,20cyclictest0-21swapper/3800:01:5432
2057699189165,20cyclictest0-21swapper/3800:01:5432
2056199186155,28cyclictest0-21swapper/2800:06:1521
2056199186155,28cyclictest0-21swapper/2800:06:1421
2055799186175,9cyclictest0-21swapper/2421:25:3517
2055799186175,9cyclictest0-21swapper/2421:25:3517
2053699185173,10cyclictest0-21swapper/622:34:2936
2053699185173,10cyclictest0-21swapper/622:34:2836
2056199182155,12cyclictest0-21swapper/2821:28:2221
2056199182155,12cyclictest0-21swapper/2821:28:2121
2057299181117,30cyclictest0-21swapper/3621:31:1630
2057299181117,30cyclictest0-21swapper/3621:31:1630
2054999181120,35cyclictest0-21swapper/1720:10:389
2054999181120,35cyclictest0-21swapper/1720:10:389
2053799181128,51cyclictest0-21swapper/721:36:2837
2053799181128,51cyclictest0-21swapper/721:36:2837
2057699179156,12cyclictest0-21swapper/3821:35:4432
2057699179156,12cyclictest0-21swapper/3821:35:4432
2057299179134,20cyclictest0-21swapper/3623:35:3930
2057299179134,20cyclictest0-21swapper/3623:35:3830
2057299179134,20cyclictest0-21swapper/3623:35:3830
2056199179162,8cyclictest0-21swapper/2822:03:2221
2056199179162,8cyclictest0-21swapper/2822:03:2221
2055799179172,3cyclictest0-21swapper/2400:09:5617
2055799179172,3cyclictest0-21swapper/2400:09:5617
205509917993,79cyclictest2454-21CPU10
205509917993,79cyclictest2454-21CPU10
2054999179129,27cyclictest0-21swapper/1721:37:309
2054999179129,27cyclictest0-21swapper/1721:37:299
2057299178154,10cyclictest171rcu_preempt22:11:5830
2057299178154,10cyclictest171rcu_preempt22:11:5830
2057299178154,10cyclictest171rcu_preempt22:11:5830
2057299177151,14cyclictest171rcu_preempt19:22:5030
2057299177151,14cyclictest171rcu_preempt19:22:5030
2057299177110,60cyclictest3548-21CPU30
2057299177110,60cyclictest3548-21CPU30
20537991771,173cyclictest0-21swapper/721:22:3037
20537991771,173cyclictest0-21swapper/721:22:3037
2057299176134,21cyclictest0-21swapper/3623:59:3630
2057299176134,21cyclictest0-21swapper/3623:59:3630
2057299176125,18cyclictest0-21swapper/3623:44:4630
2057299176125,18cyclictest0-21swapper/3623:44:4630
205769917594,70cyclictest3548-21CPU32
205769917594,70cyclictest3548-21CPU32
2057699175109,61cyclictest2447-21CPU32
2057699175109,61cyclictest2447-21CPU32
2057699175109,61cyclictest2447-21CPU32
2057299175111,50cyclictest0-21swapper/3622:04:5330
2057299175111,50cyclictest0-21swapper/3622:04:5230
2055499175161,6cyclictest0-21swapper/2100:05:2214
2055499175161,6cyclictest0-21swapper/2100:05:2214
205379917595,74cyclictest0-21swapper/700:00:5037
205379917595,74cyclictest0-21swapper/700:00:5037
2057299174156,7cyclictest171rcu_preempt23:54:4530
2057299174156,7cyclictest171rcu_preempt23:54:4430
2057299174156,7cyclictest171rcu_preempt23:54:4430
2057299174125,15cyclictest0-21swapper/3621:44:4130
2057299174125,15cyclictest0-21swapper/3621:44:4130
2057299174125,15cyclictest0-21swapper/3621:44:4030
2054299174168,4cyclictest0-21swapper/1123:03:413
2054299174168,4cyclictest0-21swapper/1123:03:413
2057299173165,5cyclictest0-21swapper/3621:21:4930
2057299173165,5cyclictest0-21swapper/3621:21:4930
2057799172164,6cyclictest0-21swapper/3923:17:3333
2057799172164,6cyclictest0-21swapper/3923:17:3333
2057799172164,6cyclictest0-21swapper/3923:17:3233
2057699172159,11cyclictest0-21swapper/3800:18:1732
2057699172159,11cyclictest0-21swapper/3800:18:1732
2057699172159,11cyclictest0-21swapper/3800:18:1732
2057699172144,20cyclictest0-21swapper/3819:21:3832
2057699172144,20cyclictest0-21swapper/3819:21:3732
2056199172154,15cyclictest0-21swapper/2819:20:0621
2056199172154,15cyclictest0-21swapper/2819:20:0521
2054999172117,28cyclictest0-21swapper/1719:28:239
2054999172117,28cyclictest0-21swapper/1719:28:229
2057299171149,10cyclictest171rcu_preempt00:21:5930
2057299171149,10cyclictest171rcu_preempt00:21:5930
2057299171149,10cyclictest171rcu_preempt00:21:5830
2057299171122,17cyclictest0-21swapper/3600:04:0630
2057299171122,17cyclictest0-21swapper/3600:04:0630
2055999171113,54cyclictest3609-21CPU19
2055999171113,54cyclictest3609-21CPU19
2053699171160,9cyclictest0-21swapper/619:26:0136
2053699171160,9cyclictest0-21swapper/619:26:0136
2057299170120,31cyclictest0-21swapper/3623:12:1530
2057299170120,31cyclictest0-21swapper/3623:12:1530
2055499170163,5cyclictest0-21swapper/2100:10:2114
2055499170163,5cyclictest0-21swapper/2100:10:2114
2055099170107,48cyclictest37806-21systemctl22:38:4710
2055099170107,48cyclictest37806-21systemctl22:38:4710
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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