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2026-09-17 - 23:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Sep 17, 2026 13:02:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2409099282272,4cyclictest2456-21CPU36
2409099282272,4cyclictest2456-21CPU36
24122992611,2cyclictest0-21swapper/3312:10:1927
24122992611,2cyclictest0-21swapper/3312:10:1927
24122992610,8cyclictest3535-21qemu-system-x8610:30:2227
24122992610,8cyclictest3535-21qemu-system-x8610:30:2227
24122992571,245cyclictest0-21swapper/3309:15:4127
24122992571,245cyclictest0-21swapper/3309:15:4127
24122992571,245cyclictest0-21swapper/3309:15:4127
24122992561,3cyclictest0-21swapper/3309:45:2227
24122992561,3cyclictest0-21swapper/3309:45:2127
24122992541,3cyclictest17481-21nfsd11:00:1527
24122992541,3cyclictest17481-21nfsd11:00:1427
24122992541,3cyclictest17481-21nfsd11:00:1427
24122992531,246cyclictest0-21swapper/3310:00:1927
24122992531,246cyclictest0-21swapper/3310:00:1827
24122992521,4cyclictest25005-21gdbus11:35:1427
24122992521,4cyclictest25005-21gdbus11:35:1427
24122992460,2cyclictest0-21swapper/3310:53:3227
24122992460,2cyclictest0-21swapper/3310:53:3227
24122992460,2cyclictest0-21swapper/3310:53:3227
24122992441,233cyclictest0-21swapper/3310:10:4927
24122992441,233cyclictest0-21swapper/3310:10:4927
24122992441,233cyclictest0-21swapper/3310:10:4927
24122992421,238cyclictest0-21swapper/3309:34:1427
24122992421,238cyclictest0-21swapper/3309:34:1427
24122992411,236cyclictest0-21swapper/3310:40:1027
24122992411,236cyclictest0-21swapper/3310:40:1027
24122992411,236cyclictest0-21swapper/3310:40:1027
24122992410,2cyclictest0-21swapper/3311:20:4227
24122992410,2cyclictest0-21swapper/3311:20:4227
24122992410,2cyclictest0-21swapper/3311:20:4227
24122992401,236cyclictest0-21swapper/3311:50:2027
24122992401,236cyclictest0-21swapper/3311:50:1927
24122992391,4cyclictest2454-21CPU27
24122992391,4cyclictest2454-21CPU27
24122992391,3cyclictest3600-21qemu-system-x8609:43:2527
24122992391,3cyclictest3600-21qemu-system-x8609:43:2527
24122992351,230cyclictest0-21swapper/3311:48:4027
24122992351,230cyclictest0-21swapper/3311:48:4027
24122992350,2cyclictest0-21swapper/3312:36:5027
24122992350,2cyclictest0-21swapper/3312:36:5027
24122992350,2cyclictest0-21swapper/3312:36:5027
24122992350,2cyclictest0-21swapper/3310:46:0927
24122992350,2cyclictest0-21swapper/3310:46:0827
24122992350,2cyclictest0-21swapper/3310:46:0827
24122992341,2cyclictest0-21swapper/3312:20:0227
24122992341,2cyclictest0-21swapper/3312:20:0227
24122992340,2cyclictest0-21swapper/3309:13:1927
24122992340,2cyclictest0-21swapper/3309:13:1927
24122992340,2cyclictest0-21swapper/3309:13:1927
24122992332,228cyclictest0-21swapper/3312:20:2627
24122992332,228cyclictest0-21swapper/3312:20:2527
24122992331,228cyclictest0-21swapper/3310:25:1227
24122992331,228cyclictest0-21swapper/3310:25:1227
24122992313,221cyclictest37268-21CPU27
24122992313,221cyclictest37268-21CPU27
24122992310,2cyclictest0-21swapper/3310:23:5227
24122992310,2cyclictest0-21swapper/3310:23:5227
24122992310,2cyclictest0-21swapper/3310:23:5227
24122992301,2cyclictest0-21swapper/3311:40:1727
24122992301,2cyclictest0-21swapper/3311:40:1727
24122992300,2cyclictest0-21swapper/3309:55:2327
24122992300,2cyclictest0-21swapper/3309:55:2327
24122992300,2cyclictest0-21swapper/3309:55:2327
24122992300,2cyclictest0-21swapper/3308:22:0227
24122992300,2cyclictest0-21swapper/3308:22:0227
24122992291,2cyclictest0-21swapper/3309:21:2227
24122992291,2cyclictest0-21swapper/3309:21:2227
24122992291,225cyclictest0-21swapper/3311:55:3427
24122992291,225cyclictest0-21swapper/3311:55:3427
24122992291,220cyclictest0-21swapper/3312:00:1127
24122992291,220cyclictest0-21swapper/3312:00:1127
24122992281,224cyclictest0-21swapper/3310:36:2027
24122992281,224cyclictest0-21swapper/3310:36:2027
24122992281,224cyclictest0-21swapper/3310:36:2027
24122992271,2cyclictest0-21swapper/3308:40:0127
24122992271,2cyclictest0-21swapper/3308:40:0127
24122992251,2cyclictest0-21swapper/3308:05:2127
24122992251,2cyclictest0-21swapper/3308:05:2127
24122992251,2cyclictest0-21swapper/3307:49:1327
24122992251,2cyclictest0-21swapper/3307:49:1327
24122992250,2cyclictest0-21swapper/3311:32:5627
24122992250,2cyclictest0-21swapper/3311:32:5627
24122992250,2cyclictest0-21swapper/3310:57:5527
24122992250,2cyclictest0-21swapper/3310:57:5527
24122992231,219cyclictest0-21swapper/3307:45:0127
24122992221,214cyclictest0-21swapper/3311:08:3727
24122992221,214cyclictest0-21swapper/3311:08:3727
24122992221,214cyclictest0-21swapper/3311:08:3727
24122992220,2cyclictest0-21swapper/3310:05:1927
24122992220,2cyclictest0-21swapper/3310:05:1927
24122992220,2cyclictest0-21swapper/3310:05:1927
24122992211,2cyclictest0-21swapper/3312:34:1927
24122992211,2cyclictest0-21swapper/3312:34:1927
24122992211,2cyclictest0-21swapper/3312:34:1927
24122992211,2cyclictest0-21swapper/3312:28:2227
24122992211,2cyclictest0-21swapper/3312:28:2227
24122992210,2cyclictest0-21swapper/3312:05:2527
24122992210,2cyclictest0-21swapper/3312:05:2527
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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