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2026-01-17 - 21:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Jan 17, 2026 13:01:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2214799250246,2cyclictest0-21swapper/3810:20:1632
2214799250246,2cyclictest0-21swapper/3810:20:1632
2210399221200,11cyclictest0-21swapper/210:32:5812
2210399221200,11cyclictest0-21swapper/210:32:5812
2210399220195,12cyclictest0-21swapper/212:18:3612
2210399220195,12cyclictest0-21swapper/212:18:3612
2211299219214,3cyclictest0-21swapper/1010:15:192
2211299219214,3cyclictest0-21swapper/1010:15:182
2210399217205,7cyclictest0-21swapper/211:00:0112
2210399217205,7cyclictest0-21swapper/211:00:0112
2210399217205,7cyclictest0-21swapper/211:00:0012
2210399213206,5cyclictest0-21swapper/211:00:1512
2210399213206,5cyclictest0-21swapper/211:00:1512
2210399213206,5cyclictest0-21swapper/211:00:1512
2210399213203,8cyclictest0-21swapper/209:58:0112
2210399213203,8cyclictest0-21swapper/209:58:0112
2210399213203,8cyclictest0-21swapper/209:58:0112
2210399212206,5cyclictest33946-21sshd11:46:5412
2210399212206,5cyclictest33946-21sshd11:46:5312
2210299212171,14cyclictest171rcu_preempt10:35:581
2210299212171,14cyclictest171rcu_preempt10:35:581
2210299212171,14cyclictest171rcu_preempt10:35:581
2210399210204,4cyclictest0-21swapper/211:09:1912
2210399210204,4cyclictest0-21swapper/211:09:1912
2212599209139,64cyclictest4407-21CPU14
2212599209139,64cyclictest4407-21CPU14
2210399209202,4cyclictest18747-21if_err_eno410:50:2212
2210399209202,4cyclictest18747-21if_err_eno410:50:2112
2210399209202,4cyclictest18747-21if_err_eno410:50:2112
2214799207197,5cyclictest3542-21CPU32
2214799207197,5cyclictest3542-21CPU32
2213099207191,13cyclictest0-21swapper/2610:12:1619
2213099207191,13cyclictest0-21swapper/2610:12:1619
2212399207183,22cyclictest0-21swapper/1909:34:4411
2212399207183,22cyclictest0-21swapper/1909:34:4311
2212399207183,22cyclictest0-21swapper/1909:34:4311
2210399207199,4cyclictest3542-21CPU12
2210399207199,4cyclictest3542-21CPU12
2210399207199,4cyclictest3542-21CPU12
2210399205199,3cyclictest18605-21sshd09:40:2212
2210399205199,3cyclictest18605-21sshd09:40:2212
2210399205199,3cyclictest18605-21sshd09:40:2112
2210399204200,2cyclictest4775-21sshd10:45:3412
2210399204200,2cyclictest4775-21sshd10:45:3412
2210399204200,2cyclictest4775-21sshd10:45:3312
2210399204197,5cyclictest0-21swapper/207:40:1412
2210399204197,5cyclictest0-21swapper/207:40:1412
2210399204195,7cyclictest1360-21systemd-logind12:25:2312
2210399204195,7cyclictest1360-21systemd-logind12:25:2312
2210399204195,7cyclictest1360-21systemd-logind12:25:2212
2210399202194,5cyclictest0-21swapper/209:16:5512
2210399202194,5cyclictest0-21swapper/209:16:5512
2210399202188,12cyclictest0-21swapper/207:39:0712
2210399202188,12cyclictest0-21swapper/207:39:0712
2210399201195,4cyclictest0-21swapper/212:02:2912
2210399201195,4cyclictest0-21swapper/212:02:2912
2210399201195,4cyclictest0-21swapper/209:45:1312
2210399201195,4cyclictest0-21swapper/209:45:1312
2210399201195,4cyclictest0-21swapper/209:45:1312
2212299200180,16cyclictest0-21swapper/1809:14:2010
2212299200180,16cyclictest0-21swapper/1809:14:2010
2210399200195,3cyclictest0-21swapper/209:11:3212
2210399200195,3cyclictest0-21swapper/209:11:3212
2210399200194,4cyclictest0-21swapper/210:35:2012
2210399200194,4cyclictest0-21swapper/210:35:2012
2210399200194,4cyclictest0-21swapper/210:35:1912
2210399199193,4cyclictest1392-21gdbus10:00:4212
2210399199193,4cyclictest1392-21gdbus10:00:4212
2210399199193,4cyclictest1392-21gdbus10:00:4212
2210399199193,4cyclictest0-21swapper/210:41:1612
2210399199193,4cyclictest0-21swapper/210:41:1612
2210399199192,5cyclictest0-21swapper/210:21:3312
2210399199192,5cyclictest0-21swapper/210:21:3312
2212299198171,23cyclictest0-21swapper/1810:07:5610
2212299198171,23cyclictest0-21swapper/1810:07:5510
2212299198171,23cyclictest0-21swapper/1810:07:5510
2210399198192,5cyclictest0-21swapper/209:20:0712
2210399198192,5cyclictest0-21swapper/209:20:0712
2210399198192,5cyclictest0-21swapper/209:20:0712
2210399198190,4cyclictest3542-21CPU12
2210399198190,4cyclictest3542-21CPU12
2210399197187,7cyclictest0-21swapper/209:52:2412
2210399197187,7cyclictest0-21swapper/209:52:2412
2210399197187,7cyclictest0-21swapper/209:52:2312
2213199196192,2cyclictest0-21swapper/2711:20:0120
2213199196192,2cyclictest0-21swapper/2711:20:0120
2213199196192,2cyclictest0-21swapper/2711:20:0120
2210399196189,5cyclictest0-21swapper/210:25:2412
2210399196189,5cyclictest0-21swapper/210:25:2312
2210399196189,5cyclictest0-21swapper/210:25:2312
2210399196183,10cyclictest0-21swapper/208:50:2012
2210399196183,10cyclictest0-21swapper/208:50:2012
2213099195189,4cyclictest0-21swapper/2611:38:5419
2213099195189,4cyclictest0-21swapper/2611:38:5419
2213099195189,4cyclictest0-21swapper/2611:38:5319
2212399195171,21cyclictest0-21swapper/1912:10:5911
2212399195171,21cyclictest0-21swapper/1912:10:5911
2212399195171,21cyclictest0-21swapper/1912:10:5911
2212199195190,3cyclictest2462-21CPU9
2212199195190,3cyclictest2462-21CPU9
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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