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2026-07-05 - 22:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Jul 05, 2026 13:01:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4073599220213,2cyclictest0-21swapper/3211:20:0026
4073599220213,2cyclictest0-21swapper/3211:20:0026
4072599215201,6cyclictest0-21swapper/2211:11:5815
4072599215201,6cyclictest0-21swapper/2211:11:5815
4073999206197,2cyclictest0-21swapper/3609:36:0230
4073999206197,2cyclictest0-21swapper/3609:36:0230
4073999206197,2cyclictest0-21swapper/3609:36:0230
4072599199189,6cyclictest3546-21CPU15
4072599199189,6cyclictest3546-21CPU15
4072599199189,6cyclictest3546-21CPU15
4072599198184,6cyclictest0-21swapper/2209:40:1515
4072599198184,6cyclictest0-21swapper/2209:40:1515
4072599198184,6cyclictest0-21swapper/2209:40:1415
4072599197184,11cyclictest0-21swapper/2211:09:2715
4072599197184,11cyclictest0-21swapper/2211:09:2615
4072599196182,12cyclictest0-21swapper/2211:04:5515
4072599196182,12cyclictest0-21swapper/2211:04:5515
4072499194173,12cyclictest0-21swapper/2111:53:4714
4072499194173,12cyclictest0-21swapper/2111:53:4614
4072899193179,4cyclictest171rcu_preempt12:08:2718
4072899193179,4cyclictest171rcu_preempt12:08:2718
4072599192183,5cyclictest0-21swapper/2211:22:5515
4072599192183,5cyclictest0-21swapper/2211:22:5415
4070699191154,34cyclictest0-21swapper/311:32:5523
4070699191154,34cyclictest0-21swapper/311:32:5523
4072599186180,4cyclictest0-21swapper/2207:45:0115
4072599186180,4cyclictest0-21swapper/2207:45:0015
4072499186160,23cyclictest3610-21CPU14
4072499186160,23cyclictest3610-21CPU14
4072499186160,23cyclictest3610-21CPU14
4072599185177,5cyclictest0-21swapper/2210:58:1215
4072599185177,5cyclictest0-21swapper/2210:58:1215
4072599185176,6cyclictest0-21swapper/2208:45:1215
4072599185176,6cyclictest0-21swapper/2208:45:1215
4072599184176,5cyclictest4398-21qemu-system-x8611:48:2615
4072599184176,5cyclictest4398-21qemu-system-x8611:48:2615
4072599182175,5cyclictest0-21swapper/2210:40:0415
4072599182175,5cyclictest0-21swapper/2210:40:0415
4072599182170,9cyclictest0-21swapper/2209:51:5315
4072599182170,9cyclictest0-21swapper/2209:51:5315
4070699182152,20cyclictest0-21swapper/312:07:0923
4070699182152,20cyclictest0-21swapper/312:07:0923
4073699181152,13cyclictest0-21swapper/3311:10:4327
4073699181152,13cyclictest0-21swapper/3311:10:4227
4072599181173,4cyclictest2466-21CPU15
4072599181173,4cyclictest2466-21CPU15
4072599180175,4cyclictest0-21swapper/2209:25:3415
4072599180175,4cyclictest0-21swapper/2209:25:3415
4072599180174,5cyclictest0-21swapper/2211:53:5915
4072599180174,5cyclictest0-21swapper/2211:53:5915
4072599180169,9cyclictest0-21swapper/2208:20:2115
4070599180164,14cyclictest0-21swapper/209:52:0712
4070599180164,14cyclictest0-21swapper/209:52:0712
4074299179155,21cyclictest0-21swapper/3909:49:1333
4074299179155,21cyclictest0-21swapper/3909:49:1233
4074299179155,21cyclictest0-21swapper/3909:49:1233
4072999179171,3cyclictest0-21swapper/2611:15:2919
4072999179171,3cyclictest0-21swapper/2611:15:2919
4072599179173,4cyclictest0-21swapper/2208:40:0815
4072599179173,4cyclictest0-21swapper/2208:40:0815
4073999178166,10cyclictest0-21swapper/3611:56:3930
4073999178166,10cyclictest0-21swapper/3611:56:3930
4073799178173,3cyclictest0-21swapper/3410:30:0028
4073799178173,3cyclictest0-21swapper/3410:30:0028
4072599178173,4cyclictest0-21swapper/2211:31:5415
4072599178173,4cyclictest0-21swapper/2211:31:5315
4072599178172,4cyclictest4398-21qemu-system-x8611:27:4315
4072599178172,4cyclictest4398-21qemu-system-x8611:27:4315
4072599178172,4cyclictest4398-21qemu-system-x8611:27:4315
4071099178153,23cyclictest0-21swapper/710:24:0437
4071099178153,23cyclictest0-21swapper/710:24:0437
4071099178138,31cyclictest0-21swapper/710:01:0437
4071099178138,31cyclictest0-21swapper/710:01:0437
4071099178127,41cyclictest0-21swapper/711:46:5137
4071099178127,41cyclictest0-21swapper/711:46:5137
407399917780,94cyclictest0-21swapper/3611:20:0130
407399917780,94cyclictest0-21swapper/3611:20:0030
4072599177172,4cyclictest0-21swapper/2210:45:4315
4072599177172,4cyclictest0-21swapper/2210:45:4315
4072599177172,4cyclictest0-21swapper/2209:48:2715
4072599177172,4cyclictest0-21swapper/2209:48:2715
4072599177172,4cyclictest0-21swapper/2209:48:2715
4072599177171,4cyclictest0-21swapper/2210:25:0015
4072599177171,4cyclictest0-21swapper/2210:25:0015
4071999177144,31cyclictest0-21swapper/1608:13:288
4073999176171,2cyclictest0-21swapper/3611:47:2930
4073999176171,2cyclictest0-21swapper/3611:47:2930
4073899176124,49cyclictest37265-21CPU29
4073899176124,49cyclictest37265-21CPU29
4073899176124,49cyclictest37265-21CPU29
4072599176170,4cyclictest0-21swapper/2210:04:4615
4072599176170,4cyclictest0-21swapper/2210:04:4515
4072499176167,6cyclictest0-21swapper/2108:17:1314
4072299176125,47cyclictest37358-21CPU11
4072299176125,47cyclictest37358-21CPU11
4072199176170,4cyclictest0-21swapper/1811:40:3710
4072199176170,4cyclictest0-21swapper/1811:40:3710
4071899176170,5cyclictest0-21swapper/1512:18:417
4071899176170,5cyclictest0-21swapper/1512:18:417
4071899176170,5cyclictest0-21swapper/1512:18:407
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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