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2026-04-17 - 16:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri Apr 17, 2026 13:02:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6701992471,242cyclictest37346-21qemu-system-x8609:26:210
6701992471,242cyclictest37346-21qemu-system-x8609:26:200
6701992450,242cyclictest0-21swapper/009:15:480
6701992450,242cyclictest0-21swapper/009:15:470
6701992371,233cyclictest0-21swapper/010:56:460
6701992371,233cyclictest0-21swapper/010:56:450
6701992361,232cyclictest17230-21systemd11:40:270
6701992361,232cyclictest17230-21systemd11:40:270
6701992361,232cyclictest17230-21systemd11:40:270
6701992361,232cyclictest0-21swapper/010:00:170
6701992361,232cyclictest0-21swapper/010:00:170
6701992350,233cyclictest0-21swapper/010:19:390
6701992350,233cyclictest0-21swapper/010:19:390
6701992342,226cyclictest3610-21CPU0
6701992342,226cyclictest3610-21CPU0
6701992331,229cyclictest0-21swapper/011:27:440
6701992331,229cyclictest0-21swapper/011:27:440
6701992331,229cyclictest0-21swapper/011:27:440
6701992311,227cyclictest0-21swapper/009:53:290
6701992311,227cyclictest0-21swapper/009:53:290
6701992301,227cyclictest0-21swapper/009:40:010
6701992301,227cyclictest0-21swapper/009:40:010
6701992301,227cyclictest0-21swapper/009:40:010
6701992301,226cyclictest2459-21CPU0
6701992301,226cyclictest2459-21CPU0
6701992301,226cyclictest0-21swapper/012:06:430
6701992301,226cyclictest0-21swapper/012:06:430
6701992301,226cyclictest0-21swapper/010:05:290
6701992301,226cyclictest0-21swapper/010:05:290
6701992301,224cyclictest2456-21CPU0
6701992301,224cyclictest2456-21CPU0
6701992300,228cyclictest0-21swapper/010:24:230
6701992300,228cyclictest0-21swapper/010:24:230
6701992300,228cyclictest0-21swapper/010:24:230
6701992300,225cyclictest0-21swapper/009:48:020
6701992300,225cyclictest0-21swapper/009:48:020
6701992291,225cyclictest0-21swapper/009:44:330
6701992291,225cyclictest0-21swapper/009:44:330
6701992291,225cyclictest0-21swapper/009:44:320
6701992291,224cyclictest0-21swapper/010:25:550
6701992291,224cyclictest0-21swapper/010:25:550
6701992281,224cyclictest0-21swapper/011:09:550
6701992281,224cyclictest0-21swapper/011:09:540
6701992281,224cyclictest0-21swapper/011:09:540
6701992271,216cyclictest0-21swapper/010:14:260
6701992271,216cyclictest0-21swapper/010:14:260
6701992270,2cyclictest0-21swapper/011:04:220
6701992270,2cyclictest0-21swapper/011:04:220
6701992270,2cyclictest0-21swapper/011:04:220
6701992270,223cyclictest0-21swapper/007:10:180
6701992270,223cyclictest0-21swapper/007:10:180
6701992261,222cyclictest0-21swapper/012:03:470
6701992261,222cyclictest0-21swapper/012:03:460
6701992261,222cyclictest0-21swapper/012:03:460
6701992261,222cyclictest0-21swapper/010:31:430
6701992261,222cyclictest0-21swapper/010:31:430
6701992261,222cyclictest0-21swapper/010:31:430
6701992261,221cyclictest37353-21CPU0
6701992261,221cyclictest37353-21CPU0
6701992261,216cyclictest0-21swapper/012:26:380
6701992261,216cyclictest0-21swapper/012:26:370
6701992261,216cyclictest0-21swapper/012:26:370
6701992260,2cyclictest0-21swapper/009:13:540
6701992260,2cyclictest0-21swapper/009:13:540
6701992260,223cyclictest0-21swapper/010:40:010
6701992260,223cyclictest0-21swapper/010:40:010
6701992252,219cyclictest37358-21CPU0
6701992252,219cyclictest37358-21CPU0
6701992252,219cyclictest37358-21CPU0
6701992251,220cyclictest0-21swapper/010:52:320
6701992251,220cyclictest0-21swapper/010:52:320
6701992251,220cyclictest0-21swapper/010:52:310
6701992250,2cyclictest0-21swapper/009:55:240
6701992250,2cyclictest0-21swapper/009:55:230
6701992241,221cyclictest0-21swapper/012:14:060
6701992241,221cyclictest0-21swapper/012:14:050
6701992241,221cyclictest0-21swapper/009:32:030
6701992241,221cyclictest0-21swapper/009:32:020
6701992241,221cyclictest0-21swapper/009:32:020
6701992241,220cyclictest0-21swapper/011:30:240
6701992241,220cyclictest0-21swapper/011:30:230
6701992230,2cyclictest0-21swapper/009:01:490
6701992230,2cyclictest0-21swapper/009:01:490
6701992230,221cyclictest0-21swapper/011:38:540
6701992230,221cyclictest0-21swapper/011:38:540
6701992230,221cyclictest0-21swapper/011:38:540
6701992230,221cyclictest0-21swapper/008:51:300
6701992230,221cyclictest0-21swapper/008:51:300
6701992220,2cyclictest0-21swapper/011:57:010
6701992220,2cyclictest0-21swapper/011:57:010
6701992220,2cyclictest0-21swapper/011:57:010
6701992220,2cyclictest0-21swapper/008:00:330
6701992220,2cyclictest0-21swapper/008:00:330
6701992220,219cyclictest1-21systemd10:43:480
6701992220,219cyclictest1-21systemd10:43:470
6701992220,219cyclictest1-21systemd10:43:470
6701992220,219cyclictest0-21swapper/011:20:480
6701992220,219cyclictest0-21swapper/011:20:480
6701992211,217cyclictest0-21swapper/011:50:480
6701992211,217cyclictest0-21swapper/011:50:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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