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2026-01-16 - 19:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri Jan 16, 2026 13:00:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218299227188,27cyclictest0-21swapper/2609:20:1219
218299227188,27cyclictest0-21swapper/2609:20:1219
218299227188,27cyclictest0-21swapper/2609:20:1219
218299217203,9cyclictest0-21swapper/2611:10:1119
218299217203,9cyclictest0-21swapper/2611:10:1119
219299209159,45cyclictest0-21swapper/3509:26:5729
219299209159,45cyclictest0-21swapper/3509:26:5729
219299209159,45cyclictest0-21swapper/3509:26:5729
215199205191,7cyclictest0-21swapper/009:58:270
215199205191,7cyclictest0-21swapper/009:58:260
215199205191,7cyclictest0-21swapper/009:58:260
218099201195,4cyclictest0-21swapper/2409:14:0417
218099201195,4cyclictest0-21swapper/2409:14:0417
218099201195,4cyclictest0-21swapper/2409:14:0317
216999198180,13cyclictest0-21swapper/1610:47:138
216999198180,13cyclictest0-21swapper/1610:47:138
216999198180,13cyclictest0-21swapper/1610:47:138
218499196191,3cyclictest0-21swapper/2809:54:2821
218499196191,3cyclictest0-21swapper/2809:54:2821
218499196191,3cyclictest0-21swapper/2809:54:2821
218299195182,8cyclictest0-21swapper/2612:12:5819
218299195182,8cyclictest0-21swapper/2612:12:5819
218299195182,8cyclictest0-21swapper/2612:12:5819
218299194187,5cyclictest11980-21sshd11:52:5819
218299194187,5cyclictest11980-21sshd11:52:5819
218299194187,5cyclictest11980-21sshd11:52:5819
218299193182,7cyclictest0-21swapper/2610:15:1819
218299193182,7cyclictest0-21swapper/2610:15:1819
218299193182,7cyclictest0-21swapper/2610:15:1719
216599193166,13cyclictest171rcu_preempt09:19:204
216599193166,13cyclictest171rcu_preempt09:19:204
218299192181,9cyclictest0-21swapper/2611:25:2019
218299192181,9cyclictest0-21swapper/2611:25:2019
218299192181,9cyclictest0-21swapper/2611:25:2019
219299191176,12cyclictest0-21swapper/3510:49:3429
219299191176,12cyclictest0-21swapper/3510:49:3429
219299191176,12cyclictest0-21swapper/3510:49:3429
216899191159,25cyclictest0-21swapper/1510:35:557
216899191159,25cyclictest0-21swapper/1510:35:557
216899191159,25cyclictest0-21swapper/1510:35:557
218299190179,6cyclictest0-21swapper/2609:45:5119
218299190179,6cyclictest0-21swapper/2609:45:5119
218299190163,22cyclictest2461-21CPU19
218299190163,22cyclictest2461-21CPU19
216899190127,53cyclictest0-21swapper/1511:28:467
216899190127,53cyclictest0-21swapper/1511:28:457
216899190127,53cyclictest0-21swapper/1511:28:457
218299189180,6cyclictest4408-21CPU19
218299189180,6cyclictest4408-21CPU19
218299189180,6cyclictest4408-21CPU19
218299189180,5cyclictest0-21swapper/2609:26:0919
218299189180,5cyclictest0-21swapper/2609:26:0819
218299189180,5cyclictest0-21swapper/2609:26:0819
218099189169,13cyclictest0-21swapper/2411:18:2317
218099189169,13cyclictest0-21swapper/2411:18:2317
216599189177,8cyclictest0-21swapper/1211:46:034
216599189177,8cyclictest0-21swapper/1211:46:034
218299188179,5cyclictest37358-21CPU19
218299188179,5cyclictest37358-21CPU19
216999187150,33cyclictest3546-21CPU8
216999187150,33cyclictest3546-21CPU8
21689918772,111cyclictest0-21swapper/1510:45:167
21689918772,111cyclictest0-21swapper/1510:45:157
21689918772,111cyclictest0-21swapper/1510:45:157
216599186149,19cyclictest0-21swapper/1210:00:104
216599186149,19cyclictest0-21swapper/1210:00:104
2154991861,181cyclictest0-21swapper/207:10:2312
2154991861,181cyclictest0-21swapper/207:10:2312
218499184177,5cyclictest0-21swapper/2809:37:4521
218499184177,5cyclictest0-21swapper/2809:37:4421
218499184177,5cyclictest0-21swapper/2809:37:4421
218299184176,5cyclictest1367-21dbus-daemon10:54:3919
218299184176,5cyclictest1367-21dbus-daemon10:54:3919
218299183174,6cyclictest0-21swapper/2611:40:1819
218299183174,6cyclictest0-21swapper/2611:40:1819
218299183174,6cyclictest0-21swapper/2611:40:1819
218299183170,11cyclictest0-21swapper/2611:23:5019
218299183170,11cyclictest0-21swapper/2611:23:5019
216599183151,14cyclictest0-21swapper/1210:10:094
216599183151,14cyclictest0-21swapper/1210:10:094
216599183151,14cyclictest0-21swapper/1210:10:094
218499182147,29cyclictest171rcu_preempt11:28:5121
218499182147,29cyclictest171rcu_preempt11:28:5121
218499182147,29cyclictest171rcu_preempt11:28:5121
218299182177,4cyclictest0-21swapper/2612:24:1119
218299182177,4cyclictest0-21swapper/2612:24:1119
218299182175,5cyclictest0-21swapper/2610:35:2119
218299182175,5cyclictest0-21swapper/2610:35:2119
218299182175,5cyclictest0-21swapper/2610:35:2119
218299182174,5cyclictest1392-21gdbus10:25:2419
218299182174,5cyclictest1392-21gdbus10:25:2419
217799182170,10cyclictest0-21swapper/2111:24:4514
217799182170,10cyclictest0-21swapper/2111:24:4514
215499182158,20cyclictest0-21swapper/211:09:0112
215499182158,20cyclictest0-21swapper/211:09:0112
219899181174,3cyclictest0-21swapper/3910:55:4833
219899181174,3cyclictest0-21swapper/3910:55:4833
219899181174,3cyclictest0-21swapper/3910:55:4733
218799181149,13cyclictest171rcu_preempt11:37:5424
218799181149,13cyclictest171rcu_preempt11:37:5424
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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