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2026-01-25 - 14:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Jan 25, 2026 13:00:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1998799224215,5cyclictest3545-21CPU33
1998799224215,5cyclictest3545-21CPU33
1998799221214,5cyclictest0-21swapper/3909:20:2133
1998799221214,5cyclictest0-21swapper/3909:20:2133
1998799220211,6cyclictest0-21swapper/3911:15:0133
1998799220211,6cyclictest0-21swapper/3911:15:0133
1998799218207,8cyclictest0-21swapper/3911:36:0233
1998799218207,8cyclictest0-21swapper/3911:36:0233
1998799218207,8cyclictest0-21swapper/3911:36:0233
1998799216209,5cyclictest0-21swapper/3909:57:4433
1998799216209,5cyclictest0-21swapper/3909:57:4433
1998799216209,5cyclictest0-21swapper/3909:57:4433
1998799216198,13cyclictest0-21swapper/3910:40:1733
1998799216198,13cyclictest0-21swapper/3910:40:1633
1998799214206,6cyclictest0-21swapper/3912:15:0633
1998799214206,6cyclictest0-21swapper/3912:15:0633
1998799211194,14cyclictest0-21swapper/3910:33:5233
1998799211194,14cyclictest0-21swapper/3910:33:5233
1998799211194,14cyclictest0-21swapper/3910:33:5233
1998799210205,4cyclictest0-21swapper/3912:09:0333
1998799210205,4cyclictest0-21swapper/3912:09:0333
1998799210203,5cyclictest0-21swapper/3910:14:4633
1998799210203,5cyclictest0-21swapper/3910:14:4633
1998699210190,10cyclictest171rcu_preempt11:21:3732
1998699210190,10cyclictest171rcu_preempt11:21:3732
1998699210190,10cyclictest171rcu_preempt11:21:3732
1998799209203,5cyclictest0-21swapper/3909:05:1733
1998799209203,5cyclictest0-21swapper/3909:05:1733
1998799209202,5cyclictest0-21swapper/3910:20:1133
1998799209202,5cyclictest0-21swapper/3910:20:1133
1998799208187,15cyclictest0-21swapper/3912:17:1333
1998799208187,15cyclictest0-21swapper/3912:17:1333
1998799208187,15cyclictest0-21swapper/3912:17:1333
1998799206188,11cyclictest16534-21systemd-cgroups11:32:2033
1998799206188,11cyclictest16534-21systemd-cgroups11:32:2033
1998799206188,11cyclictest16534-21systemd-cgroups11:32:1933
1998799206186,16cyclictest0-21swapper/3910:57:1633
1998799206186,16cyclictest0-21swapper/3910:57:1633
1998799206186,16cyclictest0-21swapper/3910:57:1633
1998799205193,10cyclictest0-21swapper/3912:04:2333
1998799205193,10cyclictest0-21swapper/3912:04:2333
1998799205189,8cyclictest0-21swapper/3911:43:0733
1998799205189,8cyclictest0-21swapper/3911:43:0733
1998799204197,5cyclictest0-21swapper/3910:17:5633
1998799204197,5cyclictest0-21swapper/3910:17:5633
1998799204191,9cyclictest38353-21systemd-cgroups09:15:1433
1998799204191,9cyclictest38353-21systemd-cgroups09:15:1433
1994999204190,9cyclictest0-21swapper/812:00:3638
1994999204190,9cyclictest0-21swapper/812:00:3638
1998799203191,8cyclictest0-21swapper/3910:50:3533
1998799203191,8cyclictest0-21swapper/3910:50:3533
1998799203183,18cyclictest0-21swapper/3911:05:0233
1998799203183,18cyclictest0-21swapper/3911:05:0233
1998799202190,9cyclictest0-21swapper/3909:26:4233
1998799202190,9cyclictest0-21swapper/3909:26:4233
1998799202190,9cyclictest0-21swapper/3909:26:4233
1998799199192,5cyclictest0-21swapper/3911:54:0333
1998799199192,5cyclictest0-21swapper/3911:54:0333
1998799199192,5cyclictest0-21swapper/3911:54:0333
1998799199191,6cyclictest39323-21sshd11:26:3533
1998799199191,6cyclictest39323-21sshd11:26:3533
1998799199187,9cyclictest0-21swapper/3910:29:4933
1998799199187,9cyclictest0-21swapper/3910:29:4933
1998799199187,9cyclictest0-21swapper/3910:29:4933
1998799199184,13cyclictest35409-21sshd11:06:1333
1998799199184,13cyclictest35409-21sshd11:06:1333
199679919996,99cyclictest4408-21CPU15
199679919996,99cyclictest4408-21CPU15
199679919996,99cyclictest4408-21CPU15
1994399199182,15cyclictest0-21swapper/208:25:0412
1994399199182,15cyclictest0-21swapper/208:25:0412
1998799198188,6cyclictest0-21swapper/3910:45:2033
1998799198188,6cyclictest0-21swapper/3910:45:2033
1998799198188,6cyclictest0-21swapper/3910:45:1933
1998799198188,4cyclictest10374-21sed12:30:2733
1998799198188,4cyclictest10374-21sed12:30:2733
1998799198187,8cyclictest0-21swapper/3911:50:0233
1998799198187,8cyclictest0-21swapper/3911:50:0233
1997799198192,4cyclictest0-21swapper/3108:40:2025
1997799198192,4cyclictest0-21swapper/3108:40:2025
1994999198181,10cyclictest0-21swapper/810:59:2538
1994999198181,10cyclictest0-21swapper/810:59:2538
1994999198181,10cyclictest0-21swapper/810:59:2538
1998799197186,7cyclictest37357-21CPU33
1998799197186,7cyclictest37357-21CPU33
1998799197179,11cyclictest0-21swapper/3909:35:2633
1998799197179,11cyclictest0-21swapper/3909:35:2633
1998799197179,11cyclictest0-21swapper/3909:35:2633
1998699197181,9cyclictest0-21swapper/3810:22:2432
1998699197181,9cyclictest0-21swapper/3810:22:2432
1998799196187,7cyclictest0-21swapper/3912:38:3533
1998799196187,7cyclictest0-21swapper/3912:38:3533
1998799196187,7cyclictest0-21swapper/3912:38:3533
1994399196168,11cyclictest0-21swapper/210:55:4712
1994399196168,11cyclictest0-21swapper/210:55:4712
1994399196168,11cyclictest0-21swapper/210:55:4712
1998799195188,5cyclictest0-21swapper/3911:21:3333
1998799195188,5cyclictest0-21swapper/3911:21:3333
1998799195188,5cyclictest0-21swapper/3911:21:3333
1998799195181,7cyclictest37355-21CPU33
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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