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2026-02-14 - 21:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Feb 14, 2026 13:03:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3771499224204,13cyclictest0-21swapper/1012:14:402
3771499224204,13cyclictest0-21swapper/1012:14:392
3771499220211,7cyclictest0-21swapper/1010:50:152
3771499220211,7cyclictest0-21swapper/1010:50:142
3771499218211,5cyclictest0-21swapper/1008:40:132
3771499218211,5cyclictest0-21swapper/1008:40:122
3771499217208,7cyclictest0-21swapper/1009:16:542
3771499217208,7cyclictest0-21swapper/1009:16:542
3771499217208,7cyclictest0-21swapper/1009:16:532
3771499217206,7cyclictest0-21swapper/1011:40:152
3771499217206,7cyclictest0-21swapper/1011:40:152
3771499217206,7cyclictest0-21swapper/1011:40:142
3771499217185,20cyclictest0-21swapper/1011:20:072
3771499217185,20cyclictest0-21swapper/1011:20:072
3771499216190,18cyclictest0-21swapper/1009:14:412
3771499216190,18cyclictest0-21swapper/1009:14:402
3771499215194,13cyclictest0-21swapper/1011:10:012
3771499215194,13cyclictest0-21swapper/1011:10:002
3771499215194,13cyclictest0-21swapper/1011:10:002
3771499214202,10cyclictest0-21swapper/1012:01:342
3771499214202,10cyclictest0-21swapper/1012:01:332
3771499214198,9cyclictest0-21swapper/1009:26:352
3771499214198,9cyclictest0-21swapper/1009:26:342
3771499214198,9cyclictest0-21swapper/1009:26:342
3771499214194,15cyclictest0-21swapper/1012:21:442
3771499214194,15cyclictest0-21swapper/1012:21:432
3771499214188,19cyclictest0-21swapper/1008:35:182
3771499214188,19cyclictest0-21swapper/1008:35:182
3771499213186,18cyclictest0-21swapper/1009:51:162
3771499213186,18cyclictest0-21swapper/1009:51:162
3771499213186,18cyclictest0-21swapper/1009:51:152
3771499213186,14cyclictest0-21swapper/1010:32:522
3771499213186,14cyclictest0-21swapper/1010:32:522
3771499213186,14cyclictest0-21swapper/1010:32:512
3771499210185,16cyclictest37346-21qemu-system-x8609:41:322
3771499210185,16cyclictest37346-21qemu-system-x8609:41:312
3771499210185,16cyclictest37346-21qemu-system-x8609:41:312
3771499210179,16cyclictest0-21swapper/1011:51:082
3771499210179,16cyclictest0-21swapper/1011:51:072
3771499210179,16cyclictest0-21swapper/1011:51:072
3771499208188,17cyclictest0-21swapper/1008:10:142
3771499208188,17cyclictest0-21swapper/1008:10:142
3771499207195,8cyclictest0-21swapper/1011:33:472
3771499207195,8cyclictest0-21swapper/1011:33:472
3771499206191,13cyclictest0-21swapper/1008:21:252
3771499206191,13cyclictest0-21swapper/1008:21:252
3771499206183,15cyclictest0-21swapper/1011:46:122
3771499206183,15cyclictest0-21swapper/1011:46:112
3771499206180,20cyclictest0-21swapper/1012:15:122
3771499206180,20cyclictest0-21swapper/1012:15:112
3771499204191,8cyclictest0-21swapper/1011:11:072
3771499204191,8cyclictest0-21swapper/1011:11:072
3771499204191,8cyclictest0-21swapper/1011:11:072
3771499202182,9cyclictest0-21swapper/1010:25:272
3771499202182,9cyclictest0-21swapper/1010:25:272
3771499202182,9cyclictest0-21swapper/1010:25:262
3771499202181,13cyclictest1285-21jbd2/sdb1-809:20:102
3771499202181,13cyclictest1285-21jbd2/sdb1-809:20:102
3771499202181,13cyclictest1285-21jbd2/sdb1-809:20:092
3773599201180,12cyclictest0-21swapper/2707:40:0120
3773599201180,12cyclictest0-21swapper/2707:40:0120
3771499201182,7cyclictest0-21swapper/1011:39:282
3771499201182,7cyclictest0-21swapper/1011:39:272
3771499201182,7cyclictest0-21swapper/1011:39:272
3771499201179,19cyclictest0-21swapper/1009:37:262
3771499201179,19cyclictest0-21swapper/1009:37:262
3771499199177,20cyclictest0-21swapper/1009:55:302
3771499199177,20cyclictest0-21swapper/1009:55:292
3771499199177,20cyclictest0-21swapper/1009:55:292
3771499198185,6cyclictest0-21swapper/1010:11:172
3771499198185,6cyclictest0-21swapper/1010:11:172
3771499198185,6cyclictest0-21swapper/1010:11:172
3771499198174,13cyclictest0-21swapper/1011:58:342
3771499198174,13cyclictest0-21swapper/1011:58:332
3774199197127,51cyclictest0-21swapper/3311:40:3427
3774199197127,51cyclictest0-21swapper/3311:40:3427
3774199197127,51cyclictest0-21swapper/3311:40:3327
3771499197178,9cyclictest0-21swapper/1011:00:202
3771499197178,9cyclictest0-21swapper/1011:00:202
3771499197178,9cyclictest0-21swapper/1011:00:192
3771499196181,11cyclictest0-21swapper/1012:30:462
3771499196181,11cyclictest0-21swapper/1012:30:462
3771499196176,14cyclictest0-21swapper/1012:25:212
3771499196176,14cyclictest0-21swapper/1012:25:202
3771499195180,6cyclictest0-21swapper/1011:16:102
3772699194181,2cyclictest0-21swapper/2108:11:2014
3772699194181,2cyclictest0-21swapper/2108:11:2014
3771499194172,11cyclictest1360-21systemd-logind10:09:202
3771499194172,11cyclictest1360-21systemd-logind10:09:202
3771499194172,11cyclictest1360-21systemd-logind10:09:192
3771499194169,12cyclictest0-21swapper/1009:49:592
3771499194169,12cyclictest0-21swapper/1009:49:592
3771499194169,12cyclictest0-21swapper/1009:49:582
3771499192185,4cyclictest0-21swapper/1007:40:162
3771499192185,4cyclictest0-21swapper/1007:40:162
3771499191183,6cyclictest0-21swapper/1009:30:192
3771499191183,6cyclictest0-21swapper/1009:30:192
3771499191183,6cyclictest0-21swapper/1009:30:182
3771499191178,6cyclictest0-21swapper/1007:54:182
3771499191178,6cyclictest0-21swapper/1007:54:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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