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2026-09-17 - 06:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Sep 17, 2026 01:02:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114699223199,20cyclictest0-21swapper/3223:20:0126
114699223199,20cyclictest0-21swapper/3223:20:0126
114699217204,11cyclictest0-21swapper/3223:20:2226
114699217204,11cyclictest0-21swapper/3223:20:2226
114899214204,8cyclictest0-21swapper/3419:15:2228
114899214204,8cyclictest0-21swapper/3419:15:2228
110899214207,5cyclictest0-21swapper/100:06:501
110899214207,5cyclictest0-21swapper/100:06:491
114899213207,4cyclictest0-21swapper/3422:13:2628
114899213207,4cyclictest0-21swapper/3422:13:2628
114899213202,9cyclictest0-21swapper/3423:00:1328
114899213202,9cyclictest0-21swapper/3423:00:1328
114899209202,6cyclictest0-21swapper/3423:50:3328
114899209202,6cyclictest0-21swapper/3423:50:3328
114899209193,13cyclictest0-21swapper/3421:20:1728
114899209193,13cyclictest0-21swapper/3421:20:1628
114899205180,5cyclictest0-21swapper/3420:00:2628
114899205180,5cyclictest0-21swapper/3420:00:2628
110899205200,3cyclictest0-21swapper/100:00:251
110899205200,3cyclictest0-21swapper/100:00:251
114899204193,9cyclictest0-21swapper/3421:10:3028
114899204193,9cyclictest0-21swapper/3421:10:3028
114899204190,12cyclictest0-21swapper/3423:30:3928
114899204190,12cyclictest0-21swapper/3423:30:3928
114899202195,5cyclictest0-21swapper/3423:35:1928
114899202195,5cyclictest0-21swapper/3423:35:1828
114899202192,8cyclictest33430-21sshd23:12:2628
114899202192,8cyclictest33430-21sshd23:12:2628
114899202192,8cyclictest33430-21sshd23:12:2628
114699202193,5cyclictest2454-21CPU26
114699202193,5cyclictest2454-21CPU26
114699202193,5cyclictest2454-21CPU26
114899200191,7cyclictest37257-21qemu-system-x8622:50:5028
114899200191,7cyclictest37257-21qemu-system-x8622:50:5028
114899200188,10cyclictest0-21swapper/3420:35:2728
114899200188,10cyclictest0-21swapper/3420:35:2728
114899200187,11cyclictest0-21swapper/3422:22:2828
114899200187,11cyclictest0-21swapper/3422:22:2828
114899199187,9cyclictest2462-21CPU28
114899199187,9cyclictest2462-21CPU28
114899199186,11cyclictest0-21swapper/3422:06:4728
114899199186,11cyclictest0-21swapper/3422:06:4728
110899199189,7cyclictest0-21swapper/123:55:241
110899199189,7cyclictest0-21swapper/123:55:241
110899199189,7cyclictest0-21swapper/123:55:241
114899198187,9cyclictest0-21swapper/3420:25:1428
114899198181,14cyclictest1360-21systemd-logind22:30:1828
114899198181,14cyclictest1360-21systemd-logind22:30:1828
114899198180,15cyclictest4398-21qemu-system-x8619:25:2528
112299198191,5cyclictest0-21swapper/1222:34:494
112299198191,5cyclictest0-21swapper/1222:34:494
114899197190,6cyclictest0-21swapper/3420:20:5528
114899196188,6cyclictest0-21swapper/3421:01:3028
114899196188,6cyclictest0-21swapper/3421:01:3028
114899195187,7cyclictest0-21swapper/3423:07:5628
114899195187,7cyclictest0-21swapper/3423:07:5628
114899195178,15cyclictest0-21swapper/3420:15:2728
114899194183,9cyclictest0-21swapper/3421:58:1728
114899194183,9cyclictest0-21swapper/3421:58:1728
111899194183,9cyclictest0-21swapper/823:36:1638
111899194183,9cyclictest0-21swapper/823:36:1638
114899193185,6cyclictest0-21swapper/3423:41:5228
114899193185,6cyclictest0-21swapper/3423:41:5228
114899193185,4cyclictest0-21swapper/3422:18:1628
114899193185,4cyclictest0-21swapper/3422:18:1628
114899193184,7cyclictest0-21swapper/3420:40:1728
114899193184,7cyclictest0-21swapper/3420:40:1728
114899193183,9cyclictest0-21swapper/3423:19:1128
114899193183,9cyclictest0-21swapper/3423:19:1128
114899193183,8cyclictest0-21swapper/3419:15:0128
114899193183,8cyclictest0-21swapper/3419:15:0028
113599193168,16cyclictest0-21swapper/2321:45:5016
113599193168,16cyclictest0-21swapper/2321:45:5016
114899192183,5cyclictest0-21swapper/3422:25:1328
114899192183,5cyclictest0-21swapper/3422:25:1328
114899192180,10cyclictest0-21swapper/3421:31:1228
114899192180,10cyclictest0-21swapper/3421:31:1228
114899192180,10cyclictest0-21swapper/3421:31:1228
114899191185,4cyclictest0-21swapper/3421:25:3328
114899191185,4cyclictest0-21swapper/3421:25:3328
114899191185,4cyclictest0-21swapper/3421:25:3328
114899190182,6cyclictest0-21swapper/3423:45:3528
114899190182,6cyclictest0-21swapper/3423:45:3528
114899190182,6cyclictest0-21swapper/3423:45:3528
114899190176,11cyclictest0-21swapper/3419:35:2728
114899190176,11cyclictest0-21swapper/3419:35:2728
114699190184,4cyclictest0-21swapper/3220:54:5326
114699190184,4cyclictest0-21swapper/3220:54:5326
114899189176,11cyclictest0-21swapper/3419:40:2028
114899189176,11cyclictest0-21swapper/3419:40:2028
114899189175,12cyclictest0-21swapper/3422:46:0128
114899189175,12cyclictest0-21swapper/3422:46:0128
114899189170,17cyclictest0-21swapper/3422:00:1928
114899189170,17cyclictest0-21swapper/3422:00:1928
113599189181,5cyclictest0-21swapper/2300:20:4516
113599189181,5cyclictest0-21swapper/2300:20:4516
113599189181,5cyclictest0-21swapper/2300:20:4516
114899188178,8cyclictest0-21swapper/3421:18:5128
114899188178,8cyclictest0-21swapper/3421:18:5128
114799188168,17cyclictest0-21swapper/3319:50:0127
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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