You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-12 - 02:37
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Apr 12, 2026 01:01:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1685799235225,8cyclictest0-21swapper/1421:30:226
1685799235225,8cyclictest0-21swapper/1421:30:226
1686599224218,3cyclictest0-21swapper/2222:20:5615
1686599224218,3cyclictest0-21swapper/2222:20:5515
1685799220212,5cyclictest0-21swapper/1421:45:226
1685799220212,5cyclictest0-21swapper/1421:45:226
1685799219211,6cyclictest0-21swapper/1421:35:246
1685799219211,6cyclictest0-21swapper/1421:35:246
1685599214208,4cyclictest0-21swapper/1323:28:455
1685599214208,4cyclictest0-21swapper/1323:28:455
1685599214208,4cyclictest0-21swapper/1323:28:455
1685799212206,4cyclictest0-21swapper/1423:46:136
1685799212206,4cyclictest0-21swapper/1423:46:126
1685799211202,7cyclictest24586-21systemd21:10:086
1685799211202,7cyclictest24586-21systemd21:10:086
1685799211202,5cyclictest2456-21CPU6
1685799211202,5cyclictest2456-21CPU6
1687199210203,5cyclictest0-21swapper/2700:31:2120
1687199210203,5cyclictest0-21swapper/2700:31:2120
1687199210203,5cyclictest0-21swapper/2700:31:2020
1685799210205,4cyclictest0-21swapper/1420:35:036
1685799210205,4cyclictest0-21swapper/1420:35:036
1685799210204,4cyclictest0-21swapper/1421:24:116
1685799210204,4cyclictest0-21swapper/1421:24:116
1685799210204,4cyclictest0-21swapper/1421:24:116
1684299210202,6cyclictest0-21swapper/223:49:3112
1684299210202,6cyclictest0-21swapper/223:49:3112
1684299210201,7cyclictest0-21swapper/223:16:5812
1684299210201,7cyclictest0-21swapper/223:16:5812
1687199209200,5cyclictest0-21swapper/2723:50:4620
1687199209200,5cyclictest0-21swapper/2723:50:4520
1687199209193,12cyclictest37355-21CPU20
1687199209193,12cyclictest37355-21CPU20
1685799209203,5cyclictest0-21swapper/1400:34:446
1685799209203,5cyclictest0-21swapper/1400:34:446
1685799209203,5cyclictest0-21swapper/1400:34:446
1687199208198,4cyclictest0-21swapper/2700:25:3020
1687199208198,4cyclictest0-21swapper/2700:25:2920
1685799208200,6cyclictest0-21swapper/1421:25:166
1685799208200,6cyclictest0-21swapper/1421:25:156
1685799208200,6cyclictest0-21swapper/1421:25:156
1687199207201,4cyclictest37257-21qemu-system-x8621:55:1420
1687199207201,4cyclictest37257-21qemu-system-x8621:55:1420
1685799207198,7cyclictest0-21swapper/1423:59:556
1685799207198,7cyclictest0-21swapper/1423:59:556
1685799207198,7cyclictest0-21swapper/1423:59:556
1685799207195,10cyclictest0-21swapper/1423:42:076
1685799207195,10cyclictest0-21swapper/1423:42:076
1687299206201,3cyclictest0-21swapper/2822:15:1621
1687299206201,3cyclictest0-21swapper/2822:15:1521
1687299206201,3cyclictest0-21swapper/2822:15:1521
1684299206198,7cyclictest0-21swapper/223:36:1712
1684299206198,7cyclictest0-21swapper/223:36:1612
1685799205198,5cyclictest0-21swapper/1421:42:186
1685799205198,5cyclictest0-21swapper/1421:42:186
1685799205198,5cyclictest0-21swapper/1400:13:016
1685799205198,5cyclictest0-21swapper/1400:13:006
1685799205198,5cyclictest0-21swapper/1400:13:006
1685799205197,4cyclictest2459-21CPU6
1687199204198,5cyclictest0-21swapper/2700:24:2220
1687199204198,5cyclictest0-21swapper/2700:24:2120
1685799204198,4cyclictest0-21swapper/1400:35:446
1685799204198,4cyclictest0-21swapper/1400:35:436
1685799204198,4cyclictest0-21swapper/1400:35:436
1684299204198,3cyclictest3609-21CPU12
1684299204198,3cyclictest3609-21CPU12
1684299204191,10cyclictest0-21swapper/221:50:1512
1684299204191,10cyclictest0-21swapper/221:50:1512
1687199203192,9cyclictest0-21swapper/2720:15:2720
1687199203192,9cyclictest0-21swapper/2720:15:2720
1684299203195,6cyclictest0-21swapper/222:03:2212
1684299203195,6cyclictest0-21swapper/222:03:2212
1685799202190,10cyclictest0-21swapper/1423:25:236
1685799202190,10cyclictest0-21swapper/1423:25:236
1685799202190,10cyclictest0-21swapper/1423:25:226
1684299202192,5cyclictest37355-21CPU12
1684299202192,5cyclictest37355-21CPU12
1685799201194,5cyclictest0-21swapper/1420:58:076
1685799201194,5cyclictest0-21swapper/1420:58:076
1685799201193,6cyclictest0-21swapper/1423:09:056
1685799201193,6cyclictest0-21swapper/1423:09:056
1685599201195,4cyclictest0-21swapper/1300:03:025
1685599201195,4cyclictest0-21swapper/1300:03:025
1684299201194,5cyclictest0-21swapper/223:21:5612
1684299201194,5cyclictest0-21swapper/223:21:5612
1687199200157,27cyclictest0-21swapper/2723:00:1820
1687199200157,27cyclictest0-21swapper/2723:00:1720
1686499199168,25cyclictest3548-21CPU14
1686499199168,25cyclictest3548-21CPU14
1685799199192,5cyclictest37346-21qemu-system-x8620:30:036
1685799199192,5cyclictest37346-21qemu-system-x8620:30:036
1685799199191,6cyclictest0-21swapper/1423:36:556
1685799199191,6cyclictest0-21swapper/1423:36:556
1684299199193,4cyclictest0-21swapper/221:59:4212
1684299199193,4cyclictest0-21swapper/221:59:4212
1685799198192,4cyclictest0-21swapper/1421:58:496
1685799198192,4cyclictest0-21swapper/1421:58:496
1685799197192,4cyclictest0-21swapper/1421:05:176
1685799197192,4cyclictest0-21swapper/1421:05:176
1685799197188,6cyclictest0-21swapper/1421:15:196
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional