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2026-01-18 - 10:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Jan 18, 2026 01:00:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
944699197191,3cyclictest0-21swapper/022:54:510
944699197191,3cyclictest0-21swapper/022:54:510
944699197191,3cyclictest0-21swapper/022:54:510
949499196166,12cyclictest171rcu_preempt22:25:2833
949499196166,12cyclictest171rcu_preempt22:25:2833
947599195184,8cyclictest0-21swapper/2421:15:2017
947599195184,8cyclictest0-21swapper/2421:15:2017
946999191187,2cyclictest0-21swapper/1919:30:1411
946999191187,2cyclictest0-21swapper/1919:30:1411
944999191187,2cyclictest0-21swapper/321:18:2423
944999191187,2cyclictest0-21swapper/321:18:2423
948599190186,3cyclictest0-21swapper/3322:07:1827
948599190186,3cyclictest0-21swapper/3322:07:1827
948599190186,3cyclictest0-21swapper/3322:07:1727
946299189182,4cyclictest0-21swapper/1421:46:136
946299189182,4cyclictest0-21swapper/1421:46:136
946299189182,4cyclictest0-21swapper/1421:46:136
946099187177,8cyclictest0-21swapper/1321:15:405
946099187177,8cyclictest0-21swapper/1321:15:405
945399187168,16cyclictest0-21swapper/700:28:0337
945399187168,16cyclictest0-21swapper/700:28:0337
945399187168,16cyclictest0-21swapper/700:28:0337
949499186171,8cyclictest171rcu_preempt22:01:5233
949499186171,8cyclictest171rcu_preempt22:01:5133
947699185146,36cyclictest3544-21CPU18
947699185146,36cyclictest3544-21CPU18
947699185146,36cyclictest3544-21CPU18
946399185175,8cyclictest0-21swapper/1519:39:487
946399185175,8cyclictest0-21swapper/1519:39:487
94659918472,103cyclictest0-21swapper/1600:00:218
94659918472,103cyclictest0-21swapper/1600:00:218
949499183173,8cyclictest0-21swapper/3923:31:4533
949499183173,8cyclictest0-21swapper/3923:31:4533
949499183173,8cyclictest0-21swapper/3923:31:4533
949499183140,16cyclictest171rcu_preempt22:53:3233
949499183140,16cyclictest171rcu_preempt22:53:3233
949499183140,16cyclictest171rcu_preempt22:53:3233
949299183171,6cyclictest0-21swapper/3800:24:5232
949299183171,6cyclictest0-21swapper/3800:24:5232
947099183170,10cyclictest0-21swapper/2000:35:4513
947099183170,10cyclictest0-21swapper/2000:35:4513
946399183172,5cyclictest0-21swapper/1500:35:037
946399183172,5cyclictest0-21swapper/1500:35:027
9483991821,5cyclictest27821-21sshd21:25:1725
9483991821,5cyclictest27821-21sshd21:25:1725
94659918272,37cyclictest0-21swapper/1623:25:198
94659918272,37cyclictest0-21swapper/1623:25:198
94659918272,37cyclictest0-21swapper/1623:25:198
946399182170,8cyclictest0-21swapper/1520:16:137
946399182170,8cyclictest0-21swapper/1520:16:137
949499181153,16cyclictest171rcu_preempt21:38:4133
949499181153,16cyclictest171rcu_preempt21:38:4133
949499181153,16cyclictest171rcu_preempt21:38:4133
948999181178,2cyclictest0-21swapper/3621:20:1930
948999181178,2cyclictest0-21swapper/3621:20:1930
949499180165,8cyclictest171rcu_preempt19:21:5033
949499180165,8cyclictest171rcu_preempt19:21:5033
949499180114,35cyclictest0-21swapper/3921:56:1733
949499180114,35cyclictest0-21swapper/3921:56:1733
946399180165,8cyclictest171rcu_preempt19:21:247
946399180165,8cyclictest171rcu_preempt19:21:237
946399180152,18cyclictest0-21swapper/1521:57:067
946399180152,18cyclictest0-21swapper/1521:57:067
946399180116,24cyclictest0-21swapper/1519:19:507
946399180116,24cyclictest0-21swapper/1519:19:507
946299180166,8cyclictest1360-21systemd-logind00:39:336
946299180166,8cyclictest1360-21systemd-logind00:39:336
949499179171,6cyclictest0-21swapper/3923:26:3433
949499179171,6cyclictest0-21swapper/3923:26:3433
949499179171,6cyclictest0-21swapper/3923:26:3433
949499179163,8cyclictest171rcu_preempt20:42:1533
949499179163,8cyclictest171rcu_preempt20:42:1533
946299179128,25cyclictest0-21swapper/1419:24:486
946299179128,25cyclictest0-21swapper/1419:24:486
949499178160,11cyclictest171rcu_preempt20:36:1433
949499178160,11cyclictest171rcu_preempt20:36:1433
949499178129,26cyclictest0-21swapper/3919:34:0133
949499178129,26cyclictest0-21swapper/3919:34:0133
946299178173,4cyclictest0-21swapper/1423:19:246
946299178173,4cyclictest0-21swapper/1423:19:246
944999178170,6cyclictest0-21swapper/321:43:3123
944999178170,6cyclictest0-21swapper/321:43:3123
949499177149,15cyclictest171rcu_preempt22:19:3433
949499177149,15cyclictest171rcu_preempt22:19:3433
949499177131,26cyclictest0-21swapper/3900:16:2833
949499177131,26cyclictest0-21swapper/3900:16:2733
946099177156,11cyclictest0-21swapper/1300:30:315
946099177156,11cyclictest0-21swapper/1300:30:315
949499176118,28cyclictest0-21swapper/3919:47:2133
949499176118,28cyclictest0-21swapper/3919:47:2133
947799176166,8cyclictest0-21swapper/2619:20:0919
947799176166,8cyclictest0-21swapper/2619:20:0919
946299176134,27cyclictest0-21swapper/1400:09:166
946299176134,27cyclictest0-21swapper/1400:09:166
944999176161,12cyclictest0-21swapper/321:34:5623
944999176161,12cyclictest0-21swapper/321:34:5623
944999176161,12cyclictest0-21swapper/321:34:5623
949499175132,23cyclictest0-21swapper/3923:35:1033
949499175132,23cyclictest0-21swapper/3923:35:0933
949199175169,4cyclictest0-21swapper/3723:56:3531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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