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2026-01-24 - 19:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sat Jan 24, 2026 13:01:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2521999209202,3cyclictest3544-21CPU6
2521999209202,3cyclictest3544-21CPU6
2521999209202,3cyclictest3544-21CPU6
2521999207199,5cyclictest0-21swapper/1412:29:326
2521999207199,5cyclictest0-21swapper/1412:29:326
2521999207199,5cyclictest0-21swapper/1412:29:316
2524099206155,48cyclictest0-21swapper/3112:13:1125
2524099206155,48cyclictest0-21swapper/3112:13:1125
2524099206155,48cyclictest0-21swapper/3112:13:1125
2521999204197,3cyclictest4408-21CPU6
2521999204197,3cyclictest4408-21CPU6
2523399201190,8cyclictest1442-21gdbus11:05:1419
2523399201190,8cyclictest1442-21gdbus11:05:1419
2521999199192,5cyclictest0-21swapper/1410:25:136
2521999199192,5cyclictest0-21swapper/1410:25:136
2521999199192,5cyclictest0-21swapper/1410:25:136
2522999198192,4cyclictest0-21swapper/2307:10:2216
2522999198192,4cyclictest0-21swapper/2307:10:2216
2521999198192,4cyclictest0-21swapper/1409:22:046
2521999198192,4cyclictest0-21swapper/1409:22:046
2521999198192,4cyclictest0-21swapper/1409:22:036
2521999198189,6cyclictest0-21swapper/1409:20:076
2521999198189,6cyclictest0-21swapper/1409:20:076
2521999198187,9cyclictest0-21swapper/1411:30:236
2521999198187,9cyclictest0-21swapper/1411:30:236
2524099197172,23cyclictest0-21swapper/3110:10:5225
2524099197172,23cyclictest0-21swapper/3110:10:5225
25248991961,3cyclictest0-21swapper/3810:50:1232
25248991961,3cyclictest0-21swapper/3810:50:1232
2521999195187,5cyclictest0-21swapper/1410:51:056
2521999195187,5cyclictest0-21swapper/1410:51:056
2521999194186,5cyclictest24944-21chrt11:04:266
2521999194186,5cyclictest24944-21chrt11:04:266
2521999194186,5cyclictest24944-21chrt11:04:256
2521999193187,4cyclictest0-21swapper/1410:06:016
2521999193187,4cyclictest0-21swapper/1410:06:016
2521999193186,3cyclictest3541-21CPU6
2521999193186,3cyclictest3541-21CPU6
2521999193186,3cyclictest3541-21CPU6
2521999193183,6cyclictest2459-21CPU6
2521999193183,6cyclictest2459-21CPU6
2521999193178,13cyclictest0-21swapper/1409:30:306
2521999193178,13cyclictest0-21swapper/1409:30:306
2521999193178,13cyclictest0-21swapper/1409:30:306
2521999192189,2cyclictest0-21swapper/1412:07:106
2521999192189,2cyclictest0-21swapper/1412:07:106
2521999191185,4cyclictest0-21swapper/1410:20:076
2521999191185,4cyclictest0-21swapper/1410:20:076
2521999191185,4cyclictest0-21swapper/1410:20:076
2521999190184,4cyclictest0-21swapper/1409:50:266
2521999190184,4cyclictest0-21swapper/1409:50:266
2521999190184,4cyclictest0-21swapper/1409:50:266
2521999190180,8cyclictest0-21swapper/1411:12:266
2521999190180,8cyclictest0-21swapper/1411:12:266
2521999189183,4cyclictest0-21swapper/1407:45:146
2521999187182,4cyclictest0-21swapper/1411:52:106
2521999187182,4cyclictest0-21swapper/1411:52:096
2521999187179,6cyclictest0-21swapper/1410:36:326
2521999187179,6cyclictest0-21swapper/1410:36:326
2521999187179,6cyclictest0-21swapper/1410:36:316
2521999186179,5cyclictest755-21systemd-journal10:44:006
2521999186179,5cyclictest755-21systemd-journal10:44:006
2522699185166,9cyclictest171rcu_preempt10:40:5913
2522699185166,9cyclictest171rcu_preempt10:40:5813
2521999185179,4cyclictest0-21swapper/1411:55:376
2521999185179,4cyclictest0-21swapper/1411:55:376
2521999185179,4cyclictest0-21swapper/1411:55:376
25240991840,2cyclictest0-21swapper/3109:00:1225
25240991840,2cyclictest0-21swapper/3109:00:1225
2521999184181,2cyclictest0-21swapper/1412:10:516
2521999184181,2cyclictest0-21swapper/1412:10:516
2521999184181,2cyclictest0-21swapper/1412:10:506
2521999184177,4cyclictest2466-21CPU6
2521999184169,13cyclictest0-21swapper/1411:16:596
2521999184169,13cyclictest0-21swapper/1411:16:596
2521999184169,13cyclictest0-21swapper/1411:16:586
2521999184168,13cyclictest0-21swapper/1409:15:116
2521999183178,4cyclictest0-21swapper/1412:33:206
2521999183178,4cyclictest0-21swapper/1412:33:206
2521999183178,4cyclictest0-21swapper/1412:33:196
2521999183177,4cyclictest0-21swapper/1411:06:306
2521999183177,4cyclictest0-21swapper/1411:06:306
2521999183176,3cyclictest3545-21CPU6
2521999183176,3cyclictest3545-21CPU6
2521999183176,3cyclictest3545-21CPU6
2521999183174,5cyclictest2464-21CPU6
2521999183174,5cyclictest2464-21CPU6
2521999183174,5cyclictest2464-21CPU6
2521999182174,4cyclictest2459-21CPU6
2521999182174,4cyclictest2459-21CPU6
2521999182173,7cyclictest0-21swapper/1409:39:506
2521999182173,7cyclictest0-21swapper/1409:39:506
2521999182173,7cyclictest0-21swapper/1409:39:506
2521999182171,5cyclictest1367-21dbus-daemon09:25:136
2521999182171,5cyclictest1367-21dbus-daemon09:25:136
2521999182171,5cyclictest1367-21dbus-daemon09:25:136
2521999182169,11cyclictest1367-21dbus-daemon10:04:536
2521999182169,11cyclictest1367-21dbus-daemon10:04:526
2521999182169,11cyclictest1367-21dbus-daemon10:04:526
2521999182166,13cyclictest0-21swapper/1411:27:596
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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