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2026-07-25 - 00:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri Jul 24, 2026 13:02:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20541992501,245cyclictest0-21swapper/009:40:230
20541992501,245cyclictest0-21swapper/009:40:230
20541992501,245cyclictest0-21swapper/009:40:020
20541992501,245cyclictest0-21swapper/009:40:020
20541992481,243cyclictest4398-21qemu-system-x8612:03:260
20541992481,243cyclictest4398-21qemu-system-x8612:03:250
20541992461,242cyclictest0-21swapper/011:20:200
20541992461,242cyclictest0-21swapper/011:20:200
20541992461,242cyclictest0-21swapper/011:20:200
20541992431,239cyclictest0-21swapper/012:20:160
20541992431,239cyclictest0-21swapper/012:20:160
20541992420,239cyclictest17484-21nfsd09:20:200
20541992420,239cyclictest17484-21nfsd09:20:200
20541992420,239cyclictest17484-21nfsd09:20:200
20541992420,239cyclictest0-21swapper/012:35:180
20541992420,239cyclictest0-21swapper/012:35:180
20541992400,232cyclictest0-21swapper/010:01:280
20541992400,232cyclictest0-21swapper/010:01:270
20541992400,232cyclictest0-21swapper/010:01:270
20541992391,236cyclictest0-21swapper/008:15:270
20541992391,236cyclictest0-21swapper/008:15:270
20541992371,221cyclictest0-21swapper/009:25:160
20541992371,221cyclictest0-21swapper/009:25:150
20541992371,221cyclictest0-21swapper/009:25:150
20541992370,234cyclictest0-21swapper/010:41:150
20541992370,234cyclictest0-21swapper/010:41:140
20541992370,234cyclictest0-21swapper/010:41:140
20541992361,232cyclictest0-21swapper/008:21:230
20541992361,232cyclictest0-21swapper/008:21:220
20541992360,232cyclictest2462-21CPU0
20541992360,232cyclictest2462-21CPU0
20541992340,229cyclictest0-21swapper/009:48:180
20541992340,229cyclictest0-21swapper/009:48:170
20541992331,227cyclictest2466-21CPU0
20541992331,227cyclictest2466-21CPU0
20541992321,228cyclictest1367-21dbus-daemon10:35:120
20541992321,228cyclictest1367-21dbus-daemon10:35:120
20541992320,226cyclictest0-21swapper/009:10:520
20541992320,226cyclictest0-21swapper/009:10:520
20541992311,227cyclictest27332-21sshd12:32:240
20541992311,227cyclictest27332-21sshd12:32:230
20541992311,226cyclictest0-21swapper/011:45:130
20541992311,226cyclictest0-21swapper/011:45:130
20541992310,221cyclictest0-21swapper/010:30:220
20541992310,221cyclictest0-21swapper/010:30:210
20541992310,221cyclictest0-21swapper/010:30:210
20541992300,223cyclictest23705-21sshd11:10:170
20541992300,223cyclictest23705-21sshd11:10:170
20541992291,221cyclictest0-21swapper/009:50:400
20541992291,221cyclictest0-21swapper/009:50:400
20541992271,222cyclictest0-21swapper/010:20:010
20541992271,222cyclictest0-21swapper/010:20:010
20541992270,223cyclictest0-21swapper/008:52:040
20541992260,223cyclictest0-21swapper/007:55:240
20541992260,223cyclictest0-21swapper/007:55:240
20541992250,223cyclictest0-21swapper/010:48:250
20541992250,223cyclictest0-21swapper/010:48:250
20541992250,223cyclictest0-21swapper/010:48:250
20541992250,222cyclictest0-21swapper/009:33:080
20541992250,222cyclictest0-21swapper/009:33:080
20541992250,222cyclictest0-21swapper/009:33:080
20541992250,216cyclictest0-21swapper/011:00:450
20541992250,216cyclictest0-21swapper/011:00:450
20541992242,216cyclictest37265-21CPU0
20541992242,216cyclictest37265-21CPU0
20541992241,219cyclictest0-21swapper/008:55:220
20541992241,219cyclictest0-21swapper/008:55:220
20541992240,221cyclictest0-21swapper/010:58:340
20541992240,221cyclictest0-21swapper/010:58:340
20541992231,217cyclictest0-21swapper/009:16:150
20541992231,217cyclictest0-21swapper/009:16:150
20541992230,221cyclictest0-21swapper/012:07:580
20541992230,221cyclictest0-21swapper/012:07:580
20541992230,218cyclictest0-21swapper/010:21:180
20541992230,218cyclictest0-21swapper/010:21:170
20541992230,217cyclictest0-21swapper/010:12:040
20541992230,217cyclictest0-21swapper/010:12:030
20541992230,217cyclictest0-21swapper/010:12:030
20541992220,219cyclictest0-21swapper/011:41:030
20541992220,219cyclictest0-21swapper/011:41:020
20541992220,219cyclictest0-21swapper/011:41:020
20541992201,216cyclictest1-21systemd11:16:110
20541992201,216cyclictest1-21systemd11:16:110
20541992201,216cyclictest1-21systemd11:16:110
20541992201,216cyclictest0-21swapper/012:17:360
20541992201,216cyclictest0-21swapper/012:17:350
20541992201,216cyclictest0-21swapper/012:17:350
20541992200,217cyclictest0-21swapper/011:35:020
20541992200,217cyclictest0-21swapper/011:35:020
20541992200,217cyclictest0-21swapper/011:35:010
20541992191,214cyclictest0-21swapper/012:27:370
20541992191,214cyclictest0-21swapper/012:27:370
20541992190,217cyclictest0-21swapper/008:06:290
20541992190,217cyclictest0-21swapper/008:06:290
20541992180,216cyclictest0-21swapper/008:47:460
20541992180,216cyclictest0-21swapper/008:47:460
20541992180,215cyclictest17480-21nfsd08:15:000
20541992180,215cyclictest17480-21nfsd08:15:000
20541992170,215cyclictest0-21swapper/007:15:050
20541992160,213cyclictest0-21swapper/011:08:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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