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2026-05-10 - 06:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun May 10, 2026 01:01:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1805599220209,8cyclictest20255-21sshd21:32:5026
1805599220209,8cyclictest20255-21sshd21:32:5026
1805599218211,5cyclictest0-21swapper/3200:10:0026
1805599218211,5cyclictest0-21swapper/3200:10:0026
1805599216209,5cyclictest0-21swapper/3222:01:2126
1805599216209,5cyclictest0-21swapper/3222:01:2126
1805599215209,5cyclictest0-21swapper/3219:40:0026
1805599215209,5cyclictest0-21swapper/3219:40:0026
1805599215207,5cyclictest1-21systemd00:00:2626
1805599215207,5cyclictest1-21systemd00:00:2526
1805599213208,4cyclictest0-21swapper/3223:15:2426
1805599213208,4cyclictest0-21swapper/3223:15:2426
1805599211201,8cyclictest0-21swapper/3223:53:4026
1805599211201,8cyclictest0-21swapper/3223:53:4026
1805599208204,2cyclictest27061-21ls21:10:1526
1805599208204,2cyclictest27061-21ls21:10:1526
1805599208200,6cyclictest0-21swapper/3222:52:4726
1805599208200,6cyclictest0-21swapper/3222:52:4626
1805599207202,4cyclictest0-21swapper/3221:28:5926
1805599207202,4cyclictest0-21swapper/3221:28:5926
1805599207201,4cyclictest0-21swapper/3200:35:4126
1805599207201,4cyclictest0-21swapper/3200:35:4026
1805599206194,9cyclictest0-21swapper/3221:44:4726
1805599206194,9cyclictest0-21swapper/3221:44:4726
1805599205197,5cyclictest0-21swapper/3221:50:4326
1805599205197,5cyclictest0-21swapper/3221:50:4226
1805599205197,5cyclictest0-21swapper/3221:50:4226
1805599204197,5cyclictest0-21swapper/3223:26:1126
1805599204197,5cyclictest0-21swapper/3223:26:1126
1805599204196,6cyclictest0-21swapper/3200:20:2426
1805599204196,6cyclictest0-21swapper/3200:20:2426
1805699203187,12cyclictest3546-21CPU27
1805699203187,12cyclictest3546-21CPU27
1805699203187,12cyclictest3546-21CPU27
1805599203198,4cyclictest0-21swapper/3200:14:5126
1805599203198,4cyclictest0-21swapper/3200:14:5126
1805599203198,4cyclictest0-21swapper/3200:14:5026
1805599203197,4cyclictest0-21swapper/3223:56:0326
1805599203197,4cyclictest0-21swapper/3223:56:0326
1805599203197,4cyclictest0-21swapper/3220:22:1926
1805599203197,4cyclictest0-21swapper/3220:22:1926
1806099202188,11cyclictest0-21swapper/3723:38:4031
1806099202188,11cyclictest0-21swapper/3723:38:3931
1805599202196,4cyclictest0-21swapper/3221:00:2626
1805599202196,4cyclictest0-21swapper/3221:00:2626
1805599202194,5cyclictest2462-21CPU26
1805599202194,5cyclictest2462-21CPU26
1805599202193,7cyclictest39892-21systemctl23:23:1326
1805599202193,7cyclictest39892-21systemctl23:23:1226
1804499202193,7cyclictest1-21systemd23:49:3116
1804499202193,7cyclictest1-21systemd23:49:3016
1803499202192,9cyclictest0-21swapper/1422:55:016
1803499202192,9cyclictest0-21swapper/1422:55:006
1805699201192,3cyclictest4408-21CPU27
1805699201192,3cyclictest4408-21CPU27
1804499201196,4cyclictest0-21swapper/2300:39:2616
1804499201196,4cyclictest0-21swapper/2300:39:2516
1804499201180,17cyclictest0-21swapper/2323:41:3916
1804499201180,17cyclictest0-21swapper/2323:41:3916
1806199200196,2cyclictest0-21swapper/3821:20:2032
1806199200196,2cyclictest0-21swapper/3821:20:2032
1805599200193,5cyclictest0-21swapper/3223:32:3226
1805599200193,5cyclictest0-21swapper/3223:32:3226
1805599200192,5cyclictest0-21swapper/3200:17:2526
1805599200192,5cyclictest0-21swapper/3200:17:2526
1803499200192,6cyclictest0-21swapper/1422:55:126
1803499200192,6cyclictest0-21swapper/1422:55:126
1805699199192,5cyclictest0-21swapper/3322:11:2627
1805699199192,5cyclictest0-21swapper/3322:11:2627
1805599199195,2cyclictest26210-21systemd21:56:3726
1805599199195,2cyclictest26210-21systemd21:56:3626
1805599199193,4cyclictest37257-21qemu-system-x8622:13:1826
1805599199193,4cyclictest37257-21qemu-system-x8622:13:1826
1805599199192,5cyclictest10713-21tune2fs21:20:1926
1805599199192,5cyclictest10713-21tune2fs21:20:1826
1805599198192,4cyclictest0-21swapper/3221:47:5626
1805599198192,4cyclictest0-21swapper/3221:47:5626
1805599198192,4cyclictest0-21swapper/3221:47:5626
1805599198190,5cyclictest0-21swapper/3219:55:0126
1805599198190,5cyclictest0-21swapper/3219:55:0126
1805599197190,5cyclictest0-21swapper/3220:45:3126
1805599197190,5cyclictest0-21swapper/3220:45:3126
1805699196189,5cyclictest0-21swapper/3322:09:4527
1805699196189,5cyclictest0-21swapper/3322:09:4527
1805599196191,3cyclictest0-21swapper/3223:15:0126
1805599196191,3cyclictest0-21swapper/3223:15:0026
1805599196188,5cyclictest3535-21qemu-system-x8620:35:5326
1805599196188,5cyclictest3535-21qemu-system-x8620:35:5326
1804499196190,5cyclictest0-21swapper/2300:08:0116
1804499196190,5cyclictest0-21swapper/2300:08:0116
1805599195186,7cyclictest0-21swapper/3221:17:1926
1805599195186,7cyclictest0-21swapper/3221:17:1826
1804499195190,4cyclictest0-21swapper/2323:29:1716
1804499195190,4cyclictest0-21swapper/2323:29:1716
1805599194186,6cyclictest0-21swapper/3219:55:2126
1805599194186,6cyclictest0-21swapper/3219:55:2026
1805599194183,9cyclictest0-21swapper/3221:00:0026
1805599194183,9cyclictest0-21swapper/3220:59:5926
1805699193186,4cyclictest25005-21gdbus22:35:0727
1805699193185,6cyclictest0-21swapper/3320:20:0027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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