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2026-01-28 - 07:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Jan 28, 2026 01:01:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2251299245240,3cyclictest0-21swapper/2321:10:1716
2251299245240,3cyclictest0-21swapper/2321:10:1716
2251699240235,3cyclictest0-21swapper/2600:20:2819
2251699240235,3cyclictest0-21swapper/2600:20:2819
2251699240235,3cyclictest0-21swapper/2600:20:2819
2250899240227,9cyclictest0-21swapper/2019:35:1813
2250899240227,9cyclictest0-21swapper/2019:35:1813
2251999239236,2cyclictest0-21swapper/2923:41:3422
2251999239236,2cyclictest0-21swapper/2923:41:3422
2251999239236,2cyclictest0-21swapper/2923:41:3422
2250899234221,11cyclictest0-21swapper/2023:10:1813
2250899234221,11cyclictest0-21swapper/2023:10:1813
2252799222218,2cyclictest0-21swapper/3623:30:1730
2252799222218,2cyclictest0-21swapper/3623:30:1730
2250699218209,6cyclictest0-21swapper/1821:10:1410
2250699218209,6cyclictest0-21swapper/1821:10:1410
2250699217212,4cyclictest0-21swapper/1821:34:0210
2250699217212,4cyclictest0-21swapper/1821:34:0210
2250699217212,4cyclictest0-21swapper/1821:34:0210
2249599216213,2cyclictest0-21swapper/820:20:2738
2249599216213,2cyclictest0-21swapper/820:20:2738
2249699214209,3cyclictest0-21swapper/923:23:2239
2249699214209,3cyclictest0-21swapper/923:23:2239
2250699208203,4cyclictest0-21swapper/1820:24:1810
2250699208203,4cyclictest0-21swapper/1820:24:1810
2250599208187,17cyclictest5760-21kworker/u82:2-events_unbound22:12:009
2250599208187,17cyclictest5760-21kworker/u82:2-events_unbound22:12:009
2250599208187,17cyclictest5760-21kworker/u82:2-events_unbound22:12:009
2249999204200,2cyclictest0-21swapper/1219:45:244
2249999204200,2cyclictest0-21swapper/1219:45:244
2250699203197,4cyclictest0-21swapper/1820:15:1810
2250699203197,4cyclictest0-21swapper/1820:15:1810
2250699203197,4cyclictest0-21swapper/1820:10:1110
2250699203197,4cyclictest0-21swapper/1820:10:1110
2250199203188,13cyclictest0-21swapper/1400:04:546
2250199203188,13cyclictest0-21swapper/1400:04:546
2250199203188,13cyclictest0-21swapper/1400:04:546
2250099202198,2cyclictest0-21swapper/1319:25:175
2250099202198,2cyclictest0-21swapper/1319:25:175
2250099202192,8cyclictest0-21swapper/1319:30:165
2250099202192,8cyclictest0-21swapper/1319:30:165
224949920214,96cyclictest0-21swapper/721:15:1837
224949920214,96cyclictest0-21swapper/721:15:1837
2250099199189,8cyclictest0-21swapper/1319:35:205
2250099199189,8cyclictest0-21swapper/1319:35:195
2250699198190,3cyclictest3543-21CPU10
2250699198190,3cyclictest3543-21CPU10
2250699198190,3cyclictest3543-21CPU10
2250699198189,5cyclictest3541-21CPU10
2250699198189,5cyclictest3541-21CPU10
2250699197192,4cyclictest0-21swapper/1821:29:4710
2250699197192,4cyclictest0-21swapper/1821:29:4710
2250699197191,4cyclictest0-21swapper/1821:17:0810
2250699197191,4cyclictest0-21swapper/1821:17:0810
2250699196191,4cyclictest0-21swapper/1821:48:1510
2250699196191,4cyclictest0-21swapper/1821:48:1510
2250699196191,4cyclictest0-21swapper/1821:48:1510
22484991952,4cyclictest2461-21CPU0
22484991952,4cyclictest2461-21CPU0
22484991952,4cyclictest2461-21CPU0
2251099194178,12cyclictest0-21swapper/2222:34:4215
2251099194178,12cyclictest0-21swapper/2222:34:4215
2250099194186,6cyclictest0-21swapper/1300:03:105
2250099194186,6cyclictest0-21swapper/1300:03:105
2250099194186,6cyclictest0-21swapper/1300:03:105
2248699194185,5cyclictest2461-21CPU12
2248699194185,5cyclictest2461-21CPU12
2248699194185,5cyclictest2461-21CPU12
2250699193171,14cyclictest0-21swapper/1820:00:2410
2250699193171,14cyclictest0-21swapper/1820:00:2410
2251599192188,3cyclictest0-21swapper/2523:15:2018
2251599192188,3cyclictest0-21swapper/2523:15:2018
2250699192187,4cyclictest0-21swapper/1821:23:1210
2250699192187,4cyclictest0-21swapper/1821:23:1210
2250699192187,4cyclictest0-21swapper/1821:23:1210
22510991915,183cyclictest0-21swapper/2200:30:1215
22510991915,183cyclictest0-21swapper/2200:30:1115
2248699191184,3cyclictest37268-21CPU12
2248699191184,3cyclictest37268-21CPU12
2248699191184,3cyclictest37268-21CPU12
2251999189186,2cyclictest0-21swapper/2923:57:0822
2251999189186,2cyclictest0-21swapper/2923:57:0822
2251999189186,2cyclictest0-21swapper/2923:57:0822
2250699189184,4cyclictest0-21swapper/1821:35:2010
2250699189184,4cyclictest0-21swapper/1821:35:2010
2250099189148,23cyclictest37267-21CPU5
2250099189148,23cyclictest37267-21CPU5
2253099188175,11cyclictest0-21swapper/3900:17:2633
2253099188175,11cyclictest0-21swapper/3900:17:2633
2250699188183,4cyclictest0-21swapper/1821:03:0910
2250699188183,4cyclictest0-21swapper/1821:03:0910
2250699188182,4cyclictest0-21swapper/1820:25:2010
2250699188182,4cyclictest0-21swapper/1820:25:2010
2250699188181,5cyclictest0-21swapper/1820:40:5910
2249799188184,2cyclictest0-21swapper/1020:20:212
2249799188184,2cyclictest0-21swapper/1020:20:212
22484991881,3cyclictest0-21swapper/023:59:220
22484991881,3cyclictest0-21swapper/023:59:220
22484991881,3cyclictest0-21swapper/023:59:220
2250699187182,4cyclictest0-21swapper/1819:50:1810
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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