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2026-02-19 - 14:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Feb 19, 2026 13:03:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2025999240216,17cyclictest0-21swapper/2512:20:1818
2025999240216,17cyclictest0-21swapper/2512:20:1718
2025999227207,9cyclictest0-21swapper/2511:05:1918
2025999227207,9cyclictest0-21swapper/2511:05:1918
2025999215209,4cyclictest0-21swapper/2508:50:1518
2025999215209,4cyclictest0-21swapper/2508:50:1418
2025999214204,6cyclictest3610-21CPU18
2025999214204,6cyclictest3610-21CPU18
2025999213206,5cyclictest0-21swapper/2509:25:3418
2025999213206,5cyclictest0-21swapper/2509:25:3318
2025999213206,5cyclictest0-21swapper/2509:25:3318
2025999207200,5cyclictest0-21swapper/2511:55:2018
2025999207200,5cyclictest0-21swapper/2511:55:1918
2025399207170,30cyclictest37354-21CPU14
2025399207170,30cyclictest37354-21CPU14
2025399207170,30cyclictest37354-21CPU14
2025999204196,6cyclictest0-21swapper/2510:32:1618
2025999204196,6cyclictest0-21swapper/2510:32:1618
2025999204196,6cyclictest0-21swapper/2510:32:1518
2025999202190,9cyclictest0-21swapper/2509:20:1618
2025999202190,9cyclictest0-21swapper/2509:20:1518
2025999201192,5cyclictest37268-21CPU18
2025999201192,5cyclictest37268-21CPU18
2025999200192,5cyclictest0-21swapper/2510:19:2318
2025999200192,5cyclictest0-21swapper/2510:19:2318
2025999200192,5cyclictest0-21swapper/2510:19:2318
2025999199191,6cyclictest0-21swapper/2512:05:5818
2025999199191,6cyclictest0-21swapper/2512:05:5718
2025999199191,6cyclictest0-21swapper/2512:05:5718
2025999199191,6cyclictest0-21swapper/2509:43:0318
2025999199191,6cyclictest0-21swapper/2509:43:0318
2025999199191,6cyclictest0-21swapper/2509:43:0318
2025999199190,5cyclictest3543-21CPU18
2025999199190,5cyclictest3543-21CPU18
2025999199189,7cyclictest0-21swapper/2510:50:2818
2025999199189,7cyclictest0-21swapper/2510:50:2818
2025999199189,7cyclictest0-21swapper/2510:50:2818
2025999198191,5cyclictest0-21swapper/2511:00:1118
2025999198191,5cyclictest0-21swapper/2511:00:1118
2025999198191,5cyclictest0-21swapper/2511:00:1118
2025999197191,3cyclictest33833-21bash10:10:2518
2025999197191,3cyclictest33833-21bash10:10:2418
2025999197188,7cyclictest0-21swapper/2510:55:2018
2025999197188,7cyclictest0-21swapper/2510:55:2018
2025999197185,9cyclictest0-21swapper/2511:20:1718
2025999197185,9cyclictest0-21swapper/2511:20:1718
2025999197184,6cyclictest0-21swapper/2510:44:5518
2025999197184,6cyclictest0-21swapper/2510:44:5518
2025999196189,5cyclictest0-21swapper/2510:05:0118
2025999196189,5cyclictest0-21swapper/2510:05:0118
2025999196189,5cyclictest0-21swapper/2510:05:0018
2025999196184,7cyclictest0-21swapper/2509:13:1218
2025999196184,7cyclictest0-21swapper/2509:13:1218
2025999196184,7cyclictest0-21swapper/2509:13:1218
2025999196183,10cyclictest3679-21sshd12:11:5618
2025999196183,10cyclictest3679-21sshd12:11:5518
2025999196183,10cyclictest3679-21sshd12:11:5518
2025999195187,6cyclictest0-21swapper/2511:10:1918
2025999195187,6cyclictest0-21swapper/2511:10:1918
2025999195185,7cyclictest0-21swapper/2512:30:2118
2025999195185,7cyclictest0-21swapper/2512:30:2018
2025999195185,7cyclictest0-21swapper/2512:30:2018
2025999195180,11cyclictest0-21swapper/2510:25:1418
2025999195180,11cyclictest0-21swapper/2510:25:1418
2025999195180,11cyclictest0-21swapper/2510:25:1418
2025399195188,5cyclictest0-21swapper/2109:29:1514
2025399195188,5cyclictest0-21swapper/2109:29:1514
2025399195188,5cyclictest0-21swapper/2109:29:1514
2025999194186,5cyclictest0-21swapper/2509:58:2118
2025999194186,5cyclictest0-21swapper/2509:58:2118
2025999194186,5cyclictest0-21swapper/2509:58:2118
2025999194186,4cyclictest0-21swapper/2511:32:0718
2025999194186,4cyclictest0-21swapper/2511:32:0718
2025999194186,4cyclictest0-21swapper/2511:32:0618
2025999194185,7cyclictest0-21swapper/2512:36:3218
2025999194185,7cyclictest0-21swapper/2512:36:3218
2025999194185,7cyclictest0-21swapper/2512:36:3218
2025999194184,8cyclictest0-21swapper/2510:46:1118
2025999194184,8cyclictest0-21swapper/2510:46:1018
2025999193182,5cyclictest0-21swapper/2509:32:2518
2025999193182,5cyclictest0-21swapper/2509:32:2418
2024099193178,7cyclictest0-21swapper/1007:21:122
2024099193178,7cyclictest0-21swapper/1007:21:122
2023999193171,21cyclictest0-21swapper/910:45:4139
2023999193171,21cyclictest0-21swapper/910:45:4039
2023999193146,45cyclictest0-21swapper/909:51:1639
2023999193146,45cyclictest0-21swapper/909:51:1539
2025999192185,5cyclictest0-21swapper/2512:19:4418
2025999192185,5cyclictest0-21swapper/2512:19:4418
2025999192185,5cyclictest0-21swapper/2512:19:4318
2025999192182,6cyclictest0-21swapper/2508:50:0518
2025999192182,6cyclictest0-21swapper/2508:50:0418
2025999192182,4cyclictest3544-21CPU18
2025999192182,4cyclictest3544-21CPU18
2025999192182,4cyclictest3544-21CPU18
2025999192181,8cyclictest27966-21uname11:28:0218
2025999192181,8cyclictest27966-21uname11:28:0218
2025999192181,8cyclictest27966-21uname11:28:0218
2026999191177,7cyclictest171rcu_preempt09:37:3229
2026999191177,7cyclictest171rcu_preempt09:37:3229
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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