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2026-06-25 - 14:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Jun 25, 2026 13:03:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128299256233,7cyclictest0-21swapper/211:00:2012
128299256233,7cyclictest0-21swapper/211:00:1912
128299223215,6cyclictest0-21swapper/210:47:5312
128299223215,6cyclictest0-21swapper/210:47:5312
128299222210,9cyclictest1711-21sshd09:31:0012
128299222210,9cyclictest1711-21sshd09:31:0012
130299217186,18cyclictest0-21swapper/1608:20:468
130299217186,18cyclictest0-21swapper/1608:20:468
128299214207,3cyclictest37267-21CPU12
128299214207,3cyclictest37267-21CPU12
128299214207,3cyclictest37267-21CPU12
128299213205,6cyclictest0-21swapper/210:20:0012
128299213205,6cyclictest0-21swapper/210:20:0012
128299212206,4cyclictest0-21swapper/209:12:1212
128299212206,4cyclictest0-21swapper/209:12:1212
13219921053,145cyclictest3610-21CPU26
13219921053,145cyclictest3610-21CPU26
13219921053,145cyclictest3610-21CPU26
128299210205,4cyclictest0-21swapper/210:07:1212
128299210205,4cyclictest0-21swapper/210:07:1112
128299210205,4cyclictest0-21swapper/210:07:1112
128299210203,5cyclictest0-21swapper/207:20:4512
128299210203,5cyclictest0-21swapper/207:20:4512
128299210202,6cyclictest2462-21CPU12
128299210202,6cyclictest2462-21CPU12
128299210202,6cyclictest2462-21CPU12
128299209204,4cyclictest0-21swapper/209:40:4712
128299209204,4cyclictest0-21swapper/209:40:4712
128299209204,4cyclictest0-21swapper/209:40:4612
128299209200,5cyclictest3548-21CPU12
128299209200,5cyclictest3548-21CPU12
128299208203,4cyclictest0-21swapper/210:21:5912
128299208203,4cyclictest0-21swapper/210:21:5912
128299208201,5cyclictest0-21swapper/211:06:3212
128299208201,5cyclictest0-21swapper/211:06:3212
128299208201,5cyclictest0-21swapper/211:06:3212
128299207203,2cyclictest0-21swapper/207:40:1912
128299207203,2cyclictest0-21swapper/207:40:1812
128299207200,5cyclictest0-21swapper/210:53:2512
128299207200,5cyclictest0-21swapper/210:53:2512
128299207200,5cyclictest0-21swapper/210:53:2512
128299207200,5cyclictest0-21swapper/210:41:3212
128299207200,5cyclictest0-21swapper/210:41:3212
128299207200,5cyclictest0-21swapper/210:41:3112
128299207200,5cyclictest0-21swapper/209:47:0812
128299207200,5cyclictest0-21swapper/209:47:0812
128299207200,5cyclictest0-21swapper/209:47:0712
128299204201,2cyclictest0-21swapper/211:30:4012
128299204201,2cyclictest0-21swapper/211:30:3912
128299204201,2cyclictest0-21swapper/211:30:3912
128299204199,4cyclictest0-21swapper/209:52:4512
128299204199,4cyclictest0-21swapper/209:52:4512
128299204198,4cyclictest17480-21nfsd10:40:0412
128299204198,4cyclictest17480-21nfsd10:40:0312
128299204198,4cyclictest17480-21nfsd10:40:0312
128299204197,4cyclictest33985-21sshd09:37:3812
128299204197,4cyclictest33985-21sshd09:37:3812
128299204193,8cyclictest37346-21qemu-system-x8609:59:2912
128299204193,8cyclictest37346-21qemu-system-x8609:59:2912
128299204193,8cyclictest37346-21qemu-system-x8609:59:2912
128299203198,4cyclictest0-21swapper/208:05:1412
128299203198,4cyclictest0-21swapper/208:05:1412
128299203197,5cyclictest0-21swapper/210:27:1612
128299203197,5cyclictest0-21swapper/210:27:1612
128299203196,5cyclictest3834-21cstates11:10:1412
128299203196,5cyclictest3834-21cstates11:10:1412
131199202194,5cyclictest2459-21CPU17
131199202194,5cyclictest2459-21CPU17
128299202195,5cyclictest0-21swapper/209:21:0712
128299202195,5cyclictest0-21swapper/209:21:0612
128299200195,4cyclictest0-21swapper/209:27:3312
128299200195,4cyclictest0-21swapper/209:27:3212
128299200195,4cyclictest0-21swapper/209:27:3212
128299199195,3cyclictest0-21swapper/209:15:3812
128299199195,3cyclictest0-21swapper/209:15:3712
128299199195,3cyclictest0-21swapper/209:15:3712
128299196189,5cyclictest0-21swapper/207:35:1712
128299196189,5cyclictest0-21swapper/207:35:1712
128299196183,10cyclictest0-21swapper/210:03:1212
128299196183,10cyclictest0-21swapper/210:03:1212
128299195188,5cyclictest37257-21qemu-system-x8609:05:5212
128299195188,5cyclictest37257-21qemu-system-x8609:05:5112
128299195188,5cyclictest37257-21qemu-system-x8609:05:5112
128299195187,6cyclictest3535-21qemu-system-x8610:10:2112
128299195187,6cyclictest3535-21qemu-system-x8610:10:2112
128299195187,6cyclictest3535-21qemu-system-x8610:10:2112
128099195168,24cyclictest0-21swapper/010:41:090
128099195168,24cyclictest0-21swapper/010:41:090
128099195168,24cyclictest0-21swapper/010:41:080
128299193186,5cyclictest0-21swapper/210:31:3912
128299193186,5cyclictest0-21swapper/210:31:3812
128299192186,4cyclictest0-21swapper/207:49:5212
128299192186,4cyclictest0-21swapper/207:49:5112
128299192185,5cyclictest0-21swapper/207:25:1212
128299192185,5cyclictest0-21swapper/207:25:1212
13219919044,143cyclictest0-21swapper/3210:05:0126
13219919044,143cyclictest0-21swapper/3210:05:0026
129999190151,28cyclictest0-21swapper/1309:22:115
129999190151,28cyclictest0-21swapper/1309:22:105
128299190184,4cyclictest0-21swapper/208:15:2312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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