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2026-02-27 - 22:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Fri Feb 27, 2026 13:03:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2974199219203,12cyclictest0-21swapper/3410:04:0428
2974199219203,12cyclictest0-21swapper/3410:04:0328
2972599218210,5cyclictest0-21swapper/2110:59:5814
2972599218210,5cyclictest0-21swapper/2110:59:5814
2972299217211,4cyclictest0-21swapper/1807:55:2010
2970799216213,2cyclictest0-21swapper/507:55:2835
2973899215208,4cyclictest0-21swapper/3112:16:3825
2973899215208,4cyclictest0-21swapper/3112:16:3825
2972599215201,11cyclictest0-21swapper/2112:39:5914
2972599215201,11cyclictest0-21swapper/2112:39:5914
2971799211206,3cyclictest0-21swapper/1408:35:166
2971799211206,3cyclictest0-21swapper/1408:35:166
2973599210195,13cyclictest0-21swapper/2812:17:0221
2973599210195,13cyclictest0-21swapper/2812:17:0221
2971999209203,3cyclictest0-21swapper/1610:10:198
2971999209203,3cyclictest0-21swapper/1610:10:198
2972599204194,8cyclictest0-21swapper/2110:45:3614
2972599204194,8cyclictest0-21swapper/2110:45:3614
2971499202198,2cyclictest0-21swapper/1109:12:453
2971499202198,2cyclictest0-21swapper/1109:12:453
2973599201187,12cyclictest0-21swapper/2810:29:4221
2973599201187,12cyclictest0-21swapper/2810:29:4221
2973599201187,12cyclictest0-21swapper/2810:29:4221
2972599201195,4cyclictest0-21swapper/2109:10:4014
2972599201195,4cyclictest0-21swapper/2109:10:4014
2970499201194,4cyclictest0-21swapper/312:00:4623
2970499201194,4cyclictest0-21swapper/312:00:4623
2973499200180,9cyclictest0-21swapper/2711:48:1820
2973499200180,9cyclictest0-21swapper/2711:48:1820
2973499200180,9cyclictest0-21swapper/2711:48:1720
2972599200188,10cyclictest0-21swapper/2107:30:1614
2972599200188,10cyclictest0-21swapper/2107:30:1614
2971999200196,2cyclictest0-21swapper/1612:06:278
2971999200196,2cyclictest0-21swapper/1612:06:278
2971999200196,2cyclictest0-21swapper/1612:06:268
2972599199192,5cyclictest1367-21dbus-daemon12:31:2114
2972599199192,5cyclictest1367-21dbus-daemon12:31:2114
2972599199192,5cyclictest1367-21dbus-daemon12:31:2114
2970199199194,3cyclictest0-21swapper/007:50:160
2970199199194,3cyclictest0-21swapper/007:50:150
2973999198193,3cyclictest0-21swapper/3207:55:0026
2973999198193,3cyclictest0-21swapper/3207:54:5926
2972599198190,7cyclictest0-21swapper/2108:50:2114
2971999198194,2cyclictest0-21swapper/1607:55:218
2970999198179,15cyclictest0-21swapper/607:35:0136
2970999198179,15cyclictest0-21swapper/607:35:0136
2973499197190,5cyclictest0-21swapper/2707:35:1420
2973499197190,5cyclictest0-21swapper/2707:35:1420
2974799196187,2cyclictest0-21swapper/3909:05:1833
2974799196187,2cyclictest0-21swapper/3909:05:1833
2974799196187,2cyclictest0-21swapper/3909:05:1733
2973899196182,11cyclictest0-21swapper/3107:50:2125
2973899196182,11cyclictest0-21swapper/3107:50:2025
2973399196180,14cyclictest0-21swapper/2610:37:5319
2973399196180,14cyclictest0-21swapper/2610:37:5319
2971099196192,2cyclictest0-21swapper/712:09:3737
2971099196192,2cyclictest0-21swapper/712:09:3737
2971099196192,2cyclictest0-21swapper/712:09:3737
2970499196189,5cyclictest0-21swapper/307:55:1423
2970499196189,3cyclictest4407-21CPU23
2972599195189,2cyclictest3544-21CPU14
2972599195189,2cyclictest3544-21CPU14
2970499194189,4cyclictest0-21swapper/311:58:4223
2970499194189,4cyclictest0-21swapper/311:58:4123
2973499193183,6cyclictest3548-21CPU20
2973499193183,6cyclictest3548-21CPU20
2973499193183,6cyclictest3548-21CPU20
2972599193184,5cyclictest4407-21CPU14
2972599193184,5cyclictest4407-21CPU14
29724991930,80cyclictest0-21swapper/2007:50:2013
29724991930,80cyclictest0-21swapper/2007:50:2013
2972599192185,5cyclictest0-21swapper/2112:23:5314
2972599192185,5cyclictest0-21swapper/2112:23:5314
2972599191180,9cyclictest0-21swapper/2111:10:1314
2972599191180,9cyclictest0-21swapper/2111:10:1314
2972599191180,9cyclictest0-21swapper/2111:10:1214
2972499191159,27cyclictest0-21swapper/2012:26:5813
2972499191159,27cyclictest0-21swapper/2012:26:5813
2972499191159,27cyclictest0-21swapper/2012:26:5813
2971099191188,2cyclictest0-21swapper/709:14:2537
2971099191188,2cyclictest0-21swapper/709:14:2537
2974599190158,26cyclictest0-21swapper/3709:45:5331
2974599190158,26cyclictest0-21swapper/3709:45:5331
2974599190158,26cyclictest0-21swapper/3709:45:5231
2973499190184,4cyclictest0-21swapper/2710:11:0920
2973499190184,4cyclictest0-21swapper/2710:11:0920
2970499190185,4cyclictest0-21swapper/308:37:5923
2970499190185,4cyclictest0-21swapper/308:37:5923
2970499190183,3cyclictest37265-21CPU23
2970499190183,3cyclictest37265-21CPU23
2970499190180,3cyclictest3609-21CPU23
2970499190180,3cyclictest3609-21CPU23
2970499190180,3cyclictest3609-21CPU23
2973899189183,4cyclictest0-21swapper/3112:21:0425
2973899189183,4cyclictest0-21swapper/3112:21:0325
2972599189182,5cyclictest0-21swapper/2110:40:0814
2972599189181,4cyclictest0-21swapper/2111:05:0214
2972599189181,4cyclictest0-21swapper/2111:05:0214
2972599189180,7cyclictest0-21swapper/2110:40:2314
2972599189180,7cyclictest0-21swapper/2110:40:2314
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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