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2026-01-27 - 10:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Jan 27, 2026 00:59:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1238999231222,6cyclictest0-21swapper/2622:40:3419
1238999231222,6cyclictest0-21swapper/2622:40:3319
1238999222196,13cyclictest0-21swapper/2623:29:4119
1238999222196,13cyclictest0-21swapper/2623:29:4019
1238999220213,5cyclictest0-21swapper/2620:41:2919
1238999220213,5cyclictest0-21swapper/2620:41:2819
1238799220213,3cyclictest0-21swapper/2421:52:2817
1238799220213,3cyclictest0-21swapper/2421:52:2817
1238999218206,6cyclictest3543-21CPU19
1238999218206,6cyclictest3543-21CPU19
1238999218206,6cyclictest3543-21CPU19
1238999216210,4cyclictest0-21swapper/2622:39:5319
1238999216210,4cyclictest0-21swapper/2622:39:5319
1238999216210,4cyclictest0-21swapper/2622:39:5319
1238999214208,4cyclictest0-21swapper/2621:40:1319
1238999214208,4cyclictest0-21swapper/2621:40:1319
1238999214208,4cyclictest0-21swapper/2621:40:1219
1238999214207,5cyclictest0-21swapper/2623:10:1719
1238999214207,5cyclictest0-21swapper/2623:10:1719
1238999212207,3cyclictest0-21swapper/2619:50:1519
1238999212207,3cyclictest0-21swapper/2619:50:1519
1238499212179,21cyclictest28821-21apt19:20:1214
1238999211197,12cyclictest0-21swapper/2621:30:0219
1238999211197,12cyclictest0-21swapper/2621:30:0219
1238999211197,12cyclictest0-21swapper/2621:30:0219
1238999210202,5cyclictest0-21swapper/2623:20:0419
1238999210202,5cyclictest0-21swapper/2623:20:0419
1238999210195,12cyclictest0-21swapper/2623:20:2019
1238999210195,12cyclictest0-21swapper/2623:20:2019
1238999210195,12cyclictest0-21swapper/2623:20:1919
1240499209199,8cyclictest0-21swapper/3722:10:5131
1240499209199,8cyclictest0-21swapper/3722:10:5131
1240499209199,8cyclictest0-21swapper/3722:10:5131
1238999209203,4cyclictest0-21swapper/2623:37:4819
1238999209203,4cyclictest0-21swapper/2623:37:4819
1238999209196,11cyclictest0-21swapper/2620:25:2019
1238999209196,11cyclictest0-21swapper/2620:25:2019
1236899208203,3cyclictest0-21swapper/823:30:1438
1236899208203,3cyclictest0-21swapper/823:30:1338
1238999206191,7cyclictest0-21swapper/2623:06:1919
1238999206191,7cyclictest0-21swapper/2623:06:1919
1238999205196,6cyclictest2462-21CPU19
1238999205196,6cyclictest2462-21CPU19
1240499204183,19cyclictest0-21swapper/3723:51:2631
1240499204183,19cyclictest0-21swapper/3723:51:2631
1238999204198,4cyclictest0-21swapper/2619:55:2319
1238999204198,4cyclictest0-21swapper/2619:55:2319
1238999204196,5cyclictest0-21swapper/2621:00:1219
1238999204191,11cyclictest0-21swapper/2623:48:1219
1238999204191,11cyclictest0-21swapper/2623:48:1219
1238999203197,4cyclictest0-21swapper/2622:19:3719
1238999203197,4cyclictest0-21swapper/2622:19:3719
1238999203196,5cyclictest0-21swapper/2621:39:4719
1238999203196,5cyclictest0-21swapper/2621:39:4719
1238499203197,4cyclictest0-21swapper/2121:56:3414
1238499203197,4cyclictest0-21swapper/2121:56:3414
1240499202193,6cyclictest0-21swapper/3721:44:1931
1240499202193,6cyclictest0-21swapper/3721:44:1931
1240499202193,6cyclictest0-21swapper/3721:44:1931
1238999202195,4cyclictest18357-21expr23:00:1219
1238999202195,4cyclictest18357-21expr23:00:1219
1238999202195,4cyclictest18357-21expr23:00:1219
1238999202194,6cyclictest0-21swapper/2622:21:1719
1238999202194,6cyclictest0-21swapper/2622:21:1719
1238999202191,7cyclictest37257-21qemu-system-x8622:45:1819
1238999202191,7cyclictest37257-21qemu-system-x8622:45:1819
1238799202178,14cyclictest3541-21CPU17
1238799202178,14cyclictest3541-21CPU17
1238999201193,5cyclictest0-21swapper/2623:55:1819
1238999201193,5cyclictest0-21swapper/2623:55:1819
1238999201193,5cyclictest0-21swapper/2623:55:1819
1240499200193,5cyclictest0-21swapper/3721:46:4231
1240499200193,5cyclictest0-21swapper/3721:46:4231
1238799200194,4cyclictest0-21swapper/2419:25:1817
1238799200194,4cyclictest0-21swapper/2419:25:1817
1237499200188,10cyclictest0-21swapper/1321:12:285
1237499200188,10cyclictest0-21swapper/1321:12:285
1237499200188,10cyclictest0-21swapper/1321:12:285
1236899200185,7cyclictest0-21swapper/821:52:2438
1236899200185,7cyclictest0-21swapper/821:52:2338
1238999199193,4cyclictest0-21swapper/2620:06:2219
1238999198192,4cyclictest37346-21qemu-system-x8622:56:5219
1238999198192,4cyclictest37346-21qemu-system-x8622:56:5219
1238999198189,7cyclictest0-21swapper/2623:53:3319
1238999198189,7cyclictest0-21swapper/2623:53:3319
1238999198188,6cyclictest0-21swapper/2621:30:1919
1238999198188,6cyclictest0-21swapper/2621:30:1919
1238999198188,6cyclictest0-21swapper/2621:30:1919
1238999197190,4cyclictest0-21swapper/2622:34:0319
1238999197190,4cyclictest0-21swapper/2622:34:0319
1238999197186,7cyclictest37352-21CPU19
1238999197186,7cyclictest37352-21CPU19
1237499197183,12cyclictest0-21swapper/1300:38:125
1237499197183,12cyclictest0-21swapper/1300:38:125
1237499197183,12cyclictest0-21swapper/1300:38:125
1238999196191,3cyclictest0-21swapper/2600:04:2519
1238999196191,3cyclictest0-21swapper/2600:04:2519
1238999196190,4cyclictest0-21swapper/2620:51:0019
1238999196190,4cyclictest0-21swapper/2620:51:0019
1238999196180,11cyclictest0-21swapper/2620:00:1719
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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