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2026-03-02 - 03:27
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Mar 02, 2026 01:02:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2421899225173,40cyclictest37265-21CPU5
2421899225173,40cyclictest37265-21CPU5
2421599216211,3cyclictest0-21swapper/1023:45:002
2421599216211,3cyclictest0-21swapper/1023:45:002
2423199208179,14cyclictest0-21swapper/2423:12:4017
2423199208179,14cyclictest0-21swapper/2423:12:3917
2423199208179,14cyclictest0-21swapper/2423:12:3917
2424099206201,4cyclictest0-21swapper/3120:01:5425
2424099206201,4cyclictest0-21swapper/3120:01:5425
2423899203194,7cyclictest0-21swapper/2923:18:1422
2423899203194,7cyclictest0-21swapper/2923:18:1322
2422799203197,4cyclictest0-21swapper/2121:25:3914
2422799203197,4cyclictest0-21swapper/2121:25:3914
2422799203197,4cyclictest0-21swapper/2121:25:3814
2422499203197,3cyclictest0-21swapper/1823:45:0210
2422499203197,3cyclictest0-21swapper/1823:45:0110
2422899201193,6cyclictest0-21swapper/2219:35:0615
2422899201193,6cyclictest0-21swapper/2219:35:0515
2421899201198,2cyclictest0-21swapper/1321:22:415
2421899201198,2cyclictest0-21swapper/1321:22:415
2424099200192,6cyclictest0-21swapper/3119:59:5225
2424099200192,6cyclictest0-21swapper/3119:59:5225
2422799199195,2cyclictest755-21systemd-journal21:15:2014
2422799199195,2cyclictest755-21systemd-journal21:15:1914
2422799199193,4cyclictest0-21swapper/2119:40:3614
2422799199193,4cyclictest0-21swapper/2119:40:3514
2423699198190,6cyclictest1367-21dbus-daemon23:49:5320
2423699198190,6cyclictest1367-21dbus-daemon23:49:5320
2423699198190,6cyclictest1367-21dbus-daemon23:49:5320
2422799198192,4cyclictest0-21swapper/2100:23:0414
2422799198192,4cyclictest0-21swapper/2100:23:0414
2422799198189,7cyclictest0-21swapper/2100:18:2014
2422799198189,7cyclictest0-21swapper/2100:18:1914
2423899197189,6cyclictest0-21swapper/2923:40:1122
2423899197189,6cyclictest0-21swapper/2923:40:1122
2422799196179,9cyclictest0-21swapper/2121:20:2814
2422799196179,9cyclictest0-21swapper/2121:20:2814
2423899195143,47cyclictest2447-21CPU22
2423899195143,47cyclictest2447-21CPU22
2423799193189,3cyclictest0-21swapper/2800:20:0121
2423799193189,3cyclictest0-21swapper/2800:20:0121
2423799193158,28cyclictest37353-21CPU21
2423799193158,28cyclictest37353-21CPU21
2420599193181,9cyclictest0-21swapper/219:35:0512
2420599193181,9cyclictest0-21swapper/219:35:0512
2423899192168,16cyclictest0-21swapper/2900:01:1722
2423899192168,16cyclictest0-21swapper/2900:01:1722
2423899192168,16cyclictest0-21swapper/2900:01:1622
2422799192186,5cyclictest0-21swapper/2123:38:2714
2422799192186,5cyclictest0-21swapper/2123:38:2714
2422799192186,5cyclictest0-21swapper/2123:38:2614
2422799192186,4cyclictest0-21swapper/2119:12:0314
2422799192186,4cyclictest0-21swapper/2119:12:0314
2421299192189,2cyclictest0-21swapper/723:33:3737
2421299192189,2cyclictest0-21swapper/723:33:3637
2421299192184,6cyclictest0-21swapper/722:07:4337
2421299192184,6cyclictest0-21swapper/722:07:4337
2421299192184,6cyclictest0-21swapper/722:07:4337
2424099191183,6cyclictest0-21swapper/3120:57:0225
2424099191183,6cyclictest0-21swapper/3120:57:0225
2424099191170,8cyclictest171rcu_preempt22:12:0825
2424099191170,8cyclictest171rcu_preempt22:12:0725
2424099191170,8cyclictest171rcu_preempt22:12:0725
2423799191184,4cyclictest0-21swapper/2822:55:3521
2423799191184,4cyclictest0-21swapper/2822:55:3521
2423799191184,4cyclictest0-21swapper/2822:55:3521
2423899190185,3cyclictest0-21swapper/2922:52:5722
2423899190185,3cyclictest0-21swapper/2922:52:5722
2423899190185,3cyclictest0-21swapper/2922:52:5622
2423799190185,4cyclictest0-21swapper/2820:20:2121
2423799190185,4cyclictest0-21swapper/2820:20:2121
2422799190184,4cyclictest0-21swapper/2119:39:4014
2422799190184,4cyclictest0-21swapper/2119:39:4014
2422799190184,4cyclictest0-21swapper/2119:16:4914
2422799190184,4cyclictest0-21swapper/2119:16:4814
2422799190183,4cyclictest0-21swapper/2121:00:3014
2422799190183,4cyclictest0-21swapper/2121:00:3014
2423799189183,4cyclictest0-21swapper/2822:46:4921
2423799189183,4cyclictest0-21swapper/2822:46:4921
2423799189183,4cyclictest0-21swapper/2822:46:4921
2423799189182,5cyclictest0-21swapper/2800:22:3621
2423799189182,5cyclictest0-21swapper/2800:22:3521
2422199189186,2cyclictest0-21swapper/1623:45:248
2422199189186,2cyclictest0-21swapper/1623:45:238
2422199189186,2cyclictest0-21swapper/1623:45:238
2421099189182,3cyclictest3542-21CPU36
2421099189182,3cyclictest3542-21CPU36
2421099189182,3cyclictest3542-21CPU36
2421099189181,6cyclictest0-21swapper/623:11:2536
2421099189181,6cyclictest0-21swapper/623:11:2536
2421099189181,6cyclictest0-21swapper/623:11:2436
2423799188177,10cyclictest0-21swapper/2823:32:0921
2423799188177,10cyclictest0-21swapper/2823:32:0821
2424099187182,4cyclictest0-21swapper/3120:45:0425
2424099187151,19cyclictest0-21swapper/3123:44:2725
2424099187151,19cyclictest0-21swapper/3123:44:2625
2423899187171,13cyclictest0-21swapper/2900:30:3322
2423899187171,13cyclictest0-21swapper/2900:30:3222
2423799187179,5cyclictest0-21swapper/2819:46:5721
2423799187179,5cyclictest0-21swapper/2819:46:5721
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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