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2026-02-26 - 21:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Feb 26, 2026 13:03:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
774699232222,5cyclictest0-21swapper/1109:10:163
774699232222,5cyclictest0-21swapper/1109:10:163
774699232222,5cyclictest0-21swapper/1109:10:153
774499231224,5cyclictest0-21swapper/907:25:0639
774499231224,5cyclictest0-21swapper/907:25:0539
774699230223,5cyclictest0-21swapper/1109:21:563
774699230223,5cyclictest0-21swapper/1109:21:553
774699226212,8cyclictest0-21swapper/1110:46:453
774699226212,8cyclictest0-21swapper/1110:46:453
774699224218,3cyclictest27317-21systemd-cgroups09:18:133
774699224218,3cyclictest27317-21systemd-cgroups09:18:123
774699223212,8cyclictest3544-21CPU3
774699223212,8cyclictest3544-21CPU3
774699223212,8cyclictest3544-21CPU3
774699221213,3cyclictest3547-21CPU3
774699221213,3cyclictest3547-21CPU3
774699221211,6cyclictest0-21swapper/1110:50:413
774699221211,6cyclictest0-21swapper/1110:50:413
774699221211,6cyclictest0-21swapper/1110:50:403
777099220211,5cyclictest2454-21CPU26
777099220211,5cyclictest2454-21CPU26
776099219205,6cyclictest0-21swapper/2309:27:0316
776099219205,6cyclictest0-21swapper/2309:27:0316
776099219205,6cyclictest0-21swapper/2309:27:0216
776099218211,3cyclictest3544-21CPU16
776099218211,3cyclictest3544-21CPU16
776099218211,3cyclictest3544-21CPU16
774699217205,10cyclictest0-21swapper/1112:35:203
774699217205,10cyclictest0-21swapper/1112:35:203
774699217205,10cyclictest0-21swapper/1112:35:203
774699216209,3cyclictest3548-21CPU3
774699216209,3cyclictest3548-21CPU3
774699216209,3cyclictest3548-21CPU3
774699216209,3cyclictest3548-21CPU3
776099215207,5cyclictest1367-21dbus-daemon11:17:2716
776099215207,5cyclictest1367-21dbus-daemon11:17:2616
775099215208,5cyclictest0-21swapper/1407:18:136
775099215208,5cyclictest0-21swapper/1407:18:136
773699215211,2cyclictest0-21swapper/211:45:2112
773699215211,2cyclictest0-21swapper/211:45:2112
773699215211,2cyclictest0-21swapper/211:45:2012
774699213204,6cyclictest0-21swapper/1109:30:323
774699213204,6cyclictest0-21swapper/1109:30:313
774699213204,6cyclictest0-21swapper/1109:30:313
776099212205,5cyclictest0-21swapper/2311:34:5416
776099212205,5cyclictest0-21swapper/2311:34:5416
776099212205,5cyclictest0-21swapper/2311:34:5316
774699212206,5cyclictest0-21swapper/1110:30:013
774699212206,5cyclictest0-21swapper/1110:30:003
774699212204,6cyclictest0-21swapper/1110:32:293
774699212204,6cyclictest0-21swapper/1110:32:283
774699212204,6cyclictest0-21swapper/1110:32:283
77659921190,118cyclictest0-21swapper/2809:15:1421
77659921190,118cyclictest0-21swapper/2809:15:1421
774499211205,5cyclictest0-21swapper/907:24:4739
774499211205,5cyclictest0-21swapper/907:24:4739
776099210202,5cyclictest0-21swapper/2311:38:2216
776099210202,5cyclictest0-21swapper/2311:38:2116
776099210184,12cyclictest3543-21CPU16
776099210184,12cyclictest3543-21CPU16
776099210184,12cyclictest3543-21CPU16
776099210184,12cyclictest3543-21CPU16
774699210205,3cyclictest0-21swapper/1109:55:143
774699210205,3cyclictest0-21swapper/1109:55:143
774699210203,5cyclictest0-21swapper/1110:55:113
774699210203,5cyclictest0-21swapper/1110:55:113
774699210203,5cyclictest0-21swapper/1110:55:103
776099209203,4cyclictest0-21swapper/2310:10:1216
776099209203,4cyclictest0-21swapper/2310:10:1216
776099209203,4cyclictest0-21swapper/2310:10:1216
776099209203,4cyclictest0-21swapper/2310:10:1116
774699209203,4cyclictest0-21swapper/1109:50:143
774699209203,4cyclictest0-21swapper/1109:50:143
774699209202,5cyclictest0-21swapper/1112:18:323
774699209202,5cyclictest0-21swapper/1112:18:313
774699209188,16cyclictest19081-2110-uname11:07:333
774699209188,16cyclictest19081-2110-uname11:07:333
774699209188,16cyclictest19081-2110-uname11:07:323
774699207202,2cyclictest3548-21CPU3
774699207202,2cyclictest3548-21CPU3
774699207201,4cyclictest0-21swapper/1112:09:133
774699207201,4cyclictest0-21swapper/1112:09:123
774699207200,5cyclictest0-21swapper/1107:22:063
774699207200,5cyclictest0-21swapper/1107:22:053
774699206194,8cyclictest37356-21CPU3
774699206194,8cyclictest37356-21CPU3
774699206194,8cyclictest37356-21CPU3
776699205201,2cyclictest0-21swapper/2911:45:1822
776699205201,2cyclictest0-21swapper/2911:45:1722
776699205201,2cyclictest0-21swapper/2911:45:1722
774699205197,6cyclictest0-21swapper/1110:05:233
774699205197,6cyclictest0-21swapper/1110:05:233
774699205197,6cyclictest0-21swapper/1110:05:233
774699205197,4cyclictest2462-21CPU3
774699205197,4cyclictest2462-21CPU3
776099204199,4cyclictest0-21swapper/2311:50:1816
776099204199,4cyclictest0-21swapper/2311:50:1816
774699204196,5cyclictest0-21swapper/1110:00:493
774699204196,5cyclictest0-21swapper/1110:00:483
776099203194,6cyclictest0-21swapper/2311:29:3016
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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