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2026-07-28 - 02:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Jul 28, 2026 01:01:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31371992191,209cyclictest0-21swapper/3121:30:2125
31371992191,209cyclictest0-21swapper/3121:30:2125
3136799219215,2cyclictest0-21swapper/2821:25:1621
3136799219215,2cyclictest0-21swapper/2821:25:1621
3136999216209,3cyclictest4408-21CPU22
3136999216209,3cyclictest4408-21CPU22
3136999216209,3cyclictest4408-21CPU22
3136999216205,8cyclictest12951-21sshd00:14:1622
3136999216205,8cyclictest12951-21sshd00:14:1622
3133999214204,5cyclictest0-21swapper/321:40:4723
3133999214204,5cyclictest0-21swapper/321:40:4723
3133999214204,5cyclictest0-21swapper/321:40:4723
3134799212193,10cyclictest0-21swapper/1022:30:202
3134799212193,10cyclictest0-21swapper/1022:30:202
3136999211203,3cyclictest37270-21CPU22
3136999211203,3cyclictest37270-21CPU22
3136399211173,15cyclictest0-21swapper/2421:20:3617
3136399211173,15cyclictest0-21swapper/2421:20:3617
3136999207196,9cyclictest5732-2110-uname00:17:2022
3136999207196,9cyclictest5732-2110-uname00:17:2022
3134499204201,2cyclictest0-21swapper/822:21:1238
3134499204201,2cyclictest0-21swapper/822:21:1138
3136599202190,11cyclictest0-21swapper/2622:04:4319
3136599202190,11cyclictest0-21swapper/2622:04:4319
3136599201190,9cyclictest0-21swapper/2621:32:1219
3136599201190,9cyclictest0-21swapper/2621:32:1119
3136299201192,5cyclictest2456-21CPU16
3136299201192,5cyclictest2456-21CPU16
3133999200184,7cyclictest0-21swapper/323:37:0123
3133999200184,7cyclictest0-21swapper/323:37:0123
3137399199186,10cyclictest0-21swapper/3322:18:3027
3137399199186,10cyclictest0-21swapper/3322:18:3027
3136999199192,5cyclictest38521-21sshd21:46:2322
3136999199192,5cyclictest38521-21sshd21:46:2222
3136999199192,4cyclictest0-21swapper/2921:38:0822
3136999199192,4cyclictest0-21swapper/2921:38:0822
3136999199183,8cyclictest15416-21systemd-cgroups22:00:2122
3136999199183,8cyclictest15416-21systemd-cgroups22:00:2122
3136999197189,6cyclictest0-21swapper/2923:00:3122
3136999197188,5cyclictest0-21swapper/2900:03:3022
3136999197188,5cyclictest0-21swapper/2900:03:2922
3136999195187,5cyclictest34528-21cat00:20:1722
3136999195187,5cyclictest34528-21cat00:20:1622
3136399195154,16cyclictest0-21swapper/2400:16:3117
3136399195154,16cyclictest0-21swapper/2400:16:3017
3137599194184,8cyclictest0-21swapper/3421:46:3128
3137599194184,8cyclictest0-21swapper/3421:46:3128
3136999194187,5cyclictest0-21swapper/2921:44:1622
3136999194187,5cyclictest0-21swapper/2921:44:1622
3136999194187,5cyclictest0-21swapper/2921:44:1622
3136999194185,5cyclictest3544-21CPU22
3136999194185,5cyclictest3544-21CPU22
3136999194177,14cyclictest0-21swapper/2921:30:2822
3136999194177,14cyclictest0-21swapper/2921:30:2822
3136999193187,5cyclictest0-21swapper/2922:27:3422
3136999193187,5cyclictest0-21swapper/2922:27:3422
3136999193187,5cyclictest0-21swapper/2922:27:3422
3136999193186,5cyclictest28991-21sshd00:07:3922
3136999193186,5cyclictest28991-21sshd00:07:3922
3136999193186,3cyclictest37356-21CPU22
3136999193186,3cyclictest37356-21CPU22
3136999192184,5cyclictest37257-21qemu-system-x8622:53:4222
3136999192184,5cyclictest37257-21qemu-system-x8622:53:4222
3136999192184,5cyclictest37257-21qemu-system-x8622:53:4222
3136999192184,5cyclictest2507-21sshd00:25:1222
3136999192184,5cyclictest2507-21sshd00:25:1222
3136999192184,4cyclictest0-21swapper/2900:30:2122
3136999192184,4cyclictest0-21swapper/2900:30:2122
3136999192182,5cyclictest37352-21CPU22
3136999192182,5cyclictest37352-21CPU22
3137599191180,9cyclictest0-21swapper/3422:52:2828
3137599191180,9cyclictest0-21swapper/3422:52:2828
3137599191180,9cyclictest0-21swapper/3422:52:2828
3136999191185,4cyclictest0-21swapper/2923:38:1122
3136999191185,4cyclictest0-21swapper/2923:38:1022
3136999191183,6cyclictest0-21swapper/2923:53:4322
3136999191183,6cyclictest0-21swapper/2923:53:4322
3136999191181,7cyclictest3546-21CPU22
3136999191181,7cyclictest3546-21CPU22
3136999191179,7cyclictest0-21swapper/2923:20:4922
3136999191179,7cyclictest0-21swapper/2923:20:4922
3136199191183,4cyclictest2447-21CPU15
3136199191183,4cyclictest2447-21CPU15
3136999190185,4cyclictest0-21swapper/2922:41:1522
3136999190185,4cyclictest0-21swapper/2922:41:1522
3136599190186,2cyclictest0-21swapper/2621:21:5819
3136599190186,2cyclictest0-21swapper/2621:21:5819
3136599190179,9cyclictest0-21swapper/2621:01:0219
3136599190179,9cyclictest0-21swapper/2621:01:0219
3138299189180,7cyclictest0-21swapper/3922:12:1233
3138299189180,7cyclictest0-21swapper/3922:12:1233
3136999189185,2cyclictest17484-21nfsd23:08:2522
3136999189185,2cyclictest17484-21nfsd23:08:2422
3136999189184,4cyclictest0-21swapper/2920:15:1922
3136999189184,4cyclictest0-21swapper/2920:15:1822
3136599189162,23cyclictest0-21swapper/2623:54:4319
3136599189162,23cyclictest0-21swapper/2623:54:4319
3137199188142,42cyclictest3545-21CPU25
3137199188142,42cyclictest3545-21CPU25
31371991881,184cyclictest0-21swapper/3100:30:1925
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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