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2026-01-22 - 02:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Thu Jan 22, 2026 01:00:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
456499242237,3cyclictest0-21swapper/3523:00:1829
456499242237,3cyclictest0-21swapper/3523:00:1829
456499242237,3cyclictest0-21swapper/3523:00:1829
455499235228,3cyclictest37263-21CPU20
455499235228,3cyclictest37263-21CPU20
455499235228,3cyclictest37263-21CPU20
456899226221,3cyclictest0-21swapper/3922:30:2033
456899226221,3cyclictest0-21swapper/3922:30:2033
456899226221,3cyclictest0-21swapper/3922:30:2033
454799225212,8cyclictest3544-21CPU14
454799225212,8cyclictest3544-21CPU14
456899223220,2cyclictest0-21swapper/3900:25:1833
456899223220,2cyclictest0-21swapper/3900:25:1833
456199221177,34cyclictest2466-21CPU26
456199221177,34cyclictest2466-21CPU26
456199221177,34cyclictest2466-21CPU26
456499220217,2cyclictest0-21swapper/3522:55:1129
456499220217,2cyclictest0-21swapper/3522:55:1129
456499220217,2cyclictest0-21swapper/3522:55:1129
454799219206,5cyclictest0-21swapper/2121:25:1814
454799219206,5cyclictest0-21swapper/2121:25:1814
454599218214,2cyclictest0-21swapper/1923:00:0011
454599218214,2cyclictest0-21swapper/1923:00:0011
454599218214,2cyclictest0-21swapper/1923:00:0011
452099218176,18cyclictest0-21swapper/023:00:540
452099218176,18cyclictest0-21swapper/023:00:540
452099218176,18cyclictest0-21swapper/023:00:540
454799216194,15cyclictest4398-21qemu-system-x8621:40:0114
454799216194,15cyclictest4398-21qemu-system-x8621:40:0114
454799214203,8cyclictest0-21swapper/2121:40:4314
454799214203,8cyclictest0-21swapper/2121:40:4314
454799212193,15cyclictest3545-21CPU14
454799212193,15cyclictest3545-21CPU14
454199211175,31cyclictest0-21swapper/1623:26:018
454199211175,31cyclictest0-21swapper/1623:26:018
455299210185,17cyclictest0-21swapper/2600:22:3519
455299210185,17cyclictest0-21swapper/2600:22:3519
455299209193,14cyclictest0-21swapper/2620:45:0019
452799209193,6cyclictest0-21swapper/500:28:2135
452799209193,6cyclictest0-21swapper/500:28:2135
454799207198,6cyclictest0-21swapper/2121:31:5614
454799207198,6cyclictest0-21swapper/2121:31:5614
454799206197,7cyclictest0-21swapper/2122:18:3614
454799206197,7cyclictest0-21swapper/2122:18:3614
454799206197,7cyclictest0-21swapper/2122:18:3614
452099205139,33cyclictest2454-21CPU0
452099205139,33cyclictest2454-21CPU0
452099205139,33cyclictest2454-21CPU0
454799204188,10cyclictest0-21swapper/2121:46:0614
454799204188,10cyclictest0-21swapper/2121:46:0614
454599203198,3cyclictest0-21swapper/1921:51:5811
454599203198,3cyclictest0-21swapper/1921:51:5811
454899202187,12cyclictest0-21swapper/2222:50:3815
454899202187,12cyclictest0-21swapper/2222:50:3815
454899202187,12cyclictest0-21swapper/2222:50:3815
454799202195,5cyclictest0-21swapper/2122:01:1214
454799202195,5cyclictest0-21swapper/2122:01:1214
454799202192,8cyclictest0-21swapper/2121:12:4414
454799202192,8cyclictest0-21swapper/2121:12:4414
454799201193,6cyclictest0-21swapper/2121:59:1914
454799201193,6cyclictest0-21swapper/2121:59:1914
454099201195,3cyclictest0-21swapper/1523:00:007
454099201195,3cyclictest0-21swapper/1523:00:007
454099201195,3cyclictest0-21swapper/1523:00:007
452099201197,2cyclictest0-21swapper/000:00:430
452099201197,2cyclictest0-21swapper/000:00:430
452099201197,2cyclictest0-21swapper/000:00:430
455099200185,12cyclictest0-21swapper/2419:22:4517
455099200185,12cyclictest0-21swapper/2419:22:4517
452499200160,36cyclictest3548-21CPU12
452499200160,36cyclictest3548-21CPU12
452099200179,5cyclictest0-21swapper/023:15:500
452099200179,5cyclictest0-21swapper/023:15:490
454799198191,4cyclictest0-21swapper/2121:05:1514
454799198191,4cyclictest0-21swapper/2121:05:1514
454799198190,6cyclictest0-21swapper/2121:16:1914
454799198190,6cyclictest0-21swapper/2121:16:1914
454099198195,2cyclictest0-21swapper/1519:10:167
454099198195,2cyclictest0-21swapper/1519:10:167
453399198194,2cyclictest0-21swapper/922:30:1839
453399198194,2cyclictest0-21swapper/922:30:1839
453399198194,2cyclictest0-21swapper/922:30:1839
452599197174,19cyclictest0-21swapper/323:33:1123
452599197174,19cyclictest0-21swapper/323:33:1123
455899196190,3cyclictest2462-21CPU24
455899196190,3cyclictest2462-21CPU24
455899196190,3cyclictest2462-21CPU24
454899196180,12cyclictest0-21swapper/2219:18:0815
454899196180,12cyclictest0-21swapper/2219:18:0815
453599195191,2cyclictest0-21swapper/1022:58:122
453599195191,2cyclictest0-21swapper/1022:58:122
453599195191,2cyclictest0-21swapper/1022:58:122
452499195187,6cyclictest0-21swapper/222:39:0212
452499195187,6cyclictest0-21swapper/222:39:0212
452099195166,20cyclictest0-21swapper/022:46:000
452099195166,20cyclictest0-21swapper/022:46:000
455299193168,21cyclictest37356-21CPU19
455299193168,21cyclictest37356-21CPU19
455299193168,21cyclictest37356-21CPU19
452099193180,6cyclictest0-21swapper/019:19:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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