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2026-02-23 - 08:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Feb 23, 2026 01:03:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
532999217211,4cyclictest0-21swapper/1020:00:002
532999217211,4cyclictest0-21swapper/1020:00:002
535099205198,5cyclictest0-21swapper/2720:30:1920
535099199195,2cyclictest0-21swapper/2722:28:1220
535099199195,2cyclictest0-21swapper/2722:28:1220
532999194187,4cyclictest2466-21CPU2
532999194187,4cyclictest2466-21CPU2
5328991931,3cyclictest0-21swapper/919:36:4939
535099192182,8cyclictest0-21swapper/2722:11:2820
535099192182,8cyclictest0-21swapper/2722:11:2820
535099192126,29cyclictest0-21swapper/2723:21:1020
535099192126,29cyclictest0-21swapper/2723:21:1020
532099192183,6cyclictest0-21swapper/421:10:0734
532099192183,6cyclictest0-21swapper/421:10:0734
535099191181,8cyclictest0-21swapper/2722:43:1620
535099191181,8cyclictest0-21swapper/2722:43:1620
535099190182,5cyclictest0-21swapper/2722:30:1420
535099190182,5cyclictest0-21swapper/2722:30:1420
535099190182,5cyclictest0-21swapper/2722:30:1420
533999188181,6cyclictest0-21swapper/1923:55:0011
533999188181,6cyclictest0-21swapper/1923:55:0011
532099187166,7cyclictest0-21swapper/420:30:3434
535099186180,4cyclictest0-21swapper/2722:39:4220
535099186180,4cyclictest0-21swapper/2722:39:4220
535099186170,12cyclictest0-21swapper/2722:17:4820
535099186170,12cyclictest0-21swapper/2722:17:4820
535099186170,12cyclictest0-21swapper/2722:17:4820
532099186176,4cyclictest2456-21CPU34
532099186157,16cyclictest0-21swapper/400:28:4434
532099186157,16cyclictest0-21swapper/400:28:4434
532099186157,16cyclictest0-21swapper/400:28:4434
533999185173,9cyclictest0-21swapper/1900:05:0411
533999185173,9cyclictest0-21swapper/1900:05:0411
532999185176,6cyclictest24414-21fschecks_time19:50:192
532999185176,6cyclictest24414-21fschecks_time19:50:192
532999185174,7cyclictest0-21swapper/1020:08:472
532999185174,7cyclictest0-21swapper/1020:08:472
535099184173,4cyclictest4407-21CPU20
535099184173,4cyclictest4407-21CPU20
535099184169,9cyclictest0-21swapper/2722:22:1320
535099184169,9cyclictest0-21swapper/2722:22:1320
532099184175,7cyclictest0-21swapper/421:09:5234
532099184175,7cyclictest0-21swapper/421:09:5234
532099184175,7cyclictest0-21swapper/421:09:5234
532099184170,12cyclictest0-21swapper/419:21:2634
532099184170,12cyclictest0-21swapper/419:21:2634
532099183166,15cyclictest0-21swapper/422:11:2334
532099183166,15cyclictest0-21swapper/422:11:2334
532999182176,4cyclictest0-21swapper/1019:44:102
532999182176,4cyclictest0-21swapper/1019:44:102
531999182130,42cyclictest0-21swapper/321:34:4523
531999182130,42cyclictest0-21swapper/321:34:4523
533999181175,4cyclictest0-21swapper/1900:16:1011
533999181175,4cyclictest0-21swapper/1900:16:1011
533999181175,4cyclictest0-21swapper/1900:16:1011
533999181173,6cyclictest1442-21gdbus23:56:4511
533999181173,6cyclictest1442-21gdbus23:56:4511
533999181173,6cyclictest1442-21gdbus23:56:4511
533999181173,6cyclictest1442-21gdbus23:56:4511
533999181168,11cyclictest0-21swapper/1923:01:4611
533999181168,11cyclictest0-21swapper/1923:01:4611
533999181168,11cyclictest0-21swapper/1923:01:4611
532999181173,4cyclictest0-21swapper/1019:48:582
532999181173,4cyclictest0-21swapper/1019:48:582
532099181172,7cyclictest0-21swapper/419:26:2534
532099181172,7cyclictest0-21swapper/419:26:2534
535099180175,4cyclictest0-21swapper/2720:28:1320
535099180170,8cyclictest0-21swapper/2720:52:0520
535099180170,8cyclictest0-21swapper/2720:52:0520
533999180172,3cyclictest3547-21CPU11
533999180172,3cyclictest3547-21CPU11
533999180172,3cyclictest3547-21CPU11
532099180170,7cyclictest0-21swapper/419:30:3234
532099180170,7cyclictest0-21swapper/419:30:3234
532099180168,11cyclictest0-21swapper/421:37:3134
532099180168,11cyclictest0-21swapper/421:37:3134
532099180168,11cyclictest0-21swapper/421:37:3134
532099180165,9cyclictest0-21swapper/419:17:0134
532099180165,9cyclictest0-21swapper/419:17:0134
532099180114,56cyclictest37268-21CPU34
532099180114,56cyclictest37268-21CPU34
533999179167,10cyclictest0-21swapper/1923:17:3611
533999179167,10cyclictest0-21swapper/1923:17:3611
533999179167,10cyclictest0-21swapper/1923:17:3611
53319917820,93cyclictest0-21swapper/1223:05:194
53319917820,93cyclictest0-21swapper/1223:05:194
53319917820,93cyclictest0-21swapper/1223:05:194
535799177170,5cyclictest0-21swapper/3321:55:2627
535799177170,5cyclictest0-21swapper/3321:55:2627
535799177170,5cyclictest0-21swapper/3321:55:2627
535099177159,2cyclictest0-21swapper/2723:32:1920
535099177159,2cyclictest0-21swapper/2723:32:1920
533999177170,5cyclictest0-21swapper/1922:54:2511
533999177170,5cyclictest0-21swapper/1922:54:2511
533999177170,5cyclictest0-21swapper/1922:54:2511
535099176170,5cyclictest0-21swapper/2720:46:4920
535099176170,5cyclictest0-21swapper/2720:46:4920
5328991768,150cyclictest0-21swapper/923:15:1939
5328991768,150cyclictest0-21swapper/923:15:1939
5328991768,150cyclictest0-21swapper/923:15:1939
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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