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2026-02-02 - 06:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Feb 02, 2026 01:00:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2149399230224,3cyclictest0-21swapper/2622:30:1119
2149399230224,3cyclictest0-21swapper/2622:30:1119
2150599229214,13cyclictest0-21swapper/3721:26:2031
2150599229214,13cyclictest0-21swapper/3721:26:2031
2150599229214,13cyclictest0-21swapper/3721:26:2031
2149399226216,8cyclictest25005-21gdbus22:20:0119
2149399226216,8cyclictest25005-21gdbus22:20:0119
2149399226216,8cyclictest25005-21gdbus22:20:0119
2149399223209,8cyclictest3610-21CPU19
2149399223209,8cyclictest3610-21CPU19
2149399223209,8cyclictest3610-21CPU19
2149399222215,5cyclictest0-21swapper/2622:29:0419
2149399222215,5cyclictest0-21swapper/2622:29:0419
2149399222215,5cyclictest0-21swapper/2622:29:0419
2149399220209,9cyclictest0-21swapper/2619:40:1519
2149399220209,9cyclictest0-21swapper/2619:40:1519
2149399218213,4cyclictest0-21swapper/2622:36:0919
2149399218213,4cyclictest0-21swapper/2622:36:0919
2149399216210,4cyclictest0-21swapper/2619:19:1919
2149399216210,4cyclictest0-21swapper/2619:19:1919
2149399216208,6cyclictest0-21swapper/2600:25:1519
2149399216208,6cyclictest0-21swapper/2600:25:1519
2149399215207,5cyclictest0-21swapper/2621:27:1519
2149399215207,5cyclictest0-21swapper/2621:27:1519
2149399215207,5cyclictest0-21swapper/2621:27:1519
2149399212205,5cyclictest0-21swapper/2621:15:3319
2149399212205,5cyclictest0-21swapper/2621:15:3319
2149399211205,4cyclictest5361-21systemd23:25:0719
2149399211205,4cyclictest5361-21systemd23:25:0719
2149399209202,4cyclictest2454-21CPU19
2149399209202,4cyclictest2454-21CPU19
2149399209201,6cyclictest0-21swapper/2622:23:5519
2149399209201,6cyclictest0-21swapper/2622:23:5519
2149399209201,6cyclictest0-21swapper/2622:23:5519
2149399209201,6cyclictest0-21swapper/2600:30:5819
2149399209201,6cyclictest0-21swapper/2600:30:5819
2149399209201,6cyclictest0-21swapper/2600:05:1319
2149399209201,6cyclictest0-21swapper/2600:05:1319
2149399209201,6cyclictest0-21swapper/2600:05:1319
2149399209191,14cyclictest37346-21qemu-system-x8623:45:1419
2149399209191,14cyclictest37346-21qemu-system-x8623:45:1319
2150599208101,100cyclictest4407-21CPU31
2150599208101,100cyclictest4407-21CPU31
2149399208202,4cyclictest0-21swapper/2600:15:1919
2149399208202,4cyclictest0-21swapper/2600:15:1819
2149399207201,5cyclictest0-21swapper/2623:29:2819
2149399207201,5cyclictest0-21swapper/2623:29:2819
2149399207201,5cyclictest0-21swapper/2623:29:2819
2149399207199,6cyclictest17482-21nfsd22:40:1219
2149399207199,6cyclictest17482-21nfsd22:40:1219
2149399206200,5cyclictest0-21swapper/2622:58:0119
2149399206200,5cyclictest0-21swapper/2622:58:0119
2149399206199,5cyclictest0-21swapper/2622:45:1319
2149399206199,5cyclictest0-21swapper/2622:45:1319
2149399206196,8cyclictest0-21swapper/2623:40:1019
2149399206196,8cyclictest0-21swapper/2623:40:1019
2149399206196,8cyclictest0-21swapper/2623:40:1019
2146199206198,5cyclictest0-21swapper/300:10:0723
2146199206198,5cyclictest0-21swapper/300:10:0723
2149399205200,3cyclictest0-21swapper/2623:33:5719
2149399205200,3cyclictest0-21swapper/2623:33:5719
2149399205199,4cyclictest0-21swapper/2622:08:5219
2149399205199,4cyclictest0-21swapper/2622:08:5219
2149399205198,5cyclictest7890-21systemd-cgroups21:36:2319
2149399205198,5cyclictest7890-21systemd-cgroups21:36:2319
2149399205198,5cyclictest7890-21systemd-cgroups21:36:2319
2149399204187,13cyclictest0-21swapper/2621:23:3319
2149399204187,13cyclictest0-21swapper/2621:23:3319
2149399204187,13cyclictest0-21swapper/2621:23:3319
2149399204175,24cyclictest0-21swapper/2621:33:5619
2149399204175,24cyclictest0-21swapper/2621:33:5619
2149399204175,24cyclictest0-21swapper/2621:33:5619
2149399203198,3cyclictest0-21swapper/2619:20:1419
2149399203198,3cyclictest0-21swapper/2619:20:1419
2149399203190,10cyclictest0-21swapper/2621:10:1519
2149399203190,10cyclictest0-21swapper/2621:10:1519
2149399203190,10cyclictest0-21swapper/2621:10:1419
2149399202197,4cyclictest0-21swapper/2619:30:1119
2149399202197,4cyclictest0-21swapper/2619:30:1119
2149399202195,5cyclictest0-21swapper/2622:04:2819
2149399202195,5cyclictest0-21swapper/2622:04:2819
2149399202194,5cyclictest0-21swapper/2619:10:3719
2149399202194,5cyclictest0-21swapper/2619:10:3719
2149399201195,4cyclictest0-21swapper/2621:47:1619
2149399201195,4cyclictest0-21swapper/2621:47:1619
2149399200191,6cyclictest0-21swapper/2600:11:2019
2149399200191,6cyclictest0-21swapper/2600:11:2019
2146199200192,5cyclictest0-21swapper/319:35:2923
2146199200192,5cyclictest0-21swapper/319:35:2923
2149399199193,4cyclictest0-21swapper/2600:38:2719
2149399199193,4cyclictest0-21swapper/2600:38:2719
2149399199191,6cyclictest0-21swapper/2622:10:1619
2149399199191,6cyclictest0-21swapper/2622:10:1619
2149399199191,5cyclictest0-21swapper/2622:50:5219
2149399199191,5cyclictest0-21swapper/2622:50:5219
2149399199189,8cyclictest0-21swapper/2621:51:4119
2149399199189,8cyclictest0-21swapper/2621:51:4119
2149399198193,3cyclictest0-21swapper/2619:45:2719
2149399198193,3cyclictest0-21swapper/2619:45:2719
2149399198192,4cyclictest0-21swapper/2620:51:1419
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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