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2026-02-03 - 22:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Feb 03, 2026 13:04:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2149499221210,9cyclictest0-21swapper/3409:13:5628
2149499221210,9cyclictest0-21swapper/3409:13:5528
2148499212198,7cyclictest0-21swapper/2509:50:4618
2148499212198,7cyclictest0-21swapper/2509:50:4618
2148499212198,7cyclictest0-21swapper/2509:50:4518
2149799211199,10cyclictest0-21swapper/3610:45:3430
2149799211199,10cyclictest0-21swapper/3610:45:3430
2149799211199,10cyclictest0-21swapper/3610:45:3330
2145999209181,26cyclictest0-21swapper/312:09:3023
2145999209181,26cyclictest0-21swapper/312:09:2923
2148499208201,5cyclictest0-21swapper/2509:58:4118
2148499208201,5cyclictest0-21swapper/2509:58:4018
2148499208201,5cyclictest0-21swapper/2509:58:4018
2148499208199,3cyclictest0-21swapper/2509:15:4118
2148499208199,3cyclictest0-21swapper/2509:15:4018
2147299204192,10cyclictest0-21swapper/1512:08:077
2147299204192,10cyclictest0-21swapper/1512:08:067
2149899202194,6cyclictest0-21swapper/3708:45:2231
2149899202194,6cyclictest0-21swapper/3708:45:2231
2148599201175,21cyclictest0-21swapper/2610:57:1119
2148599201175,21cyclictest0-21swapper/2610:57:1119
2148599201175,21cyclictest0-21swapper/2610:57:1119
2148499199188,7cyclictest3544-21CPU18
2148499199188,7cyclictest3544-21CPU18
2148499197188,7cyclictest17481-21nfsd11:46:4418
2148499197188,7cyclictest17481-21nfsd11:46:4318
2148499197188,7cyclictest17481-21nfsd11:46:4318
2148699195185,8cyclictest0-21swapper/2709:14:4120
2148699195185,8cyclictest0-21swapper/2709:14:4120
2148499195189,5cyclictest0-21swapper/2510:01:4418
2148499195189,5cyclictest0-21swapper/2510:01:4418
2148499194182,10cyclictest0-21swapper/2512:21:2618
2148499194182,10cyclictest0-21swapper/2512:21:2618
2148499194182,10cyclictest0-21swapper/2512:21:2518
2148499194182,10cyclictest0-21swapper/2512:21:2518
2149899193187,5cyclictest0-21swapper/3708:00:3531
2149899193187,5cyclictest0-21swapper/3708:00:3531
2148499192188,2cyclictest1367-21dbus-daemon10:11:1418
2148499192188,2cyclictest1367-21dbus-daemon10:11:1418
2148499192183,5cyclictest0-21swapper/2512:39:5018
2148499192183,5cyclictest0-21swapper/2512:39:5018
2148499192183,5cyclictest0-21swapper/2512:39:4918
2148499192183,5cyclictest0-21swapper/2512:39:4918
2148499192182,7cyclictest0-21swapper/2507:19:0518
2148499192182,7cyclictest0-21swapper/2507:19:0518
2148099192187,3cyclictest0-21swapper/2109:00:2014
2148099192187,3cyclictest0-21swapper/2109:00:2014
2148499191184,5cyclictest0-21swapper/2510:32:2518
2148499191184,5cyclictest0-21swapper/2510:32:2518
2148499191184,5cyclictest0-21swapper/2510:32:2418
2148499191183,6cyclictest0-21swapper/2510:28:0118
2148499191183,6cyclictest0-21swapper/2510:28:0118
2148499191183,6cyclictest0-21swapper/2510:28:0018
2148499191177,5cyclictest0-21swapper/2511:29:0518
2148499191177,5cyclictest0-21swapper/2511:29:0418
2148499191177,5cyclictest0-21swapper/2511:29:0418
2148499191176,9cyclictest2456-21CPU18
2148499191176,9cyclictest2456-21CPU18
2148499191176,9cyclictest2456-21CPU18
2145899191185,4cyclictest0-21swapper/211:48:5312
2145899191185,4cyclictest0-21swapper/211:48:5312
2145899191185,4cyclictest0-21swapper/211:48:5212
2148499190182,6cyclictest0-21swapper/2512:30:1818
2148499190182,6cyclictest0-21swapper/2512:30:1718
2148499190172,11cyclictest0-21swapper/2511:30:1318
2148499190172,11cyclictest0-21swapper/2511:30:1218
2148499190172,11cyclictest0-21swapper/2511:30:1218
2147699190142,34cyclictest3548-21CPU9
2147699190142,34cyclictest3548-21CPU9
2147699190142,34cyclictest3548-21CPU9
2149899189184,4cyclictest0-21swapper/3708:25:3231
2149899189184,4cyclictest0-21swapper/3708:25:3231
2148699189127,51cyclictest2461-21CPU20
2148699189127,51cyclictest2461-21CPU20
2148499189177,8cyclictest0-21swapper/2512:17:0018
2148499189177,8cyclictest0-21swapper/2512:17:0018
2148499189177,8cyclictest0-21swapper/2512:16:5918
2148499189174,6cyclictest755-21systemd-journal09:40:1518
2148499189174,6cyclictest755-21systemd-journal09:40:1518
2148499189174,6cyclictest755-21systemd-journal09:40:1418
2148499189174,10cyclictest0-21swapper/2510:09:2618
2148499189174,10cyclictest0-21swapper/2510:09:2618
2147999189134,10cyclictest0-21swapper/2009:58:1213
2147999189134,10cyclictest0-21swapper/2009:58:1113
2147999189134,10cyclictest0-21swapper/2009:58:1113
2147699189185,2cyclictest0-21swapper/1710:05:199
2147699189185,2cyclictest0-21swapper/1710:05:199
214609918910,121cyclictest0-21swapper/408:55:2934
214609918910,121cyclictest0-21swapper/408:55:2834
2149899188183,4cyclictest0-21swapper/3708:20:4031
2149899188183,4cyclictest0-21swapper/3708:20:4031
2148499188183,4cyclictest0-21swapper/2511:23:5318
2148499188183,4cyclictest0-21swapper/2511:23:5318
2148499188183,4cyclictest0-21swapper/2511:23:5218
2148499188182,4cyclictest0-21swapper/2509:34:1418
2148499188182,4cyclictest0-21swapper/2509:34:1418
2148499188182,4cyclictest0-21swapper/2509:34:1318
2148499188180,3cyclictest3545-21CPU18
2148499188180,3cyclictest3545-21CPU18
2146599188158,23cyclictest3547-21CPU38
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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