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2026-02-25 - 19:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Feb 25, 2026 13:02:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2536599215208,4cyclictest0-21swapper/3311:40:2127
2536599215208,4cyclictest0-21swapper/3311:40:2027
2536599215208,4cyclictest0-21swapper/3311:40:2027
2532699214207,4cyclictest4398-21qemu-system-x8607:25:131
2533499208201,3cyclictest3548-21CPU38
2533499208201,3cyclictest3548-21CPU38
2532699207200,5cyclictest0-21swapper/110:18:241
2532699207200,5cyclictest0-21swapper/110:18:241
2532699207198,5cyclictest3609-21CPU1
2532699207198,5cyclictest3609-21CPU1
2532699207198,5cyclictest3609-21CPU1
2532699207196,8cyclictest0-21swapper/111:38:411
2532699207196,8cyclictest0-21swapper/111:38:411
2532699207196,8cyclictest0-21swapper/111:38:401
2537199206200,4cyclictest0-21swapper/3912:02:2333
2537199206200,4cyclictest0-21swapper/3912:02:2233
2535599206187,16cyclictest0-21swapper/2511:20:2018
2535599206187,16cyclictest0-21swapper/2511:20:2018
2535399206158,44cyclictest0-21swapper/2310:34:2316
2535399206158,44cyclictest0-21swapper/2310:34:2216
2535399206158,44cyclictest0-21swapper/2310:34:2216
2537199205200,4cyclictest0-21swapper/3912:05:1833
2537199205200,4cyclictest0-21swapper/3912:05:1733
2537199205199,4cyclictest0-21swapper/3907:11:0433
2537199205199,4cyclictest0-21swapper/3907:11:0333
2532699205198,4cyclictest1-21systemd09:35:261
2532699205198,4cyclictest1-21systemd09:35:251
2532699205194,8cyclictest0-21swapper/109:11:411
2532699205194,8cyclictest0-21swapper/109:11:411
2537199203197,5cyclictest0-21swapper/3909:44:2533
2537199203197,5cyclictest0-21swapper/3909:44:2533
2537199203197,4cyclictest0-21swapper/3908:37:5833
2537199203197,4cyclictest0-21swapper/3908:37:5833
2532699203197,4cyclictest0-21swapper/110:32:131
2532699203197,4cyclictest0-21swapper/110:32:131
2532699203197,4cyclictest0-21swapper/110:32:131
2536599202195,3cyclictest0-21swapper/3309:41:1527
2536599202195,3cyclictest0-21swapper/3309:41:1527
2532699202193,6cyclictest39185-21systemd12:27:091
2532699202193,6cyclictest39185-21systemd12:27:081
2537199201194,5cyclictest0-21swapper/3907:21:0233
2537199201194,5cyclictest0-21swapper/3907:21:0233
2532699201192,6cyclictest0-21swapper/112:07:461
2532699201192,6cyclictest0-21swapper/112:07:451
2532699200194,4cyclictest0-21swapper/107:50:151
2532699200194,4cyclictest0-21swapper/107:50:151
2532699200190,5cyclictest2454-21CPU1
2532699200190,5cyclictest2454-21CPU1
2537199199193,4cyclictest0-21swapper/3908:52:1633
2537199199193,4cyclictest0-21swapper/3908:52:1633
2533499199195,2cyclictest0-21swapper/808:35:1438
2533499199195,2cyclictest0-21swapper/808:35:1438
2537199198192,4cyclictest0-21swapper/3908:49:5133
2537199198192,4cyclictest0-21swapper/3908:49:5133
2533499198192,5cyclictest0-21swapper/808:55:2138
2533499198192,5cyclictest0-21swapper/808:55:2138
2533499198192,5cyclictest0-21swapper/808:55:2038
2535599197190,5cyclictest37257-21qemu-system-x8610:51:5018
2535599197190,5cyclictest37257-21qemu-system-x8610:51:4918
2535599197190,5cyclictest37257-21qemu-system-x8610:51:4918
2533499197192,3cyclictest12460-21sshd09:22:1538
2533499197192,3cyclictest12460-21sshd09:22:1538
2532699197190,6cyclictest0-21swapper/112:11:481
2532699197190,6cyclictest0-21swapper/112:11:471
2537199196189,5cyclictest0-21swapper/3908:20:1933
2536599196186,8cyclictest0-21swapper/3309:30:0127
2536599196186,8cyclictest0-21swapper/3309:30:0127
2536599196186,8cyclictest0-21swapper/3309:30:0027
2533499196190,4cyclictest0-21swapper/808:54:4238
2533499196190,4cyclictest0-21swapper/808:54:4238
2532699196189,5cyclictest2461-21CPU1
2532699196189,5cyclictest2461-21CPU1
2532699196187,6cyclictest0-21swapper/112:15:191
2532699196187,6cyclictest0-21swapper/112:15:181
2532699196187,6cyclictest0-21swapper/112:15:181
2537199195189,5cyclictest0-21swapper/3909:37:2633
2537199195189,5cyclictest0-21swapper/3909:37:2633
2537199195189,4cyclictest0-21swapper/3909:55:0733
2536599195188,5cyclictest0-21swapper/3312:01:2127
2536599195188,5cyclictest0-21swapper/3312:01:2027
2535499195174,17cyclictest3610-21CPU17
2535499195174,17cyclictest3610-21CPU17
2535499195174,17cyclictest3610-21CPU17
2533499195189,4cyclictest0-21swapper/809:58:1338
2533499195189,4cyclictest0-21swapper/809:58:1338
2533499195189,4cyclictest0-21swapper/809:58:1338
2537199194187,5cyclictest0-21swapper/3908:05:2733
2537199194187,5cyclictest0-21swapper/3908:05:2733
2534099194189,4cyclictest0-21swapper/1211:03:004
2534099194189,4cyclictest0-21swapper/1211:03:004
2534099194189,4cyclictest0-21swapper/1211:02:594
2534099194187,4cyclictest0-21swapper/1210:05:564
2534099194187,4cyclictest0-21swapper/1210:05:564
2533899194155,36cyclictest3544-21CPU3
2533899194155,36cyclictest3544-21CPU3
2533499194187,5cyclictest37257-21qemu-system-x8607:41:1138
2533499194187,5cyclictest37257-21qemu-system-x8607:41:1138
2532699194186,6cyclictest0-21swapper/109:45:461
2532699194186,6cyclictest0-21swapper/109:45:461
2537199193188,4cyclictest0-21swapper/3912:39:4933
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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