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2026-04-28 - 12:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Tue Apr 28, 2026 01:02:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1270499230225,4cyclictest0-21swapper/3520:25:1629
1270499230225,4cyclictest0-21swapper/3520:25:1629
1268799218200,14cyclictest0-21swapper/2023:43:4713
1268799218200,14cyclictest0-21swapper/2023:43:4613
1268799216203,9cyclictest0-21swapper/2023:55:1613
1268799216203,9cyclictest0-21swapper/2023:55:1613
1268799216203,9cyclictest0-21swapper/2023:55:1613
1270199212205,5cyclictest0-21swapper/3221:26:0426
1270199212205,5cyclictest0-21swapper/3221:26:0326
1270199212205,5cyclictest0-21swapper/3221:26:0326
1270199211204,3cyclictest37358-21CPU26
1270199211204,3cyclictest37358-21CPU26
1268799205197,6cyclictest0-21swapper/2023:45:2013
1268799205197,6cyclictest0-21swapper/2023:45:2013
1268599205183,13cyclictest0-21swapper/1800:14:2210
1268599205183,13cyclictest0-21swapper/1800:14:2210
1270499201194,3cyclictest37264-21CPU29
1270499201194,3cyclictest37264-21CPU29
1270199201196,3cyclictest3508-21sshd21:20:2026
1270199201196,3cyclictest3508-21sshd21:20:2026
1270499199192,5cyclictest0-21swapper/3520:05:1729
1270499199192,5cyclictest0-21swapper/3520:05:1629
1270199197192,4cyclictest0-21swapper/3221:16:4226
1270199197192,4cyclictest0-21swapper/3221:16:4226
1270199197192,4cyclictest0-21swapper/3221:16:4226
1268799196187,5cyclictest37356-21CPU13
1268799196187,5cyclictest37356-21CPU13
1268799195187,6cyclictest0-21swapper/2023:22:5913
1268799195187,6cyclictest0-21swapper/2023:22:5913
1268799194188,4cyclictest0-21swapper/2019:42:5313
1268799194188,4cyclictest0-21swapper/2019:42:5313
1270199193186,5cyclictest0-21swapper/3223:27:5326
1270199193186,5cyclictest0-21swapper/3223:27:5226
1270199193186,5cyclictest0-21swapper/3223:27:5226
1270599192166,23cyclictest3545-21CPU30
1270599192166,23cyclictest3545-21CPU30
1270599192166,23cyclictest3545-21CPU30
1269099192187,3cyclictest0-21swapper/2321:59:5916
1269099192187,3cyclictest0-21swapper/2321:59:5916
1270199191186,4cyclictest0-21swapper/3221:31:2326
1270199191186,4cyclictest0-21swapper/3221:31:2326
1268799191183,5cyclictest0-21swapper/2000:25:2113
1268799191183,5cyclictest0-21swapper/2000:25:2013
1268799191181,8cyclictest0-21swapper/2023:34:5713
1268799191181,8cyclictest0-21swapper/2023:34:5613
1268799190184,4cyclictest0-21swapper/2019:55:0113
1268799190184,4cyclictest0-21swapper/2019:55:0113
1270499189184,4cyclictest0-21swapper/3520:40:2229
1270499189184,4cyclictest0-21swapper/3520:40:2129
1269499189184,4cyclictest0-21swapper/2620:23:0119
1269499189184,4cyclictest0-21swapper/2620:23:0119
1269099189180,5cyclictest3545-21CPU16
1269099189180,5cyclictest3545-21CPU16
1267299189184,3cyclictest0-21swapper/821:10:0138
1267299189184,3cyclictest0-21swapper/821:10:0038
1267299189184,3cyclictest0-21swapper/821:10:0038
1269499188182,4cyclictest2456-21CPU19
1269499188182,4cyclictest2456-21CPU19
1268799188184,3cyclictest0-21swapper/2000:01:5413
1268799188184,3cyclictest0-21swapper/2000:01:5413
1268799188184,3cyclictest0-21swapper/2000:01:5313
1268799188178,8cyclictest0-21swapper/2000:30:2513
1268799188178,8cyclictest0-21swapper/2000:30:2413
1268799188178,8cyclictest0-21swapper/2000:30:2413
1268799188173,9cyclictest0-21swapper/2023:35:1413
1268799188173,9cyclictest0-21swapper/2023:35:1413
1270499187178,7cyclictest37257-21qemu-system-x8620:33:2429
1270299187178,6cyclictest0-21swapper/3323:37:3627
1270299187178,6cyclictest0-21swapper/3323:37:3627
1270199185180,4cyclictest0-21swapper/3221:09:4126
1270199185180,4cyclictest0-21swapper/3221:09:4026
1270199185180,4cyclictest0-21swapper/3221:09:4026
1269199185139,33cyclictest4407-21CPU17
1269199185139,33cyclictest4407-21CPU17
1269199185139,33cyclictest4407-21CPU17
1269099185178,5cyclictest0-21swapper/2322:43:3316
1269099185178,5cyclictest0-21swapper/2322:43:3316
1269099185178,5cyclictest0-21swapper/2322:43:3216
1268799185177,3cyclictest3610-21CPU13
1268799185177,3cyclictest3610-21CPU13
12708991841,3cyclictest0-21swapper/3900:15:2333
12708991841,3cyclictest0-21swapper/3900:15:2333
1269199184175,6cyclictest0-21swapper/2423:11:0417
1269199184175,6cyclictest0-21swapper/2423:11:0417
1269199184136,25cyclictest0-21swapper/2400:26:0017
1269199184136,25cyclictest0-21swapper/2400:26:0017
1269099184179,3cyclictest16598-21systemctl23:09:3116
1269099184179,3cyclictest16598-21systemctl23:09:3116
1269099184179,3cyclictest16598-21systemctl23:09:3016
1268799184175,7cyclictest22165-21cp00:10:1613
1268799184175,7cyclictest22165-21cp00:10:1513
1268799184174,3cyclictest0-21swapper/2000:05:1813
1268799184174,3cyclictest0-21swapper/2000:05:1813
1270499183176,3cyclictest3546-21CPU29
1270499183176,3cyclictest3546-21CPU29
1269499183152,16cyclictest0-21swapper/2620:10:5619
1269499183152,16cyclictest0-21swapper/2620:10:5619
1269199183139,19cyclictest0-21swapper/2422:17:1417
1269199183139,19cyclictest0-21swapper/2422:17:1317
1268799183173,8cyclictest24952-21packagekitd23:25:1413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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