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2026-03-17 - 00:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Mon Mar 16, 2026 13:03:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
366299221199,10cyclictest171rcu_preempt07:25:0433
366299221199,10cyclictest171rcu_preempt07:25:0433
3639992001,183cyclictest0-21swapper/3211:25:1326
3639992001,183cyclictest0-21swapper/3211:25:1326
3639992001,183cyclictest0-21swapper/3211:25:1226
359299195178,10cyclictest0-21swapper/1010:37:132
359299195178,10cyclictest0-21swapper/1010:37:132
359299195178,10cyclictest0-21swapper/1010:37:132
362899190182,6cyclictest0-21swapper/2509:11:4218
362899190182,6cyclictest0-21swapper/2509:11:4218
362899190182,6cyclictest0-21swapper/2509:11:4218
358899189122,53cyclictest0-21swapper/611:47:5636
358899189122,53cyclictest0-21swapper/611:47:5536
358899189122,53cyclictest0-21swapper/611:47:5536
362899187179,6cyclictest0-21swapper/2507:20:2418
362899187179,6cyclictest0-21swapper/2507:20:2418
362899187174,11cyclictest0-21swapper/2511:51:0318
362899187174,11cyclictest0-21swapper/2511:51:0218
362899187174,11cyclictest0-21swapper/2511:51:0218
362899185170,10cyclictest0-21swapper/2512:15:3718
362899185170,10cyclictest0-21swapper/2512:15:3718
358899184171,7cyclictest0-21swapper/611:27:5836
358899184171,7cyclictest0-21swapper/611:27:5836
358899184171,7cyclictest0-21swapper/611:27:5736
366199183173,8cyclictest0-21swapper/3807:18:4032
366199183173,8cyclictest0-21swapper/3807:18:4032
358399182173,4cyclictest0-21swapper/209:38:5512
358399182173,4cyclictest0-21swapper/209:38:5512
362899181170,6cyclictest2454-21CPU18
362899181170,6cyclictest2454-21CPU18
358399181176,2cyclictest0-21swapper/209:27:4812
358399181176,2cyclictest0-21swapper/209:27:4812
358399181176,2cyclictest0-21swapper/209:27:4812
35889918080,69cyclictest2454-21CPU36
358899180159,12cyclictest171rcu_preempt12:17:4936
358899180159,12cyclictest171rcu_preempt12:17:4936
358399179171,6cyclictest0-21swapper/208:35:0112
358399179171,6cyclictest0-21swapper/208:35:0112
366299178159,17cyclictest0-21swapper/3908:20:1833
366299178159,17cyclictest0-21swapper/3908:20:1733
363499178149,13cyclictest0-21swapper/3009:33:2524
363499178149,13cyclictest0-21swapper/3009:33:2524
363499178149,13cyclictest0-21swapper/3009:33:2424
362899178169,7cyclictest0-21swapper/2509:25:1918
362899178169,7cyclictest0-21swapper/2509:25:1918
362899178169,7cyclictest0-21swapper/2509:25:1818
358899178153,11cyclictest171rcu_preempt07:13:5836
358499178151,23cyclictest22170-21systemctl11:09:5023
358499178151,23cyclictest22170-21systemctl11:09:5023
358499178151,23cyclictest22170-21systemctl11:09:5023
358199178173,3cyclictest0-21swapper/009:50:170
358199178173,3cyclictest0-21swapper/009:50:170
358899177153,10cyclictest0-21swapper/609:31:5136
358899177153,10cyclictest0-21swapper/609:31:5136
358899177153,10cyclictest0-21swapper/609:31:5136
358899177125,38cyclictest0-21swapper/609:55:1736
358899177125,38cyclictest0-21swapper/609:55:1736
358899177125,38cyclictest0-21swapper/609:55:1736
358899177125,38cyclictest0-21swapper/609:55:1736
366199176166,6cyclictest3547-21CPU32
366199176166,6cyclictest3547-21CPU32
366199176166,6cyclictest3547-21CPU32
36149917693,78cyclictest0-21swapper/1907:20:1611
36149917693,78cyclictest0-21swapper/1907:20:1611
358899176157,5cyclictest0-21swapper/610:55:5136
358899176157,5cyclictest0-21swapper/610:55:5136
362899175170,4cyclictest0-21swapper/2508:20:2718
362899175170,4cyclictest0-21swapper/2508:20:2618
362899175169,4cyclictest0-21swapper/2509:23:4118
362899175169,4cyclictest0-21swapper/2509:23:4118
362899175169,4cyclictest0-21swapper/2509:23:4118
362899175163,10cyclictest0-21swapper/2508:15:1818
362899175163,10cyclictest0-21swapper/2508:15:1818
362199175168,4cyclictest22509-21cstates09:50:1414
362199175168,4cyclictest22509-21cstates09:50:1414
358899175154,9cyclictest171rcu_preempt12:02:2236
358899175154,9cyclictest171rcu_preempt12:02:2236
358899175154,9cyclictest171rcu_preempt12:02:2136
363499174144,13cyclictest171rcu_preempt09:36:2624
363499174144,13cyclictest171rcu_preempt09:36:2624
359599174169,3cyclictest0-21swapper/1312:35:155
359599174169,3cyclictest0-21swapper/1312:35:155
359599174169,3cyclictest0-21swapper/1312:35:155
359499174161,6cyclictest0-21swapper/1211:50:424
359499174161,6cyclictest0-21swapper/1211:50:424
359499174161,6cyclictest0-21swapper/1211:50:424
358899174163,9cyclictest0-21swapper/610:25:4636
358899174163,9cyclictest0-21swapper/610:25:4636
358399174165,7cyclictest0-21swapper/208:40:2012
358399174165,7cyclictest0-21swapper/208:40:2012
364499173155,15cyclictest2454-21CPU30
364499173155,15cyclictest2454-21CPU30
363499173145,13cyclictest171rcu_preempt09:16:0124
363499173145,13cyclictest171rcu_preempt09:16:0124
363499173141,14cyclictest171rcu_preempt07:18:5224
363499173141,14cyclictest171rcu_preempt07:18:5124
362899173160,11cyclictest0-21swapper/2509:01:1518
359499173167,5cyclictest0-21swapper/1210:50:474
359499173167,5cyclictest0-21swapper/1210:50:474
359499173167,5cyclictest0-21swapper/1210:50:474
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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