You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-01 - 20:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Mar 01, 2026 13:03:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2989999224195,17cyclictest0-21swapper/1911:34:0211
2989999224195,17cyclictest0-21swapper/1911:34:0211
2988299216171,15cyclictest0-21swapper/511:12:4135
2988299216171,15cyclictest0-21swapper/511:12:4135
2989999207180,17cyclictest0-21swapper/1910:46:3711
2989999207180,17cyclictest0-21swapper/1910:46:3611
2989999203190,9cyclictest1748150nfsd11:27:0411
2989999203190,9cyclictest1748150nfsd11:27:0411
2989999203190,9cyclictest1748150nfsd11:27:0411
2991399200192,4cyclictest2462-21CPU26
2991399200192,4cyclictest2462-21CPU26
2991399200192,4cyclictest2462-21CPU26
2991399200192,4cyclictest2462-21CPU26
2991799199192,5cyclictest0-21swapper/3411:56:0628
2991799199192,5cyclictest0-21swapper/3411:56:0628
2989999198191,4cyclictest0-21swapper/1911:51:4311
2989999198191,4cyclictest0-21swapper/1911:51:4311
2989999198191,4cyclictest0-21swapper/1911:51:4311
2988099197185,8cyclictest0-21swapper/310:43:3023
2988099197185,8cyclictest0-21swapper/310:43:3023
2988099197185,8cyclictest0-21swapper/310:43:2923
2991799196191,4cyclictest0-21swapper/3412:13:4728
2991799196191,4cyclictest0-21swapper/3412:13:4628
2991799196191,4cyclictest0-21swapper/3412:13:4628
2991799196191,4cyclictest0-21swapper/3412:13:4628
2989999196190,4cyclictest0-21swapper/1910:40:1011
2989999196190,4cyclictest0-21swapper/1910:40:1011
2989999196190,4cyclictest0-21swapper/1910:40:1011
2989999194188,3cyclictest29325-21bash10:30:1711
2989999194188,3cyclictest29325-21bash10:30:1611
2989999194188,3cyclictest29325-21bash10:30:1611
2989999192184,6cyclictest1358-21ModemManager10:39:0011
2989999192184,6cyclictest1358-21ModemManager10:38:5911
2989999192184,6cyclictest1358-21ModemManager10:38:5911
2989199190166,21cyclictest3610-21CPU5
2989199190166,21cyclictest3610-21CPU5
2989199190166,21cyclictest3610-21CPU5
2988099190171,6cyclictest0-21swapper/312:18:2723
2988099190171,6cyclictest0-21swapper/312:18:2623
2988099190171,6cyclictest0-21swapper/312:18:2623
2988099190162,23cyclictest0-21swapper/309:45:5123
2988099190162,23cyclictest0-21swapper/309:45:5123
2988099190162,23cyclictest0-21swapper/309:45:5123
2991799189182,5cyclictest0-21swapper/3412:20:1728
2991799189182,5cyclictest0-21swapper/3412:20:1628
2991799189181,4cyclictest3543-21CPU28
2989999189182,5cyclictest0-21swapper/1911:45:1411
2989999189182,5cyclictest0-21swapper/1911:45:1311
2989999189182,5cyclictest0-21swapper/1911:45:1311
2989999189177,9cyclictest0-21swapper/1911:04:2111
2989999189177,9cyclictest0-21swapper/1911:04:2111
2989999189177,9cyclictest0-21swapper/1911:04:2011
2989399189142,44cyclictest0-21swapper/1510:21:077
2989399189142,44cyclictest0-21swapper/1510:21:067
2989399189142,44cyclictest0-21swapper/1510:21:067
2989199189161,11cyclictest171rcu_preempt10:05:535
2989199189161,11cyclictest171rcu_preempt10:05:525
2989199189161,11cyclictest171rcu_preempt10:05:525
2991799188180,6cyclictest0-21swapper/3409:25:5728
2991799188180,6cyclictest0-21swapper/3409:25:5728
2991799188180,6cyclictest0-21swapper/3409:25:5728
2989199188183,4cyclictest0-21swapper/1307:49:345
2989199188183,4cyclictest0-21swapper/1307:49:335
2989999187182,4cyclictest0-21swapper/1910:30:0811
2989199187179,6cyclictest0-21swapper/1307:50:235
2989199187179,6cyclictest0-21swapper/1307:50:235
2991799186181,4cyclictest0-21swapper/3412:03:4728
2991799186181,4cyclictest0-21swapper/3412:03:4728
2991799186181,4cyclictest0-21swapper/3412:03:4728
2991799186177,5cyclictest3610-21CPU28
2991799186177,5cyclictest3610-21CPU28
2991799186177,5cyclictest3610-21CPU28
2989999186178,6cyclictest0-21swapper/1910:22:2811
2989999186178,6cyclictest0-21swapper/1910:22:2711
2989999186178,6cyclictest0-21swapper/1910:22:2711
2989999186176,7cyclictest0-21swapper/1910:05:1911
2989999186176,7cyclictest0-21swapper/1910:05:1911
2989999186176,7cyclictest0-21swapper/1910:05:1911
2991799185178,5cyclictest0-21swapper/3412:25:3528
2991799185178,5cyclictest0-21swapper/3412:25:3528
2991799185178,5cyclictest0-21swapper/3412:25:3428
2991799185178,5cyclictest0-21swapper/3409:21:5128
2991799185178,5cyclictest0-21swapper/3409:21:5028
2991799185178,5cyclictest0-21swapper/3409:21:5028
2989999185178,5cyclictest0-21swapper/1910:30:0111
2990899184177,3cyclictest0-21swapper/2811:15:2421
2990899184177,3cyclictest0-21swapper/2811:15:2421
2989999184179,2cyclictest0-21swapper/1911:22:4911
2989999184179,2cyclictest0-21swapper/1911:22:4811
2989999184179,2cyclictest0-21swapper/1911:22:4811
2989999184177,5cyclictest0-21swapper/1910:55:1311
2989999184177,5cyclictest0-21swapper/1910:55:1311
2989999184177,5cyclictest0-21swapper/1910:14:4511
2989999184177,5cyclictest0-21swapper/1910:14:4411
2988199184172,9cyclictest0-21swapper/412:08:5434
2988199184172,9cyclictest0-21swapper/412:08:5434
2988199184172,9cyclictest0-21swapper/412:08:5334
2989999183175,5cyclictest0-21swapper/1911:16:3511
2989999183175,5cyclictest0-21swapper/1911:16:3511
2989199183180,2cyclictest0-21swapper/1307:35:555
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional