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2026-02-22 - 07:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Sun Feb 22, 2026 01:03:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1652699214205,6cyclictest1392-21gdbus22:08:470
1652699214205,6cyclictest1392-21gdbus22:08:470
1652699214205,6cyclictest1392-21gdbus22:08:460
1652699205197,6cyclictest0-21swapper/022:25:080
1652699205197,6cyclictest0-21swapper/022:25:070
1652699205197,6cyclictest0-21swapper/022:25:070
1657399199190,7cyclictest0-21swapper/3621:29:2430
1657399199190,7cyclictest0-21swapper/3621:29:2430
1656399199140,55cyclictest37265-21CPU22
1656399199140,55cyclictest37265-21CPU22
1657299198177,13cyclictest0-21swapper/3500:13:4929
1657299198177,13cyclictest0-21swapper/3500:13:4929
1652699198186,4cyclictest0-21swapper/022:42:200
1652699198186,4cyclictest0-21swapper/022:42:200
1652699197191,5cyclictest0-21swapper/022:35:090
1652699197191,5cyclictest0-21swapper/022:35:090
1652699197191,5cyclictest0-21swapper/022:35:080
1652699195191,2cyclictest33488-21sshd21:35:090
1652699195191,2cyclictest33488-21sshd21:35:090
1653599194115,76cyclictest0-21swapper/821:30:0338
1653599194115,76cyclictest0-21swapper/821:30:0238
1652699194182,10cyclictest0-21swapper/022:32:380
1652699194182,10cyclictest0-21swapper/022:32:380
1652699194182,10cyclictest0-21swapper/022:32:380
1657399193185,6cyclictest0-21swapper/3621:21:2730
1657399193185,6cyclictest0-21swapper/3621:21:2630
1652699192185,5cyclictest0-21swapper/019:55:150
1652699192185,5cyclictest0-21swapper/019:55:150
1656399190171,7cyclictest0-21swapper/2922:37:3422
1656399190171,7cyclictest0-21swapper/2922:37:3422
1656399190171,7cyclictest0-21swapper/2922:37:3422
1652699189177,9cyclictest1360-21systemd-logind21:29:010
1652699189177,9cyclictest1360-21systemd-logind21:29:010
1656199188171,13cyclictest0-21swapper/2723:43:2920
1656199188171,13cyclictest0-21swapper/2723:43:2920
1652699188182,4cyclictest0-21swapper/023:05:150
1652699188182,4cyclictest0-21swapper/023:05:150
1652699188182,4cyclictest0-21swapper/023:05:150
1654899187182,3cyclictest0-21swapper/1822:25:1910
1654899187182,3cyclictest0-21swapper/1822:25:1810
1654899187182,3cyclictest0-21swapper/1822:25:1810
1653599187153,22cyclictest0-21swapper/823:45:1038
1653599187153,22cyclictest0-21swapper/823:45:1038
1653599187153,22cyclictest0-21swapper/823:45:1038
1652699187181,4cyclictest0-21swapper/022:55:330
1652699187181,4cyclictest0-21swapper/022:55:330
1652699187180,5cyclictest0-21swapper/022:54:150
1652699187180,5cyclictest0-21swapper/022:54:150
1652699187178,6cyclictest0-21swapper/022:18:400
1652699187178,6cyclictest0-21swapper/022:18:400
1652699186176,8cyclictest0-21swapper/023:25:020
1652699186176,8cyclictest0-21swapper/023:25:020
1652699186176,8cyclictest0-21swapper/023:25:010
1656399185151,29cyclictest0-21swapper/2919:30:1322
1656399185151,29cyclictest0-21swapper/2919:30:1222
1652699185174,10cyclictest0-21swapper/023:03:100
1652699185174,10cyclictest0-21swapper/023:03:100
1655499184152,26cyclictest4407-21CPU16
1655499184152,26cyclictest4407-21CPU16
1655499184152,26cyclictest4407-21CPU16
16535991841,139cyclictest2466-21CPU38
16535991841,139cyclictest2466-21CPU38
1652699184173,7cyclictest37354-21CPU0
1652699184173,7cyclictest37354-21CPU0
1652699184170,12cyclictest0-21swapper/021:48:270
1652699184170,12cyclictest0-21swapper/021:48:270
1652699184170,12cyclictest0-21swapper/021:48:260
1656199183173,8cyclictest0-21swapper/2700:32:3820
1656199183173,8cyclictest0-21swapper/2700:32:3820
1656199183173,8cyclictest0-21swapper/2700:32:3820
1656399182177,2cyclictest0-21swapper/2921:27:2122
1656399182177,2cyclictest0-21swapper/2921:27:2122
1652699182176,4cyclictest0-21swapper/021:32:110
1652699182176,4cyclictest0-21swapper/021:32:110
1652699182176,4cyclictest0-21swapper/021:32:100
1652699182163,11cyclictest0-21swapper/022:13:240
1652699182163,11cyclictest0-21swapper/022:13:240
1652699180154,24cyclictest0-21swapper/022:46:290
1652699180154,24cyclictest0-21swapper/022:46:280
1652699180112,64cyclictest3545-21CPU0
1652699180112,64cyclictest3545-21CPU0
1657699179151,24cyclictest0-21swapper/3921:50:0833
1657699179151,24cyclictest0-21swapper/3921:50:0733
1656399179173,4cyclictest0-21swapper/2900:07:2722
1656399179173,4cyclictest0-21swapper/2900:07:2722
1652699179169,8cyclictest0-21swapper/023:51:420
1652699179169,8cyclictest0-21swapper/023:51:420
1657399178172,4cyclictest0-21swapper/3621:15:3730
1657399178172,4cyclictest0-21swapper/3621:15:3730
1652699178170,6cyclictest0-21swapper/021:23:050
1652699178170,6cyclictest0-21swapper/021:23:040
1652699177172,4cyclictest0-21swapper/021:41:160
1652699177172,4cyclictest0-21swapper/021:41:160
1652699177172,4cyclictest0-21swapper/019:40:210
1652699177172,4cyclictest0-21swapper/019:40:200
1656299176164,10cyclictest0-21swapper/2821:47:1621
1656299176164,10cyclictest0-21swapper/2821:47:1621
1656299176164,10cyclictest0-21swapper/2821:47:1521
16539991760,6cyclictest18409-21cstates23:25:153
16539991760,6cyclictest18409-21cstates23:25:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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