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2026-02-18 - 18:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Feb 18, 2026 13:03:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4009799210193,13cyclictest3544-21CPU34
4009799210193,13cyclictest3544-21CPU34
4009799210193,13cyclictest3544-21CPU34
4012599198170,19cyclictest0-21swapper/2812:00:2621
4012599198170,19cyclictest0-21swapper/2812:00:2621
4013199197160,29cyclictest0-21swapper/3411:49:3128
4013199197160,29cyclictest0-21swapper/3411:49:3128
4013199197160,29cyclictest0-21swapper/3411:49:3128
4009799197190,5cyclictest0-21swapper/409:42:5534
4009799197190,5cyclictest0-21swapper/409:42:5534
4011299196188,6cyclictest0-21swapper/1809:11:5110
4011299196188,6cyclictest0-21swapper/1809:11:5110
4009999194184,9cyclictest0-21swapper/609:48:2436
4009999194184,9cyclictest0-21swapper/609:48:2336
4009999194184,9cyclictest0-21swapper/609:48:2336
4010999191161,20cyclictest0-21swapper/1610:53:308
4010999191161,20cyclictest0-21swapper/1610:53:298
4010999191161,20cyclictest0-21swapper/1610:53:298
4013199189127,56cyclictest2459-21CPU28
4013199189127,56cyclictest2459-21CPU28
4013599187178,4cyclictest0-21swapper/3709:33:1931
4013599187178,4cyclictest0-21swapper/3709:33:1931
4013599187178,4cyclictest0-21swapper/3709:33:1931
4013499187175,8cyclictest3544-21CPU30
4013499187175,8cyclictest3544-21CPU30
4012799187177,8cyclictest0-21swapper/3009:34:3924
4012799187177,8cyclictest0-21swapper/3009:34:3924
4012799187177,8cyclictest0-21swapper/3009:34:3824
4013499184172,4cyclictest0-21swapper/3610:07:5230
4013499184172,4cyclictest0-21swapper/3610:07:5230
4009999184168,13cyclictest0-21swapper/611:03:3836
4009999184168,13cyclictest0-21swapper/611:03:3836
4009799184171,10cyclictest0-21swapper/410:52:0634
4009799184171,10cyclictest0-21swapper/410:52:0534
4009799184171,10cyclictest0-21swapper/410:52:0534
4009799183170,11cyclictest0-21swapper/410:57:3134
4009799183170,11cyclictest0-21swapper/410:57:3134
4013499182170,6cyclictest0-21swapper/3608:57:3830
4013499182170,6cyclictest0-21swapper/3608:57:3830
4013199182140,38cyclictest0-21swapper/3412:35:0528
4013199182140,38cyclictest0-21swapper/3412:35:0428
40131991821,160cyclictest0-21swapper/3411:50:1828
40131991821,160cyclictest0-21swapper/3411:50:1728
40131991821,160cyclictest0-21swapper/3411:50:1728
4011899181131,44cyclictest0-21swapper/2312:25:2516
4011899181131,44cyclictest0-21swapper/2312:25:2516
4013599180164,6cyclictest0-21swapper/3707:20:1131
4013599180164,6cyclictest0-21swapper/3707:20:1131
4013599180138,16cyclictest0-21swapper/3707:18:2531
4013599180138,16cyclictest0-21swapper/3707:18:2431
4013499180169,9cyclictest0-21swapper/3611:23:2130
4013499180169,9cyclictest0-21swapper/3611:23:2130
4013199180144,26cyclictest0-21swapper/3409:19:2628
4013199180144,26cyclictest0-21swapper/3409:19:2528
4012799180132,17cyclictest171rcu_preempt11:02:1824
4012799180132,17cyclictest171rcu_preempt11:02:1824
4012799179149,9cyclictest171rcu_preempt10:22:0524
4012799179149,9cyclictest171rcu_preempt10:22:0424
401209917944,127cyclictest0-21swapper/2412:25:0117
401209917944,127cyclictest0-21swapper/2412:25:0017
4009999179169,7cyclictest0-21swapper/610:01:3036
4009999179169,7cyclictest0-21swapper/610:01:2936
4009999179158,8cyclictest0-21swapper/609:13:3336
4009999179158,8cyclictest0-21swapper/609:13:3336
4009799179167,10cyclictest0-21swapper/410:37:0134
4009799179167,10cyclictest0-21swapper/410:37:0134
4009799179167,10cyclictest0-21swapper/410:37:0134
4012799178141,16cyclictest171rcu_preempt12:29:0224
4012799178141,16cyclictest171rcu_preempt12:29:0224
4009699178166,9cyclictest0-21swapper/308:25:2123
4009699178166,9cyclictest0-21swapper/308:25:2023
4013499177157,12cyclictest0-21swapper/3612:00:3130
4013499177157,12cyclictest0-21swapper/3612:00:3030
4012099177157,16cyclictest0-21swapper/2411:05:3917
4012099177157,16cyclictest0-21swapper/2411:05:3917
4012099177157,16cyclictest0-21swapper/2411:05:3917
4009699177166,9cyclictest0-21swapper/311:54:2223
4009699177166,9cyclictest0-21swapper/311:54:2223
4009699177166,9cyclictest0-21swapper/311:54:2223
4013499176168,4cyclictest0-21swapper/3611:59:3130
4013499176168,4cyclictest0-21swapper/3611:59:3130
4013499176168,4cyclictest0-21swapper/3611:59:3030
4013499176168,4cyclictest0-21swapper/3611:59:3030
40131991762,161cyclictest37358-21CPU28
40131991762,161cyclictest37358-21CPU28
40131991762,161cyclictest37358-21CPU28
4013199176149,26cyclictest0-21swapper/3412:03:2928
4013199176149,26cyclictest0-21swapper/3412:03:2928
4013199176108,65cyclictest0-21swapper/3409:23:4828
4013199176108,65cyclictest0-21swapper/3409:23:4728
4013199176108,65cyclictest0-21swapper/3409:23:4728
4012799176155,11cyclictest0-21swapper/3007:28:0924
4012799176155,11cyclictest0-21swapper/3007:28:0924
4010499176161,6cyclictest0-21swapper/1110:21:273
4010499176161,6cyclictest0-21swapper/1110:21:273
4012799175115,29cyclictest0-21swapper/3009:58:3524
4012799175115,29cyclictest0-21swapper/3009:58:3424
4012599175160,10cyclictest0-21swapper/2810:51:5121
4012599175160,10cyclictest0-21swapper/2810:51:5121
4012599175160,10cyclictest0-21swapper/2810:51:5121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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