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2025-11-26 - 05:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot0.osadl.org (updated Wed Nov 26, 2025 01:00:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3547699273236,20cyclictest0-21swapper/1423:35:186
3547699273236,20cyclictest0-21swapper/1423:35:186
3550299244241,2cyclictest0-21swapper/3621:30:2430
3550299244241,2cyclictest0-21swapper/3621:30:2430
355069922024,182cyclictest23182-21inotify_reader20:35:2133
3547699217198,12cyclictest0-21swapper/1421:05:186
3547699217198,12cyclictest0-21swapper/1421:05:186
3547699217198,12cyclictest0-21swapper/1421:05:186
3545599215203,10cyclictest0-21swapper/023:04:560
3545599215203,10cyclictest0-21swapper/023:04:560
3545599215203,10cyclictest0-21swapper/023:04:560
3549099210190,11cyclictest0-21swapper/2523:52:3818
3549099210190,11cyclictest0-21swapper/2523:52:3818
3548299210206,2cyclictest0-21swapper/2020:35:1913
3545599207121,71cyclictest4632-21CPU0
3545599207121,71cyclictest4632-21CPU0
3547699206197,7cyclictest0-21swapper/1400:10:486
3547699206197,7cyclictest0-21swapper/1400:10:486
3549499205173,17cyclictest36795-21nfsd00:30:1822
3549499205173,17cyclictest36795-21nfsd00:30:1822
3547699205184,4cyclictest23763-2110-uname22:25:186
3547699205184,4cyclictest23763-2110-uname22:25:186
3547699204195,5cyclictest0-21swapper/1421:10:496
3547699204195,5cyclictest0-21swapper/1421:10:496
3545599202181,5cyclictest0-21swapper/020:34:380
3545599202181,5cyclictest0-21swapper/020:34:380
3545699201163,29cyclictest0-21swapper/121:01:021
3545699201163,29cyclictest0-21swapper/121:01:021
3547699200193,5cyclictest0-21swapper/1423:41:476
3547699200193,5cyclictest0-21swapper/1423:41:476
3547699200193,5cyclictest0-21swapper/1423:41:476
3547699200193,4cyclictest0-21swapper/1421:56:276
3547699200193,4cyclictest0-21swapper/1421:56:276
3547699200193,4cyclictest0-21swapper/1421:56:276
3549699199181,13cyclictest27824-21NetworkChangeNo00:20:1925
3549699199181,13cyclictest27824-21NetworkChangeNo00:20:1925
3549699199181,13cyclictest27824-21NetworkChangeNo00:20:1925
3547699199192,5cyclictest0-21swapper/1421:18:316
3547699199192,5cyclictest0-21swapper/1421:18:316
3547699198191,3cyclictest0-21swapper/1419:35:206
3547699198187,6cyclictest9327-21CPU6
3547699198187,6cyclictest9327-21CPU6
3547699197187,7cyclictest0-21swapper/1423:52:066
3547699197187,7cyclictest0-21swapper/1423:52:066
3547399196175,10cyclictest171rcu_preempt23:09:304
3547399196175,10cyclictest171rcu_preempt23:09:304
3545599196134,44cyclictest4909-21CPU0
3545599196134,44cyclictest4909-21CPU0
3545599196134,44cyclictest4909-21CPU0
35502991951,190cyclictest26841-21TaskSchedulerSi19:35:2030
3549099195189,4cyclictest0-21swapper/2522:31:3918
3549099195189,4cyclictest0-21swapper/2522:31:3918
3548199194174,15cyclictest4905-21CPU11
3548199194174,15cyclictest4905-21CPU11
3547899194101,77cyclictest4630-21CPU8
3547899194101,77cyclictest4630-21CPU8
3547699194186,4cyclictest15979-21CPU6
3547699194186,4cyclictest15979-21CPU6
3547699194186,4cyclictest15979-21CPU6
3547699194184,8cyclictest0-21swapper/1420:24:336
3547699194184,8cyclictest0-21swapper/1420:24:336
3547699193170,13cyclictest134-21ksoftirqd/1422:54:076
3547699193170,13cyclictest134-21ksoftirqd/1422:54:076
3547699193170,13cyclictest134-21ksoftirqd/1422:54:076
3545799193181,9cyclictest0-21swapper/221:38:5912
3545799193181,9cyclictest0-21swapper/221:38:5912
3549099192171,19cyclictest0-21swapper/2521:57:4418
3549099192171,19cyclictest0-21swapper/2521:57:4418
3549099192171,19cyclictest0-21swapper/2521:57:4418
3548299191186,3cyclictest0-21swapper/2000:20:1613
3548299191186,3cyclictest0-21swapper/2000:20:1613
3548299191186,3cyclictest0-21swapper/2000:20:1613
3548199191167,22cyclictest0-21swapper/1923:59:1011
3548199191167,22cyclictest0-21swapper/1923:59:1011
3548199191167,22cyclictest0-21swapper/1923:59:1011
3547699191185,4cyclictest0-21swapper/1421:25:496
3547699191185,4cyclictest0-21swapper/1421:25:496
3549699190123,63cyclictest15983-21CPU25
3549699190123,63cyclictest15983-21CPU25
3547699190184,5cyclictest0-21swapper/1400:24:046
3547699190184,5cyclictest0-21swapper/1400:24:046
3547699190184,5cyclictest0-21swapper/1400:24:046
3547699190168,11cyclictest15979-21CPU6
3547699190168,11cyclictest15979-21CPU6
3547699189183,4cyclictest0-21swapper/1423:13:186
3547699189183,4cyclictest0-21swapper/1423:13:186
3547699189183,4cyclictest0-21swapper/1423:13:186
3547699189183,4cyclictest0-21swapper/1420:30:156
3547699189183,4cyclictest0-21swapper/1420:30:156
3547699189175,11cyclictest0-21swapper/1421:41:386
3547699189175,11cyclictest0-21swapper/1421:41:386
3545799189172,12cyclictest1908-21sshd23:49:0412
3545799189172,12cyclictest1908-21sshd23:49:0412
3545799189172,12cyclictest1908-21sshd23:49:0412
3545599189139,30cyclictest0-21swapper/019:25:560
3545599189139,30cyclictest0-21swapper/019:25:560
3545599189131,29cyclictest0-21swapper/022:56:180
3545599189131,29cyclictest0-21swapper/022:56:180
3545599189131,29cyclictest0-21swapper/022:56:180
3545599189128,25cyclictest0-21swapper/023:21:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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