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2025-10-06 - 13:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Oct 06, 2025 01:01:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4011799251244,3cyclictest0-21swapper/1521:50:267
4011799251244,3cyclictest0-21swapper/1521:50:267
4011799251244,3cyclictest0-21swapper/1521:50:267
40137992341,107cyclictest1187-21TaskSchedulerSi22:10:2126
40137992341,107cyclictest1187-21TaskSchedulerSi22:10:2026
40137992341,107cyclictest1187-21TaskSchedulerSi22:10:2026
4012199232225,4cyclictest15983-21CPU11
4012199232225,4cyclictest15983-21CPU11
4012199232225,4cyclictest15983-21CPU11
401209922218,118cyclictest9334-21CPU10
401209922218,118cyclictest9334-21CPU10
40137992140,212cyclictest0-21swapper/3219:10:0226
40137992140,212cyclictest0-21swapper/3219:10:0126
4013099207200,5cyclictest0-21swapper/2722:17:4920
4013099207200,5cyclictest0-21swapper/2722:17:4920
4013099207200,5cyclictest0-21swapper/2722:17:4920
34172992070,69rtkit-daemon4906-21CPU10
34172992070,69rtkit-daemon4906-21CPU10
401139920576,107cyclictest0-21swapper/1122:05:193
401139920576,107cyclictest0-21swapper/1122:05:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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