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2026-04-08 - 14:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Apr 08, 2026 13:02:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
825399218176,30cyclictest0-21swapper/511:20:1035
825399218176,30cyclictest0-21swapper/511:20:0935
825399207197,8cyclictest0-21swapper/509:22:1635
825399207197,8cyclictest0-21swapper/509:22:1635
825399207197,8cyclictest0-21swapper/509:22:1535
825399205190,8cyclictest0-21swapper/511:06:5335
825399205190,8cyclictest0-21swapper/511:06:5335
825399205190,8cyclictest0-21swapper/511:06:5335
825399203193,7cyclictest0-21swapper/509:25:2735
825399203193,7cyclictest0-21swapper/509:25:2735
825399203193,7cyclictest0-21swapper/509:25:2735
827699201195,4cyclictest0-21swapper/2410:18:0617
827699201195,4cyclictest0-21swapper/2410:18:0617
827699201195,4cyclictest0-21swapper/2410:18:0617
825399200191,7cyclictest0-21swapper/510:52:4235
825399200191,7cyclictest0-21swapper/510:52:4235
825399200183,15cyclictest0-21swapper/510:59:1435
825399200183,15cyclictest0-21swapper/510:59:1435
827699195188,3cyclictest37270-21CPU17
827699195188,3cyclictest37270-21CPU17
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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