You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-22 - 18:56
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Nov 22, 2025 13:02:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1591599254216,17cyclictest23206-21TaskSchedulerSi10:10:200
1591599254216,17cyclictest23206-21TaskSchedulerSi10:10:200
1591599254216,17cyclictest23206-21TaskSchedulerSi10:10:200
1592999244241,2cyclictest0-21swapper/1311:30:235
1592999244241,2cyclictest0-21swapper/1311:30:235
1591599240223,9cyclictest0-21swapper/009:10:180
1591599240223,9cyclictest0-21swapper/009:10:180
1591599240223,9cyclictest0-21swapper/009:10:180
1591599233208,2cyclictest0-21swapper/010:05:210
1591599233208,2cyclictest0-21swapper/010:05:210
1591599233208,2cyclictest0-21swapper/010:05:200
1598999227200,10cyclictest0-21swapper/3807:50:2232
1598999227200,10cyclictest0-21swapper/3807:50:2232
15926992251,21cyclictest0-21swapper/1112:35:203
15926992251,21cyclictest0-21swapper/1112:35:203
1592499223199,5cyclictest15980-21CPU39
1592499223199,5cyclictest15980-21CPU39
1592499218194,14cyclictest0-21swapper/910:30:2139
1592499218194,14cyclictest0-21swapper/910:30:2139
1591599217193,12cyclictest7431-21NetworkChangeNo07:45:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional