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2026-01-06 - 21:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Jan 06, 2026 13:02:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1944499242234,5cyclictest0-21swapper/1709:50:169
1944499242234,5cyclictest0-21swapper/1709:50:169
1944499242234,5cyclictest0-21swapper/1709:50:169
1944499227216,7cyclictest0-21swapper/1710:10:229
1944499227216,7cyclictest0-21swapper/1710:10:229
1944499211203,6cyclictest0-21swapper/1711:50:019
1944499211203,6cyclictest0-21swapper/1711:50:019
1944499211203,6cyclictest0-21swapper/1711:50:019
1944499201189,9cyclictest16635-21cups-browsed09:18:369
1944499201189,9cyclictest16635-21cups-browsed09:18:369
1944499201189,9cyclictest16635-21cups-browsed09:18:369
1944499196188,5cyclictest1367-21dbus-daemon12:13:499
1944499196188,5cyclictest1367-21dbus-daemon12:13:499
1944499196188,5cyclictest1367-21dbus-daemon12:13:499
1944499196185,7cyclictest3548-21CPU9
1944499196185,7cyclictest3548-21CPU9
1944499196185,7cyclictest3548-21CPU9
1944499195189,3cyclictest9495-21systemd-cgroups10:07:379
1944499195189,3cyclictest9495-21systemd-cgroups10:07:379
1944499194186,5cyclictest24764-21cat11:05:139
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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