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2025-05-03 - 02:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri May 02, 2025 13:01:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1259299264239,10cyclictest0-21swapper/409:00:2134
1259299264239,10cyclictest0-21swapper/409:00:2134
1259499240215,3cyclictest36796-21nfsd12:30:1836
1259499240215,3cyclictest36796-21nfsd12:30:1836
1259499240215,3cyclictest36796-21nfsd12:30:1836
1259499225211,4cyclictest0-21swapper/610:40:2236
1259499225211,4cyclictest0-21swapper/610:40:2236
1259499225211,4cyclictest0-21swapper/610:40:2236
126419921215,32cyclictest19018-21inotify_reader09:35:2030
126419921215,32cyclictest19018-21inotify_reader09:35:2030
126419921215,32cyclictest19018-21inotify_reader09:35:2030
1261099206135,60cyclictest0-21swapper/1511:26:167
1261099206135,60cyclictest0-21swapper/1511:26:167
126229920020,155cyclictest2421-21sshd10:15:2119
126229920020,155cyclictest2421-21sshd10:15:2119
126229920020,155cyclictest2421-21sshd10:15:2119
1262099197129,65cyclictest24780-21NetworkChangeNo08:35:2118
1262099197129,65cyclictest24780-21NetworkChangeNo08:35:2118
1259499196188,4cyclictest15985-21CPU36
1259499196188,4cyclictest15985-21CPU36
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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