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2025-08-21 - 22:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Aug 21, 2025 13:02:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2511099283273,2cyclictest0-21swapper/109:05:181
2511099283273,2cyclictest0-21swapper/109:05:181
2511099283273,2cyclictest0-21swapper/109:05:181
2511599259230,17cyclictest0-21swapper/508:15:1935
2511599259230,17cyclictest0-21swapper/508:15:1935
2516299247224,10cyclictest25922-21TaskSchedulerSi11:15:1831
2516299247224,10cyclictest25922-21TaskSchedulerSi11:15:1831
2516299247224,10cyclictest25922-21TaskSchedulerSi11:15:1831
2513099230202,12cyclictest36072-21sshd09:20:199
2513099230202,12cyclictest36072-21sshd09:20:189
2513099230202,12cyclictest36072-21sshd09:20:189
25165992221,14cyclictest0-21swapper/3911:30:1833
25165992221,14cyclictest0-21swapper/3911:30:1833
25165992221,14cyclictest0-21swapper/3911:30:1733
25154992052,198cyclictest4910-21CPU28
25154992052,198cyclictest4910-21CPU28
25154992052,198cyclictest4910-21CPU28
251159920533,150cyclictest0-21swapper/510:25:1835
251159920533,150cyclictest0-21swapper/510:25:1835
251159920533,150cyclictest0-21swapper/510:25:1835
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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