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2026-05-23 - 18:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat May 23, 2026 13:02:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
874899225221,2cyclictest0-21swapper/2411:24:4317
874899225221,2cyclictest0-21swapper/2411:24:4317
876499222208,10cyclictest0-21swapper/3709:20:1631
876499222208,10cyclictest0-21swapper/3709:20:1531
876499219203,14cyclictest0-21swapper/3710:00:0131
876499219203,14cyclictest0-21swapper/3710:00:0131
876499219203,14cyclictest0-21swapper/3710:00:0131
876499215201,11cyclictest0-21swapper/3710:40:2431
876499215201,11cyclictest0-21swapper/3710:40:2431
874799215206,2cyclictest0-21swapper/2311:25:2116
874799215206,2cyclictest0-21swapper/2311:25:2016
874799215206,2cyclictest0-21swapper/2311:25:2016
876499214207,5cyclictest0-21swapper/3709:45:5831
876499214207,5cyclictest0-21swapper/3709:45:5731
876499214207,5cyclictest0-21swapper/3709:45:5731
876499214206,6cyclictest0-21swapper/3710:16:4831
876499214206,6cyclictest0-21swapper/3710:16:4831
876499213205,6cyclictest0-21swapper/3710:08:4131
876499213205,6cyclictest0-21swapper/3710:08:4131
876699212208,2cyclictest0-21swapper/3907:10:2533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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