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2025-09-04 - 06:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Thu Sep 04, 2025 01:01:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31040992911,151cyclictest0-21swapper/1600:25:218
31040992911,151cyclictest0-21swapper/1600:25:218
310429922683,136cyclictest0-21swapper/1821:55:1810
310429922683,136cyclictest0-21swapper/1821:55:1810
31066992229,83cyclictest18794-21TaskSchedulerSi21:30:1631
31066992229,83cyclictest18794-21TaskSchedulerSi21:30:1631
31066992229,83cyclictest18794-21TaskSchedulerSi21:30:1531
310609922127,185cyclictest0-21swapper/3200:35:1826
310609922127,185cyclictest0-21swapper/3200:35:1826
310609922122,178cyclictest9401-21TaskSchedulerSi23:40:1526
310609922122,178cyclictest9401-21TaskSchedulerSi23:40:1526
310609922122,178cyclictest9401-21TaskSchedulerSi23:40:1526
31055992099,87cyclictest15981-21CPU21
31055992099,87cyclictest15981-21CPU21
3101799207187,18cyclictest0-21swapper/1022:29:002
3101799207187,18cyclictest0-21swapper/1022:29:002
31066992042,198cyclictest40922-21inotify_reader19:10:1831
310609920425,161cyclictest9327-21CPU26
310609920425,161cyclictest9327-21CPU26
3106699197134,47cyclictest0-21swapper/3723:35:0131
3106699197134,47cyclictest0-21swapper/3723:35:0131
3106699197134,47cyclictest0-21swapper/3723:35:0131
31066991970,2cyclictest0-21swapper/3719:10:0331
3101799196187,6cyclictest0-21swapper/1019:11:022
310609919533,158cyclictest0-21swapper/3221:10:2526
310609919533,158cyclictest0-21swapper/3221:10:2526
310609919533,158cyclictest0-21swapper/3221:10:2526
310609919428,154cyclictest767-21systemd-journal00:24:3226
310609919428,154cyclictest767-21systemd-journal00:24:3126
310609919237,152cyclictest0-21swapper/3200:15:1526
310609919237,152cyclictest0-21swapper/3200:15:1526
310609919237,152cyclictest0-21swapper/3200:15:1526
3106099192181,9cyclictest0-21swapper/3221:07:1426
3106099192181,9cyclictest0-21swapper/3221:07:1426
310609919180,101cyclictest0-21swapper/3221:42:3226
310609919180,101cyclictest0-21swapper/3221:42:3226
310499919192,89cyclictest11903-21CPU15
310609919030,157cyclictest0-21swapper/3222:38:3526
310609919030,157cyclictest0-21swapper/3222:38:3526
310089919051,129cyclictest31359-21NetworkChangeNo22:35:2023
310089919051,129cyclictest31359-21NetworkChangeNo22:35:2023
310619918922,146cyclictest11262-21inotify_reader22:15:2227
310619918922,146cyclictest11262-21inotify_reader22:15:2227
310619918922,146cyclictest11262-21inotify_reader22:15:2227
309969918942,142cyclictest4908-21CPU0
309969918942,142cyclictest4908-21CPU0
309969918942,142cyclictest4908-21CPU0
31060991889,176cyclictest0-21swapper/3221:15:1726
31060991889,176cyclictest0-21swapper/3221:15:1726
310609918833,153cyclictest0-21swapper/3200:28:5426
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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