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2026-05-14 - 00:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Wed May 13, 2026 13:02:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11802992170,209cyclictest0-21swapper/1707:50:209
1182699201153,36cyclictest0-21swapper/3711:46:4131
1182699201153,36cyclictest0-21swapper/3711:46:4031
1182399183129,44cyclictest0-21swapper/3509:35:3029
1182399183129,44cyclictest0-21swapper/3509:35:2929
1178599180145,9cyclictest2447-21CPU23
1178599180145,9cyclictest2447-21CPU23
11802991791,173cyclictest0-21swapper/1708:00:199
11802991791,173cyclictest0-21swapper/1708:00:199
117969917984,70cyclictest3610-21CPU5
117969917984,70cyclictest3610-21CPU5
117969917984,70cyclictest3610-21CPU5
11802991780,175cyclictest0-21swapper/1708:06:349
11802991780,175cyclictest0-21swapper/1708:06:349
1179799178145,6cyclictest0-21swapper/1408:04:226
1179799178145,6cyclictest0-21swapper/1408:04:226
1182399175149,16cyclictest0-21swapper/3512:27:5229
1182399175149,16cyclictest0-21swapper/3512:27:5229
1182399175149,16cyclictest0-21swapper/3512:27:5229
1182399174126,36cyclictest0-21swapper/3510:30:2029
1182399174126,36cyclictest0-21swapper/3510:30:1929
11802991740,171cyclictest0-21swapper/1707:30:509
11802991740,171cyclictest0-21swapper/1707:30:509
1178599174128,28cyclictest0-21swapper/310:32:4823
1178599174128,28cyclictest0-21swapper/310:32:4723
118239917385,78cyclictest37265-21CPU29
118239917385,78cyclictest37265-21CPU29
11802991731,168cyclictest0-21swapper/1708:35:149
11802991731,168cyclictest0-21swapper/1708:35:139
11802991730,171cyclictest0-21swapper/1707:45:339
11802991730,171cyclictest0-21swapper/1707:45:329
11802991730,170cyclictest0-21swapper/1707:37:159
11802991730,170cyclictest0-21swapper/1707:37:149
1182399172161,8cyclictest0-21swapper/3509:19:4129
1182399172161,8cyclictest0-21swapper/3509:19:4029
11802991720,3cyclictest0-21swapper/1708:45:019
11802991720,3cyclictest0-21swapper/1708:45:019
117909917252,105cyclictest3541-21CPU37
117909917252,105cyclictest3541-21CPU37
117909917252,105cyclictest3541-21CPU37
1178299172148,5cyclictest0-21swapper/011:16:510
1178299172148,5cyclictest0-21swapper/011:16:500
11812991710,3cyclictest35894-21systemd09:50:1320
11812991710,3cyclictest35894-21systemd09:50:1320
11812991710,3cyclictest35894-21systemd09:50:1320
11802991710,3cyclictest0-21swapper/1708:10:409
11802991710,3cyclictest0-21swapper/1708:10:399
11802991710,168cyclictest0-21swapper/1708:30:269
11802991710,168cyclictest0-21swapper/1708:30:259
11802991710,167cyclictest0-21swapper/1707:25:269
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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