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2026-03-29 - 22:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Sun Mar 29, 2026 13:03:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1193199220209,8cyclictest0-21swapper/009:18:030
1193199220209,8cyclictest0-21swapper/009:18:030
1196399195184,9cyclictest0-21swapper/2812:09:3621
1196399195184,9cyclictest0-21swapper/2812:09:3621
1196399195184,9cyclictest0-21swapper/2812:09:3621
1194699194184,8cyclictest0-21swapper/1412:17:446
1194699194184,8cyclictest0-21swapper/1412:17:436
1196399189167,20cyclictest0-21swapper/2811:20:4321
1196399189167,20cyclictest0-21swapper/2811:20:4321
1196399189167,20cyclictest0-21swapper/2811:20:4321
119339918957,125cyclictest0-21swapper/209:25:1912
119339918957,125cyclictest0-21swapper/209:25:1912
11976991881,2cyclictest0-21swapper/3907:15:1433
11976991881,2cyclictest0-21swapper/3907:15:1433
1195599188154,11cyclictest0-21swapper/2111:45:1814
1195599188154,11cyclictest0-21swapper/2111:45:1814
1195599186164,20cyclictest0-21swapper/2109:59:1414
1195599186164,20cyclictest0-21swapper/2109:59:1414
1195599186164,20cyclictest0-21swapper/2109:59:1414
1194899185168,7cyclictest0-21swapper/1610:58:168
1194899185168,7cyclictest0-21swapper/1610:58:158
1194899185168,7cyclictest0-21swapper/1610:58:158
1193799185177,6cyclictest0-21swapper/610:49:2636
1193799185177,6cyclictest0-21swapper/610:49:2636
1195899183135,44cyclictest37358-21CPU16
1195899183135,44cyclictest37358-21CPU16
1197299182161,18cyclictest0-21swapper/3610:01:4330
1197299182161,18cyclictest0-21swapper/3610:01:4330
1196599181176,3cyclictest0-21swapper/3012:15:1524
1196599181176,3cyclictest0-21swapper/3012:15:1524
1196399181169,9cyclictest0-21swapper/2810:19:1521
1196399181169,9cyclictest0-21swapper/2810:19:1521
1196399181169,9cyclictest0-21swapper/2810:19:1521
1197499180160,9cyclictest0-21swapper/3807:28:0232
1197499180160,9cyclictest0-21swapper/3807:28:0232
1197299180167,7cyclictest27962-21systemd11:50:1530
1197299180167,7cyclictest27962-21systemd11:50:1530
1197299180167,7cyclictest27962-21systemd11:50:1530
11933991802,167cyclictest3609-21CPU12
11933991802,167cyclictest3609-21CPU12
1196399179174,3cyclictest0-21swapper/2809:29:4021
1196399179174,3cyclictest0-21swapper/2809:29:3921
1195599179156,21cyclictest0-21swapper/2109:47:2314
1195599179156,21cyclictest0-21swapper/2109:47:2314
1194899179169,8cyclictest0-21swapper/1610:17:568
1194899179169,8cyclictest0-21swapper/1610:17:558
1194899179169,8cyclictest0-21swapper/1610:17:558
1196499178168,8cyclictest0-21swapper/2911:23:1722
1196499178168,8cyclictest0-21swapper/2911:23:1722
1196499178168,8cyclictest0-21swapper/2911:23:1722
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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