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2026-01-28 - 15:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Wed Jan 28, 2026 13:00:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2135699201177,21cyclictest0-21swapper/1610:40:078
2135699201177,21cyclictest0-21swapper/1610:40:078
2135699201177,21cyclictest0-21swapper/1610:40:078
2134399193188,3cyclictest0-21swapper/512:00:0035
2134399193188,3cyclictest0-21swapper/512:00:0035
2134399193188,3cyclictest0-21swapper/512:00:0035
2136599191110,75cyclictest3548-21CPU15
21340991910,187cyclictest17483-21nfsd12:15:2112
21340991910,187cyclictest17483-21nfsd12:15:2012
21340991910,187cyclictest17483-21nfsd12:15:2012
2138499190114,72cyclictest0-21swapper/3809:35:2032
2138499190114,72cyclictest0-21swapper/3809:35:2032
2136899190102,84cyclictest3544-21CPU18
2136899190102,84cyclictest3544-21CPU18
2136899190102,84cyclictest3544-21CPU18
21340991891,81cyclictest0-21swapper/211:30:1912
21340991891,81cyclictest0-21swapper/211:30:1812
2136699187149,14cyclictest0-21swapper/2311:23:0916
2136699187149,14cyclictest0-21swapper/2311:23:0916
21340991871,87cyclictest0-21swapper/211:50:1612
21340991871,87cyclictest0-21swapper/211:50:1612
2138099186172,12cyclictest0-21swapper/3611:34:2030
2138099186172,12cyclictest0-21swapper/3611:34:2030
21370991861,102cyclictest0-21swapper/2712:06:4320
21370991861,102cyclictest0-21swapper/2712:06:4320
2134099186142,41cyclictest0-21swapper/210:22:2812
2134099186142,41cyclictest0-21swapper/210:22:2812
21356991842,87cyclictest0-21swapper/1607:50:148
21356991842,87cyclictest0-21swapper/1607:50:148
21384991831,174cyclictest0-21swapper/3809:40:1232
21384991831,174cyclictest0-21swapper/3809:40:1132
2134699183170,9cyclictest0-21swapper/811:04:1338
2134699183170,9cyclictest0-21swapper/811:04:1338
2137099182140,37cyclictest0-21swapper/2709:38:4220
2137099182140,37cyclictest0-21swapper/2709:38:4120
21356991821,131cyclictest0-21swapper/1609:25:138
21356991821,131cyclictest0-21swapper/1609:25:138
21356991821,131cyclictest0-21swapper/1609:25:138
2138099181176,2cyclictest0-21swapper/3609:36:1630
2138099181176,2cyclictest0-21swapper/3609:36:1630
21370991802,91cyclictest2459-21CPU20
21370991802,91cyclictest2459-21CPU20
21370991802,91cyclictest2459-21CPU20
2136599180167,11cyclictest0-21swapper/2212:18:1715
2136599180167,11cyclictest0-21swapper/2212:18:1715
2136599180167,11cyclictest0-21swapper/2212:18:1615
2136599179172,2cyclictest0-21swapper/2209:00:2515
2136599179172,2cyclictest0-21swapper/2209:00:2515
2136599179166,5cyclictest0-21swapper/2208:27:5615
2136599179166,5cyclictest0-21swapper/2208:27:5615
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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