You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-14 - 14:08
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Sun Dec 14, 2025 12:59:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1155399224219,4cyclictest0-21swapper/1409:33:136
1155399224219,4cyclictest0-21swapper/1409:33:136
1155399213204,5cyclictest0-21swapper/1410:20:146
1155399213204,5cyclictest0-21swapper/1410:20:146
1153999212203,6cyclictest0-21swapper/107:30:131
1153999212203,6cyclictest0-21swapper/107:30:131
1155399211204,5cyclictest0-21swapper/1411:42:436
1155399211204,5cyclictest0-21swapper/1411:42:436
1155399210202,3cyclictest37358-21CPU6
1155399210202,3cyclictest37358-21CPU6
1155699208200,6cyclictest0-21swapper/1711:03:159
1155699208200,6cyclictest0-21swapper/1711:03:159
1153999208188,9cyclictest0-21swapper/111:30:041
1153999208188,9cyclictest0-21swapper/111:30:041
1155699207199,6cyclictest0-21swapper/1709:53:539
1155699207199,6cyclictest0-21swapper/1709:53:539
1155699207197,6cyclictest2447-21CPU9
1155699207197,6cyclictest2447-21CPU9
1155699206199,4cyclictest0-21swapper/1710:48:099
1155699206199,4cyclictest0-21swapper/1710:48:099
1153999206202,2cyclictest0-21swapper/112:29:241
1153999206202,2cyclictest0-21swapper/112:29:241
1155699203198,4cyclictest0-21swapper/1709:57:449
1155699203198,4cyclictest0-21swapper/1709:57:449
1155699203192,8cyclictest0-21swapper/1709:19:019
1155699203192,8cyclictest0-21swapper/1709:19:019
1155399202196,5cyclictest0-21swapper/1411:23:496
1155399202196,5cyclictest0-21swapper/1411:23:496
1155399202193,7cyclictest0-21swapper/1411:39:116
1155399202193,7cyclictest0-21swapper/1411:39:116
1155399202193,7cyclictest0-21swapper/1411:39:116
1154699202190,8cyclictest0-21swapper/811:50:5038
1154699202190,8cyclictest0-21swapper/811:50:5038
1154699202190,8cyclictest0-21swapper/811:50:5038
1155699201194,6cyclictest0-21swapper/1712:24:139
1155699201194,6cyclictest0-21swapper/1712:24:139
1155699201194,6cyclictest0-21swapper/1712:24:139
1155699201168,9cyclictest171rcu_preempt11:36:239
1155699201168,9cyclictest171rcu_preempt11:36:239
1155699201168,9cyclictest171rcu_preempt11:36:239
1154199201193,6cyclictest0-21swapper/312:39:4723
1154199201193,6cyclictest0-21swapper/312:39:4723
1156799200100,96cyclictest37265-21CPU18
1156799200100,96cyclictest37265-21CPU18
1155699199185,8cyclictest30083-21sshd10:50:459
1155699199185,8cyclictest30083-21sshd10:50:459
1155399199192,5cyclictest0-21swapper/1409:29:156
1155399199192,5cyclictest0-21swapper/1409:29:156
1155399199192,5cyclictest0-21swapper/1409:29:156
1157899198191,5cyclictest0-21swapper/3508:30:2329
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional