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2025-07-13 - 10:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Sun Jul 13, 2025 01:00:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
262829925290,65cyclictest9579-21inotify_reader22:15:222
262829925290,65cyclictest9579-21inotify_reader22:15:222
262829925290,65cyclictest9579-21inotify_reader22:15:222
2629599224201,10cyclictest0-21swapper/2122:35:2214
2629599224201,10cyclictest0-21swapper/2122:35:2214
2629599224201,10cyclictest0-21swapper/2122:35:2214
262769922438,168cyclictest4635-21CPU36
262769922438,168cyclictest4635-21CPU36
262769922438,168cyclictest4635-21CPU36
2631099223220,2cyclictest0-21swapper/3319:10:5627
2631099223220,2cyclictest0-21swapper/3319:10:5627
2627399216213,2cyclictest0-21swapper/421:55:3034
2627399216213,2cyclictest0-21swapper/421:55:3034
2629599209195,8cyclictest0-21swapper/2121:00:2114
2629599209195,8cyclictest0-21swapper/2121:00:2114
2631599203193,8cyclictest0-21swapper/3821:18:4532
2631599203193,8cyclictest0-21swapper/3821:18:4532
2631599203193,8cyclictest0-21swapper/3821:18:4532
2626899201174,14cyclictest171rcu_preempt19:37:410
2626899201174,14cyclictest171rcu_preempt19:37:410
263149920060,133cyclictest0-21swapper/3722:35:2231
263149920060,133cyclictest0-21swapper/3722:35:2231
263149920060,133cyclictest0-21swapper/3722:35:2131
263019919826,167cyclictest26932-21inotify_reader23:05:2120
263019919826,167cyclictest26932-21inotify_reader23:05:2120
263019919826,167cyclictest26932-21inotify_reader23:05:2120
262939919747,127cyclictest33412-21inotify_reader22:45:1811
262939919747,127cyclictest33412-21inotify_reader22:45:1711
26315991947,170cyclictest0-21swapper/3822:45:1932
26315991947,170cyclictest0-21swapper/3822:45:1932
2629999194179,7cyclictest171rcu_preempt23:37:1618
2629999194179,7cyclictest171rcu_preempt23:37:1618
2627199193154,17cyclictest171rcu_preempt19:48:2512
2627199192182,5cyclictest0-21swapper/219:37:4012
2627199192182,5cyclictest0-21swapper/219:37:4012
2626899192137,30cyclictest0-21swapper/023:52:100
2626899192137,30cyclictest0-21swapper/023:52:090
2626899192137,30cyclictest0-21swapper/023:52:090
26308991911,186cyclictest14738-21inotify_reader22:35:2225
26308991911,186cyclictest14738-21inotify_reader22:35:2225
26308991911,186cyclictest14738-21inotify_reader22:35:2225
26308991911,178cyclictest0-21swapper/3121:55:2025
26308991911,178cyclictest0-21swapper/3121:55:2025
2629999191178,11cyclictest0-21swapper/2523:14:5918
2629999191178,11cyclictest0-21swapper/2523:14:5918
2629999191178,11cyclictest0-21swapper/2523:14:5918
2627399190181,7cyclictest34228-21kworker/u81:4-events_unbound22:25:0634
2627399190181,7cyclictest34228-21kworker/u81:4-events_unbound22:25:0634
2627399190181,7cyclictest34228-21kworker/u81:4-events_unbound22:25:0634
2631599189144,42cyclictest0-21swapper/3819:28:2532
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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