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2025-05-02 - 12:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Fri May 02, 2025 01:00:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
272299928127,239cyclictest40018-21sshd23:10:2019
272299928127,239cyclictest40018-21sshd23:10:2019
272299928127,239cyclictest40018-21sshd23:10:1919
272299926924,226cyclictest0-21swapper/2623:50:2319
272299926924,226cyclictest0-21swapper/2623:50:2319
272299926348,200cyclictest0-21swapper/2600:30:2119
272299926348,200cyclictest0-21swapper/2600:30:2019
272209922960,55cyclictest0-21swapper/1822:45:1810
272209922960,55cyclictest0-21swapper/1822:45:1810
272299921849,151cyclictest18542-21inotify_reader22:00:1919
272299921849,151cyclictest18542-21inotify_reader22:00:1919
272299921849,151cyclictest18542-21inotify_reader22:00:1919
272299921823,177cyclictest0-21swapper/2619:40:2619
272299921823,177cyclictest0-21swapper/2619:40:2619
272299920331,161cyclictest15985-21CPU19
272299920331,161cyclictest15985-21CPU19
2722899203190,11cyclictest0-21swapper/2521:25:0018
2722899203190,11cyclictest0-21swapper/2521:25:0018
2722899203190,11cyclictest0-21swapper/2521:25:0018
2720999203184,12cyclictest0-21swapper/1121:27:563
2720999203184,12cyclictest0-21swapper/1121:27:563
2720999203184,12cyclictest0-21swapper/1121:27:563
2719699203197,4cyclictest0-21swapper/822:38:4938
2719699203197,4cyclictest0-21swapper/822:38:4938
2722999202191,9cyclictest0-21swapper/2623:37:1619
2722999202191,9cyclictest0-21swapper/2623:37:1619
2721399202187,6cyclictest0-21swapper/1322:57:135
2721399202187,6cyclictest0-21swapper/1322:57:135
2722099199164,32cyclictest9327-21CPU10
2722099199164,32cyclictest9327-21CPU10
2721499199193,4cyclictest0-21swapper/1421:30:136
2721499199193,4cyclictest0-21swapper/1421:30:136
27225991964,187cyclictest13967-21NetworkChangeNo23:00:2015
27225991964,187cyclictest13967-21NetworkChangeNo23:00:2015
27225991964,187cyclictest13967-21NetworkChangeNo23:00:2015
2717099196148,26cyclictest0-21swapper/222:27:4512
2717099196148,26cyclictest0-21swapper/222:27:4512
2717099196148,26cyclictest0-21swapper/222:27:4512
27225991952,3cyclictest9334-21CPU15
27225991952,3cyclictest9334-21CPU15
2716999195188,5cyclictest0-21swapper/123:22:561
2716999195188,5cyclictest0-21swapper/123:22:561
2716999195188,5cyclictest0-21swapper/123:22:561
272299919410,179cyclictest0-21swapper/2622:25:2019
272299919410,179cyclictest0-21swapper/2622:25:2019
272299919410,179cyclictest0-21swapper/2622:25:2019
27225991931,176cyclictest0-21swapper/2222:30:2115
27225991931,176cyclictest0-21swapper/2222:30:2115
27225991931,176cyclictest0-21swapper/2222:30:2115
27225991925,4cyclictest15979-21CPU15
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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