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2025-04-19 - 19:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Sat Apr 19, 2025 13:01:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
459799330327,2cyclictest0-21swapper/1709:56:119
459799330327,2cyclictest0-21swapper/1709:56:119
4622992251,208cyclictest0-21swapper/3709:10:2231
4622992251,208cyclictest0-21swapper/3709:10:2231
461599211202,7cyclictest0-21swapper/3110:19:4525
461599211202,7cyclictest0-21swapper/3110:19:4525
461599211202,7cyclictest0-21swapper/3110:19:4525
459799206195,8cyclictest0-21swapper/1711:40:219
459799206195,8cyclictest0-21swapper/1711:40:219
459799206195,8cyclictest0-21swapper/1711:40:219
459799204201,2cyclictest0-21swapper/1708:15:309
459799204201,2cyclictest0-21swapper/1708:15:309
459799200179,10cyclictest0-21swapper/1710:55:189
459799200179,10cyclictest0-21swapper/1710:55:189
459799200179,10cyclictest0-21swapper/1710:55:189
459799199192,5cyclictest0-21swapper/1710:35:199
459799199192,5cyclictest0-21swapper/1710:35:199
459799199192,5cyclictest0-21swapper/1710:35:199
458699199186,11cyclictest0-21swapper/710:26:1837
458699199186,11cyclictest0-21swapper/710:26:1837
458699199186,11cyclictest0-21swapper/710:26:1837
45879919890,89cyclictest31459-21inotify_reader10:55:1938
45879919890,89cyclictest31459-21inotify_reader10:55:1938
45879919890,89cyclictest31459-21inotify_reader10:55:1938
462899196180,13cyclictest0-21swapper/3810:17:3932
462899196180,13cyclictest0-21swapper/3810:17:3932
462899196180,13cyclictest0-21swapper/3810:17:3932
4582991951,160cyclictest0-21swapper/510:09:2535
4582991951,160cyclictest0-21swapper/510:09:2535
4582991951,160cyclictest0-21swapper/510:09:2535
462899194191,2cyclictest0-21swapper/3812:17:3032
462899194191,2cyclictest0-21swapper/3812:17:2932
461599194165,12cyclictest171rcu_preempt11:31:5825
461599194165,12cyclictest171rcu_preempt11:31:5825
461599194165,12cyclictest171rcu_preempt11:31:5825
462899193187,3cyclictest0-21swapper/3809:05:2032
462899193187,3cyclictest0-21swapper/3809:05:2032
459799193180,12cyclictest36795-21nfsd08:25:229
459799193180,12cyclictest36795-21nfsd08:25:229
459799192185,5cyclictest0-21swapper/1711:00:139
459799192185,5cyclictest0-21swapper/1711:00:139
459799192185,5cyclictest0-21swapper/1711:00:139
459799191177,9cyclictest0-21swapper/1709:50:449
459799191177,9cyclictest0-21swapper/1709:50:449
459799191177,9cyclictest0-21swapper/1709:50:449
46099919044,61cyclictest4912-21CPU18
46099919044,61cyclictest4912-21CPU18
46099919044,61cyclictest4912-21CPU18
459799190183,4cyclictest1526-21dbus-daemon10:50:119
459799190183,4cyclictest1526-21dbus-daemon10:50:119
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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