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2026-08-12 - 13:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Wed Aug 12, 2026 01:01:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
703899216208,6cyclictest3535-21qemu-system-x8623:50:2120
703899216208,6cyclictest3535-21qemu-system-x8623:50:2120
703899216208,6cyclictest3535-21qemu-system-x8623:50:2120
703899208190,11cyclictest2447-21CPU20
703899208190,11cyclictest2447-21CPU20
700699205182,7cyclictest0-21swapper/022:25:380
700699205182,7cyclictest0-21swapper/022:25:380
703899202194,6cyclictest0-21swapper/2700:11:0020
703899202194,6cyclictest0-21swapper/2700:11:0020
704299200196,2cyclictest0-21swapper/3019:35:0124
704299200196,2cyclictest0-21swapper/3019:35:0124
703899200186,6cyclictest0-21swapper/2722:15:3420
703899200186,6cyclictest0-21swapper/2722:15:3320
703899200186,6cyclictest0-21swapper/2722:15:3320
703899200185,7cyclictest0-21swapper/2722:07:3220
703899200185,7cyclictest0-21swapper/2722:07:3220
703899200185,7cyclictest0-21swapper/2722:07:3220
702099200183,9cyclictest0-21swapper/1122:47:413
702099200183,9cyclictest0-21swapper/1122:47:413
702099200183,9cyclictest0-21swapper/1122:47:413
703899198187,8cyclictest0-21swapper/2722:10:5520
703899198187,8cyclictest0-21swapper/2722:10:5520
703899198166,20cyclictest0-21swapper/2722:40:3920
703899198166,20cyclictest0-21swapper/2722:40:3820
703899196187,6cyclictest25005-21gdbus21:38:4820
703899196187,6cyclictest25005-21gdbus21:38:4820
703899195188,5cyclictest0-21swapper/2723:12:2120
703899195188,5cyclictest0-21swapper/2723:12:2120
703899195187,3cyclictest4407-21CPU20
703899195187,3cyclictest4407-21CPU20
700699195188,4cyclictest0-21swapper/023:54:050
700699195188,4cyclictest0-21swapper/023:54:050
700699195188,4cyclictest0-21swapper/023:54:050
703899194185,4cyclictest0-21swapper/2700:19:4620
703899194185,4cyclictest0-21swapper/2700:19:4620
702899193180,12cyclictest0-21swapper/1820:01:2310
704599192174,16cyclictest0-21swapper/3222:44:5226
704599192174,16cyclictest0-21swapper/3222:44:5226
703899192183,7cyclictest0-21swapper/2721:40:3120
703899192183,7cyclictest0-21swapper/2721:40:3020
703899189180,7cyclictest0-21swapper/2721:30:1620
703899189180,7cyclictest0-21swapper/2721:30:1620
703899189177,10cyclictest17482-21nfsd23:55:1820
703899189177,10cyclictest17482-21nfsd23:55:1820
703899189177,10cyclictest17482-21nfsd23:55:1720
703899189162,14cyclictest0-21swapper/2723:40:0120
703899189162,14cyclictest0-21swapper/2723:40:0120
703899189162,14cyclictest0-21swapper/2723:40:0020
703899187168,15cyclictest1367-21dbus-daemon00:33:1420
703899187168,15cyclictest1367-21dbus-daemon00:33:1420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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