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2025-06-17 - 02:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot0.osadl.org (updated Tue Jun 17, 2025 01:00:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1672799236232,2cyclictest0-21swapper/920:19:0939
1672799236232,2cyclictest0-21swapper/920:19:0939
1673699235229,3cyclictest0-21swapper/1522:17:317
1673699235229,3cyclictest0-21swapper/1522:17:317
1672099225114,67cyclictest0-21swapper/322:55:1723
1672099225114,67cyclictest0-21swapper/322:55:1723
1672199214201,11cyclictest0-21swapper/422:57:1334
1672199214201,11cyclictest0-21swapper/422:57:1334
1675099211191,13cyclictest0-21swapper/2720:47:3520
1675099211191,13cyclictest0-21swapper/2720:47:3520
1675299210204,3cyclictest16944-21kworker/u80:0-ext4-rsv-conversion21:37:3522
1675299210204,3cyclictest16944-21kworker/u80:0-ext4-rsv-conversion21:37:3522
1675199210145,44cyclictest0-21swapper/2822:25:1921
1675199210145,44cyclictest0-21swapper/2822:25:1921
1674499209168,28cyclictest0-21swapper/2220:20:2115
1674499209168,28cyclictest0-21swapper/2220:20:2115
1672199208192,14cyclictest0-21swapper/400:18:4834
1672199208192,14cyclictest0-21swapper/400:18:4834
1672199208192,14cyclictest0-21swapper/400:18:4834
1672199208192,14cyclictest0-21swapper/400:18:4834
1672199205181,22cyclictest0-21swapper/421:32:4434
1672199205181,22cyclictest0-21swapper/421:32:4434
1672199205181,22cyclictest0-21swapper/421:32:4434
1672199205180,23cyclictest0-21swapper/422:11:2934
1672199205180,23cyclictest0-21swapper/422:11:2934
1672199202193,7cyclictest0-21swapper/423:59:5434
1672199202193,7cyclictest0-21swapper/423:59:5434
1672199202193,7cyclictest0-21swapper/423:59:5434
167379920195,65cyclictest27802-21inotify_reader00:15:208
167379920195,65cyclictest27802-21inotify_reader00:15:208
167379920195,65cyclictest27802-21inotify_reader00:15:208
167379920195,65cyclictest27802-21inotify_reader00:15:208
1675299200167,20cyclictest0-21swapper/2922:50:3222
1675299200167,20cyclictest0-21swapper/2922:50:3122
1675299200167,20cyclictest0-21swapper/2922:50:3122
1675099200186,9cyclictest0-21swapper/2721:03:1420
1675099199189,7cyclictest0-21swapper/2719:20:2920
1675099199189,7cyclictest0-21swapper/2719:20:2920
1675099199184,13cyclictest0-21swapper/2722:33:0720
1675099199184,13cyclictest0-21swapper/2722:33:0720
1675099199184,13cyclictest0-21swapper/2722:33:0720
1675099199183,14cyclictest0-21swapper/2720:36:0020
1675099199183,14cyclictest0-21swapper/2720:36:0020
1674399199171,12cyclictest0-21swapper/2120:20:4414
1674399199171,12cyclictest0-21swapper/2120:20:4414
167339919850,143cyclictest19017-21TaskSchedulerSi21:20:235
167339919850,143cyclictest19017-21TaskSchedulerSi21:20:235
167339919850,143cyclictest19017-21TaskSchedulerSi21:20:235
1675299197187,8cyclictest0-21swapper/2921:49:0322
1675299197187,8cyclictest0-21swapper/2921:49:0322
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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