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2026-08-03 - 21:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Aug 03, 2026 13:02:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1411399232229,2cyclictest0-21swapper/1708:45:259
1411399232229,2cyclictest0-21swapper/1708:45:259
1409399219208,7cyclictest37346-21qemu-system-x8610:00:200
1409399219208,7cyclictest37346-21qemu-system-x8610:00:200
1413299217213,2cyclictest0-21swapper/3209:00:1526
1413299217213,2cyclictest0-21swapper/3209:00:1526
1409399215204,8cyclictest0-21swapper/010:05:230
1409399215204,8cyclictest0-21swapper/010:05:230
1412599214196,12cyclictest0-21swapper/2611:34:1119
1412599214196,12cyclictest0-21swapper/2611:34:1119
1413799213208,4cyclictest0-21swapper/3509:15:3029
1413799213208,4cyclictest0-21swapper/3509:15:3029
1413799213208,4cyclictest0-21swapper/3509:15:2929
1410599213208,4cyclictest0-21swapper/1011:43:312
1410599213208,4cyclictest0-21swapper/1011:43:312
1410599212207,4cyclictest0-21swapper/1007:41:202
1410599212204,5cyclictest3547-21CPU2
1410599212204,5cyclictest3547-21CPU2
1409399212196,12cyclictest17484-21nfsd11:30:150
1409399212196,12cyclictest17484-21nfsd11:30:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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