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2025-11-26 - 03:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Nov 26, 2025 01:00:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3547699273236,20cyclictest0-21swapper/1423:35:186
3547699273236,20cyclictest0-21swapper/1423:35:186
3550299244241,2cyclictest0-21swapper/3621:30:2430
3550299244241,2cyclictest0-21swapper/3621:30:2430
355069922024,182cyclictest23182-21inotify_reader20:35:2133
3547699217198,12cyclictest0-21swapper/1421:05:186
3547699217198,12cyclictest0-21swapper/1421:05:186
3547699217198,12cyclictest0-21swapper/1421:05:186
3545599215203,10cyclictest0-21swapper/023:04:560
3545599215203,10cyclictest0-21swapper/023:04:560
3545599215203,10cyclictest0-21swapper/023:04:560
3549099210190,11cyclictest0-21swapper/2523:52:3818
3549099210190,11cyclictest0-21swapper/2523:52:3818
3548299210206,2cyclictest0-21swapper/2020:35:1913
3545599207121,71cyclictest4632-21CPU0
3545599207121,71cyclictest4632-21CPU0
3547699206197,7cyclictest0-21swapper/1400:10:486
3547699206197,7cyclictest0-21swapper/1400:10:486
3549499205173,17cyclictest36795-21nfsd00:30:1822
3549499205173,17cyclictest36795-21nfsd00:30:1822
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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