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2026-07-12 - 21:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Jul 12, 2026 13:01:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3315599200183,13cyclictest0-21swapper/3112:30:1325
3315599200183,13cyclictest0-21swapper/3112:30:1325
3315299196190,4cyclictest0-21swapper/2810:32:0321
3315299196190,4cyclictest0-21swapper/2810:32:0321
3315299196190,4cyclictest0-21swapper/2810:32:0321
3315599193183,8cyclictest0-21swapper/3111:45:1625
3315599193183,8cyclictest0-21swapper/3111:45:1625
3315599193183,8cyclictest0-21swapper/3111:45:1625
3315599187179,6cyclictest0-21swapper/3111:52:5125
3315599187179,6cyclictest0-21swapper/3111:52:5125
3315599187179,4cyclictest0-21swapper/3110:20:1625
3315599187179,4cyclictest0-21swapper/3110:20:1625
3315599187179,4cyclictest0-21swapper/3110:20:1625
3315599186178,5cyclictest0-21swapper/3111:37:5325
3315599186178,5cyclictest0-21swapper/3111:37:5325
3316099184126,30cyclictest0-21swapper/3510:49:1029
3316099184126,30cyclictest0-21swapper/3510:49:1029
3316099184126,30cyclictest0-21swapper/3510:49:1029
331389918490,83cyclictest2461-21CPU9
331389918490,83cyclictest2461-21CPU9
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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