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2026-02-05 - 09:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Feb 05, 2026 01:02:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
205389920015,178cyclictest0-21swapper/820:20:5938
205389920015,178cyclictest0-21swapper/820:20:5938
2056199198167,15cyclictest171rcu_preempt00:27:5821
2056199198167,15cyclictest171rcu_preempt00:27:5821
2056199198167,15cyclictest171rcu_preempt00:27:5821
2056199196189,5cyclictest0-21swapper/2823:46:1721
2056199196189,5cyclictest0-21swapper/2823:46:1721
20537991961,188cyclictest0-21swapper/722:15:0137
20537991961,188cyclictest0-21swapper/722:15:0137
20537991961,188cyclictest0-21swapper/722:15:0037
2057699189165,20cyclictest0-21swapper/3800:01:5432
2057699189165,20cyclictest0-21swapper/3800:01:5432
2056199186155,28cyclictest0-21swapper/2800:06:1521
2056199186155,28cyclictest0-21swapper/2800:06:1421
2055799186175,9cyclictest0-21swapper/2421:25:3517
2055799186175,9cyclictest0-21swapper/2421:25:3517
2053699185173,10cyclictest0-21swapper/622:34:2936
2053699185173,10cyclictest0-21swapper/622:34:2836
2056199182155,12cyclictest0-21swapper/2821:28:2221
2056199182155,12cyclictest0-21swapper/2821:28:2121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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