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2026-05-09 - 03:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat May 09, 2026 01:01:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2751199254242,10cyclictest13018-21kworker/u81:3+events_unbound22:25:1015
2751199254242,10cyclictest13018-21kworker/u81:3+events_unbound22:25:1015
27511992471,243cyclictest755-21systemd-journal23:04:0915
27511992471,243cyclictest755-21systemd-journal23:04:0915
27511992470,3cyclictest1442-21gdbus21:51:5715
27511992470,3cyclictest1442-21gdbus21:51:5615
27511992470,3cyclictest1442-21gdbus21:51:5615
27511992451,240cyclictest4398-21qemu-system-x8622:40:2415
27511992451,240cyclictest4398-21qemu-system-x8622:40:2415
27511992441,232cyclictest0-21swapper/2221:13:5615
27511992441,232cyclictest0-21swapper/2221:13:5615
27511992441,232cyclictest0-21swapper/2221:13:5515
27511992411,4cyclictest755-21systemd-journal21:40:2015
27511992411,4cyclictest755-21systemd-journal21:40:2015
27511992411,4cyclictest755-21systemd-journal21:40:2015
27511992391,5cyclictest28908-21bash22:36:5415
27511992391,5cyclictest28908-21bash22:36:5415
27511992361,4cyclictest35865-21sshd00:31:2915
27511992361,4cyclictest35865-21sshd00:31:2815
27511992341,3cyclictest0-21swapper/2221:20:0115
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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