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2026-09-05 - 01:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Sep 04, 2026 13:01:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22333992591,2cyclictest0-21swapper/111:00:011
22333992591,2cyclictest0-21swapper/111:00:011
22333992461,2cyclictest0-21swapper/109:20:441
22333992461,2cyclictest0-21swapper/109:20:441
22333992461,2cyclictest0-21swapper/109:20:441
22333992440,2cyclictest0-21swapper/112:22:211
22333992440,2cyclictest0-21swapper/112:22:211
22333992432,4cyclictest37356-21CPU1
22333992432,4cyclictest37356-21CPU1
22333992432,4cyclictest37356-21CPU1
22333992430,2cyclictest0-21swapper/111:43:161
22333992430,2cyclictest0-21swapper/111:43:161
22333992430,2cyclictest0-21swapper/111:43:161
22333992410,2cyclictest0-21swapper/110:15:241
22333992410,2cyclictest0-21swapper/110:15:241
22333992362,3cyclictest37267-21CPU1
22333992362,3cyclictest37267-21CPU1
22333992343,226cyclictest3610-21CPU1
22333992343,226cyclictest3610-21CPU1
22333992331,2cyclictest0-21swapper/112:04:521
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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