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2026-07-16 - 16:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Jul 16, 2026 13:01:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
931399226207,7cyclictest0-21swapper/3409:35:1428
931399226207,7cyclictest0-21swapper/3409:35:1328
931399226207,7cyclictest0-21swapper/3409:35:1328
927599223210,11cyclictest0-21swapper/212:39:2412
927599223210,11cyclictest0-21swapper/212:39:2312
931399222211,7cyclictest4407-21CPU28
931399222211,7cyclictest4407-21CPU28
928799222215,4cyclictest15456-21sshd10:06:314
928799222215,4cyclictest15456-21sshd10:06:304
928799222215,4cyclictest15456-21sshd10:06:304
928799219199,16cyclictest0-21swapper/1210:00:394
928799219199,16cyclictest0-21swapper/1210:00:394
929799215208,5cyclictest0-21swapper/2111:40:2914
929799215208,5cyclictest0-21swapper/2111:40:2914
929799215208,5cyclictest0-21swapper/2111:40:2914
929799214208,4cyclictest0-21swapper/2111:54:3614
929799214208,4cyclictest0-21swapper/2111:54:3514
929799214208,4cyclictest0-21swapper/2111:54:3514
927599214209,3cyclictest0-21swapper/207:25:1812
927599214209,3cyclictest0-21swapper/207:25:1812
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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