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2026-05-18 - 05:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon May 18, 2026 01:01:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2190599216211,4cyclictest0-21swapper/3323:09:4727
2190599216211,4cyclictest0-21swapper/3323:09:4727
2187599212200,10cyclictest0-21swapper/721:10:0237
2187599212200,10cyclictest0-21swapper/721:10:0237
2190599208200,6cyclictest0-21swapper/3322:00:1827
2190599208200,6cyclictest0-21swapper/3322:00:1827
2190599207201,4cyclictest0-21swapper/3323:15:2927
2190599207201,4cyclictest0-21swapper/3323:15:2827
2187599206196,6cyclictest3542-21CPU37
2190599205198,5cyclictest0-21swapper/3321:22:4927
2190599205198,5cyclictest0-21swapper/3321:22:4827
2187599205195,9cyclictest0-21swapper/722:45:0537
2190599204198,5cyclictest0-21swapper/3321:34:0527
2190599204198,5cyclictest0-21swapper/3321:34:0527
2190599203197,4cyclictest0-21swapper/3319:55:1427
2190599203197,4cyclictest0-21swapper/3319:55:1327
2190599203196,5cyclictest0-21swapper/3319:45:2127
2190599203196,5cyclictest0-21swapper/3319:45:2027
2187599203187,13cyclictest0-21swapper/722:08:0737
2187599203187,13cyclictest0-21swapper/722:08:0737
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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