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2026-05-03 - 08:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun May 03, 2026 01:01:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3687499210202,5cyclictest3535-21qemu-system-x8623:15:1418
3687499210202,5cyclictest3535-21qemu-system-x8623:15:1418
3688199209203,4cyclictest0-21swapper/3120:57:3325
3688199209203,4cyclictest0-21swapper/3120:57:3325
3688199208191,13cyclictest0-21swapper/3120:50:4325
3688199208191,13cyclictest0-21swapper/3120:50:4325
3687499207197,7cyclictest4398-21qemu-system-x8600:06:4718
3687499207197,7cyclictest4398-21qemu-system-x8600:06:4718
3688199205197,6cyclictest0-21swapper/3119:20:1325
3688199205197,6cyclictest0-21swapper/3119:20:1225
3688199204196,6cyclictest0-21swapper/3120:00:1225
3688199204196,6cyclictest0-21swapper/3120:00:1225
3688199202197,4cyclictest0-21swapper/3120:15:5425
3688199202197,4cyclictest0-21swapper/3120:15:5425
3687499202191,7cyclictest0-21swapper/2523:35:1118
3687499202191,7cyclictest0-21swapper/2523:35:1118
3688199200195,3cyclictest37970-21gzip20:05:3125
3688199200195,3cyclictest37970-21gzip20:05:3125
3688199200193,5cyclictest0-21swapper/3120:30:0225
3688199200193,5cyclictest0-21swapper/3120:30:0125
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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