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2026-07-01 - 04:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Jul 01, 2026 01:01:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1657299211133,74cyclictest3548-21CPU12
1657299211133,74cyclictest3548-21CPU12
1658999202187,11cyclictest0-21swapper/1720:20:159
1658999202187,11cyclictest0-21swapper/1720:20:159
1658999193185,6cyclictest0-21swapper/1721:40:259
1658999193185,6cyclictest0-21swapper/1721:40:259
1658999191183,6cyclictest0-21swapper/1721:17:239
1658999191183,6cyclictest0-21swapper/1721:17:239
1658999190182,6cyclictest0-21swapper/1722:15:109
1658999190182,6cyclictest0-21swapper/1722:15:109
1658999188183,4cyclictest0-21swapper/1721:35:169
1658999188183,4cyclictest0-21swapper/1721:35:159
1658999188181,5cyclictest0-21swapper/1720:43:369
1658999186166,16cyclictest0-21swapper/1721:49:349
1658999186166,16cyclictest0-21swapper/1721:49:349
1658999186166,16cyclictest0-21swapper/1721:49:349
1657099186182,2cyclictest36040-21kworker/u81:5+events_unbound23:45:160
1657099186182,2cyclictest36040-21kworker/u81:5+events_unbound23:45:150
1658999185179,4cyclictest0-21swapper/1721:12:389
1658999185179,4cyclictest0-21swapper/1721:12:389
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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