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2026-07-30 - 19:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Jul 30, 2026 13:01:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3023199228212,6cyclictest0-21swapper/310:07:2823
3023199228212,6cyclictest0-21swapper/310:07:2823
3023199212205,6cyclictest0-21swapper/308:10:4723
3025199210202,6cyclictest0-21swapper/2008:41:2513
3026899201194,5cyclictest0-21swapper/3307:45:2027
3023299199185,4cyclictest0-21swapper/410:38:1634
3023299199185,4cyclictest0-21swapper/410:38:1634
3023299199185,4cyclictest0-21swapper/410:38:1634
3026899198192,4cyclictest0-21swapper/3308:00:4227
3026899198192,4cyclictest0-21swapper/3308:00:4227
3026899198187,9cyclictest0-21swapper/3307:41:3227
3026899198187,9cyclictest0-21swapper/3307:41:3227
3026899197184,11cyclictest0-21swapper/3308:10:0427
3026899197184,11cyclictest0-21swapper/3308:10:0327
3023199197192,3cyclictest0-21swapper/309:15:3623
3023199197192,3cyclictest0-21swapper/309:15:3523
3026299196177,15cyclictest0-21swapper/2809:39:0421
3026299196177,15cyclictest0-21swapper/2809:39:0321
3023199196185,5cyclictest0-21swapper/311:46:1423
3023199196185,5cyclictest0-21swapper/311:46:1323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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