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2026-06-21 - 04:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Jun 21, 2026 01:01:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2639992401,234cyclictest0-21swapper/1900:14:5711
2639992401,234cyclictest0-21swapper/1900:14:5611
2639992351,230cyclictest0-21swapper/1921:00:1411
2639992351,224cyclictest0-21swapper/1923:48:0511
2639992351,224cyclictest0-21swapper/1923:48:0411
2639992351,224cyclictest0-21swapper/1923:48:0411
2639992341,2cyclictest0-21swapper/1922:02:4011
2639992341,2cyclictest0-21swapper/1922:02:4011
2639992323,224cyclictest2454-21CPU11
2639992323,224cyclictest2454-21CPU11
2639992323,224cyclictest2454-21CPU11
2639992321,3cyclictest4398-21qemu-system-x8623:19:5811
2639992321,3cyclictest4398-21qemu-system-x8623:19:5811
2639992321,3cyclictest4398-21qemu-system-x8623:19:5811
2639992321,228cyclictest0-21swapper/1922:22:3611
2639992321,228cyclictest0-21swapper/1922:22:3511
2639992311,5cyclictest4317-21sshd00:26:2311
2639992311,5cyclictest4317-21sshd00:26:2311
2639992293,221cyclictest3610-21CPU11
2639992293,221cyclictest3610-21CPU11
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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