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2026-06-09 - 00:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Jun 08, 2026 13:02:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3405699212209,2cyclictest0-21swapper/3510:01:1429
3405699212209,2cyclictest0-21swapper/3510:01:1429
3405699212209,2cyclictest0-21swapper/3510:01:1429
3404399205199,4cyclictest0-21swapper/2512:06:3518
3404399205199,4cyclictest0-21swapper/2512:06:3418
3404399203197,4cyclictest0-21swapper/2507:35:0018
3404399203197,4cyclictest0-21swapper/2507:35:0018
3405899201193,5cyclictest0-21swapper/3712:35:5231
3405899201193,5cyclictest0-21swapper/3712:35:5231
3405899201193,5cyclictest0-21swapper/3712:35:5131
3404399201193,6cyclictest0-21swapper/2509:20:0118
3404399201193,6cyclictest0-21swapper/2509:20:0118
3404399201187,12cyclictest27379-21taskset10:41:2418
3404399201187,12cyclictest27379-21taskset10:41:2418
3404399201187,12cyclictest27379-21taskset10:41:2318
34041991993,86cyclictest0-21swapper/2408:55:2717
3405899198191,4cyclictest0-21swapper/3711:52:1431
3405899198191,4cyclictest0-21swapper/3711:52:1431
3405699198191,4cyclictest3610-21CPU29
3405699198191,4cyclictest3610-21CPU29
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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