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2025-12-14 - 13:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Dec 14, 2025 01:00:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
964899214209,3cyclictest0-21swapper/920:50:1939
964899214209,3cyclictest0-21swapper/920:50:1939
966599205198,5cyclictest0-21swapper/2523:49:1318
966599205198,5cyclictest0-21swapper/2523:49:1318
966599205198,5cyclictest0-21swapper/2523:49:1318
965599202194,6cyclictest25005-21gdbus22:10:208
965599202194,6cyclictest25005-21gdbus22:10:208
964099200195,4cyclictest0-21swapper/300:22:1423
964099200195,4cyclictest0-21swapper/300:22:1423
964099200195,4cyclictest0-21swapper/300:22:1423
965599199193,4cyclictest0-21swapper/1621:51:128
965599199193,4cyclictest0-21swapper/1621:51:128
966899198193,4cyclictest0-21swapper/2723:17:3120
966899198193,4cyclictest0-21swapper/2723:17:3120
965799198106,80cyclictest0-21swapper/1821:05:0210
9646991980,3cyclictest0-21swapper/821:17:0538
9646991980,3cyclictest0-21swapper/821:17:0538
965599197192,4cyclictest0-21swapper/1623:21:218
965599197192,4cyclictest0-21swapper/1623:21:218
965599197176,19cyclictest0-21swapper/1623:49:058
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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