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2025-10-19 - 12:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Oct 19, 2025 01:00:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2436899311308,2cyclictest0-21swapper/2421:10:2817
2436899311308,2cyclictest0-21swapper/2421:10:2817
2436899282277,2cyclictest0-21swapper/2421:59:3517
2436899282277,2cyclictest0-21swapper/2421:59:3517
24351992321,68cyclictest0-21swapper/1322:15:205
24351992321,68cyclictest0-21swapper/1322:15:195
243399922520,202cyclictest18560-21TaskSchedulerSi00:05:1638
243399922520,202cyclictest18560-21TaskSchedulerSi00:05:1638
243399922520,202cyclictest18560-21TaskSchedulerSi00:05:1638
2435199211121,83cyclictest0-21swapper/1319:20:205
2435199211121,83cyclictest0-21swapper/1319:20:205
24362992101,197cyclictest20600-21sshd00:35:0011
24362992101,197cyclictest20600-21sshd00:35:0011
2436899209187,10cyclictest36794-21nfsd22:55:2017
2436899209187,10cyclictest36794-21nfsd22:55:2017
2436799209177,18cyclictest34009-21inotify_reader20:20:2016
2436799209177,18cyclictest34009-21inotify_reader20:20:2016
2430999206192,3cyclictest0-21swapper/000:25:200
2430999206192,3cyclictest0-21swapper/000:25:200
2430999206192,3cyclictest0-21swapper/000:25:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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