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2026-07-14 - 00:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Jul 13, 2026 13:02:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2306199237228,4cyclictest3546-21CPU29
2306199237228,4cyclictest3546-21CPU29
2306199237228,4cyclictest3546-21CPU29
2302799221202,7cyclictest0-21swapper/810:57:5238
2302799221202,7cyclictest0-21swapper/810:57:5138
23064992161,3cyclictest0-21swapper/3811:00:0232
23064992161,3cyclictest0-21swapper/3811:00:0232
2305399213200,9cyclictest0-21swapper/2912:25:1722
2305399213200,9cyclictest0-21swapper/2912:25:1722
2305399213200,9cyclictest0-21swapper/2912:25:1722
2302799213200,5cyclictest0-21swapper/809:53:2238
2302799213200,5cyclictest0-21swapper/809:53:2238
2302799213200,5cyclictest0-21swapper/809:53:2138
2305399211204,5cyclictest0-21swapper/2912:18:2922
2305399211204,5cyclictest0-21swapper/2912:18:2822
2305399211204,5cyclictest0-21swapper/2912:18:2822
2303599211202,5cyclictest3545-21CPU4
2303599211202,5cyclictest3545-21CPU4
2305399210204,3cyclictest0-21swapper/2909:35:1722
2305399210204,3cyclictest0-21swapper/2909:35:1622
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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