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2025-11-23 - 16:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Nov 23, 2025 13:02:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
710999400374,4cyclictest3078-21CPU2
710999400374,4cyclictest3078-21CPU2
710999400374,4cyclictest3078-21CPU2
7126992621,3cyclictest0-21swapper/2511:05:1918
7126992621,3cyclictest0-21swapper/2511:05:1918
7126992621,3cyclictest0-21swapper/2511:05:1918
71199925111,231cyclictest0-21swapper/1910:20:2111
71199925111,231cyclictest0-21swapper/1910:20:2111
71199925111,231cyclictest0-21swapper/1910:20:2011
712599250245,2cyclictest0-21swapper/2411:03:3017
712599250245,2cyclictest0-21swapper/2411:03:3017
712599250245,2cyclictest0-21swapper/2411:03:2917
712599235198,21cyclictest32878-21NetworkChangeNo12:10:2017
712599235198,21cyclictest32878-21NetworkChangeNo12:10:2017
712599235198,21cyclictest32878-21NetworkChangeNo12:10:2017
712599234208,8cyclictest9079-21inotify_reader08:05:1817
712599234208,8cyclictest9079-21inotify_reader08:05:1817
712599233218,9cyclictest0-21swapper/2411:40:1917
712599233218,9cyclictest0-21swapper/2411:40:1917
712599233218,9cyclictest0-21swapper/2411:40:1917
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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