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2025-09-16 - 23:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Sep 16, 2025 13:01:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2255599326321,2cyclictest0-21swapper/1010:30:262
2255599326321,2cyclictest0-21swapper/1010:30:262
2259099242223,7cyclictest0-21swapper/3807:55:1932
2259099242223,7cyclictest0-21swapper/3807:55:1932
2256899225220,3cyclictest0-21swapper/2109:25:2614
2256899225220,3cyclictest0-21swapper/2109:25:2614
2256899225220,3cyclictest0-21swapper/2109:25:2614
2254599224137,57cyclictest15979-21CPU12
2254599224137,57cyclictest15979-21CPU12
2256899219207,9cyclictest32015-21inotify_reader10:35:1914
2256899219207,9cyclictest32015-21inotify_reader10:35:1914
2259099218205,7cyclictest15983-21CPU32
2259099218205,7cyclictest15983-21CPU32
22545992181,89cyclictest0-21swapper/211:50:1712
22545992181,89cyclictest0-21swapper/211:50:1712
2257199209129,58cyclictest28780-21TaskSchedulerSi08:00:1716
2257199209129,58cyclictest28780-21TaskSchedulerSi08:00:1716
2256899209176,30cyclictest12196-21inotify_reader12:15:2014
2256899209176,30cyclictest12196-21inotify_reader12:15:2014
2256899209176,30cyclictest12196-21inotify_reader12:15:2014
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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