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2025-12-15 - 16:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Dec 15, 2025 13:00:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1939799205196,6cyclictest0-21swapper/807:17:4138
1939799194185,7cyclictest0-21swapper/807:23:1438
1939799194185,7cyclictest0-21swapper/807:23:1438
1938999194150,8cyclictest0-21swapper/111:04:431
1938999194150,8cyclictest0-21swapper/111:04:431
1941499186125,14cyclictest0-21swapper/2211:20:5315
1941499186125,14cyclictest0-21swapper/2211:20:5315
1939699185146,9cyclictest0-21swapper/711:08:4537
1939699185146,9cyclictest0-21swapper/711:08:4537
1939699185146,9cyclictest0-21swapper/711:08:4537
1939799184178,4cyclictest0-21swapper/807:45:0138
1939799184178,4cyclictest0-21swapper/807:45:0138
1939799181173,5cyclictest0-21swapper/807:35:2238
1939799181173,5cyclictest0-21swapper/807:35:2238
1939699181153,26cyclictest0-21swapper/711:19:3237
1939699181153,26cyclictest0-21swapper/711:19:3237
1938999181158,11cyclictest0-21swapper/109:20:561
1938999181158,11cyclictest0-21swapper/109:20:561
1938999181158,11cyclictest0-21swapper/109:20:561
1938999181135,40cyclictest3544-21CPU1
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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