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2026-09-19 - 21:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Sep 19, 2026 13:02:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1871499198192,4cyclictest0-21swapper/3607:55:3230
1871499198192,4cyclictest0-21swapper/3607:55:3230
1868899195184,5cyclictest0-21swapper/1311:39:015
1868899195184,5cyclictest0-21swapper/1311:39:015
1871499193177,13cyclictest0-21swapper/3609:57:1330
1871499193177,13cyclictest0-21swapper/3609:57:1330
1871499193177,13cyclictest0-21swapper/3609:57:1330
186779919386,96cyclictest3548-21CPU23
186779919386,96cyclictest3548-21CPU23
186779919386,96cyclictest3548-21CPU23
1868599191140,48cyclictest0-21swapper/1109:38:413
1868599191140,48cyclictest0-21swapper/1109:38:413
18673991901,186cyclictest0-21swapper/112:20:131
18673991901,186cyclictest0-21swapper/112:20:131
1868899189181,5cyclictest0-21swapper/1309:25:015
1868899189181,5cyclictest0-21swapper/1309:25:005
1871499188180,5cyclictest0-21swapper/3609:24:5930
1871499188180,5cyclictest0-21swapper/3609:24:5930
1871299187177,8cyclictest0-21swapper/3410:21:2128
1871299187177,8cyclictest0-21swapper/3410:21:2128
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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