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2025-11-26 - 23:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Nov 26, 2025 13:01:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
572299263230,14cyclictest0-21swapper/908:30:1839
572299263230,14cyclictest0-21swapper/908:30:1839
575499258255,2cyclictest0-21swapper/3612:22:0830
575499258255,2cyclictest0-21swapper/3612:22:0830
5724992581,143cyclictest0-21swapper/1107:20:203
5724992581,143cyclictest0-21swapper/1107:20:203
572799253234,11cyclictest10767-21inotify_reader07:35:185
572799253234,11cyclictest10767-21inotify_reader07:35:185
574099244223,5cyclictest4907-21CPU16
574099244223,5cyclictest4907-21CPU16
572799239201,22cyclictest15985-21CPU5
572799239201,22cyclictest15985-21CPU5
575299228202,12cyclictest0-21swapper/3407:15:0428
572299227209,3cyclictest0-21swapper/907:30:1939
572299227209,3cyclictest0-21swapper/907:30:1839
57579921964,140cyclictest32988-21inotify_reader11:15:1932
57579921964,140cyclictest32988-21inotify_reader11:15:1932
5751992192,5cyclictest4912-21CPU27
5751992192,5cyclictest4912-21CPU27
5751992192,5cyclictest4912-21CPU27
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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