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2026-08-25 - 06:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Aug 25, 2026 01:02:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5341992491,244cyclictest4398-21qemu-system-x8621:17:136
5341992491,244cyclictest4398-21qemu-system-x8621:17:136
5341992471,240cyclictest0-21swapper/1420:15:226
5341992471,240cyclictest0-21swapper/1420:15:226
5341992461,241cyclictest0-21swapper/1422:00:166
5341992461,241cyclictest0-21swapper/1422:00:166
5341992461,241cyclictest0-21swapper/1422:00:166
5341992421,238cyclictest0-21swapper/1421:28:456
5341992421,238cyclictest0-21swapper/1421:28:456
5341992401,236cyclictest0-21swapper/1423:16:256
5341992401,236cyclictest0-21swapper/1423:16:256
5341992400,237cyclictest38488-21sshd23:40:196
5341992400,237cyclictest38488-21sshd23:40:196
5341992400,236cyclictest19105-21sshd21:41:526
5341992400,236cyclictest19105-21sshd21:41:526
5341992391,236cyclictest0-21swapper/1421:45:206
5341992391,236cyclictest0-21swapper/1421:45:206
5341992382,230cyclictest3548-21CPU6
5341992382,230cyclictest3548-21CPU6
5341992381,234cyclictest0-21swapper/1400:04:446
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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