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2026-08-10 - 07:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Aug 10, 2026 01:02:25)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1638499242239,2cyclictest0-21swapper/2023:25:1613
1638499242239,2cyclictest0-21swapper/2023:25:1613
1638499242239,2cyclictest0-21swapper/2023:25:1613
1639599225215,8cyclictest0-21swapper/2921:10:2222
1639599225215,8cyclictest0-21swapper/2921:10:2222
1639599225215,8cyclictest0-21swapper/2921:10:2222
1639599224209,11cyclictest12272-21perl21:30:2222
1639599224209,11cyclictest12272-21perl21:30:2222
1639599221216,3cyclictest40705-21sshd00:02:0122
1639599221216,3cyclictest40705-21sshd00:02:0022
1639599221207,10cyclictest585-21cpuspeed_turbos19:55:1522
1639599221207,10cyclictest585-21cpuspeed_turbos19:55:1422
1639899217195,11cyclictest0-21swapper/3221:15:3526
1639899217195,11cyclictest0-21swapper/3221:15:3526
1639899217195,11cyclictest0-21swapper/3221:15:3426
1639599215208,5cyclictest17482-21nfsd22:50:1822
1639599215208,5cyclictest17482-21nfsd22:50:1722
1639599215207,6cyclictest0-21swapper/2923:30:3322
1639599215207,6cyclictest0-21swapper/2923:30:3322
1639599215207,3cyclictest4407-21CPU22
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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