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2026-09-25 - 00:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Sep 24, 2026 13:02:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3981199216209,3cyclictest3546-21CPU33
3981199212205,5cyclictest0-21swapper/3910:39:4033
3981199212205,5cyclictest0-21swapper/3910:39:4033
3981199210204,4cyclictest0-21swapper/3911:01:3133
3981199210204,4cyclictest0-21swapper/3911:01:3133
3981199210204,4cyclictest0-21swapper/3911:01:3133
3981199208203,4cyclictest0-21swapper/3907:15:5533
3981199208198,8cyclictest1367-21dbus-daemon10:32:1733
3981199208198,8cyclictest1367-21dbus-daemon10:32:1733
3981199205197,5cyclictest0-21swapper/3911:10:4633
3981199205197,5cyclictest0-21swapper/3911:10:4533
3981199205197,5cyclictest0-21swapper/3911:10:4533
397849920212,176cyclictest4953-21timerwakeupswit07:11:269
397849920212,176cyclictest4953-21timerwakeupswit07:11:269
3977499202193,6cyclictest0-21swapper/812:12:4038
3977499202193,6cyclictest0-21swapper/812:12:3938
3981199201196,4cyclictest0-21swapper/3911:06:2233
3981199201196,4cyclictest0-21swapper/3911:06:2233
3981199201196,4cyclictest0-21swapper/3911:06:2233
3981199199194,3cyclictest30467-21sshd10:15:5833
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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