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2026-06-15 - 19:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Jun 15, 2026 13:03:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3502599214205,6cyclictest0-21swapper/811:25:5038
3502599214205,6cyclictest0-21swapper/811:25:5038
3502599214205,6cyclictest0-21swapper/811:25:5038
3505099213198,11cyclictest0-21swapper/2911:55:1422
3505099213198,11cyclictest0-21swapper/2911:55:1422
3505099210203,5cyclictest0-21swapper/2907:25:0122
3505099210203,5cyclictest0-21swapper/2907:25:0122
3501599207202,3cyclictest0-21swapper/012:15:280
3501599207202,3cyclictest0-21swapper/012:15:280
3501599207202,3cyclictest0-21swapper/012:15:280
3505099204197,5cyclictest0-21swapper/2907:15:1822
3505099204197,5cyclictest0-21swapper/2907:15:1722
3505099202193,6cyclictest0-21swapper/2912:06:4522
3505099202193,6cyclictest0-21swapper/2912:06:4422
3505099200195,4cyclictest0-21swapper/2911:42:4622
3505099200195,4cyclictest0-21swapper/2911:42:4522
3505099200195,4cyclictest0-21swapper/2911:42:4522
3505099198186,9cyclictest0-21swapper/2910:32:0022
3505099198186,9cyclictest0-21swapper/2910:32:0022
3505099197186,9cyclictest13169-21cstates07:50:1722
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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