You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-27 - 22:54
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Nov 27, 2025 13:02:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1851799239203,28cyclictest0-21swapper/1110:55:193
1851799239203,28cyclictest0-21swapper/1110:55:193
1851799239203,28cyclictest0-21swapper/1110:55:193
185629923598,113cyclictest0-21swapper/3911:40:1833
185629923598,113cyclictest0-21swapper/3911:40:1833
185629923598,113cyclictest0-21swapper/3911:40:1833
1851799232197,14cyclictest0-21swapper/1109:55:183
1851799232197,14cyclictest0-21swapper/1109:55:183
1851799232197,14cyclictest0-21swapper/1109:55:183
18506992203,81cyclictest34119-21TaskSchedulerSi08:00:1738
18506992203,81cyclictest34119-21TaskSchedulerSi08:00:1638
1851799217182,16cyclictest0-21swapper/1111:00:193
1851799217182,16cyclictest0-21swapper/1111:00:193
1851799217182,16cyclictest0-21swapper/1111:00:193
1851799215183,6cyclictest1081rcuc/1110:50:183
1851799215183,6cyclictest1081rcuc/1110:50:183
1851799214191,6cyclictest30122-21TaskSchedulerSi09:00:183
1851799214191,6cyclictest30122-21TaskSchedulerSi09:00:183
1851799213174,19cyclictest15979-21CPU3
1851799213174,19cyclictest15979-21CPU3
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional