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2026-07-09 - 16:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Jul 09, 2026 13:02:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2961299248243,3cyclictest0-21swapper/1611:15:008
2961299248243,3cyclictest0-21swapper/1611:15:008
2960099217209,4cyclictest3548-21CPU36
2960099217209,4cyclictest3548-21CPU36
2960099216211,3cyclictest0-21swapper/612:31:2536
2960099216211,3cyclictest0-21swapper/612:31:2436
2960099216211,3cyclictest0-21swapper/612:31:2436
2960899215211,2cyclictest0-21swapper/1311:15:245
2960899215211,2cyclictest0-21swapper/1311:15:235
2962499211205,4cyclictest0-21swapper/2707:40:5820
2962499211205,4cyclictest0-21swapper/2707:40:5720
2961499210194,12cyclictest0-21swapper/1711:00:129
2961499210194,12cyclictest0-21swapper/1711:00:129
2962099207200,5cyclictest20183-21sshd12:21:1816
2962099207200,5cyclictest20183-21sshd12:21:1716
2961599207199,5cyclictest0-21swapper/1811:25:1510
2961599207199,5cyclictest0-21swapper/1811:25:1510
2961499205198,5cyclictest0-21swapper/1709:20:359
2961499205198,5cyclictest0-21swapper/1709:20:349
2961499205198,5cyclictest0-21swapper/1709:20:349
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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