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2025-12-07 - 14:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Dec 07, 2025 13:00:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1495099284211,20cyclictest0-21swapper/2309:30:2116
1495099284211,20cyclictest0-21swapper/2309:30:2116
1495099284211,20cyclictest0-21swapper/2309:30:2116
1495099238212,12cyclictest0-21swapper/2308:35:2016
1495099238212,12cyclictest0-21swapper/2308:35:2016
1496399229211,7cyclictest12297-21TaskSchedulerSi10:00:2024
1496399229211,7cyclictest12297-21TaskSchedulerSi10:00:2024
1496399229211,7cyclictest12297-21TaskSchedulerSi10:00:2024
1495099228203,10cyclictest0-21swapper/2309:55:2116
1495099228203,10cyclictest0-21swapper/2309:55:2116
1495099224197,16cyclictest25200-21inotify_reader07:40:1816
1495099224197,16cyclictest25200-21inotify_reader07:40:1816
1495099224197,16cyclictest25200-21inotify_reader07:40:1816
1495099223196,17cyclictest7598-21TaskSchedulerSi08:50:1916
1495099223196,17cyclictest7598-21TaskSchedulerSi08:50:1916
1498499222113,102cyclictest0-21swapper/3910:45:2033
1498499222113,102cyclictest0-21swapper/3910:45:2033
1498499222113,102cyclictest0-21swapper/3910:45:1933
14961992204,209cyclictest15984-21CPU22
14961992204,209cyclictest15984-21CPU22
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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