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2025-12-03 - 13:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Dec 03, 2025 01:00:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3738899279255,4cyclictest0-21swapper/722:00:1937
3738899279255,4cyclictest0-21swapper/722:00:1937
3740599275269,3cyclictest0-21swapper/1523:03:567
3740599275269,3cyclictest0-21swapper/1523:03:567
3738899268240,5cyclictest4910-21CPU37
3738899268240,5cyclictest4910-21CPU37
3738899257235,12cyclictest0-21swapper/720:25:2037
3738899257235,12cyclictest0-21swapper/720:25:2037
3742699237136,80cyclictest0-21swapper/2722:05:1820
3742699237136,80cyclictest0-21swapper/2722:05:1720
3738399235218,3cyclictest45-21ksoftirqd/322:25:1923
3738399235218,3cyclictest45-21ksoftirqd/322:25:1923
3738899233210,4cyclictest0-21swapper/720:45:2137
3738899233210,4cyclictest0-21swapper/720:45:2137
37378992241,75cyclictest0-21swapper/019:15:190
37378992241,75cyclictest0-21swapper/019:15:190
373939921721,170cyclictest4910-21CPU2
373939921721,170cyclictest4910-21CPU2
37432992101,192cyclictest0-21swapper/2923:40:1922
37432992101,192cyclictest0-21swapper/2923:40:1822
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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