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2026-07-17 - 18:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Jul 17, 2026 13:02:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2838199190185,4cyclictest0-21swapper/1212:02:434
2838199190185,4cyclictest0-21swapper/1212:02:434
2838199190185,4cyclictest0-21swapper/1212:02:434
2838199190185,4cyclictest0-21swapper/1212:02:424
2838199189183,5cyclictest0-21swapper/1209:22:414
2838199189183,5cyclictest0-21swapper/1209:22:404
2841099188179,6cyclictest0-21swapper/3611:43:1930
2841099188179,6cyclictest0-21swapper/3611:43:1930
2841099188179,6cyclictest0-21swapper/3611:43:1830
2838199185175,8cyclictest0-21swapper/1210:07:584
2838199185175,8cyclictest0-21swapper/1210:07:584
2838199185175,8cyclictest0-21swapper/1210:07:574
2838199184179,4cyclictest0-21swapper/1211:55:014
2838199184179,4cyclictest0-21swapper/1211:55:014
2838199184179,4cyclictest0-21swapper/1211:55:004
2838199183177,4cyclictest0-21swapper/1208:28:274
2838199183177,4cyclictest0-21swapper/1208:28:264
2838199183176,6cyclictest0-21swapper/1209:55:414
2838199183176,6cyclictest0-21swapper/1209:55:404
2838199183176,6cyclictest0-21swapper/1209:55:404
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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