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2026-09-02 - 22:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Sep 02, 2026 13:03:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1133499294290,2cyclictest0-21swapper/209:10:1512
1133499294290,2cyclictest0-21swapper/209:10:1412
1135499224184,20cyclictest0-21swapper/2109:46:1814
1135499224184,20cyclictest0-21swapper/2109:46:1714
1135499224184,20cyclictest0-21swapper/2109:46:1714
1134499224215,5cyclictest3546-21CPU4
1134499224215,5cyclictest3546-21CPU4
1134699223218,4cyclictest0-21swapper/1412:22:366
1134699223218,4cyclictest0-21swapper/1412:22:356
1134699223218,4cyclictest0-21swapper/1412:22:356
1134499219205,11cyclictest0-21swapper/1209:40:004
1134499219205,11cyclictest0-21swapper/1209:40:004
1134499218211,5cyclictest0-21swapper/1211:45:114
1134499218211,5cyclictest0-21swapper/1211:45:114
1134499218211,5cyclictest0-21swapper/1211:45:104
1133099218209,7cyclictest0-21swapper/011:21:330
1133099218209,7cyclictest0-21swapper/011:21:330
1133099218209,7cyclictest0-21swapper/011:21:330
1133099218208,6cyclictest0-21swapper/009:40:080
1133099218208,6cyclictest0-21swapper/009:40:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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