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2026-02-06 - 11:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Feb 06, 2026 01:03:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2203699220212,7cyclictest0-21swapper/423:45:2634
2203699220212,7cyclictest0-21swapper/423:45:2634
2206499216207,7cyclictest0-21swapper/2719:17:2020
2206499216207,7cyclictest0-21swapper/2719:17:2020
2206999213207,4cyclictest0-21swapper/3120:05:2025
2203699212204,6cyclictest11483-21kworker/u81:523:59:0934
2203699212204,6cyclictest11483-21kworker/u81:523:59:0934
2203699212204,6cyclictest11483-21kworker/u81:523:59:0934
2203699211205,4cyclictest0-21swapper/423:40:1434
2203699211205,4cyclictest0-21swapper/423:40:1434
2203699210205,4cyclictest0-21swapper/400:12:2934
2203699210205,4cyclictest0-21swapper/400:12:2834
2206999208203,4cyclictest0-21swapper/3120:10:2825
2206999208203,4cyclictest0-21swapper/3120:10:2825
2203699208202,4cyclictest0-21swapper/400:01:1834
2203699208202,4cyclictest0-21swapper/400:01:1834
2203699204196,5cyclictest0-21swapper/422:54:0734
2203699204196,5cyclictest0-21swapper/422:54:0734
2203699204196,5cyclictest0-21swapper/422:54:0734
2203699204193,6cyclictest2454-21CPU34
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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