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2026-07-01 - 18:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Jul 01, 2026 13:02:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1146799229218,8cyclictest20279-21systemd11:45:195
1146799229218,8cyclictest20279-21systemd11:45:195
1146799204196,6cyclictest0-21swapper/1309:42:345
1146799204196,6cyclictest0-21swapper/1309:42:345
1146799204196,6cyclictest0-21swapper/1309:42:345
1146799202196,4cyclictest0-21swapper/1310:17:425
1146799202196,4cyclictest0-21swapper/1310:17:415
1146799199192,5cyclictest0-21swapper/1310:10:355
1146799199192,5cyclictest0-21swapper/1310:10:355
1146799199192,5cyclictest0-21swapper/1310:10:355
1146999196187,6cyclictest0-21swapper/1511:00:127
1146999196187,6cyclictest0-21swapper/1511:00:117
1146799196189,5cyclictest0-21swapper/1311:38:355
1146799196189,5cyclictest0-21swapper/1311:38:355
1146799193185,6cyclictest0-21swapper/1312:20:155
1146799193185,6cyclictest0-21swapper/1312:20:155
1146799193185,6cyclictest0-21swapper/1311:30:015
1146799193185,6cyclictest0-21swapper/1311:30:005
1146799190184,4cyclictest0-21swapper/1311:54:295
1146799190184,4cyclictest0-21swapper/1311:54:295
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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