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2026-04-15 - 20:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Apr 15, 2026 13:02:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
148899214208,3cyclictest0-21swapper/1609:10:208
148899214208,3cyclictest0-21swapper/1609:10:208
149199201196,3cyclictest0-21swapper/1908:05:0111
149099198190,6cyclictest0-21swapper/1811:39:3410
149099198190,6cyclictest0-21swapper/1811:39:3310
149099197192,4cyclictest0-21swapper/1811:56:0810
149099197192,4cyclictest0-21swapper/1811:56:0810
149099197192,4cyclictest0-21swapper/1811:56:0810
149099196188,6cyclictest0-21swapper/1809:47:1410
149099196188,6cyclictest0-21swapper/1809:47:1410
149099196188,6cyclictest0-21swapper/1809:47:1410
149099196187,7cyclictest0-21swapper/1810:30:1110
149099196187,7cyclictest0-21swapper/1810:30:1110
149099195185,5cyclictest2462-21CPU10
149099195185,5cyclictest2462-21CPU10
149099195185,5cyclictest2462-21CPU10
149099195184,6cyclictest3548-21CPU10
149099195184,6cyclictest3548-21CPU10
149099194187,4cyclictest0-21swapper/1809:11:1510
149099194187,4cyclictest0-21swapper/1809:11:1510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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