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2026-09-18 - 17:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Sep 18, 2026 13:02:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4016999211205,4cyclictest0-21swapper/410:05:0534
4016999211205,4cyclictest0-21swapper/410:05:0534
4016999211205,4cyclictest0-21swapper/410:05:0534
4016999205188,15cyclictest0-21swapper/410:06:3734
4016999205188,15cyclictest0-21swapper/410:06:3734
4016999205188,15cyclictest0-21swapper/410:06:3634
4016999202191,9cyclictest0-21swapper/410:30:1934
4016999202191,9cyclictest0-21swapper/410:30:1934
4016999200191,6cyclictest13630-21sshd10:22:4334
4016999200191,6cyclictest13630-21sshd10:22:4334
4016999200191,6cyclictest13630-21sshd10:22:4334
4019099199141,47cyclictest0-21swapper/2112:01:2514
4019099199141,47cyclictest0-21swapper/2112:01:2514
4020099198178,3cyclictest171rcu_preempt09:35:4422
4020099198178,3cyclictest171rcu_preempt09:35:4322
4016999198190,6cyclictest0-21swapper/410:29:2734
4016999198190,6cyclictest0-21swapper/410:29:2734
4016999198190,6cyclictest0-21swapper/410:29:2734
4016999197183,12cyclictest24316-21sshd10:12:1534
4016999197183,12cyclictest24316-21sshd10:12:1434
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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