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2026-01-18 - 01:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Jan 17, 2026 13:01:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2214799250246,2cyclictest0-21swapper/3810:20:1632
2214799250246,2cyclictest0-21swapper/3810:20:1632
2210399221200,11cyclictest0-21swapper/210:32:5812
2210399221200,11cyclictest0-21swapper/210:32:5812
2210399220195,12cyclictest0-21swapper/212:18:3612
2210399220195,12cyclictest0-21swapper/212:18:3612
2211299219214,3cyclictest0-21swapper/1010:15:192
2211299219214,3cyclictest0-21swapper/1010:15:182
2210399217205,7cyclictest0-21swapper/211:00:0112
2210399217205,7cyclictest0-21swapper/211:00:0112
2210399217205,7cyclictest0-21swapper/211:00:0012
2210399213206,5cyclictest0-21swapper/211:00:1512
2210399213206,5cyclictest0-21swapper/211:00:1512
2210399213206,5cyclictest0-21swapper/211:00:1512
2210399213203,8cyclictest0-21swapper/209:58:0112
2210399213203,8cyclictest0-21swapper/209:58:0112
2210399213203,8cyclictest0-21swapper/209:58:0112
2210399212206,5cyclictest33946-21sshd11:46:5412
2210399212206,5cyclictest33946-21sshd11:46:5312
2210299212171,14cyclictest171rcu_preempt10:35:581
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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