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2026-01-19 - 02:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Jan 19, 2026 00:59:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2936599211187,13cyclictest0-21swapper/2921:57:1722
2936599211187,13cyclictest0-21swapper/2921:57:1722
2934699210204,4cyclictest0-21swapper/1419:45:006
2934699210204,4cyclictest0-21swapper/1419:45:006
2936199203196,5cyclictest0-21swapper/2500:11:4518
2936199203196,5cyclictest0-21swapper/2500:11:4518
2934699203198,3cyclictest0-21swapper/1419:46:126
2934699203198,3cyclictest0-21swapper/1419:46:126
2934699202195,6cyclictest0-21swapper/1420:08:466
2934699199188,9cyclictest0-21swapper/1419:57:196
2933899198181,11cyclictest0-21swapper/621:22:4836
2933899198181,11cyclictest0-21swapper/621:22:4836
2933799197133,60cyclictest3546-21CPU35
2933799197133,60cyclictest3546-21CPU35
2933799197133,60cyclictest3546-21CPU35
2933899194186,5cyclictest0-21swapper/600:37:1036
2933899194186,5cyclictest0-21swapper/600:37:1036
2933899194186,5cyclictest0-21swapper/600:37:1036
2937199193179,7cyclictest0-21swapper/3422:06:5528
2937199193179,7cyclictest0-21swapper/3422:06:5528
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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