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2026-08-30 - 03:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Aug 30, 2026 01:02:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2772992391,235cyclictest1367-21dbus-daemon00:29:4939
2772992391,235cyclictest1367-21dbus-daemon00:29:4839
2772992371,232cyclictest1430-21polkitd00:03:2339
2772992371,232cyclictest1430-21polkitd00:03:2339
2772992371,232cyclictest0-21swapper/900:34:3539
2772992371,232cyclictest0-21swapper/900:34:3539
2772992362,230cyclictest3543-21CPU39
2772992362,230cyclictest3543-21CPU39
2772992350,232cyclictest9502-21sshd00:06:1139
2772992350,232cyclictest9502-21sshd00:06:1039
2772992350,232cyclictest9502-21sshd00:06:1039
2772992320,229cyclictest0-21swapper/900:36:5739
2772992320,229cyclictest0-21swapper/900:36:5639
276299232221,8cyclictest2454-21CPU1
276299232221,8cyclictest2454-21CPU1
2772992311,226cyclictest0-21swapper/900:23:1239
2772992311,226cyclictest0-21swapper/900:23:1139
279699230225,3cyclictest0-21swapper/2922:35:1522
279699230225,3cyclictest0-21swapper/2922:35:1522
2772992301,227cyclictest0-21swapper/923:37:3839
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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