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2026-07-21 - 05:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Jul 21, 2026 01:01:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
940999258227,4cyclictest171rcu_preempt00:34:2438
940999258227,4cyclictest171rcu_preempt00:34:2338
942999208193,10cyclictest0-21swapper/2422:40:5117
942999208193,10cyclictest0-21swapper/2422:40:5117
942999201193,6cyclictest0-21swapper/2421:47:3317
942999201193,6cyclictest0-21swapper/2421:47:3217
940399197193,2cyclictest0-21swapper/323:50:1623
940399197193,2cyclictest0-21swapper/323:50:1623
94079919629,163cyclictest0-21swapper/600:00:1936
94079919629,163cyclictest0-21swapper/600:00:1936
944699193153,30cyclictest0-21swapper/3800:11:4632
944699193153,30cyclictest0-21swapper/3800:11:4532
942999192185,4cyclictest2456-21CPU17
942999192185,4cyclictest2456-21CPU17
942999189181,6cyclictest0-21swapper/2423:20:0817
942999189181,6cyclictest0-21swapper/2423:20:0717
942999189181,5cyclictest4407-21CPU17
942999189181,5cyclictest4407-21CPU17
940999189179,7cyclictest0-21swapper/821:54:2538
940999189179,7cyclictest0-21swapper/821:54:2538
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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