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2026-08-27 - 10:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Aug 27, 2026 01:02:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30972992621,249cyclictest0-21swapper/3821:49:4732
30972992621,249cyclictest0-21swapper/3821:49:4732
30972992451,236cyclictest0-21swapper/3823:51:1532
30972992451,236cyclictest0-21swapper/3823:51:1532
30972992451,236cyclictest0-21swapper/3823:51:1532
30972992420,233cyclictest0-21swapper/3822:17:0232
30972992420,233cyclictest0-21swapper/3822:17:0232
30972992411,230cyclictest0-21swapper/3820:20:2332
30972992411,225cyclictest0-21swapper/3821:55:1232
30972992411,225cyclictest0-21swapper/3821:55:1232
30972992390,230cyclictest0-21swapper/3800:06:1932
30972992390,230cyclictest0-21swapper/3800:06:1932
30972992380,235cyclictest14409-21cpuspeed_turbos19:25:1232
30972992370,226cyclictest0-21swapper/3820:55:2832
30972992370,226cyclictest0-21swapper/3820:55:2832
30972992361,226cyclictest0-21swapper/3821:12:3632
30972992361,226cyclictest0-21swapper/3821:12:3632
30972992340,225cyclictest0-21swapper/3823:23:0132
30972992340,225cyclictest0-21swapper/3823:23:0132
30972992331,228cyclictest25903-21kill00:02:3132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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