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2026-07-11 - 20:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Jul 11, 2026 13:02:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1528299248244,2cyclictest0-21swapper/3412:35:1528
1528299248244,2cyclictest0-21swapper/3412:35:1528
1528299248244,2cyclictest0-21swapper/3412:35:1528
1527499207199,4cyclictest3547-21CPU19
1527499207199,4cyclictest3547-21CPU19
1527499207199,4cyclictest3547-21CPU19
1526099205197,5cyclictest2461-21CPU7
1526099205197,5cyclictest2461-21CPU7
1526099205197,5cyclictest2461-21CPU7
1526599202197,3cyclictest0-21swapper/1912:30:1311
1526599202197,3cyclictest0-21swapper/1912:30:1311
1524999199191,3cyclictest3548-21CPU35
1524999199191,3cyclictest3548-21CPU35
1524999199191,3cyclictest3548-21CPU35
1524999196162,23cyclictest171rcu_preempt12:24:0935
1524999196162,23cyclictest171rcu_preempt12:24:0835
1524999196162,23cyclictest171rcu_preempt12:24:0835
1524399194189,3cyclictest29858-21ls07:19:591
1524399194184,7cyclictest0-21swapper/111:20:151
1524399194184,7cyclictest0-21swapper/111:20:151
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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