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2026-07-08 - 16:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Jul 08, 2026 13:02:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3036899200194,3cyclictest2466-21CPU31
3036899200194,3cyclictest2466-21CPU31
3036899198188,6cyclictest0-21swapper/3712:30:2031
3036899198188,6cyclictest0-21swapper/3712:30:2031
3036899198188,6cyclictest0-21swapper/3712:30:2031
3033199194174,18cyclictest0-21swapper/509:40:3235
3033199194174,18cyclictest0-21swapper/509:40:3235
3033099191179,4cyclictest0-21swapper/410:52:1534
3033099191179,4cyclictest0-21swapper/410:52:1534
3033099191179,4cyclictest0-21swapper/410:52:1534
3036899190183,5cyclictest0-21swapper/3711:15:3631
3036899190183,5cyclictest0-21swapper/3711:15:3631
3036899186178,6cyclictest0-21swapper/3712:20:0331
3036899186178,6cyclictest0-21swapper/3712:20:0231
3036899186178,6cyclictest0-21swapper/3712:20:0231
3036899185176,7cyclictest0-21swapper/3711:05:1531
3036899185176,7cyclictest0-21swapper/3711:05:1531
3036899185176,7cyclictest0-21swapper/3711:05:1531
3033399183173,8cyclictest0-21swapper/709:40:5637
3033399183173,8cyclictest0-21swapper/709:40:5637
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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