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2026-08-04 - 10:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Aug 04, 2026 01:01:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3745099270262,6cyclictest999-21kworker/u81:1+events_unbound00:08:5836
3745099270262,6cyclictest999-21kworker/u81:1+events_unbound00:08:5836
3745599223217,4cyclictest0-21swapper/1023:20:432
3745599223217,4cyclictest0-21swapper/1023:20:432
3745599223217,4cyclictest0-21swapper/1023:20:432
3744699213205,6cyclictest0-21swapper/221:21:2112
3744699213205,6cyclictest0-21swapper/221:21:2112
3745599211204,3cyclictest3609-21CPU2
3745599211204,3cyclictest3609-21CPU2
3745299203191,8cyclictest21160-21sshd22:25:2038
3745299203191,8cyclictest21160-21sshd22:25:2038
3744399203194,7cyclictest0-21swapper/022:38:250
3744399203194,7cyclictest0-21swapper/022:38:250
3744699202196,4cyclictest0-21swapper/219:31:0212
3744699202196,4cyclictest0-21swapper/219:31:0212
3744699202188,4cyclictest37358-21CPU12
3744699202188,4cyclictest37358-21CPU12
3744699202188,4cyclictest37358-21CPU12
3747799201115,83cyclictest0-21swapper/3023:22:1324
3747799201115,83cyclictest0-21swapper/3023:22:1324
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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