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2025-12-02 - 12:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Dec 02, 2025 01:00:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2214799309304,3cyclictest0-21swapper/523:16:2635
2214799309304,3cyclictest0-21swapper/523:16:2635
2216899244217,12cyclictest0-21swapper/2623:35:2119
2216899244217,12cyclictest0-21swapper/2623:35:2119
2216899244217,12cyclictest0-21swapper/2623:35:2119
2216099234213,3cyclictest0-21swapper/1821:15:1810
2216099234213,3cyclictest0-21swapper/1821:15:1810
2216099226201,4cyclictest15830-21TaskSchedulerSi00:10:2410
2216099226201,4cyclictest15830-21TaskSchedulerSi00:10:2410
2218199220216,2cyclictest0-21swapper/3523:36:5929
2218199220216,2cyclictest0-21swapper/3523:36:5929
2218199220216,2cyclictest0-21swapper/3523:36:5829
2216899220193,10cyclictest0-21swapper/2622:10:1819
2216899220193,10cyclictest0-21swapper/2622:10:1819
2216099210187,5cyclictest26301-21sshd21:25:2210
2216099210187,5cyclictest26301-21sshd21:25:2210
221799920848,154cyclictest2871ktimers/3300:15:2127
221799920848,154cyclictest2871ktimers/3300:15:2127
2216099208192,3cyclictest0-21swapper/1822:35:2110
2216099208192,3cyclictest0-21swapper/1822:35:2110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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