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2026-07-12 - 08:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Jul 12, 2026 01:01:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
630299226218,6cyclictest0-21swapper/3322:41:0327
630299226218,6cyclictest0-21swapper/3322:41:0327
630299226218,6cyclictest0-21swapper/3322:41:0327
630299222212,8cyclictest0-21swapper/3320:01:3427
629999218207,4cyclictest0-21swapper/3020:21:1124
629999218207,4cyclictest0-21swapper/3020:21:1124
628899217207,8cyclictest0-21swapper/2119:25:0114
628899217207,8cyclictest0-21swapper/2119:25:0114
630299212205,5cyclictest0-21swapper/3322:00:2227
630299212205,5cyclictest0-21swapper/3322:00:2227
630299212203,5cyclictest2466-21CPU27
630299212203,5cyclictest2466-21CPU27
630299211204,3cyclictest3541-21CPU27
630299211204,3cyclictest3541-21CPU27
630299210201,5cyclictest0-21swapper/3321:37:1827
630299210201,5cyclictest0-21swapper/3321:37:1827
630299209198,9cyclictest0-21swapper/3320:17:2127
630299209198,9cyclictest0-21swapper/3320:17:2127
630299208203,2cyclictest2286-21ntp_states22:25:3027
630299208203,2cyclictest2286-21ntp_states22:25:3027
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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