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2026-09-04 - 13:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Sep 04, 2026 01:01:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1429299241234,5cyclictest37759-21expr22:00:1527
1429299241234,5cyclictest37759-21expr22:00:1427
1429299234228,4cyclictest0-21swapper/3322:30:2627
1429299234228,4cyclictest0-21swapper/3322:30:2627
1429299234228,4cyclictest0-21swapper/3322:30:2527
1429299230208,17cyclictest0-21swapper/3323:10:2527
1429299230208,17cyclictest0-21swapper/3323:10:2427
1429299230208,17cyclictest0-21swapper/3323:10:2427
1429299228219,5cyclictest3545-21CPU27
1429299228219,5cyclictest3545-21CPU27
1429299227206,11cyclictest37356-21CPU27
1429299227206,11cyclictest37356-21CPU27
1429299222211,8cyclictest4132-21sshd23:35:1827
1429299222211,8cyclictest4132-21sshd23:35:1827
1429299220210,8cyclictest0-21swapper/3321:40:5827
1429299220210,8cyclictest0-21swapper/3321:40:5827
1429299216196,17cyclictest0-21swapper/3322:21:2527
1429299216196,17cyclictest0-21swapper/3322:21:2527
1429299215203,7cyclictest2462-21CPU27
1429299215203,7cyclictest2462-21CPU27
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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