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2026-02-02 - 09:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Feb 02, 2026 01:00:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2149399230224,3cyclictest0-21swapper/2622:30:1119
2149399230224,3cyclictest0-21swapper/2622:30:1119
2150599229214,13cyclictest0-21swapper/3721:26:2031
2150599229214,13cyclictest0-21swapper/3721:26:2031
2150599229214,13cyclictest0-21swapper/3721:26:2031
2149399226216,8cyclictest25005-21gdbus22:20:0119
2149399226216,8cyclictest25005-21gdbus22:20:0119
2149399226216,8cyclictest25005-21gdbus22:20:0119
2149399223209,8cyclictest3610-21CPU19
2149399223209,8cyclictest3610-21CPU19
2149399223209,8cyclictest3610-21CPU19
2149399222215,5cyclictest0-21swapper/2622:29:0419
2149399222215,5cyclictest0-21swapper/2622:29:0419
2149399222215,5cyclictest0-21swapper/2622:29:0419
2149399220209,9cyclictest0-21swapper/2619:40:1519
2149399220209,9cyclictest0-21swapper/2619:40:1519
2149399218213,4cyclictest0-21swapper/2622:36:0919
2149399218213,4cyclictest0-21swapper/2622:36:0919
2149399216210,4cyclictest0-21swapper/2619:19:1919
2149399216210,4cyclictest0-21swapper/2619:19:1919
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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