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2025-11-15 - 23:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Nov 15, 2025 13:01:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
80829927236,209cyclictest10586-21tune2fs12:20:2011
80829927236,209cyclictest10586-21tune2fs12:20:1911
80829927236,209cyclictest10586-21tune2fs12:20:1911
8092992291,4cyclictest15980-21CPU22
8092992291,4cyclictest15980-21CPU22
806799225221,2cyclictest0-21swapper/711:35:2537
806799225221,2cyclictest0-21swapper/711:35:2537
806799225221,2cyclictest0-21swapper/711:35:2537
806299218204,11cyclictest0-21swapper/210:00:0112
806299218204,11cyclictest0-21swapper/210:00:0112
806299218204,11cyclictest0-21swapper/210:00:0112
80829921747,164cyclictest4908-21CPU11
80829921747,164cyclictest4908-21CPU11
80829921432,179cyclictest0-21swapper/1909:38:3611
80829921432,179cyclictest0-21swapper/1909:38:3611
80829921432,179cyclictest0-21swapper/1909:38:3611
80989920732,33cyclictest0-21swapper/3510:15:2029
80989920732,33cyclictest0-21swapper/3510:15:1929
80829920627,174cyclictest0-21swapper/1909:42:1211
80829920627,174cyclictest0-21swapper/1909:42:1211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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