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2026-06-30 - 16:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Jun 30, 2026 13:02:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3590799215192,11cyclictest0-21swapper/1409:14:096
3590799215192,11cyclictest0-21swapper/1409:14:096
3590799197183,12cyclictest0-21swapper/1411:01:276
3590799197183,12cyclictest0-21swapper/1411:01:276
3590799197183,12cyclictest0-21swapper/1411:01:276
3590799194181,11cyclictest0-21swapper/1412:30:396
3590799194181,11cyclictest0-21swapper/1412:30:396
3590799194181,11cyclictest0-21swapper/1412:30:396
3589599191183,3cyclictest0-21swapper/409:37:3234
3589599191183,3cyclictest0-21swapper/409:37:3234
359079918936,143cyclictest0-21swapper/1412:35:156
359079918936,143cyclictest0-21swapper/1412:35:156
3589299189139,46cyclictest0-21swapper/212:28:3012
3589299189139,46cyclictest0-21swapper/212:28:3012
3592799188183,2cyclictest0-21swapper/3311:41:3927
3592799188183,2cyclictest0-21swapper/3311:41:3927
3592799187173,11cyclictest0-21swapper/3312:38:4227
3592799187173,11cyclictest0-21swapper/3312:38:4227
35924991878,88cyclictest0-21swapper/3011:39:1824
35924991878,88cyclictest0-21swapper/3011:39:1824
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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