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2026-05-04 - 08:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon May 04, 2026 01:01:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1133499209199,8cyclictest0-21swapper/2300:00:0116
1133499209199,8cyclictest0-21swapper/2300:00:0116
1133499209199,8cyclictest0-21swapper/2300:00:0116
1133499208201,6cyclictest0-21swapper/2322:00:3716
1133499208201,6cyclictest0-21swapper/2322:00:3616
1133499207201,4cyclictest0-21swapper/2321:40:1516
1133499207201,4cyclictest0-21swapper/2321:40:1516
1133499204194,6cyclictest2454-21CPU16
1133499204194,6cyclictest2454-21CPU16
1133499204194,6cyclictest2454-21CPU16
1133499198187,6cyclictest0-21swapper/2300:35:4616
1133499198187,6cyclictest0-21swapper/2300:35:4616
1133499198187,6cyclictest0-21swapper/2300:35:4516
1131699198128,66cyclictest3543-21CPU37
1131699198128,66cyclictest3543-21CPU37
1133499197189,5cyclictest0-21swapper/2321:25:2016
1133499197189,5cyclictest0-21swapper/2321:25:2016
1133499196174,17cyclictest37346-21qemu-system-x8623:37:1416
1133499196174,17cyclictest37346-21qemu-system-x8623:37:1416
1133499195187,3cyclictest37264-21CPU16
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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