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2026-05-22 - 09:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri May 22, 2026 01:01:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3809099205193,9cyclictest0-21swapper/120:40:051
3810199199191,5cyclictest0-21swapper/1021:45:542
3810199199191,5cyclictest0-21swapper/1021:45:542
3810199199191,5cyclictest0-21swapper/1021:45:542
3812799197189,6cyclictest0-21swapper/3221:53:3526
3812799197189,6cyclictest0-21swapper/3221:53:3426
3812499197190,5cyclictest0-21swapper/2921:43:1622
3812499197190,5cyclictest0-21swapper/2921:43:1522
3811299197192,3cyclictest0-21swapper/2122:28:3314
3811299197192,3cyclictest0-21swapper/2122:28:3314
3809299197189,5cyclictest2466-21CPU23
3809299197189,5cyclictest2466-21CPU23
381279919670,123cyclictest0-21swapper/3222:50:1126
381279919670,123cyclictest0-21swapper/3222:50:1126
3812499195187,6cyclictest0-21swapper/2921:10:1422
3812499195187,6cyclictest0-21swapper/2921:10:1422
3812499195187,6cyclictest0-21swapper/2921:10:1422
3812499195141,51cyclictest37354-21CPU22
3812499195141,51cyclictest37354-21CPU22
3812799194189,4cyclictest0-21swapper/3221:49:4426
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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