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2026-05-12 - 04:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue May 12, 2026 01:01:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1739399217202,11cyclictest0-21swapper/1420:05:156
1739399217202,11cyclictest0-21swapper/1420:05:156
1739299217208,6cyclictest0-21swapper/1320:15:015
1739299217208,6cyclictest0-21swapper/1320:15:015
1738799217209,3cyclictest3542-21CPU2
1738799217209,3cyclictest3542-21CPU2
1737399215209,3cyclictest0-21swapper/023:20:110
1737399215209,3cyclictest0-21swapper/023:20:110
1740099214210,2cyclictest0-21swapper/1819:35:1710
1740099214210,2cyclictest0-21swapper/1819:35:1710
1737499213202,8cyclictest22050-21cstates19:40:151
1737499213202,8cyclictest22050-21cstates19:40:151
1739399212205,5cyclictest0-21swapper/1400:30:216
1739399212205,5cyclictest0-21swapper/1400:30:216
1738799212207,4cyclictest0-21swapper/1019:25:052
1739399211203,6cyclictest26934-21sshd00:01:186
1739399211203,6cyclictest26934-21sshd00:01:186
1739299209201,6cyclictest0-21swapper/1323:17:525
1739299209201,6cyclictest0-21swapper/1323:17:525
1738799209205,2cyclictest0-21swapper/1019:45:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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