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2025-12-01 - 23:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Dec 01, 2025 13:00:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1291699246221,17cyclictest33412-21inotify_reader08:00:1728
1291699246221,17cyclictest33412-21inotify_reader08:00:1728
1287499226205,11cyclictest0-21swapper/207:35:1812
1287499226205,11cyclictest0-21swapper/207:35:1812
1287499224205,9cyclictest10320-21inotify_reader12:30:2012
1287499224205,9cyclictest10320-21inotify_reader12:30:1912
12912992192,206cyclictest16896-21TaskSchedulerSi08:00:1724
12912992192,206cyclictest16896-21TaskSchedulerSi08:00:1724
129109921689,110cyclictest16718-21inotify_reader07:40:1921
129109921689,110cyclictest16718-21inotify_reader07:40:1921
128879920486,102cyclictest15981-21CPU4
128879920486,102cyclictest15981-21CPU4
1287499202193,7cyclictest0-21swapper/211:06:1612
1287499202193,7cyclictest0-21swapper/211:06:1612
1287499202193,7cyclictest0-21swapper/211:06:1612
129129920010,185cyclictest15978-21CPU24
1288999199196,2cyclictest0-21swapper/1412:30:216
1288999199196,2cyclictest0-21swapper/1412:30:206
1291399198189,7cyclictest0-21swapper/3111:23:5025
1291399198189,7cyclictest0-21swapper/3111:23:5025
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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