You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-16 - 13:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Feb 16, 2026 01:01:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1947799214209,3cyclictest0-21swapper/2622:41:1519
1947799214209,3cyclictest0-21swapper/2622:41:1519
1947799213206,5cyclictest19400-21sshd00:19:3719
1947799213206,5cyclictest19400-21sshd00:19:3719
1947299213193,15cyclictest0-21swapper/2120:40:0114
1947299213193,15cyclictest0-21swapper/2120:40:0114
1947799212203,5cyclictest3610-21CPU19
1947799212203,5cyclictest3610-21CPU19
1947799210203,5cyclictest0-21swapper/2622:50:1519
1947799210203,5cyclictest0-21swapper/2622:50:1419
1945999209199,5cyclictest17028-21fschecks_time23:30:193
1945999209199,5cyclictest17028-21fschecks_time23:30:193
1945999209184,13cyclictest0-21swapper/1123:28:223
1945999209184,13cyclictest0-21swapper/1123:28:213
1945899209152,19cyclictest0-21swapper/1000:22:272
1945899209152,19cyclictest0-21swapper/1000:22:272
1945899209152,19cyclictest0-21swapper/1000:22:272
1947799207201,4cyclictest0-21swapper/2622:58:1719
1947799207201,4cyclictest0-21swapper/2622:58:1719
1947799207199,5cyclictest0-21swapper/2600:32:5719
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional