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2026-07-21 - 19:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Jul 21, 2026 13:02:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318999202187,13cyclictest12848-21sshd12:21:064
318999202187,13cyclictest12848-21sshd12:21:054
318999202186,14cyclictest39888-21systemd12:20:054
318999202186,14cyclictest39888-21systemd12:20:044
318999202186,14cyclictest39888-21systemd12:20:044
316799199137,47cyclictest0-21swapper/312:01:3623
316799199137,47cyclictest0-21swapper/312:01:3523
316799196157,28cyclictest0-21swapper/309:47:0823
316799196157,28cyclictest0-21swapper/309:47:0723
320399195131,51cyclictest0-21swapper/2512:18:4718
320399195131,51cyclictest0-21swapper/2512:18:4718
320399195131,51cyclictest0-21swapper/2512:18:4618
318999192173,10cyclictest0-21swapper/1210:59:314
318999192173,10cyclictest0-21swapper/1210:59:314
318999192173,10cyclictest0-21swapper/1210:59:304
318999187179,6cyclictest0-21swapper/1211:40:094
318999187179,6cyclictest0-21swapper/1211:40:094
318999187179,6cyclictest0-21swapper/1211:40:084
318999187172,11cyclictest28888-21systemd11:09:054
318999187172,11cyclictest28888-21systemd11:09:054
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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