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2026-05-31 - 21:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun May 31, 2026 13:02:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1737599211193,8cyclictest0-21swapper/2611:56:5519
1737599211193,8cyclictest0-21swapper/2611:56:5519
173539919990,94cyclictest0-21swapper/611:40:0736
173539919990,94cyclictest0-21swapper/611:40:0736
1737599191176,11cyclictest0-21swapper/2612:17:4819
1737599191176,11cyclictest0-21swapper/2612:17:4819
1737599191176,11cyclictest0-21swapper/2612:17:4819
1737599191167,17cyclictest0-21swapper/2610:10:5219
1737599191167,17cyclictest0-21swapper/2610:10:5219
1737599191166,14cyclictest0-21swapper/2609:15:0619
1737599191166,14cyclictest0-21swapper/2609:15:0619
1737599189156,24cyclictest0-21swapper/2611:05:2119
1737599189156,24cyclictest0-21swapper/2611:05:2119
1737599189156,24cyclictest0-21swapper/2611:05:2119
17362991891,4cyclictest0-21swapper/1410:00:006
17362991891,4cyclictest0-21swapper/1410:00:006
17362991891,4cyclictest0-21swapper/1410:00:006
1737599187153,30cyclictest0-21swapper/2607:30:0119
1737599187153,30cyclictest0-21swapper/2607:30:0119
173669918794,82cyclictest3546-21CPU9
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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