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2026-08-15 - 17:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Aug 15, 2026 13:02:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2728999257239,5cyclictest37263-21CPU26
2728999257239,5cyclictest37263-21CPU26
2728999257239,5cyclictest37263-21CPU26
2726199229222,4cyclictest2466-21CPU37
2726199229222,4cyclictest2466-21CPU37
2727399224218,3cyclictest0-21swapper/1711:05:129
2727399224218,3cyclictest0-21swapper/1711:05:129
2729799219205,7cyclictest0-21swapper/3709:20:1231
2729799219205,7cyclictest0-21swapper/3709:20:1231
2727299214207,5cyclictest0-21swapper/1607:30:228
2726899208201,5cyclictest0-21swapper/1307:35:305
2726899208201,5cyclictest0-21swapper/1307:35:305
2726899207201,4cyclictest0-21swapper/1308:25:155
2726899207201,4cyclictest0-21swapper/1308:25:155
2726899207195,10cyclictest0-21swapper/1308:00:375
2726899207195,10cyclictest0-21swapper/1308:00:375
2727099206199,4cyclictest2447-21CPU6
2727099206199,4cyclictest2447-21CPU6
2727099206199,4cyclictest2447-21CPU6
2726899206194,9cyclictest0-21swapper/1307:35:005
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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