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2026-09-14 - 20:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Sep 14, 2026 13:02:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
525699225218,4cyclictest0-21swapper/2109:25:1514
525699225218,4cyclictest0-21swapper/2109:25:1514
525699225218,4cyclictest0-21swapper/2109:25:1514
525699212200,10cyclictest0-21swapper/2110:52:5114
525699212200,10cyclictest0-21swapper/2110:52:5114
523699208179,23cyclictest0-21swapper/409:32:2534
523699208179,23cyclictest0-21swapper/409:32:2534
525699206200,3cyclictest1-21systemd10:58:4414
525699206200,3cyclictest1-21systemd10:58:4414
525699205199,4cyclictest481-21sshd09:35:1714
525699205199,4cyclictest481-21sshd09:35:1714
525699204192,10cyclictest0-21swapper/2112:21:3314
525699204192,10cyclictest0-21swapper/2112:21:3214
525699203195,5cyclictest755-21systemd-journal09:16:4414
525699203195,5cyclictest755-21systemd-journal09:16:4314
525699203193,8cyclictest0-21swapper/2111:20:2614
525699203193,8cyclictest0-21swapper/2111:20:2614
525699203193,8cyclictest0-21swapper/2111:20:2614
525699202194,5cyclictest0-21swapper/2112:00:2214
525699202194,5cyclictest0-21swapper/2112:00:2114
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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