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2026-03-10 - 19:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Mar 10, 2026 13:03:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2087599213204,3cyclictest0-21swapper/410:14:2334
2087599213204,3cyclictest0-21swapper/410:14:2334
2087599213204,3cyclictest0-21swapper/410:14:2334
2089899197182,11cyclictest0-21swapper/2309:39:2316
2089899197182,11cyclictest0-21swapper/2309:39:2316
2088399197190,6cyclictest0-21swapper/1107:18:243
2088399197190,6cyclictest0-21swapper/1107:18:243
2088399197185,8cyclictest4408-21CPU3
2088399197185,8cyclictest4408-21CPU3
2087599196188,6cyclictest0-21swapper/409:47:4334
2087599196188,6cyclictest0-21swapper/409:47:4334
2087599196188,6cyclictest0-21swapper/409:47:4334
2088399195186,7cyclictest0-21swapper/1112:29:153
2088399195186,7cyclictest0-21swapper/1112:29:143
2087699194177,13cyclictest0-21swapper/510:55:2035
2087699194177,13cyclictest0-21swapper/510:55:2035
2087699194177,13cyclictest0-21swapper/510:55:2035
2088399193186,5cyclictest1430-21polkitd12:25:033
2088399193186,5cyclictest1430-21polkitd12:25:033
2088399193183,8cyclictest0-21swapper/1112:34:543
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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