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2026-06-01 - 22:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Jun 01, 2026 13:02:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25603992721,252cyclictest3793-21lxd12:31:1033
25603992721,252cyclictest3793-21lxd12:31:1033
25603992320,2cyclictest0-21swapper/3912:40:0133
25603992320,2cyclictest0-21swapper/3912:40:0033
25603992320,2cyclictest0-21swapper/3912:40:0033
25603992301,4cyclictest1367-21dbus-daemon12:01:5233
25603992301,4cyclictest1367-21dbus-daemon12:01:5133
25603992301,4cyclictest1367-21dbus-daemon12:01:5133
25603992161,211cyclictest0-21swapper/3912:20:1733
25603992161,211cyclictest0-21swapper/3912:20:1733
25603992151,2cyclictest0-21swapper/3912:15:2633
25603992151,2cyclictest0-21swapper/3912:15:2633
25603992150,2cyclictest0-21swapper/3912:09:3933
25603992150,2cyclictest0-21swapper/3912:09:3933
25603992120,2cyclictest0-21swapper/3912:14:5833
25603992120,2cyclictest0-21swapper/3912:14:5733
25603992120,2cyclictest0-21swapper/3911:58:5133
25603992120,2cyclictest0-21swapper/3911:58:5033
25603992091,205cyclictest0-21swapper/3912:25:2633
25603992091,205cyclictest0-21swapper/3912:25:2633
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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