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2026-06-26 - 11:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Jun 26, 2026 01:01:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1819299206199,5cyclictest0-21swapper/323:35:2123
1819299206199,5cyclictest0-21swapper/323:35:2123
1819299203198,3cyclictest1243-21sshd22:30:2823
1819299203198,3cyclictest1243-21sshd22:30:2723
1819299203198,3cyclictest1243-21sshd22:30:2723
1821599201194,5cyclictest0-21swapper/2320:05:0116
1821599201194,5cyclictest0-21swapper/2320:05:0116
1820299195183,7cyclictest3548-21CPU3
1820299195183,7cyclictest3548-21CPU3
1822899193154,36cyclictest0-21swapper/3200:08:5026
1822899193154,36cyclictest0-21swapper/3200:08:4926
1823399192182,6cyclictest0-21swapper/3721:57:3331
1823399192182,6cyclictest0-21swapper/3721:57:3331
1823399192182,6cyclictest0-21swapper/3721:57:3231
181919919134,150cyclictest37265-21CPU12
181919919134,150cyclictest37265-21CPU12
1820699189171,14cyclictest37265-21CPU7
1820699189171,14cyclictest37265-21CPU7
1819199189165,9cyclictest0-21swapper/221:56:2812
1819199189165,9cyclictest0-21swapper/221:56:2712
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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