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2026-05-20 - 08:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed May 20, 2026 01:02:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
957899219216,2cyclictest0-21swapper/319:55:2223
957899219216,2cyclictest0-21swapper/319:55:2123
960499209193,8cyclictest0-21swapper/2420:40:0617
960499209193,8cyclictest0-21swapper/2420:40:0617
960499206198,4cyclictest37351-21CPU17
960499206198,4cyclictest37351-21CPU17
958599206181,6cyclictest0-21swapper/923:59:2239
958599206181,6cyclictest0-21swapper/923:59:2239
958599206181,6cyclictest0-21swapper/923:59:2139
960499204196,6cyclictest0-21swapper/2420:00:0117
960499204196,6cyclictest0-21swapper/2420:00:0117
961899203195,6cyclictest0-21swapper/3620:52:0230
961899203195,6cyclictest0-21swapper/3620:52:0130
960499203195,6cyclictest3535-21qemu-system-x8622:55:4417
960499203195,6cyclictest3535-21qemu-system-x8622:55:4417
961899201195,4cyclictest0-21swapper/3622:04:2230
961899201195,4cyclictest0-21swapper/3622:04:2230
961899200193,5cyclictest24952-21packagekitd23:18:3930
961899200193,5cyclictest24952-21packagekitd23:18:3830
961799199182,15cyclictest0-21swapper/3523:56:1429
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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