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2026-03-02 - 15:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Mar 02, 2026 13:03:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1405799240235,3cyclictest0-21swapper/007:40:220
1405799240235,3cyclictest0-21swapper/007:40:210
1409299238235,2cyclictest0-21swapper/3007:40:2324
1409299238235,2cyclictest0-21swapper/3007:40:2224
1408799236214,12cyclictest0-21swapper/2611:30:2819
1408799236214,12cyclictest0-21swapper/2611:30:2819
1408799236214,12cyclictest0-21swapper/2611:30:2819
1406299229191,24cyclictest0-21swapper/511:08:0935
1406299229191,24cyclictest0-21swapper/511:08:0935
1406299229191,24cyclictest0-21swapper/511:08:0935
1407999223196,12cyclictest0-21swapper/1810:48:3010
1407999223196,12cyclictest0-21swapper/1810:48:3010
1408799219209,6cyclictest8031-21diskstats11:00:2019
1408799219209,6cyclictest8031-21diskstats11:00:2019
1408799219209,6cyclictest8031-21diskstats11:00:1919
1408799219198,15cyclictest3610-21CPU19
1408799219198,15cyclictest3610-21CPU19
1408799216201,6cyclictest0-21swapper/2611:53:0419
1408799216201,6cyclictest0-21swapper/2611:53:0319
1408799216201,6cyclictest0-21swapper/2611:53:0319
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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