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2026-08-14 - 02:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Aug 14, 2026 01:02:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2072499225216,5cyclictest37355-21CPU18
2072499225216,5cyclictest37355-21CPU18
2072099224216,6cyclictest0-21swapper/2123:00:5414
2072099224216,6cyclictest0-21swapper/2123:00:5314
2072099217211,3cyclictest0-21swapper/2123:08:3814
2072099217211,3cyclictest0-21swapper/2123:08:3714
2072499215204,6cyclictest2454-21CPU18
2072499215204,6cyclictest2454-21CPU18
2072499210203,5cyclictest0-21swapper/2522:25:2818
2072499210203,5cyclictest0-21swapper/2522:25:2818
2072499210203,5cyclictest0-21swapper/2522:25:2818
2072099210203,5cyclictest0-21swapper/2122:54:5514
2072099210203,5cyclictest0-21swapper/2122:54:5514
2072099210203,5cyclictest0-21swapper/2122:54:5414
2072099210199,6cyclictest2466-21CPU14
2072099210199,6cyclictest2466-21CPU14
2072099210199,6cyclictest2466-21CPU14
2072499209196,10cyclictest0-21swapper/2521:20:2018
2072499209196,10cyclictest0-21swapper/2521:20:1918
2072499208195,3cyclictest1367-21dbus-daemon21:15:2018
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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