You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-27 - 01:21
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Jul 26, 2026 13:01:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1201599230221,3cyclictest37354-21CPU38
1201599230221,3cyclictest37354-21CPU38
1201599224220,2cyclictest0-21swapper/807:40:5838
1201599224220,2cyclictest0-21swapper/807:40:5738
1201599223209,11cyclictest0-21swapper/809:00:0338
1201599219213,4cyclictest0-21swapper/811:55:0138
1201599219213,4cyclictest0-21swapper/811:55:0138
1202199217209,6cyclictest0-21swapper/1308:35:015
1202199217209,6cyclictest0-21swapper/1308:35:015
1201599217209,5cyclictest1360-21systemd-logind12:05:3138
1201599217209,5cyclictest1360-21systemd-logind12:05:3138
1201599217209,5cyclictest1360-21systemd-logind12:05:3038
1201599217208,7cyclictest0-21swapper/812:00:4938
1201599217208,7cyclictest0-21swapper/812:00:4838
1202199216207,5cyclictest3609-21CPU5
1202199216207,5cyclictest3609-21CPU5
1202199214208,4cyclictest0-21swapper/1310:20:225
1202199214208,4cyclictest0-21swapper/1310:20:225
1202199214208,4cyclictest0-21swapper/1310:20:215
1202199214205,5cyclictest3609-21CPU5
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional