You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-01 - 01:23
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Jul 31, 2026 13:02:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
580299232225,4cyclictest0-21swapper/109:49:451
580299232225,4cyclictest0-21swapper/109:49:441
584199218209,4cyclictest3543-21CPU27
584199218209,4cyclictest3543-21CPU27
584199218209,4cyclictest3543-21CPU27
580799214192,14cyclictest0-21swapper/609:27:5536
580799214192,14cyclictest0-21swapper/609:27:5536
580799214192,14cyclictest0-21swapper/609:27:5536
582699202175,23cyclictest0-21swapper/2208:20:1915
582699202175,23cyclictest0-21swapper/2208:20:1915
580799201192,7cyclictest0-21swapper/612:00:2036
580799201192,7cyclictest0-21swapper/612:00:2036
580799198187,9cyclictest0-21swapper/612:21:2936
580799198187,9cyclictest0-21swapper/612:21:2836
580799198187,9cyclictest0-21swapper/612:21:2836
580799197187,6cyclictest0-21swapper/610:05:2036
580799197187,6cyclictest0-21swapper/610:05:2036
580799197187,6cyclictest0-21swapper/610:05:2036
580199196182,12cyclictest0-21swapper/011:48:130
580199196182,12cyclictest0-21swapper/011:48:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional