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2026-07-04 - 21:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Jul 04, 2026 13:01:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3449499231223,6cyclictest0-21swapper/2210:26:5015
3449499231223,6cyclictest0-21swapper/2210:26:4915
3449499209199,7cyclictest0-21swapper/2210:22:1215
3449499209199,7cyclictest0-21swapper/2210:22:1215
3449499209199,7cyclictest0-21swapper/2210:22:1215
3447499209168,28cyclictest0-21swapper/511:20:3835
3447499209168,28cyclictest0-21swapper/511:20:3735
3447499209168,28cyclictest0-21swapper/511:20:3735
3448299200183,11cyclictest0-21swapper/1212:21:054
3448299200183,11cyclictest0-21swapper/1212:21:054
3447499200185,9cyclictest0-21swapper/511:17:4935
3447499200185,9cyclictest0-21swapper/511:17:4935
3448299199192,5cyclictest0-21swapper/1211:57:104
3448299199192,5cyclictest0-21swapper/1211:57:104
3448799197187,6cyclictest3542-21CPU7
3448799197187,6cyclictest3542-21CPU7
3447599197182,13cyclictest0-21swapper/611:32:2336
3447599197182,13cyclictest0-21swapper/611:32:2336
3448299195183,10cyclictest0-21swapper/1211:52:394
3448299195183,10cyclictest0-21swapper/1211:52:394
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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