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2026-08-24 - 18:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Aug 24, 2026 13:02:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2101199232228,2cyclictest0-21swapper/1409:20:126
2101199232228,2cyclictest0-21swapper/1409:20:116
2101299222215,5cyclictest0-21swapper/1510:30:537
2101299222215,5cyclictest0-21swapper/1510:30:537
2101299219210,5cyclictest0-21swapper/1511:05:237
2101299219210,5cyclictest0-21swapper/1511:05:237
2103099218207,9cyclictest0-21swapper/2909:32:2522
2103099218207,9cyclictest0-21swapper/2909:32:2522
2102199215197,11cyclictest0-21swapper/2111:55:1914
2102199215197,11cyclictest0-21swapper/2111:55:1914
2101299215201,6cyclictest0-21swapper/1510:35:157
2101299215201,6cyclictest0-21swapper/1510:35:157
2101299215201,6cyclictest0-21swapper/1510:35:157
2103099214203,9cyclictest0-21swapper/2910:05:2822
2103099214203,9cyclictest0-21swapper/2910:05:2822
2103099214203,9cyclictest0-21swapper/2910:05:2822
2102199213204,7cyclictest0-21swapper/2111:45:2814
2102199213204,7cyclictest0-21swapper/2111:45:2714
2103099212204,6cyclictest0-21swapper/2909:45:1522
2103099212204,6cyclictest0-21swapper/2909:45:1422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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