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2025-11-25 - 06:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Nov 25, 2025 01:00:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201399260232,12cyclictest0-21swapper/3422:40:1828
201399260232,12cyclictest0-21swapper/3422:40:1828
201399235209,15cyclictest0-21swapper/3420:55:1828
201399235209,15cyclictest0-21swapper/3420:55:1828
200499230205,10cyclictest31279-21sshd00:20:2120
200499230205,10cyclictest31279-21sshd00:20:2120
19979921811,79cyclictest15981-21CPU14
19979921811,79cyclictest15981-21CPU14
19869921721,7cyclictest25044-21inotify_reader23:45:182
19869921721,7cyclictest25044-21inotify_reader23:45:182
19869921721,7cyclictest25044-21inotify_reader23:45:182
19729921737,45cyclictest39597-21NetworkChangeNo19:35:210
19729921737,45cyclictest39597-21NetworkChangeNo19:35:210
2016992149,188cyclictest6434-21inotify_reader23:45:1831
2016992149,188cyclictest6434-21inotify_reader23:45:1831
2016992149,188cyclictest6434-21inotify_reader23:45:1831
201399208189,10cyclictest0-21swapper/3421:05:1828
201399208189,10cyclictest0-21swapper/3421:05:1828
201299208199,4cyclictest4912-21CPU27
201299208199,4cyclictest4912-21CPU27
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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