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2026-07-18 - 20:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Jul 18, 2026 13:02:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1025799248242,2cyclictest0-21swapper/1911:20:1311
1025799248242,2cyclictest0-21swapper/1911:20:1311
1027599234203,16cyclictest0-21swapper/3509:22:1929
1027599234203,16cyclictest0-21swapper/3509:22:1929
1025899231228,2cyclictest0-21swapper/2011:20:2313
1025899231228,2cyclictest0-21swapper/2011:20:2313
1023999228223,3cyclictest0-21swapper/511:20:1835
1023999228223,3cyclictest0-21swapper/511:20:1835
1023499225219,2cyclictest0-21swapper/007:20:010
1023499225219,2cyclictest0-21swapper/007:20:010
1026099219216,2cyclictest0-21swapper/2211:25:0715
1026099219216,2cyclictest0-21swapper/2211:25:0715
1025899213175,36cyclictest372-21kswapd007:20:0413
1025899213175,36cyclictest372-21kswapd007:20:0413
1023499211204,4cyclictest29616-21sshd11:20:160
1023499211204,4cyclictest29616-21sshd11:20:160
1026999207200,5cyclictest0-21swapper/3011:10:1924
1026999207200,5cyclictest0-21swapper/3011:10:1824
1025499205197,5cyclictest2454-21CPU9
1025499205197,5cyclictest2454-21CPU9
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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