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2026-05-07 - 09:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu May 07, 2026 01:01:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1100199273256,13cyclictest0-21swapper/3623:20:1330
1100199273256,13cyclictest0-21swapper/3623:20:1230
1100199251245,4cyclictest0-21swapper/3621:40:0230
1100199251245,4cyclictest0-21swapper/3621:40:0230
1100199249235,9cyclictest1367-21dbus-daemon22:10:1730
1100199249235,9cyclictest1367-21dbus-daemon22:10:1730
1100199238224,12cyclictest0-21swapper/3622:05:2030
1100199238224,12cyclictest0-21swapper/3622:05:2030
1100199238209,17cyclictest0-21swapper/3621:32:3730
1100199238209,17cyclictest0-21swapper/3621:32:3730
1100199236217,15cyclictest0-21swapper/3623:50:0030
1100199236217,15cyclictest0-21swapper/3623:50:0030
1100199235220,12cyclictest0-21swapper/3623:25:1630
1100199235220,12cyclictest0-21swapper/3623:25:1630
1100199230222,6cyclictest0-21swapper/3623:45:0130
1100199230222,6cyclictest0-21swapper/3623:45:0130
1100199230222,6cyclictest0-21swapper/3623:45:0130
1100199228212,8cyclictest0-21swapper/3623:30:1930
1100199228212,8cyclictest0-21swapper/3623:30:1930
1100199227200,12cyclictest0-21swapper/3621:45:4330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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