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2025-11-17 - 21:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Nov 17, 2025 13:01:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
168499286258,3cyclictest272-21ksoftirqd/3111:15:2125
168499286258,3cyclictest272-21ksoftirqd/3111:15:2125
166599234197,18cyclictest11904-21CPU16
166599234197,18cyclictest11904-21CPU16
166599232204,13cyclictest9327-21CPU16
166599232204,13cyclictest9327-21CPU16
166599232204,13cyclictest9327-21CPU16
168699231200,29cyclictest0-21swapper/3309:39:2027
168699231200,29cyclictest0-21swapper/3309:39:2027
168699231200,29cyclictest0-21swapper/3309:39:2027
166599231209,11cyclictest22231-21inotify_reader10:50:2116
166599231209,11cyclictest22231-21inotify_reader10:50:2016
166599231209,11cyclictest22231-21inotify_reader10:50:2016
16709922418,80cyclictest27681-21inotify_reader09:05:2220
16709922418,80cyclictest27681-21inotify_reader09:05:2220
16709922418,80cyclictest27681-21inotify_reader09:05:2220
163799219109,88cyclictest15981-21CPU1
163799219109,88cyclictest15981-21CPU1
166199216211,2cyclictest0-21swapper/1908:20:2411
166199216211,2cyclictest0-21swapper/1908:20:2411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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