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2025-11-11 - 07:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Nov 11, 2025 01:01:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1084299238205,16cyclictest0-21swapper/3723:30:1931
1084299238205,16cyclictest0-21swapper/3723:30:1831
1084299238205,16cyclictest0-21swapper/3723:30:1831
108079923215,65cyclictest40617-21TaskSchedulerSi21:15:1814
108079923215,65cyclictest40617-21TaskSchedulerSi21:15:1714
108079923215,65cyclictest40617-21TaskSchedulerSi21:15:1714
10787992311,225cyclictest0-21swapper/620:40:2036
1080599229207,4cyclictest11904-21CPU11
1077999226200,24cyclictest0-21swapper/221:45:4912
1077999226200,24cyclictest0-21swapper/221:45:4912
10828992200,209cyclictest27935-21inotify_reader23:35:2028
10828992200,209cyclictest27935-21inotify_reader23:35:2028
1084299219199,12cyclictest6539-21TaskSchedulerSi20:40:2031
1077999215201,12cyclictest0-21swapper/223:32:0212
1077999215201,12cyclictest0-21swapper/223:32:0212
1077999215201,12cyclictest0-21swapper/223:32:0212
10809992118,170cyclictest32187-21inotify_reader20:35:1916
1082699209195,7cyclictest20368-21inotify_reader23:55:1827
1082699209195,7cyclictest20368-21inotify_reader23:55:1827
1082699209195,7cyclictest20368-21inotify_reader23:55:1827
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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