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2026-06-13 - 17:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Jun 13, 2026 13:03:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1468299236231,3cyclictest0-21swapper/1711:40:219
1468299236231,3cyclictest0-21swapper/1711:40:209
1470399233213,14cyclictest0-21swapper/3508:25:1329
1470399233213,14cyclictest0-21swapper/3508:25:1329
1469199214190,17cyclictest0-21swapper/2508:10:0118
1469199214190,17cyclictest0-21swapper/2508:10:0118
1470399213191,14cyclictest0-21swapper/3508:17:0029
1470399213191,14cyclictest0-21swapper/3508:16:5929
1470399210187,9cyclictest0-21swapper/3508:45:1329
1470399210187,9cyclictest0-21swapper/3508:45:1329
1470399209204,4cyclictest0-21swapper/3508:35:0129
1470399209204,4cyclictest0-21swapper/3508:35:0129
1469199207185,13cyclictest0-21swapper/2507:50:1118
1470399205195,6cyclictest20840-21cpuspeed_turbos08:40:1529
1470399205195,6cyclictest20840-21cpuspeed_turbos08:40:1529
1469199204195,7cyclictest0-21swapper/2507:46:3518
1469199204195,7cyclictest0-21swapper/2507:46:3518
146839920399,96cyclictest2447-21CPU10
146839920399,96cyclictest2447-21CPU10
1467999202184,12cyclictest0-21swapper/1410:25:296
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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