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2026-07-02 - 06:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Jul 02, 2026 01:01:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2855799232224,6cyclictest0-21swapper/3823:20:4332
2855799232224,6cyclictest0-21swapper/3823:20:4332
2855799228218,3cyclictest33434-21sshd00:27:2832
2855799228218,3cyclictest33434-21sshd00:27:2732
2855799228218,3cyclictest33434-21sshd00:27:2732
2855799225212,8cyclictest0-21swapper/3800:10:5632
2855799225212,8cyclictest0-21swapper/3800:10:5632
2855799223216,5cyclictest0-21swapper/3800:36:0832
2855799223216,5cyclictest0-21swapper/3800:36:0732
2855799222203,14cyclictest3547-21CPU32
2855799222203,14cyclictest3547-21CPU32
2855799222198,15cyclictest0-21swapper/3823:02:3432
2855799222198,15cyclictest0-21swapper/3823:02:3432
2855799220213,5cyclictest0-21swapper/3800:07:5032
2855799220213,5cyclictest0-21swapper/3800:07:5032
2855799220212,3cyclictest37267-21CPU32
2855799220212,3cyclictest37267-21CPU32
2855799220199,13cyclictest0-21swapper/3823:40:2232
2855799220199,13cyclictest0-21swapper/3823:40:2232
2855799218208,8cyclictest0-21swapper/3823:55:3032
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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