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2026-07-28 - 14:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Jul 28, 2026 13:01:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201799234220,11cyclictest0-21swapper/1412:00:126
201799234220,11cyclictest0-21swapper/1412:00:116
201799228213,12cyclictest0-21swapper/1412:21:516
201799228213,12cyclictest0-21swapper/1412:21:506
201799227218,6cyclictest0-21swapper/1412:05:226
201799227218,6cyclictest0-21swapper/1412:05:216
204699226219,5cyclictest0-21swapper/3808:30:2732
204699226219,5cyclictest0-21swapper/3808:30:2732
201799226222,2cyclictest0-21swapper/1411:20:446
201799226222,2cyclictest0-21swapper/1411:20:436
201799226218,4cyclictest4407-21CPU6
201799226218,4cyclictest4407-21CPU6
202399219213,3cyclictest2459-21CPU11
202399219213,3cyclictest2459-21CPU11
201799216210,4cyclictest0-21swapper/1412:17:196
201799216210,4cyclictest0-21swapper/1412:17:196
201799216209,5cyclictest0-21swapper/1411:35:166
201799216209,5cyclictest0-21swapper/1411:35:166
201799216209,5cyclictest0-21swapper/1411:35:156
201799216208,6cyclictest0-21swapper/1409:33:236
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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