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2026-07-25 - 22:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Jul 25, 2026 13:03:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1100099214194,11cyclictest0-21swapper/3008:15:2224
1100099214194,11cyclictest0-21swapper/3008:15:2224
1100099209203,4cyclictest0-21swapper/3008:00:4624
1100099209203,4cyclictest0-21swapper/3008:00:4524
1097499206180,23cyclictest0-21swapper/708:00:0437
1097499206180,23cyclictest0-21swapper/708:00:0337
1100599201190,10cyclictest0-21swapper/3508:41:2129
1100699200195,3cyclictest17482-21nfsd10:50:1830
1100699200195,3cyclictest17482-21nfsd10:50:1830
1099899199189,8cyclictest0-21swapper/2810:55:1021
1099899199189,8cyclictest0-21swapper/2810:55:0921
1099899199189,8cyclictest0-21swapper/2810:55:0921
109989919672,120cyclictest37354-21CPU21
109989919672,120cyclictest37354-21CPU21
1100599195191,2cyclictest0-21swapper/3510:27:1029
1100599195191,2cyclictest0-21swapper/3510:27:0929
1097499195187,5cyclictest0-21swapper/710:17:2037
1097499195187,5cyclictest0-21swapper/710:17:1937
1097499194180,7cyclictest0-21swapper/712:31:3537
1097499194180,7cyclictest0-21swapper/712:31:3437
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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