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2026-09-05 - 13:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Sep 05, 2026 01:01:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2273799217213,2cyclictest0-21swapper/2119:35:1514
2273799217213,2cyclictest0-21swapper/2119:35:1414
2273599208190,14cyclictest0-21swapper/1923:38:0911
2273599208190,14cyclictest0-21swapper/1923:38:0911
2274799207201,4cyclictest0-21swapper/3023:40:1224
2274799207201,4cyclictest0-21swapper/3023:40:1224
2274799207201,4cyclictest0-21swapper/3023:40:1224
2271499206197,7cyclictest0-21swapper/221:10:3412
2271499206197,7cyclictest0-21swapper/221:10:3412
227539920392,104cyclictest37354-21CPU28
227539920392,104cyclictest37354-21CPU28
2274799198188,8cyclictest0-21swapper/3023:45:5324
2274799198188,8cyclictest0-21swapper/3023:45:5324
2271499193187,4cyclictest0-21swapper/221:19:1312
2271499193187,4cyclictest0-21swapper/221:19:1212
2271499193187,4cyclictest0-21swapper/221:19:1212
2272599192152,31cyclictest0-21swapper/1123:41:553
2272599192152,31cyclictest0-21swapper/1123:41:553
2272599192152,31cyclictest0-21swapper/1123:41:553
227449919186,95cyclictest37358-21CPU20
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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