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2026-07-07 - 00:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Jul 06, 2026 13:02:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3146799205200,4cyclictest0-21swapper/2008:50:1713
3146799205200,4cyclictest0-21swapper/2008:50:1613
3146799204198,4cyclictest0-21swapper/2009:54:4113
3146799204198,4cyclictest0-21swapper/2009:54:4013
3146799204198,4cyclictest0-21swapper/2009:54:4013
3144399204194,8cyclictest0-21swapper/008:35:180
3144399204194,8cyclictest0-21swapper/008:35:180
3148199203197,4cyclictest0-21swapper/3111:59:5225
3148199203197,4cyclictest0-21swapper/3111:59:5225
3147499201194,5cyclictest0-21swapper/2608:40:1719
3147499201194,5cyclictest0-21swapper/2608:40:1719
3144399201194,5cyclictest0-21swapper/011:58:290
3144399201194,5cyclictest0-21swapper/011:58:290
3144399201190,9cyclictest0-21swapper/010:40:260
3144399201190,9cyclictest0-21swapper/010:40:260
3147499200194,4cyclictest0-21swapper/2612:40:0419
3147499200194,4cyclictest0-21swapper/2612:40:0419
3147499200194,4cyclictest0-21swapper/2612:40:0319
3148199198190,4cyclictest37358-21CPU25
3148199198190,4cyclictest37358-21CPU25
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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