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2026-09-18 - 02:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Sep 18, 2026 01:02:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1691099198186,10cyclictest0-21swapper/2422:16:3017
1691099198186,10cyclictest0-21swapper/2422:16:3017
1688699196123,57cyclictest0-21swapper/422:13:1934
1688699196123,57cyclictest0-21swapper/422:13:1934
1688699196123,57cyclictest0-21swapper/422:13:1934
1691099194182,7cyclictest0-21swapper/2400:01:2017
1691099194182,7cyclictest0-21swapper/2400:01:2017
1691099194182,7cyclictest0-21swapper/2400:01:1917
1691399186156,12cyclictest0-21swapper/2723:36:1120
1691399186156,12cyclictest0-21swapper/2723:36:1120
1692299184171,8cyclictest0-21swapper/3521:24:5229
1692299184171,8cyclictest0-21swapper/3521:24:5129
1691399183146,12cyclictest0-21swapper/2720:22:3420
1691399183146,12cyclictest0-21swapper/2720:22:3420
1692299182165,11cyclictest0-21swapper/3523:38:3429
1692299182165,11cyclictest0-21swapper/3523:38:3429
1691399181154,19cyclictest0-21swapper/2723:22:2720
1691399181154,19cyclictest0-21swapper/2723:22:2720
1691399181154,19cyclictest0-21swapper/2723:22:2720
1691099181174,5cyclictest0-21swapper/2421:56:1917
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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