You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-19 - 12:03
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Nov 19, 2025 01:00:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3652599226186,15cyclictest171rcu_preempt23:21:0116
3652599226186,15cyclictest171rcu_preempt23:21:0116
3653099221180,22cyclictest0-21swapper/2819:15:2121
3653099221180,22cyclictest0-21swapper/2819:15:2121
364979921814,190cyclictest1156-21inotify_reader23:20:2012
364979921814,190cyclictest1156-21inotify_reader23:20:2012
36534992151,3cyclictest0-21swapper/3122:10:1725
36534992151,3cyclictest0-21swapper/3122:10:1725
3653099209194,5cyclictest2451rcuc/2822:05:2121
3653099209194,5cyclictest2451rcuc/2822:05:2121
3652399209175,10cyclictest171rcu_preempt21:37:1314
3652399209175,10cyclictest171rcu_preempt21:37:1314
3652199205169,16cyclictest27033-21inotify_reader00:15:2111
3652199205169,16cyclictest27033-21inotify_reader00:15:2111
3652199205169,16cyclictest27033-21inotify_reader00:15:2111
3652399200176,11cyclictest171rcu_preempt20:53:2514
3652399200176,11cyclictest171rcu_preempt20:53:2514
36494992001,193cyclictest11392-21TaskSchedulerSi22:15:211
36494992001,193cyclictest11392-21TaskSchedulerSi22:15:211
36494992001,193cyclictest11392-21TaskSchedulerSi22:15:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional