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2026-07-19 - 22:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Jul 19, 2026 13:02:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
758599233216,6cyclictest0-21swapper/2910:20:1522
758599233216,6cyclictest0-21swapper/2910:20:1522
758599233216,6cyclictest0-21swapper/2910:20:1522
7577992171,213cyclictest0-21swapper/2210:20:2015
7577992171,213cyclictest0-21swapper/2210:20:2015
7577992171,213cyclictest0-21swapper/2210:20:2015
756499211206,4cyclictest0-21swapper/1109:37:173
756499211206,4cyclictest0-21swapper/1109:37:173
758399199193,2cyclictest0-21swapper/2711:57:3720
758399199193,2cyclictest0-21swapper/2711:57:3720
75879919447,143cyclictest0-21swapper/3110:15:1825
75879919447,143cyclictest0-21swapper/3110:15:1825
75879919447,143cyclictest0-21swapper/3110:15:1825
75819919423,167cyclictest0-21swapper/2510:30:2218
75819919423,167cyclictest0-21swapper/2510:30:2218
75819919423,167cyclictest0-21swapper/2510:30:2218
759499190144,17cyclictest0-21swapper/3708:58:2631
759499190144,17cyclictest0-21swapper/3708:58:2631
758799188171,13cyclictest0-21swapper/3110:29:4225
758799188171,13cyclictest0-21swapper/3110:29:4225
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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