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2025-11-21 - 11:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Nov 21, 2025 01:00:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39487992770,3cyclictest33154-21inotify_reader19:15:1939
39487992770,3cyclictest33154-21inotify_reader19:15:1939
3947899254229,4cyclictest351rcuc/222:55:2012
3947899254229,4cyclictest351rcuc/222:55:2012
3947899254229,4cyclictest351rcuc/222:55:2012
3949199230199,13cyclictest0-21swapper/1322:00:185
3949199230199,13cyclictest0-21swapper/1322:00:185
3949199230199,13cyclictest0-21swapper/1322:00:185
394939922134,167cyclictest11905-21CPU7
394939922134,167cyclictest11905-21CPU7
394899921657,152cyclictest11903-21CPU3
394899921657,152cyclictest11903-21CPU3
394899921657,152cyclictest11903-21CPU3
3947899213206,3cyclictest38031-21inotify_reader21:25:1712
3947899213206,3cyclictest38031-21inotify_reader21:25:1712
394779921320,189cyclictest10767-21inotify_reader21:25:181
394779921320,189cyclictest10767-21inotify_reader21:25:181
3948199209197,9cyclictest0-21swapper/521:51:1435
3948199209197,9cyclictest0-21swapper/521:51:1435
3947899208203,3cyclictest0-21swapper/220:00:2012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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