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2025-12-13 - 17:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Dec 13, 2025 12:59:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2671599197170,9cyclictest0-21swapper/3412:36:4528
2671599197170,9cyclictest0-21swapper/3412:36:4528
2668099192162,10cyclictest0-21swapper/412:16:5534
2668099192162,10cyclictest0-21swapper/412:16:5534
2670799189169,12cyclictest0-21swapper/2712:09:4020
2670799189169,12cyclictest0-21swapper/2712:09:4020
2670799189169,12cyclictest0-21swapper/2712:09:4020
2670799188171,5cyclictest0-21swapper/2710:24:5920
2670799188171,5cyclictest0-21swapper/2710:24:5920
2670799188171,5cyclictest0-21swapper/2710:24:5920
2670799187178,7cyclictest0-21swapper/2709:34:2520
2670799187178,7cyclictest0-21swapper/2709:34:2520
2668099187178,7cyclictest0-21swapper/411:40:3234
2668099187178,7cyclictest0-21swapper/411:40:3234
2668099187178,7cyclictest0-21swapper/411:40:3234
2670799186126,33cyclictest2464-21CPU20
2670799186104,71cyclictest3544-21CPU20
2670799186104,71cyclictest3544-21CPU20
2668299186140,32cyclictest0-21swapper/611:35:3136
2668299186140,32cyclictest0-21swapper/611:35:3136
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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