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2026-09-03 - 10:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Sep 03, 2026 01:01:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2759499203195,3cyclictest3544-21CPU38
2759499203195,3cyclictest3544-21CPU38
2759499203195,3cyclictest3544-21CPU38
2759199202189,10cyclictest0-21swapper/500:06:1235
2759199202189,10cyclictest0-21swapper/500:06:1235
2759199202189,10cyclictest0-21swapper/500:06:1135
2759599199195,2cyclictest21801-21kworker/u81:1+events_unbound22:27:2739
2759599199195,2cyclictest21801-21kworker/u81:1+events_unbound22:27:2639
2759599199195,2cyclictest21801-21kworker/u81:1+events_unbound22:27:2639
2759199199191,6cyclictest20043-21sshd00:00:1635
2759199199191,6cyclictest20043-21sshd00:00:1635
2759499197189,6cyclictest0-21swapper/800:21:4738
2759499197189,6cyclictest0-21swapper/800:21:4638
2759199196192,2cyclictest0-21swapper/521:50:3335
2759199196192,2cyclictest0-21swapper/521:50:3335
2759699191181,6cyclictest0-21swapper/1022:13:592
2759699191181,6cyclictest0-21swapper/1022:13:592
2759699191181,6cyclictest0-21swapper/1022:13:592
2759199191182,7cyclictest0-21swapper/521:15:0135
2759199191182,7cyclictest0-21swapper/521:15:0135
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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