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2026-07-15 - 15:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Jul 15, 2026 13:02:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3399899215210,3cyclictest0-21swapper/809:20:1538
3399899215210,3cyclictest0-21swapper/809:20:1538
3399699211206,2cyclictest0-21swapper/609:47:4936
3399699211206,2cyclictest0-21swapper/609:47:4936
3399699211206,2cyclictest0-21swapper/609:47:4936
3399699208201,4cyclictest0-21swapper/609:59:5136
3399699208201,4cyclictest0-21swapper/609:59:5136
3399699208201,4cyclictest0-21swapper/609:59:5136
3399699204199,4cyclictest0-21swapper/609:24:1236
3399699204199,4cyclictest0-21swapper/609:24:1136
3399699204196,6cyclictest11063-21sshd10:56:5236
3399699204196,6cyclictest11063-21sshd10:56:5236
3402899203189,11cyclictest0-21swapper/2909:28:1922
3402899203189,11cyclictest0-21swapper/2909:28:1822
3399699203195,4cyclictest3610-21CPU36
3399699203195,4cyclictest3610-21CPU36
3399699203195,4cyclictest3610-21CPU36
3399699201194,5cyclictest0-21swapper/609:15:0536
3399699201194,5cyclictest0-21swapper/609:15:0536
3399699201194,5cyclictest0-21swapper/609:15:0536
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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