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2026-08-29 - 12:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Aug 29, 2026 01:01:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39525992411,221cyclictest0-21swapper/2821:35:0621
39525992411,221cyclictest0-21swapper/2821:35:0621
39525992401,235cyclictest0-21swapper/2800:35:2621
39525992401,235cyclictest0-21swapper/2800:35:2521
39525992401,230cyclictest2466-21CPU21
39525992401,230cyclictest2466-21CPU21
39525992371,233cyclictest0-21swapper/2821:23:1321
39525992371,233cyclictest0-21swapper/2821:23:1321
39525992311,226cyclictest0-21swapper/2822:21:1021
39525992311,226cyclictest0-21swapper/2822:21:0921
39525992281,215cyclictest0-21swapper/2821:26:1821
39525992281,215cyclictest0-21swapper/2821:26:1821
39525992281,215cyclictest0-21swapper/2821:26:1721
39525992251,215cyclictest0-21swapper/2821:51:1721
39525992251,215cyclictest0-21swapper/2821:51:1721
39525992251,215cyclictest0-21swapper/2821:51:1721
39525992251,214cyclictest0-21swapper/2823:35:1921
39525992251,214cyclictest0-21swapper/2823:35:1921
39525992211,2cyclictest0-21swapper/2823:52:5321
39525992211,2cyclictest0-21swapper/2823:52:5321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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