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2026-07-07 - 14:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Jul 07, 2026 01:01:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1604299213188,18cyclictest0-21swapper/1422:40:486
1604299213188,18cyclictest0-21swapper/1422:40:486
1604299213188,18cyclictest0-21swapper/1422:40:476
1606499200186,13cyclictest0-21swapper/3200:37:3526
1606499200186,13cyclictest0-21swapper/3200:37:3526
1606499200186,13cyclictest0-21swapper/3200:37:3526
1605699194132,31cyclictest0-21swapper/2519:45:4618
1605699194132,31cyclictest0-21swapper/2519:45:4518
1605799190152,34cyclictest4407-21CPU19
1605799190152,34cyclictest4407-21CPU19
1605699189172,11cyclictest0-21swapper/2523:17:2818
1605699189172,11cyclictest0-21swapper/2523:17:2818
1605499189174,13cyclictest0-21swapper/2321:35:5416
1605499189174,13cyclictest0-21swapper/2321:35:5416
1605499187110,54cyclictest3610-21CPU16
1605499187110,54cyclictest3610-21CPU16
1605799185172,11cyclictest0-21swapper/2621:15:3719
1605799185172,11cyclictest0-21swapper/2621:15:3719
1607099183140,40cyclictest0-21swapper/3722:07:0831
1607099183140,40cyclictest0-21swapper/3722:07:0731
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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