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2026-02-09 - 12:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Feb 09, 2026 01:02:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2237399228213,12cyclictest4407-21CPU18
2237399228213,12cyclictest4407-21CPU18
2235199216211,3cyclictest0-21swapper/619:20:1636
2234999210192,6cyclictest0-21swapper/421:48:5134
2234999210192,6cyclictest0-21swapper/421:48:5034
2236199208201,5cyclictest0-21swapper/1520:15:227
2236199208201,5cyclictest0-21swapper/1520:15:217
2237699200193,5cyclictest0-21swapper/2819:40:1821
2237699200193,5cyclictest0-21swapper/2819:40:1721
2238299199182,12cyclictest0-21swapper/3320:20:1627
2238299199182,12cyclictest0-21swapper/3320:20:1527
2237699199193,4cyclictest0-21swapper/2819:20:3821
2234999198183,7cyclictest0-21swapper/423:26:4734
2234999198183,7cyclictest0-21swapper/423:26:4734
2234999198183,7cyclictest0-21swapper/423:26:4734
2237699197191,4cyclictest0-21swapper/2819:19:0421
2237699197191,4cyclictest0-21swapper/2819:19:0321
2237699197185,9cyclictest0-21swapper/2822:06:3821
2237699197185,9cyclictest0-21swapper/2822:06:3721
2237699194183,9cyclictest0-21swapper/2819:30:1821
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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