You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-26 - 21:51
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Aug 26, 2026 13:02:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1480099221129,79cyclictest37266-21CPU36
1480099221129,79cyclictest37266-21CPU36
1480099221129,79cyclictest37266-21CPU36
14800992172,4cyclictest37353-21CPU36
14800992172,4cyclictest37353-21CPU36
14800992172,4cyclictest37353-21CPU36
1480499213210,2cyclictest0-21swapper/1009:40:202
1480499213210,2cyclictest0-21swapper/1009:40:192
1482599212191,15cyclictest2466-21CPU21
1482599212191,15cyclictest2466-21CPU21
1483099202191,9cyclictest0-21swapper/3307:25:0127
1483099202191,9cyclictest0-21swapper/3307:25:0027
1480199199189,5cyclictest37354-21CPU37
1480199199189,5cyclictest37354-21CPU37
1483399198194,2cyclictest0-21swapper/3509:35:0129
1483399198194,2cyclictest0-21swapper/3509:35:0029
1483199197191,5cyclictest0-21swapper/3411:35:2228
1483199197191,5cyclictest0-21swapper/3411:35:2228
1483199197191,5cyclictest0-21swapper/3411:35:2128
14806991962,189cyclictest2464-21CPU4
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional