You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-17 - 02:32
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Nov 17, 2025 01:00:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2910699241207,15cyclictest0-21swapper/821:05:2038
2910699241207,15cyclictest0-21swapper/821:05:2038
2910699240219,10cyclictest0-21swapper/821:40:2038
2910699240219,10cyclictest0-21swapper/821:40:2038
2909799238203,33cyclictest0-21swapper/322:36:5823
2909799238203,33cyclictest0-21swapper/322:36:5823
29109992297,212cyclictest0-21swapper/1122:45:193
29109992297,212cyclictest0-21swapper/1122:45:193
291089922635,186cyclictest0-21swapper/1020:20:202
291089922635,186cyclictest0-21swapper/1020:20:202
2910499224221,2cyclictest0-21swapper/722:20:0937
2913499220214,4cyclictest15978-21CPU26
2913499220214,4cyclictest15978-21CPU26
2913499220214,4cyclictest15978-21CPU26
2910699214201,3cyclictest0-21swapper/821:10:2138
2910699214201,3cyclictest0-21swapper/821:10:2138
2910699214201,3cyclictest0-21swapper/821:10:2138
2913599213210,2cyclictest0-21swapper/3300:06:0627
2913599213210,2cyclictest0-21swapper/3300:06:0627
2913599209204,3cyclictest0-21swapper/3320:50:2327
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional