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2025-12-05 - 02:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Dec 05, 2025 01:00:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3519799269264,3cyclictest0-21swapper/3500:00:2329
3519799269264,3cyclictest0-21swapper/3500:00:2329
3520699248234,6cyclictest20970-21inotify_reader21:40:1932
3520699248234,6cyclictest20970-21inotify_reader21:40:1932
3520699248234,6cyclictest20970-21inotify_reader21:40:1932
3517899231225,3cyclictest0-21swapper/2100:30:2014
3517899231225,3cyclictest0-21swapper/2100:30:2014
3517399229219,5cyclictest15985-21CPU9
3517399229219,5cyclictest15985-21CPU9
3517399229219,5cyclictest15985-21CPU9
3517399229219,5cyclictest15985-21CPU9
3517899228208,8cyclictest0-21swapper/2123:15:1914
3517899228208,8cyclictest0-21swapper/2123:15:1914
3517899228208,8cyclictest0-21swapper/2123:15:1914
35188992270,2cyclictest0-21swapper/2721:52:2720
35188992270,2cyclictest0-21swapper/2721:52:2720
35188992270,2cyclictest0-21swapper/2721:52:2720
3517899227206,11cyclictest0-21swapper/2123:25:1914
3517899227206,11cyclictest0-21swapper/2123:25:1914
3517899227206,11cyclictest0-21swapper/2123:25:1914
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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