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2026-09-08 - 07:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Sep 08, 2026 01:00:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1348499248245,2cyclictest0-21swapper/422:25:1934
1348499248245,2cyclictest0-21swapper/422:25:1934
1348699232228,2cyclictest0-21swapper/622:25:1636
1348699232228,2cyclictest0-21swapper/622:25:1636
1348599227206,18cyclictest372-21kswapd022:47:4535
1350799222203,13cyclictest37355-21CPU17
1350799217205,8cyclictest2461-21CPU17
1350799217205,8cyclictest2461-21CPU17
1350099211206,3cyclictest0-21swapper/1822:25:1610
1350099211206,3cyclictest0-21swapper/1822:25:1510
1350799199190,7cyclictest0-21swapper/2423:00:2417
1350799199190,7cyclictest0-21swapper/2423:00:2317
1350799196164,23cyclictest0-21swapper/2423:10:2117
1350799196164,23cyclictest0-21swapper/2423:10:2017
1350799194172,9cyclictest37354-21CPU17
1350799194172,9cyclictest37354-21CPU17
1350799193183,8cyclictest0-21swapper/2422:40:1717
1350799193183,8cyclictest0-21swapper/2422:40:1617
1350799192186,4cyclictest0-21swapper/2421:21:4717
1350799192169,20cyclictest0-21swapper/2422:00:2517
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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