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2026-09-28 - 16:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Sep 28, 2026 13:02:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1126399211172,36cyclictest0-21swapper/3712:37:3431
1126399211172,36cyclictest0-21swapper/3712:37:3431
1125099201186,13cyclictest0-21swapper/2510:12:3518
1125099201186,13cyclictest0-21swapper/2510:12:3518
1124299200193,4cyclictest28085-21sshd10:40:1910
1124299200193,4cyclictest28085-21sshd10:40:1910
1124299200193,4cyclictest28085-21sshd10:40:1910
1122899196183,8cyclictest0-21swapper/609:58:3536
1122899196183,8cyclictest0-21swapper/609:58:3536
1125799191182,7cyclictest0-21swapper/3110:26:5125
1125799191182,7cyclictest0-21swapper/3110:26:5125
1122899189185,2cyclictest0-21swapper/612:23:0636
1122899189185,2cyclictest0-21swapper/612:23:0636
1122899189185,2cyclictest0-21swapper/612:23:0636
1122499185177,4cyclictest4627-21CPU34
1122499185177,4cyclictest4627-21CPU34
1124799183158,22cyclictest1365-21systemd-logind12:30:1716
1124799183158,22cyclictest1365-21systemd-logind12:30:1716
1125899182176,3cyclictest0-21swapper/3210:40:3726
1125899182176,3cyclictest0-21swapper/3210:40:3726
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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