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2026-09-07 - 18:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Sep 07, 2026 13:02:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1232699206171,31cyclictest0-21swapper/2008:50:2213
1232699206171,31cyclictest0-21swapper/2008:50:2213
1232799204196,6cyclictest0-21swapper/2112:40:0214
1232799204196,6cyclictest0-21swapper/2112:40:0214
1232699199193,4cyclictest0-21swapper/2009:41:5813
1232699199193,4cyclictest0-21swapper/2009:41:5813
1232699199193,4cyclictest0-21swapper/2009:41:5713
12334991951,97cyclictest0-21swapper/2711:15:2220
12334991951,97cyclictest0-21swapper/2711:15:2120
12334991951,97cyclictest0-21swapper/2711:15:2120
1233499191146,36cyclictest0-21swapper/2711:23:2920
1233499191146,36cyclictest0-21swapper/2711:23:2920
1232699189142,28cyclictest0-21swapper/2011:04:3213
1232699189142,28cyclictest0-21swapper/2011:04:3213
1232399188160,13cyclictest0-21swapper/1707:30:079
1232399188160,13cyclictest0-21swapper/1707:30:079
1232799187156,14cyclictest171rcu_preempt09:01:4214
1232799187156,14cyclictest171rcu_preempt09:01:4214
1232799185175,6cyclictest37354-21CPU14
1232799185175,6cyclictest37354-21CPU14
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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