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2026-05-10 - 04:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun May 10, 2026 01:01:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1805599220209,8cyclictest20255-21sshd21:32:5026
1805599220209,8cyclictest20255-21sshd21:32:5026
1805599218211,5cyclictest0-21swapper/3200:10:0026
1805599218211,5cyclictest0-21swapper/3200:10:0026
1805599216209,5cyclictest0-21swapper/3222:01:2126
1805599216209,5cyclictest0-21swapper/3222:01:2126
1805599215209,5cyclictest0-21swapper/3219:40:0026
1805599215209,5cyclictest0-21swapper/3219:40:0026
1805599215207,5cyclictest1-21systemd00:00:2626
1805599215207,5cyclictest1-21systemd00:00:2526
1805599213208,4cyclictest0-21swapper/3223:15:2426
1805599213208,4cyclictest0-21swapper/3223:15:2426
1805599211201,8cyclictest0-21swapper/3223:53:4026
1805599211201,8cyclictest0-21swapper/3223:53:4026
1805599208204,2cyclictest27061-21ls21:10:1526
1805599208204,2cyclictest27061-21ls21:10:1526
1805599208200,6cyclictest0-21swapper/3222:52:4726
1805599208200,6cyclictest0-21swapper/3222:52:4626
1805599207202,4cyclictest0-21swapper/3221:28:5926
1805599207202,4cyclictest0-21swapper/3221:28:5926
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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