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2026-08-14 - 15:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Aug 14, 2026 13:02:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3122399194187,4cyclictest17483-21nfsd09:58:2321
3122399194187,4cyclictest17483-21nfsd09:58:2321
31213991941,2cyclictest0-21swapper/1911:20:0111
31213991941,2cyclictest0-21swapper/1911:20:0011
3122399190169,17cyclictest0-21swapper/2811:46:4921
3122399190169,17cyclictest0-21swapper/2811:46:4921
3120499190186,2cyclictest0-21swapper/1212:00:204
3120499190186,2cyclictest0-21swapper/1212:00:194
3120799187181,5cyclictest0-21swapper/1410:56:076
3120799187181,5cyclictest0-21swapper/1410:56:076
3120799187181,5cyclictest0-21swapper/1410:56:076
312239918694,87cyclictest2462-21CPU21
312239918694,87cyclictest2462-21CPU21
3122099186178,4cyclictest3543-21CPU18
3122099186178,4cyclictest3543-21CPU18
3122099186178,4cyclictest3543-21CPU18
3122399179165,11cyclictest0-21swapper/2807:20:2021
3122399179165,11cyclictest0-21swapper/2807:20:2021
3120799179172,5cyclictest0-21swapper/1411:34:516
3120799179172,5cyclictest0-21swapper/1411:34:516
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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