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2026-06-12 - 02:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Jun 12, 2026 01:02:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1289399206196,8cyclictest0-21swapper/2600:15:4219
1289399206196,8cyclictest0-21swapper/2600:15:4219
1289399206196,8cyclictest0-21swapper/2600:15:4219
1289399203192,9cyclictest0-21swapper/2623:34:4019
1289399203192,9cyclictest0-21swapper/2623:34:4019
1289399203192,8cyclictest4398-21qemu-system-x8621:37:4519
1289399203192,8cyclictest4398-21qemu-system-x8621:37:4519
1289399203192,8cyclictest4398-21qemu-system-x8621:37:4519
1289399202196,4cyclictest0-21swapper/2622:16:4719
1289399202196,4cyclictest0-21swapper/2622:16:4719
1289399201191,7cyclictest0-21swapper/2600:06:5019
1289399201191,7cyclictest0-21swapper/2600:06:5019
1289399201191,7cyclictest0-21swapper/2600:06:4919
1287299199195,2cyclictest0-21swapper/820:10:1538
1289399198192,4cyclictest0-21swapper/2621:49:1819
1289399198192,4cyclictest0-21swapper/2621:49:1819
1290099197188,4cyclictest0-21swapper/3121:45:5025
1290099197188,4cyclictest0-21swapper/3121:45:5025
1289399196187,5cyclictest0-21swapper/2622:50:2119
1289399196187,5cyclictest0-21swapper/2622:50:2019
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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