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2026-06-14 - 19:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Jun 14, 2026 13:02:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1479399202191,8cyclictest0-21swapper/611:47:0436
1479399202191,8cyclictest0-21swapper/611:47:0336
1479399202191,8cyclictest0-21swapper/611:47:0336
1479399201197,2cyclictest0-21swapper/611:35:1936
1479399201197,2cyclictest0-21swapper/611:35:1936
1479399201197,2cyclictest0-21swapper/611:35:1936
1479299200182,15cyclictest0-21swapper/512:00:3735
1479299200182,15cyclictest0-21swapper/512:00:3735
1479299200182,15cyclictest0-21swapper/512:00:3635
14822991961,183cyclictest0-21swapper/2912:10:1422
14822991961,183cyclictest0-21swapper/2912:10:1422
14822991961,183cyclictest0-21swapper/2912:10:1322
1483199195185,8cyclictest0-21swapper/3810:40:4132
1483199195185,8cyclictest0-21swapper/3810:40:4132
1483199195185,8cyclictest0-21swapper/3810:40:4132
1482899195190,4cyclictest0-21swapper/3512:21:5829
1482899195190,4cyclictest0-21swapper/3512:21:5729
1482599194141,40cyclictest0-21swapper/3209:55:3426
1482599194141,40cyclictest0-21swapper/3209:55:3426
1482599194141,40cyclictest0-21swapper/3209:55:3426
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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