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2026-09-17 - 13:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Sep 17, 2026 01:02:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114699223199,20cyclictest0-21swapper/3223:20:0126
114699223199,20cyclictest0-21swapper/3223:20:0126
114699217204,11cyclictest0-21swapper/3223:20:2226
114699217204,11cyclictest0-21swapper/3223:20:2226
114899214204,8cyclictest0-21swapper/3419:15:2228
114899214204,8cyclictest0-21swapper/3419:15:2228
110899214207,5cyclictest0-21swapper/100:06:501
110899214207,5cyclictest0-21swapper/100:06:491
114899213207,4cyclictest0-21swapper/3422:13:2628
114899213207,4cyclictest0-21swapper/3422:13:2628
114899213202,9cyclictest0-21swapper/3423:00:1328
114899213202,9cyclictest0-21swapper/3423:00:1328
114899209202,6cyclictest0-21swapper/3423:50:3328
114899209202,6cyclictest0-21swapper/3423:50:3328
114899209193,13cyclictest0-21swapper/3421:20:1728
114899209193,13cyclictest0-21swapper/3421:20:1628
114899205180,5cyclictest0-21swapper/3420:00:2628
114899205180,5cyclictest0-21swapper/3420:00:2628
110899205200,3cyclictest0-21swapper/100:00:251
110899205200,3cyclictest0-21swapper/100:00:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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