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2026-06-19 - 14:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Jun 19, 2026 01:01:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2733199211199,10cyclictest0-21swapper/3122:12:5625
2733199211199,10cyclictest0-21swapper/3122:12:5625
2733199211199,10cyclictest0-21swapper/3122:12:5625
2733599205195,7cyclictest0-21swapper/3321:20:1827
2733599205195,7cyclictest0-21swapper/3321:20:1727
2733599200194,5cyclictest0-21swapper/3300:12:0727
2733599200194,5cyclictest0-21swapper/3300:12:0727
2733599197190,5cyclictest0-21swapper/3321:27:0427
2733599197190,5cyclictest0-21swapper/3321:27:0427
2733599197190,5cyclictest0-21swapper/3300:02:1227
2733599197190,5cyclictest0-21swapper/3300:02:1227
2733599197190,5cyclictest0-21swapper/3300:02:1227
2730099193168,13cyclictest755-21systemd-journal23:13:0239
2730099193168,13cyclictest755-21systemd-journal23:13:0239
2733599192177,8cyclictest0-21swapper/3323:49:3427
2733599192177,8cyclictest0-21swapper/3323:49:3427
2733599191186,4cyclictest0-21swapper/3321:59:0027
2733599191186,4cyclictest0-21swapper/3321:58:5927
2734199189167,12cyclictest0-21swapper/3800:15:0932
2734199189167,12cyclictest0-21swapper/3800:15:0932
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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