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2025-11-16 - 06:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Nov 16, 2025 01:00:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
546299252230,4cyclictest12297-21TaskSchedulerSi22:55:2328
546299252230,4cyclictest12297-21TaskSchedulerSi22:55:2328
546399242237,3cyclictest0-21swapper/3522:05:2129
546399242237,3cyclictest0-21swapper/3522:05:2129
546399242237,3cyclictest0-21swapper/3522:05:2129
543699232214,10cyclictest171rcu_preempt19:46:114
543199228207,5cyclictest11904-21CPU39
543199228207,5cyclictest11904-21CPU39
544199227210,5cyclictest11905-21CPU9
544199227210,5cyclictest11905-21CPU9
544199227210,5cyclictest11905-21CPU9
54629922375,128cyclictest15978-21CPU28
54629922375,128cyclictest15978-21CPU28
543699211194,3cyclictest28343-21NetworkChangeNo23:50:194
543699211194,3cyclictest28343-21NetworkChangeNo23:50:194
543699211192,5cyclictest0-21swapper/1219:35:214
34172992040,90rtkit-daemon15978-21CPU26
34172992040,90rtkit-daemon15978-21CPU26
546499203134,63cyclictest0-21swapper/3623:45:2830
546499203134,63cyclictest0-21swapper/3623:45:2830
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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