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2025-11-16 - 19:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Nov 16, 2025 13:01:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3854099254223,15cyclictest38025-21NetworkChangeNo11:50:2030
3854099254223,15cyclictest38025-21NetworkChangeNo11:50:2030
3854099254223,15cyclictest38025-21NetworkChangeNo11:50:2030
3852999248220,8cyclictest0-21swapper/2609:55:2019
3852999248220,8cyclictest0-21swapper/2609:55:2019
38533992164,4cyclictest9189-21inotify_reader07:45:2024
38533992164,4cyclictest9189-21inotify_reader07:45:2024
3850699207200,6cyclictest0-21swapper/710:08:0537
3850699207200,6cyclictest0-21swapper/710:08:0537
3850699207200,6cyclictest0-21swapper/710:08:0537
3850199207198,6cyclictest4996-21kworker/u81:2-events_unbound11:30:4334
3850199207198,6cyclictest4996-21kworker/u81:2-events_unbound11:30:4334
3852999204197,5cyclictest0-21swapper/2610:23:3919
3852999204197,5cyclictest0-21swapper/2610:23:3919
3852999204197,5cyclictest0-21swapper/2610:23:3919
3849899204194,6cyclictest2478-21kworker/u81:0-writeback11:51:4412
3849899204194,6cyclictest2478-21kworker/u81:0-writeback11:51:4412
3849899204194,6cyclictest2478-21kworker/u81:0-writeback11:51:4412
3851999201190,9cyclictest0-21swapper/1808:51:1610
3851999201190,9cyclictest0-21swapper/1808:51:1610
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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