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2026-05-15 - 04:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri May 15, 2026 01:02:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16268992571,245cyclictest0-21swapper/2921:10:0222
16268992571,245cyclictest0-21swapper/2921:10:0222
16268992571,245cyclictest0-21swapper/2921:10:0222
16268992571,245cyclictest0-21swapper/2921:10:0222
16268992561,2cyclictest0-21swapper/2923:32:4222
16268992561,2cyclictest0-21swapper/2923:32:4222
16268992471,2cyclictest0-21swapper/2900:10:1222
16268992471,2cyclictest0-21swapper/2900:10:1122
1623899247163,72cyclictest1035-21kworker/u81:5+events_unbound00:10:0623
1623899247163,72cyclictest1035-21kworker/u81:5+events_unbound00:10:0523
16268992431,2cyclictest0-21swapper/2921:40:1322
16268992431,2cyclictest0-21swapper/2921:40:1322
16268992431,2cyclictest0-21swapper/2921:40:1322
16268992421,238cyclictest0-21swapper/2922:45:1822
16268992421,238cyclictest0-21swapper/2922:45:1722
16268992361,2cyclictest0-21swapper/2923:41:5422
16268992361,2cyclictest0-21swapper/2923:41:5322
16268992361,2cyclictest0-21swapper/2923:41:5322
16268992350,230cyclictest0-21swapper/2921:10:3422
16268992350,230cyclictest0-21swapper/2921:10:3422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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