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2026-07-04 - 07:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat Jul 04, 2026 01:01:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1890799250245,3cyclictest0-21swapper/819:50:1638
1890799250245,3cyclictest0-21swapper/819:50:1638
1890099230223,5cyclictest0-21swapper/323:00:1223
1890099230223,5cyclictest0-21swapper/323:00:1223
1890399217192,6cyclictest0-21swapper/522:42:5835
1890399217192,6cyclictest0-21swapper/522:42:5835
1890399217192,6cyclictest0-21swapper/522:42:5735
1893699216204,10cyclictest37257-21qemu-system-x8623:20:1227
1893699216204,10cyclictest37257-21qemu-system-x8623:20:1127
1890399216193,4cyclictest0-21swapper/500:25:5235
1890399216193,4cyclictest0-21swapper/500:25:5235
1890099216207,7cyclictest0-21swapper/322:20:4523
1890099216207,7cyclictest0-21swapper/322:20:4523
1890099216204,10cyclictest0-21swapper/300:34:2723
1890099216204,10cyclictest0-21swapper/300:34:2723
1894199215199,10cyclictest0-21swapper/3722:06:1931
1894199215199,10cyclictest0-21swapper/3722:06:1931
1890099215202,11cyclictest0-21swapper/323:47:2023
1890099215202,11cyclictest0-21swapper/323:47:2023
1890099215200,13cyclictest0-21swapper/323:15:2523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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