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2026-06-17 - 23:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Jun 17, 2026 13:03:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3893199233211,19cyclictest0-21swapper/010:30:370
3893199233211,19cyclictest0-21swapper/010:30:370
3895999226206,10cyclictest171rcu_preempt09:37:4518
3895999226206,10cyclictest171rcu_preempt09:37:4518
3895999226206,10cyclictest171rcu_preempt09:37:4518
3893299211193,12cyclictest0-21swapper/111:20:121
3893299211193,12cyclictest0-21swapper/111:20:121
3893299211193,12cyclictest0-21swapper/111:20:111
3893199209171,30cyclictest0-21swapper/011:52:090
3893199209171,30cyclictest0-21swapper/011:52:080
3893299208201,5cyclictest0-21swapper/109:10:171
3893299208201,5cyclictest0-21swapper/109:10:171
3893299208201,5cyclictest0-21swapper/109:10:161
3893299204196,6cyclictest0-21swapper/111:18:111
3893299204196,6cyclictest0-21swapper/111:18:111
3893299204196,6cyclictest0-21swapper/111:18:111
3893299203194,6cyclictest40448-21tr09:20:131
3893299203194,6cyclictest40448-21tr09:20:131
3893299203194,6cyclictest40448-21tr09:20:121
3894499201177,19cyclictest3544-21CPU4
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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