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2026-04-01 - 18:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Apr 01, 2026 13:03:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
279399230216,12cyclictest0-21swapper/2311:05:2016
279399230216,12cyclictest0-21swapper/2311:05:1916
279399230216,12cyclictest0-21swapper/2311:05:1916
279399215204,7cyclictest0-21swapper/2310:14:5316
279399215204,7cyclictest0-21swapper/2310:14:5316
279399215204,7cyclictest0-21swapper/2310:14:5316
279399214198,12cyclictest0-21swapper/2311:35:2216
279399214198,12cyclictest0-21swapper/2311:35:2116
279399210199,8cyclictest0-21swapper/2311:00:2216
279399210199,8cyclictest0-21swapper/2311:00:2216
279399210199,8cyclictest0-21swapper/2311:00:2216
279399208198,8cyclictest0-21swapper/2312:34:0316
279399208198,8cyclictest0-21swapper/2312:34:0316
279299206199,6cyclictest0-21swapper/2210:25:3615
279299206199,6cyclictest0-21swapper/2210:25:3615
279299206199,6cyclictest0-21swapper/2210:25:3515
279399201192,6cyclictest1-21systemd10:54:1116
279399201192,6cyclictest1-21systemd10:54:1016
279399201192,6cyclictest1-21systemd10:54:1016
279399198191,4cyclictest0-21swapper/2312:40:0116
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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