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2026-01-29 - 04:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Jan 29, 2026 00:59:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
124599212180,17cyclictest0-21swapper/3923:20:0133
124599212180,17cyclictest0-21swapper/3923:20:0133
120999209187,10cyclictest0-21swapper/923:08:1839
120999209187,10cyclictest0-21swapper/923:08:1739
121399206195,10cyclictest0-21swapper/1323:37:035
121399206195,10cyclictest0-21swapper/1323:37:035
124599204196,5cyclictest0-21swapper/3900:19:4533
124599204196,5cyclictest0-21swapper/3900:19:4533
124599204196,5cyclictest0-21swapper/3900:19:4533
120999204180,22cyclictest0-21swapper/923:12:3639
120999204180,22cyclictest0-21swapper/923:12:3639
120599203182,19cyclictest0-21swapper/523:05:2835
120599203182,19cyclictest0-21swapper/523:05:2835
124599202189,11cyclictest0-21swapper/3923:51:5733
124599202189,11cyclictest0-21swapper/3923:51:5733
124599201194,5cyclictest0-21swapper/3923:14:3633
124599201194,5cyclictest0-21swapper/3923:14:3633
120999201168,11cyclictest0-21swapper/923:44:5239
120999201168,11cyclictest0-21swapper/923:44:5239
120799201190,9cyclictest0-21swapper/721:31:0637
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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