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2026-03-19 - 07:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Mar 19, 2026 01:02:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2135999219212,5cyclictest0-21swapper/3822:10:1132
2135999219212,5cyclictest0-21swapper/3822:10:1132
2135999219212,5cyclictest0-21swapper/3822:10:1132
2135999218197,19cyclictest0-21swapper/3820:35:0232
2135999218197,19cyclictest0-21swapper/3820:35:0232
2135999214206,4cyclictest3544-21CPU32
2135999214206,4cyclictest3544-21CPU32
2135999214206,4cyclictest3544-21CPU32
2135999212204,6cyclictest0-21swapper/3800:30:0132
2135999212204,6cyclictest0-21swapper/3800:30:0132
2135999210207,2cyclictest0-21swapper/3820:20:1032
2135999210207,2cyclictest0-21swapper/3820:20:1032
2135999209204,4cyclictest0-21swapper/3821:58:2232
2135999209204,4cyclictest0-21swapper/3821:58:2232
2135999209204,4cyclictest0-21swapper/3821:58:2232
2135999207200,5cyclictest0-21swapper/3820:47:3132
2135999207200,5cyclictest0-21swapper/3820:47:3132
2135999203200,2cyclictest0-21swapper/3800:35:2132
2135999203200,2cyclictest0-21swapper/3800:35:2032
2135999203193,8cyclictest23838-2110-uname22:19:1932
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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