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2026-09-17 - 01:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Sep 16, 2026 13:03:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1674499227202,23cyclictest0-21swapper/3812:40:0732
1674499222207,11cyclictest0-21swapper/3809:52:3232
1674499222207,11cyclictest0-21swapper/3809:52:3232
1674499221208,8cyclictest0-21swapper/3810:15:2732
1674499221208,8cyclictest0-21swapper/3810:15:2732
1674499221208,8cyclictest0-21swapper/3810:15:2732
1674499221195,16cyclictest0-21swapper/3809:00:1732
1674499221195,16cyclictest0-21swapper/3809:00:1632
1674499220203,11cyclictest0-21swapper/3809:40:1632
1674499220203,11cyclictest0-21swapper/3809:40:1632
1674499220203,11cyclictest0-21swapper/3809:40:1632
1674499219193,19cyclictest0-21swapper/3810:25:1132
1674499219193,19cyclictest0-21swapper/3810:25:1132
1674499219188,19cyclictest0-21swapper/3809:21:0032
1674499219188,19cyclictest0-21swapper/3809:21:0032
1674499219188,19cyclictest0-21swapper/3809:21:0032
1674499218200,13cyclictest0-21swapper/3809:10:1232
1674499218200,13cyclictest0-21swapper/3809:10:1232
1673399218209,5cyclictest37268-21CPU24
1674499215196,11cyclictest0-21swapper/3811:55:1232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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