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2026-05-09 - 15:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sat May 09, 2026 13:03:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
675199228208,6cyclictest0-21swapper/3412:06:5028
675199228208,6cyclictest0-21swapper/3412:06:5028
675199228208,6cyclictest0-21swapper/3412:06:4928
672399225221,2cyclictest0-21swapper/1008:20:142
673699221202,10cyclictest0-21swapper/2012:04:2513
673699221202,10cyclictest0-21swapper/2012:04:2413
673599218212,4cyclictest0-21swapper/1912:32:0711
673599218212,4cyclictest0-21swapper/1912:32:0611
671399217198,9cyclictest0-21swapper/109:18:461
671399217198,9cyclictest0-21swapper/109:18:451
675199215207,6cyclictest0-21swapper/3411:40:1828
675199215207,6cyclictest0-21swapper/3411:40:1728
675199215207,6cyclictest0-21swapper/3411:40:1728
672099213170,16cyclictest171rcu_preempt09:28:4638
672099213170,16cyclictest171rcu_preempt09:28:4638
672099213170,16cyclictest171rcu_preempt09:28:4538
671399211205,4cyclictest0-21swapper/109:22:221
671399211205,4cyclictest0-21swapper/109:22:221
674299208168,37cyclictest0-21swapper/2611:53:1619
674299208168,37cyclictest0-21swapper/2611:53:1619
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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