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2026-07-10 - 17:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Fri Jul 10, 2026 13:02:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3722899226221,3cyclictest4398-21qemu-system-x8612:20:2132
3722899226221,3cyclictest4398-21qemu-system-x8612:20:2132
3719899212146,62cyclictest3544-21CPU7
3719899212146,62cyclictest3544-21CPU7
3720899208160,43cyclictest0-21swapper/2411:44:4717
3720899208160,43cyclictest0-21swapper/2411:44:4617
3718199202191,6cyclictest0-21swapper/110:04:391
3718199202191,6cyclictest0-21swapper/110:04:381
3720499201189,9cyclictest0-21swapper/2010:33:4813
3720499201189,9cyclictest0-21swapper/2010:33:4813
3720499201189,9cyclictest0-21swapper/2010:33:4713
37180991990,175cyclictest0-21swapper/009:51:250
37180991990,175cyclictest0-21swapper/009:51:250
37180991990,175cyclictest0-21swapper/009:51:240
3718099198164,31cyclictest0-21swapper/011:01:580
3718099198164,31cyclictest0-21swapper/011:01:580
3720899197118,68cyclictest0-21swapper/2411:17:5817
3720899197118,68cyclictest0-21swapper/2411:17:5817
3721599195180,5cyclictest0-21swapper/3010:45:1224
3721599195180,5cyclictest0-21swapper/3010:45:1124
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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