You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-01 - 06:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Feb 01, 2026 01:00:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3069799242229,8cyclictest1382-21in:imuxsock23:29:1834
3069799242229,8cyclictest1382-21in:imuxsock23:29:1834
3069799242229,8cyclictest1382-21in:imuxsock23:29:1834
3069799241230,9cyclictest0-21swapper/421:16:3234
3069799241230,9cyclictest0-21swapper/421:16:3234
3069799241230,9cyclictest0-21swapper/421:16:3234
3069799241230,6cyclictest0-21swapper/423:01:4434
3069799241230,6cyclictest0-21swapper/423:01:4434
3069799240226,12cyclictest0-21swapper/422:26:2534
3069799240226,12cyclictest0-21swapper/422:26:2534
3069799239227,8cyclictest0-21swapper/421:25:1534
3069799239227,8cyclictest0-21swapper/421:25:1534
3069799237211,24cyclictest0-21swapper/422:50:1934
3069799237211,24cyclictest0-21swapper/422:50:1934
3069799237211,24cyclictest0-21swapper/422:50:1934
3069799231223,4cyclictest4408-21CPU34
3069799231223,4cyclictest4408-21CPU34
3069799231223,4cyclictest4408-21CPU34
3069799226220,4cyclictest0-21swapper/422:30:5434
3069799226220,4cyclictest0-21swapper/422:30:5434
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional