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2026-07-23 - 07:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Jul 23, 2026 01:00:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2774299216208,3cyclictest4407-21CPU36
2774299216208,3cyclictest4407-21CPU36
2774299216208,3cyclictest4407-21CPU36
27741992102,4cyclictest3545-21CPU35
27741992102,4cyclictest3545-21CPU35
2774699208200,6cyclictest0-21swapper/1000:16:182
2774699208200,6cyclictest0-21swapper/1000:16:182
2773399208201,3cyclictest4408-21CPU0
2773399208201,3cyclictest4408-21CPU0
2777299206191,11cyclictest0-21swapper/3300:32:2327
2777299206191,11cyclictest0-21swapper/3300:32:2227
2777299205200,4cyclictest0-21swapper/3321:46:4227
2777299205200,4cyclictest0-21swapper/3321:46:4227
27734992044,5cyclictest4408-21CPU1
27734992044,5cyclictest4408-21CPU1
27734992044,5cyclictest4408-21CPU1
2777399203195,6cyclictest0-21swapper/3419:31:1428
2777099201126,71cyclictest2461-21CPU25
2777099201126,71cyclictest2461-21CPU25
2777099201126,71cyclictest2461-21CPU25
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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