You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-04 - 06:33
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Tue Nov 04, 2025 01:00:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3941899248220,12cyclictest34994-21inotify_reader21:45:2022
3941899248220,12cyclictest34994-21inotify_reader21:45:2022
3941899248220,12cyclictest34994-21inotify_reader21:45:2022
3940499241217,11cyclictest17284-21NetworkChangeNo19:15:0211
3940499241217,11cyclictest17284-21NetworkChangeNo19:15:0211
3941899236197,22cyclictest0-21swapper/2921:25:2122
3941899236197,22cyclictest0-21swapper/2921:25:2122
3941899236197,22cyclictest0-21swapper/2921:25:2022
3942899232213,9cyclictest13403-21NetworkChangeNo22:00:2032
3942899232213,9cyclictest13403-21NetworkChangeNo22:00:1932
3942899232213,9cyclictest13403-21NetworkChangeNo22:00:1932
3941899232218,9cyclictest11952-21TaskSchedulerSi21:00:1822
3941899232218,9cyclictest11952-21TaskSchedulerSi21:00:1822
394149923148,56cyclictest0-21swapper/2622:05:2119
394149923148,56cyclictest0-21swapper/2622:05:2019
3941899230214,12cyclictest0-21swapper/2922:55:2122
3941899230214,12cyclictest0-21swapper/2922:55:2122
3941899230214,12cyclictest0-21swapper/2922:55:2122
39427992222,88cyclictest4633-21CPU31
39427992222,88cyclictest4633-21CPU31
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional