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2026-05-25 - 14:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon May 25, 2026 13:02:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2015299256252,2cyclictest0-21swapper/1212:00:164
2015299256252,2cyclictest0-21swapper/1212:00:154
2015299256252,2cyclictest0-21swapper/1212:00:154
2015399228221,5cyclictest0-21swapper/1310:02:385
2015399228221,5cyclictest0-21swapper/1310:02:385
2014099227223,3cyclictest17480-21nfsd10:52:5323
2014099227223,3cyclictest17480-21nfsd10:52:5323
2017699213184,19cyclictest0-21swapper/3311:03:4627
2017699213184,19cyclictest0-21swapper/3311:03:4627
2018399210203,5cyclictest24952-21packagekitd11:54:2933
2018399210203,5cyclictest24952-21packagekitd11:54:2933
2015099210204,4cyclictest0-21swapper/1009:46:082
2015099210204,4cyclictest0-21swapper/1009:46:082
2015099210204,4cyclictest0-21swapper/1009:46:082
2015099209202,5cyclictest0-21swapper/1009:40:042
2015099209202,5cyclictest0-21swapper/1009:40:042
2015099208200,5cyclictest0-21swapper/1007:40:182
2015099208200,5cyclictest0-21swapper/1007:40:182
2015099206198,4cyclictest26879-21systemd-cgroups10:19:412
2015099206198,4cyclictest26879-21systemd-cgroups10:19:412
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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