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2026-06-24 - 08:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Wed Jun 24, 2026 01:01:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
509199194182,9cyclictest0-21swapper/3921:00:1233
509199194182,9cyclictest0-21swapper/3921:00:1133
509199193184,6cyclictest4362-21fschecks_count20:05:1733
509199193184,6cyclictest4362-21fschecks_count20:05:1733
509199191182,7cyclictest142350irq/45-eno1-TxRx-300:00:1433
509199191182,7cyclictest142350irq/45-eno1-TxRx-300:00:1433
509199191181,6cyclictest0-21swapper/3922:20:2233
509199191181,6cyclictest0-21swapper/3922:20:2133
509199191181,6cyclictest0-21swapper/3922:20:2133
509199189177,10cyclictest0-21swapper/3923:05:1333
509199189177,10cyclictest0-21swapper/3923:05:1333
509199188181,5cyclictest0-21swapper/3922:15:1633
509199188181,5cyclictest0-21swapper/3922:15:1633
509199187165,13cyclictest0-21swapper/3922:29:0933
509199187165,13cyclictest0-21swapper/3922:29:0933
5075991871,100cyclictest0-21swapper/2620:00:2519
5075991871,100cyclictest0-21swapper/2620:00:2519
509199184178,3cyclictest2459-21CPU33
509199184178,3cyclictest2459-21CPU33
509199184178,3cyclictest2459-21CPU33
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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