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2026-09-20 - 23:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Sep 20, 2026 13:02:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2154299208187,13cyclictest1300-21cpuspeed_turbos10:00:1323
2154299208187,13cyclictest1300-21cpuspeed_turbos10:00:1323
2154299208187,13cyclictest1300-21cpuspeed_turbos10:00:1323
2155299195156,21cyclictest0-21swapper/1112:26:053
2155299195156,21cyclictest0-21swapper/1112:26:053
2155299195156,21cyclictest0-21swapper/1112:26:043
2155599191185,4cyclictest4266-21sh10:00:216
2155599191185,4cyclictest4266-21sh10:00:216
2155599191185,4cyclictest4266-21sh10:00:206
2157899190130,14cyclictest0-21swapper/3211:03:2326
2157899190130,14cyclictest0-21swapper/3211:03:2326
2156099190110,70cyclictest2464-21CPU11
2156099190110,70cyclictest2464-21CPU11
2154299189172,15cyclictest0-21swapper/309:05:1923
2154299189172,15cyclictest0-21swapper/309:05:1923
2157299188150,7cyclictest171rcu_preempt11:49:3421
2157299188150,7cyclictest171rcu_preempt11:49:3421
215689918861,57cyclictest2462-21CPU18
215689918861,57cyclictest2462-21CPU18
2156799187178,7cyclictest0-21swapper/2410:48:4617
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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