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2026-06-11 - 14:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Thu Jun 11, 2026 13:03:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2968099227207,5cyclictest31410-21sshd09:25:1831
2968099227207,5cyclictest31410-21sshd09:25:1731
2968099227207,5cyclictest31410-21sshd09:25:1731
2964999220180,26cyclictest1392-21gdbus11:40:043
2964999220180,26cyclictest1392-21gdbus11:40:043
2964999220180,26cyclictest1392-21gdbus11:40:033
2968299210193,7cyclictest0-21swapper/3911:06:0233
2968299210193,7cyclictest0-21swapper/3911:06:0233
2968299210193,7cyclictest0-21swapper/3911:06:0133
2964299209202,4cyclictest2454-21CPU35
2964299209202,4cyclictest2454-21CPU35
2964599208203,4cyclictest0-21swapper/812:04:0838
2964599208203,4cyclictest0-21swapper/812:04:0838
2964599208203,4cyclictest0-21swapper/812:04:0838
2966799207143,59cyclictest4408-21CPU18
2966799207143,59cyclictest4408-21CPU18
2966799207143,59cyclictest4408-21CPU18
2964599206193,11cyclictest0-21swapper/811:22:1438
2964599206193,11cyclictest0-21swapper/811:22:1338
2966999205197,4cyclictest1367-21dbus-daemon09:20:1120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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