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2026-07-05 - 22:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Sun Jul 05, 2026 13:01:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4073599220213,2cyclictest0-21swapper/3211:20:0026
4073599220213,2cyclictest0-21swapper/3211:20:0026
4072599215201,6cyclictest0-21swapper/2211:11:5815
4072599215201,6cyclictest0-21swapper/2211:11:5815
4073999206197,2cyclictest0-21swapper/3609:36:0230
4073999206197,2cyclictest0-21swapper/3609:36:0230
4073999206197,2cyclictest0-21swapper/3609:36:0230
4072599199189,6cyclictest3546-21CPU15
4072599199189,6cyclictest3546-21CPU15
4072599199189,6cyclictest3546-21CPU15
4072599198184,6cyclictest0-21swapper/2209:40:1515
4072599198184,6cyclictest0-21swapper/2209:40:1515
4072599198184,6cyclictest0-21swapper/2209:40:1415
4072599197184,11cyclictest0-21swapper/2211:09:2715
4072599197184,11cyclictest0-21swapper/2211:09:2615
4072599196182,12cyclictest0-21swapper/2211:04:5515
4072599196182,12cyclictest0-21swapper/2211:04:5515
4072499194173,12cyclictest0-21swapper/2111:53:4714
4072499194173,12cyclictest0-21swapper/2111:53:4614
4072899193179,4cyclictest171rcu_preempt12:08:2718
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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