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2026-07-20 - 14:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot0.osadl.org (updated Mon Jul 20, 2026 13:01:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3598699222214,5cyclictest31747-21sshd10:00:1427
3598699222214,5cyclictest31747-21sshd10:00:1427
3598699222214,5cyclictest31747-21sshd10:00:1427
3598699216194,13cyclictest0-21swapper/3309:50:2727
3598699216194,13cyclictest0-21swapper/3309:50:2727
3598699215203,9cyclictest0-21swapper/3309:40:0627
3598699215203,9cyclictest0-21swapper/3309:40:0627
3598699214200,12cyclictest0-21swapper/3309:40:1827
3598699214200,12cyclictest0-21swapper/3309:40:1827
3598699213198,9cyclictest0-21swapper/3310:27:2927
3598699213198,9cyclictest0-21swapper/3310:27:2927
3598699213197,9cyclictest0-21swapper/3309:31:1027
3598699213197,9cyclictest0-21swapper/3309:31:0927
3598699212203,7cyclictest0-21swapper/3309:45:1527
3598699212203,7cyclictest0-21swapper/3309:45:1427
3598699212198,8cyclictest0-21swapper/3310:20:5327
3598699212198,8cyclictest0-21swapper/3310:20:5227
3598699212198,8cyclictest0-21swapper/3310:20:5227
3598699211204,5cyclictest0-21swapper/3310:05:1227
3598699211204,5cyclictest0-21swapper/3310:05:1127
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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