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2026-06-02 - 00:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Mon Jun 01, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
269732478,8sleep00-21swapper/007:03:230
272442428,8sleep10-21swapper/107:06:151
27439993534,0cyclictest168750irq/16-i91509:48:271
27439993433,0cyclictest168750irq/16-i91511:55:401
27439993433,0cyclictest168750irq/16-i91510:52:571
27439993433,0cyclictest168750irq/16-i91509:26:581
27438993433,0cyclictest246650irq/16-enp2s0f012:35:210
27438993433,0cyclictest246650irq/16-enp2s0f010:50:080
27438993433,0cyclictest246650irq/16-enp2s0f009:33:030
27438993433,0cyclictest246650irq/16-enp2s0f009:31:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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