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2025-12-06 - 00:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Fri Dec 05, 2025 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
199892610,0sleep10-21swapper/110:17:081
670624512,8sleep10-21swapper/106:57:281
709724124,8sleep00-21swapper/007:01:270
7201993932,6cyclictest245950irq/16-enp2s0f011:52:110
7201993932,6cyclictest245950irq/16-enp2s0f009:42:080
7201993932,6cyclictest245950irq/16-enp2s0f008:01:240
7201993932,6cyclictest245950irq/16-enp2s0f007:36:280
7201993832,5cyclictest245950irq/16-enp2s0f007:39:030
7201993831,6cyclictest245950irq/16-enp2s0f012:27:060
7201993831,6cyclictest245950irq/16-enp2s0f012:01:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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