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2026-06-23 - 06:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Jun 23, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325232479,8sleep00-21swapper/019:02:430
549993534,0cyclictest168750irq/16-i91519:20:491
549993433,0cyclictest168750irq/16-i91500:19:061
548993434,0cyclictest246650irq/16-enp2s0f020:47:480
548993433,0cyclictest246650irq/16-enp2s0f023:48:270
548993433,0cyclictest246650irq/16-enp2s0f019:10:290
548993432,1cyclictest246650irq/16-enp2s0f023:41:090
548993432,1cyclictest246650irq/16-enp2s0f021:47:110
548993432,1cyclictest246650irq/16-enp2s0f019:26:260
3268623413,13sleep10-21swapper/119:04:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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