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2026-09-22 - 21:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Sep 22, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
183752600,0sleep00-21swapper/010:55:240
198042449,8sleep00-21swapper/007:00:550
199632428,8sleep10-21swapper/107:02:351
20295993534,0cyclictest246650irq/16-enp2s0f011:47:380
20295993534,0cyclictest246650irq/16-enp2s0f009:39:250
20296993432,1cyclictest168750irq/16-i91511:30:111
20295993433,0cyclictest246650irq/16-enp2s0f008:12:490
20295993432,1cyclictest246650irq/16-enp2s0f012:08:350
20295993432,1cyclictest168750irq/16-i91507:52:450
20296993333,0cyclictest168750irq/16-i91509:08:561
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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