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2025-05-09 - 06:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Fri May 09, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121832488,8sleep00-21swapper/019:03:080
1213124428,8sleep10-21swapper/119:02:371
12517994232,9cyclictest245950irq/16-enp2s0f021:41:180
12517993931,7cyclictest245950irq/16-enp2s0f023:46:250
12517993931,7cyclictest245950irq/16-enp2s0f023:23:250
12517993931,7cyclictest245950irq/16-enp2s0f019:11:150
12517993831,6cyclictest245950irq/16-enp2s0f021:36:120
12517993831,6cyclictest245950irq/16-enp2s0f021:26:200
12517993831,6cyclictest245950irq/16-enp2s0f019:31:170
12517993830,7cyclictest245950irq/16-enp2s0f023:56:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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