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2025-11-17 - 13:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Mon Nov 17, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1217724513,8sleep00-21swapper/019:00:160
119622438,8sleep10-21swapper/118:58:071
12432993932,6cyclictest245950irq/16-enp2s0f020:41:580
12432993634,1cyclictest245950irq/16-enp2s0f022:37:130
12433993534,0cyclictest167950irq/16-i91519:30:181
12433993534,0cyclictest167950irq/16-i91500:09:311
12432993534,0cyclictest245950irq/16-enp2s0f000:09:310
12433993433,0cyclictest167950irq/16-i91519:36:111
12433993432,1cyclictest167950irq/16-i91523:47:311
12433993432,1cyclictest167950irq/16-i91521:42:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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