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2025-12-01 - 11:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Mon Dec 01, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
166552550,0sleep10-21swapper/100:12:001
2115625019,22sleep00-21swapper/018:57:010
2257024019,13sleep10-21swapper/119:01:231
22689993829,8cyclictest245950irq/16-enp2s0f022:37:150
22690993533,1cyclictest167950irq/16-i91521:25:211
22689993534,0cyclictest245950irq/16-enp2s0f021:39:570
22689993534,0cyclictest245950irq/16-enp2s0f021:32:000
22690993434,0cyclictest167950irq/16-i91523:44:401
22690993433,0cyclictest167950irq/16-i91522:07:051
22690993433,0cyclictest167950irq/16-i91520:47:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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