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2025-11-20 - 13:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Thu Nov 20, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
76224611,27sleep00-21swapper/018:58:070
9662428,8sleep10-21swapper/119:00:071
1235993532,0cyclictest167950irq/16-i91521:36:310
1236993432,1cyclictest167950irq/16-i91523:12:301
1236993432,1cyclictest167950irq/16-i91521:36:401
1235993434,0cyclictest245950irq/16-enp2s0f020:19:230
1235993433,0cyclictest245950irq/16-enp2s0f023:51:580
1235993432,1cyclictest245950irq/16-enp2s0f023:37:320
1235993432,1cyclictest245950irq/16-enp2s0f023:32:240
1235993432,1cyclictest245950irq/16-enp2s0f023:07:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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