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2025-11-16 - 06:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Sun Nov 16, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243462640,0sleep024347-22ntp_kernel_pll_22:22:350
284552630,0sleep00-21swapper/018:57:390
288192428,8sleep10-21swapper/119:00:271
3252400,0sleep00-21swapper/019:12:360
29060993931,7cyclictest245950irq/16-enp2s0f019:22:330
29060993531,0cyclictest167950irq/16-i91522:02:400
29061993433,0cyclictest245950irq/16-enp2s0f023:18:311
29061993433,0cyclictest245950irq/16-enp2s0f022:36:551
29061993433,0cyclictest167950irq/16-i91522:23:421
29061993432,1cyclictest185550irq/16-nvkm20:47:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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