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2026-08-04 - 14:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Aug 04, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2182924912,8sleep00-21swapper/019:02:220
22278994130,10cyclictest246650irq/16-enp2s0f021:45:350
220482369,8sleep10-21swapper/119:04:351
22278993533,1cyclictest246650irq/16-enp2s0f020:57:330
22278993432,1cyclictest246650irq/16-enp2s0f022:52:420
22278993432,1cyclictest246650irq/16-enp2s0f022:22:090
22278993432,1cyclictest246650irq/16-enp2s0f021:25:320
22278993432,1cyclictest246650irq/16-enp2s0f021:20:180
22278993432,1cyclictest246650irq/16-enp2s0f020:31:140
22278993432,1cyclictest246650irq/16-enp2s0f020:06:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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