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2026-11-10 - 23:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Nov 10, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
143682438,28sleep00-21swapper/007:00:490
1453824010,8sleep10-21swapper/107:02:361
14775993534,0cyclictest246650irq/16-enp2s0f008:03:140
14776993433,0cyclictest168750irq/16-i91509:36:441
14776993433,0cyclictest168750irq/16-i91508:03:141
14776993433,0cyclictest168750irq/16-i91507:20:591
14776993432,1cyclictest168750irq/16-i91509:24:051
14775993434,0cyclictest246650irq/16-enp2s0f009:58:250
14775993433,0cyclictest246650irq/16-enp2s0f008:55:240
14775993433,0cyclictest246650irq/16-enp2s0f007:20:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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