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2025-12-05 - 12:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Fri Dec 05, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325892488,8sleep00-21swapper/018:59:360
3432378,22sleep10-21swapper/119:01:531
408993534,0cyclictest245950irq/16-enp2s0f021:29:300
408993534,0cyclictest245950irq/16-enp2s0f000:22:130
408993533,1cyclictest245950irq/16-enp2s0f019:31:560
409993433,0cyclictest167950irq/16-i91523:45:271
409993433,0cyclictest167950irq/16-i91520:57:191
409993432,1cyclictest167950irq/16-i91523:07:351
409993432,1cyclictest167950irq/16-i91522:45:221
409993432,1cyclictest167950irq/16-i91521:42:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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