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2025-12-04 - 12:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Thu Dec 04, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
277872478,8sleep00-21swapper/018:58:210
281142449,8sleep10-21swapper/119:01:441
28198993533,1cyclictest167950irq/16-i91519:12:091
28198993432,1cyclictest167950irq/16-i91522:42:361
28198993432,1cyclictest167950irq/16-i91521:38:251
28198993432,1cyclictest167950irq/16-i91520:29:371
28198993432,1cyclictest167950irq/16-i91519:18:131
28198993432,1cyclictest167950irq/16-i91500:03:201
28197993433,0cyclictest245950irq/16-enp2s0f023:37:110
28197993433,0cyclictest245950irq/16-enp2s0f021:04:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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