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2025-12-09 - 22:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Dec 09, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
259622418,8sleep00-21swapper/006:57:120
26478993832,5cyclictest167950irq/16-i91510:34:201
26478993734,2cyclictest167950irq/16-i91511:30:301
26478993732,4cyclictest167950irq/16-i91509:39:121
26478993732,4cyclictest167950irq/16-i91508:27:031
26478993732,4cyclictest167950irq/16-i91508:22:031
26478993633,2cyclictest167950irq/16-i91509:24:101
26478993632,3cyclictest245950irq/16-enp2s0f011:19:501
26478993632,3cyclictest245950irq/16-enp2s0f011:02:021
26478993632,3cyclictest167950irq/16-i91510:22:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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