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2026-09-08 - 18:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Sep 08, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
151642550,0sleep00-21swapper/008:55:400
323672448,29sleep00-21swapper/007:00:520
420993534,0cyclictest246650irq/16-enp2s0f011:36:581
419993534,0cyclictest246650irq/16-enp2s0f011:05:250
419993534,0cyclictest246650irq/16-enp2s0f009:06:500
324842358,19sleep10-21swapper/107:02:081
420993433,0cyclictest168750irq/16-i91509:04:491
419993434,0cyclictest246650irq/16-enp2s0f008:41:330
419993434,0cyclictest246650irq/16-enp2s0f007:28:320
419993433,1cyclictest246650irq/16-enp2s0f012:12:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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