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2025-12-06 - 09:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Sat Dec 06, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1512121160,0sleep115122-22unixbench_singl00:17:171
278432660,1sleep081ktimersoftd/021:22:110
169502438,8sleep10-21swapper/118:57:091
17934994032,7cyclictest245950irq/16-enp2s0f022:57:100
17934994032,7cyclictest245950irq/16-enp2s0f021:28:350
17934993932,6cyclictest245950irq/16-enp2s0f023:52:100
17934993932,6cyclictest245950irq/16-enp2s0f022:22:060
17934993932,6cyclictest245950irq/16-enp2s0f000:27:070
17934993932,6cyclictest245950irq/16-enp2s0f000:00:410
17934993931,7cyclictest245950irq/16-enp2s0f020:02:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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