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2026-06-30 - 07:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Jun 30, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
162432438,8sleep10-21swapper/119:04:341
160522428,8sleep00-21swapper/019:02:340
16541993931,7cyclictest246650irq/16-enp2s0f023:16:280
16541993729,7cyclictest246650irq/16-enp2s0f019:20:170
16541993534,0cyclictest246650irq/16-enp2s0f023:48:060
16541993534,0cyclictest246650irq/16-enp2s0f019:58:060
16542993433,0cyclictest246650irq/16-enp2s0f023:56:051
16542993433,0cyclictest246650irq/16-enp2s0f023:14:521
16542993433,0cyclictest246650irq/16-enp2s0f021:53:471
16542993433,0cyclictest168750irq/16-i91521:22:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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