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2026-08-25 - 17:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Aug 25, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33152478,8sleep00-21swapper/007:01:570
33162438,8sleep10-21swapper/107:01:581
3772993534,0cyclictest246650irq/16-enp2s0f010:27:250
3772993534,0cyclictest246650irq/16-enp2s0f007:15:400
3773993433,0cyclictest168750irq/16-i91508:50:431
3773993432,1cyclictest168750irq/16-i91510:35:071
3773993432,1cyclictest168750irq/16-i91509:04:371
3773993432,1cyclictest168750irq/16-i91507:15:571
3772993433,0cyclictest246650irq/16-enp2s0f010:06:230
3772993432,1cyclictest246650irq/16-enp2s0f009:46:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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