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2026-08-18 - 17:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Aug 18, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218552418,26sleep00-21swapper/007:04:460
216272378,8sleep10-21swapper/107:02:221
22045993534,0cyclictest168750irq/16-i91509:02:211
22045993433,0cyclictest168750irq/16-i91511:20:231
22045993432,1cyclictest168750irq/16-i91510:13:431
22044993434,0cyclictest246650irq/16-enp2s0f011:54:200
22044993433,0cyclictest246650irq/16-enp2s0f010:49:390
22044993433,0cyclictest246650irq/16-enp2s0f008:32:510
22044993432,1cyclictest246650irq/16-enp2s0f012:29:050
22044993432,1cyclictest246650irq/16-enp2s0f012:23:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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