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2025-09-13 - 10:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Sat Sep 13, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
232142580,1sleep023215-21watchsnmpd00:28:320
2379124914,27sleep00-21swapper/019:01:270
2269723821,8sleep10-21swapper/118:58:341
24055993534,0cyclictest245950irq/16-enp2s0f023:46:061
24055993534,0cyclictest245950irq/16-enp2s0f000:13:451
24054993534,0cyclictest245950irq/16-enp2s0f022:29:340
24054993534,0cyclictest245950irq/16-enp2s0f021:53:440
24054993532,1cyclictest245950irq/16-enp2s0f021:08:520
24054993532,1cyclictest245950irq/16-enp2s0f019:24:530
24055993433,0cyclictest245950irq/16-enp2s0f023:49:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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