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2026-05-11 - 21:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Mon May 11, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24893993832,5cyclictest246650irq/16-enp2s0f012:23:590
24893993831,6cyclictest246650irq/16-enp2s0f012:14:460
24893993831,6cyclictest246650irq/16-enp2s0f011:56:060
24893993831,6cyclictest246650irq/16-enp2s0f010:18:060
246462389,8sleep10-21swapper/107:06:031
24893993734,2cyclictest246650irq/16-enp2s0f008:27:570
24893993732,4cyclictest246650irq/16-enp2s0f011:36:040
24893993732,4cyclictest246650irq/16-enp2s0f007:41:510
24893993731,5cyclictest246650irq/16-enp2s0f010:00:490
24893993731,5cyclictest246650irq/16-enp2s0f008:40:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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