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2025-12-06 - 22:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Sat Dec 06, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30372428,26sleep00-21swapper/007:01:260
28112388,22sleep10-21swapper/106:59:081
3151993734,3cyclictest167950irq/16-i91510:52:141
3151993732,4cyclictest167950irq/16-i91510:02:371
3151993732,4cyclictest167950irq/16-i91509:15:151
3151993731,5cyclictest245950irq/16-enp2s0f009:53:581
3151993731,5cyclictest167950irq/16-i91509:25:181
3151993635,0cyclictest167950irq/16-i91511:40:121
3151993634,1cyclictest167950irq/16-i91510:00:241
3151993632,3cyclictest245950irq/16-enp2s0f010:32:081
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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