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2025-12-12 - 12:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Fri Dec 12, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1960424813,8sleep10-21swapper/119:01:191
195362458,8sleep00-21swapper/019:00:380
19710993729,7cyclictest245950irq/16-enp2s0f019:17:030
19711993434,0cyclictest167950irq/16-i91523:07:121
19711993433,0cyclictest245950irq/16-enp2s0f019:48:541
19711993432,1cyclictest167950irq/16-i91523:12:071
19711993432,1cyclictest167950irq/16-i91523:02:311
19711993432,1cyclictest167950irq/16-i91520:22:001
19711993432,1cyclictest167950irq/16-i91500:02:131
19710993433,1cyclictest245950irq/16-enp2s0f022:45:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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