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2026-03-27 - 20:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Fri Mar 27, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
174522499,8sleep00-21swapper/007:06:130
172872428,8sleep10-21swapper/107:04:291
17769993534,0cyclictest246650irq/16-enp2s0f012:03:080
17769993534,0cyclictest246650irq/16-enp2s0f011:55:380
17769993533,1cyclictest246650irq/16-enp2s0f008:50:110
17770993433,0cyclictest246650irq/16-enp2s0f007:53:091
17770993433,0cyclictest168750irq/16-i91510:31:351
17769993434,0cyclictest246650irq/16-enp2s0f010:34:010
17769993434,0cyclictest246650irq/16-enp2s0f010:08:490
17769993433,0cyclictest246650irq/16-enp2s0f012:29:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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