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2025-11-13 - 04:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Thu Nov 13, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1254125011,8sleep00-21swapper/019:01:210
123332378,22sleep10-21swapper/118:59:121
12702993533,1cyclictest167950irq/16-i91521:02:431
12702993433,0cyclictest245950irq/16-enp2s0f000:07:381
12702993433,0cyclictest167950irq/16-i91522:50:031
12702993433,0cyclictest167950irq/16-i91521:58:251
12702993432,1cyclictest167950irq/16-i91523:50:131
12702993432,1cyclictest167950irq/16-i91522:12:381
12702993432,1cyclictest167950irq/16-i91521:52:381
12702993432,1cyclictest167950irq/16-i91521:22:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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