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2025-11-25 - 16:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Nov 25, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
213392990,0sleep121338-22proc_pri08:47:251
2162124925,11sleep10-21swapper/107:01:191
214182398,23sleep00-21swapper/006:59:140
21759993635,0cyclictest245950irq/16-enp2s0f008:32:210
21759993634,1cyclictest245950irq/16-enp2s0f011:42:270
21760993531,1cyclictest167950irq/16-i91508:42:211
21759993534,0cyclictest245950irq/16-enp2s0f007:48:250
21759993533,1cyclictest245950irq/16-enp2s0f007:32:450
21759993533,1cyclictest245950irq/16-enp2s0f007:14:130
21760993433,0cyclictest167950irq/16-i91511:16:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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