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2026-06-16 - 04:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Jun 16, 2026 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
85952428,8sleep00-21swapper/019:04:490
839123810,8sleep10-21swapper/119:02:441
8893993534,0cyclictest246650irq/16-enp2s0f022:24:380
8893993534,0cyclictest246650irq/16-enp2s0f021:18:200
8893993534,0cyclictest246650irq/16-enp2s0f000:02:260
8894993433,0cyclictest168750irq/16-i91500:19:361
8894993432,1cyclictest168750irq/16-i91521:10:251
8894993432,1cyclictest168750irq/16-i91520:42:301
8893993433,0cyclictest246650irq/16-enp2s0f020:25:430
8893993433,0cyclictest246650irq/16-enp2s0f019:18:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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