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2026-07-29 - 05:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Wed Jul 29, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179192488,8sleep00-21swapper/019:05:570
18027993831,6cyclictest168750irq/16-i91523:56:291
177242388,23sleep10-21swapper/119:03:541
18027993633,2cyclictest168750irq/16-i91520:55:461
18027993631,4cyclictest168750irq/16-i91519:30:321
18027993630,5cyclictest168750irq/16-i91500:12:541
18027993532,2cyclictest246650irq/16-enp2s0f023:33:271
18027993532,2cyclictest168750irq/16-i91523:45:491
18027993532,2cyclictest168750irq/16-i91523:19:551
18027993532,2cyclictest168750irq/16-i91523:02:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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