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2026-05-25 - 22:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Mon May 25, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2835324925,11sleep10-21swapper/107:04:531
28690993533,1cyclictest168750irq/16-i91507:20:171
28690993433,0cyclictest246650irq/16-enp2s0f008:43:131
28690993433,0cyclictest168750irq/16-i91509:03:271
28690993433,0cyclictest168750irq/16-i91508:26:501
28690993432,1cyclictest190650irq/16-nvkm08:17:451
28690993432,1cyclictest168750irq/16-i91511:51:021
28690993432,1cyclictest168750irq/16-i91509:40:421
28689993434,0cyclictest246650irq/16-enp2s0f009:31:230
28689993433,0cyclictest246650irq/16-enp2s0f012:27:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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