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2026-04-11 - 20:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Sat Apr 11, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1900024210,25sleep00-21swapper/007:06:480
19232993730,6cyclictest246650irq/16-enp2s0f007:56:130
19232993730,6cyclictest246650irq/16-enp2s0f007:56:130
19232993631,1cyclictest246650irq/16-enp2s0f010:09:160
191262369,8sleep10-21swapper/107:08:091
19232993534,0cyclictest246650irq/16-enp2s0f012:12:040
19233993434,0cyclictest168750irq/16-i91508:57:511
19233993433,0cyclictest168750irq/16-i91511:36:031
19233993432,1cyclictest246650irq/16-enp2s0f008:47:061
19233993432,1cyclictest168750irq/16-i91512:22:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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