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2026-07-21 - 14:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Jul 21, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
241102429,8sleep10-21swapper/107:01:551
2414824014,18sleep00-21swapper/007:02:200
24619993534,0cyclictest246650irq/16-enp2s0f007:58:350
24619993534,0cyclictest246650irq/16-enp2s0f007:17:580
24619993433,0cyclictest246650irq/16-enp2s0f012:31:230
24619993433,0cyclictest246650irq/16-enp2s0f012:13:360
24619993433,0cyclictest246650irq/16-enp2s0f011:24:210
24619993433,0cyclictest246650irq/16-enp2s0f010:11:080
24619993433,0cyclictest246650irq/16-enp2s0f009:37:550
24619993433,0cyclictest246650irq/16-enp2s0f009:34:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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