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2025-10-22 - 02:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Wed Oct 22, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246052478,8sleep00-21swapper/019:00:360
244202418,8sleep10-21swapper/118:58:471
24877993533,1cyclictest245950irq/16-enp2s0f023:38:070
24878993433,0cyclictest167950irq/16-i91522:47:561
24878993432,1cyclictest245950irq/16-enp2s0f020:20:191
24878993432,1cyclictest167950irq/16-i91523:43:061
24877993433,0cyclictest245950irq/16-enp2s0f021:48:190
24877993433,0cyclictest245950irq/16-enp2s0f021:29:580
24877993433,0cyclictest245950irq/16-enp2s0f019:50:350
24877993432,1cyclictest245950irq/16-enp2s0f023:14:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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