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2025-12-11 - 12:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Thu Dec 11, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
278012610,0sleep10-21swapper/122:12:001
144952560,0sleep00-21swapper/021:27:020
32442488,8sleep00-21swapper/018:58:460
3603993931,7cyclictest245950irq/16-enp2s0f019:22:050
35302379,21sleep10-21swapper/119:01:421
3603993533,1cyclictest245950irq/16-enp2s0f023:37:010
3603993531,0cyclictest167950irq/16-i91522:47:320
3604993433,0cyclictest167950irq/16-i91521:43:041
3604993433,0cyclictest167950irq/16-i91521:02:231
3604993432,1cyclictest167950irq/16-i91523:47:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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