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2025-06-29 - 01:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Sat Jun 28, 2025 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
287182478,8sleep00-21swapper/007:03:420
28905993931,7cyclictest245950irq/16-enp2s0f009:15:170
28906993534,0cyclictest167950irq/16-i91510:50:451
28905993534,0cyclictest245950irq/16-enp2s0f008:03:170
28905993533,1cyclictest245950irq/16-enp2s0f008:41:150
28905993533,1cyclictest245950irq/16-enp2s0f008:13:050
28906993433,0cyclictest245950irq/16-enp2s0f010:25:161
28906993432,1cyclictest167950irq/16-i91510:40:181
28906993432,1cyclictest167950irq/16-i91510:23:301
28905993434,0cyclictest245950irq/16-enp2s0f011:41:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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