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2025-12-10 - 23:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Wed Dec 10, 2025 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1977624320,16sleep10-21swapper/106:58:211
2011624114,20sleep00-21swapper/007:01:480
20179993830,7cyclictest245950irq/16-enp2s0f008:37:070
20180993433,0cyclictest167950irq/16-i91509:44:051
20180993433,0cyclictest167950irq/16-i91507:58:081
20180993432,1cyclictest167950irq/16-i91510:52:041
20180993432,1cyclictest167950irq/16-i91509:57:061
20180993432,1cyclictest167950irq/16-i91508:03:091
20179993434,0cyclictest245950irq/16-enp2s0f007:46:100
20179993433,0cyclictest245950irq/16-enp2s0f012:04:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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