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2026-09-01 - 17:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Sep 01, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
139152468,8sleep00-21swapper/007:05:050
138302429,8sleep10-21swapper/107:04:141
14043993528,6cyclictest246650irq/16-enp2s0f011:21:510
14044993433,0cyclictest168750irq/16-i91511:57:451
14043993434,0cyclictest246650irq/16-enp2s0f012:08:450
14043993433,0cyclictest246650irq/16-enp2s0f008:04:130
14043993432,1cyclictest246650irq/16-enp2s0f010:03:040
14043993432,1cyclictest246650irq/16-enp2s0f009:20:100
14043993432,1cyclictest246650irq/16-enp2s0f008:51:560
14044993333,0cyclictest168750irq/16-i91512:21:481
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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