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2026-08-11 - 14:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Aug 11, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
144232448,8sleep00-21swapper/007:02:080
145822439,8sleep10-21swapper/107:03:481
14879993534,0cyclictest246650irq/16-enp2s0f011:00:581
14879993534,0cyclictest246650irq/16-enp2s0f007:52:301
14879993534,0cyclictest168750irq/16-i91510:13:411
14878993534,0cyclictest246650irq/16-enp2s0f007:30:270
14878993532,2cyclictest246650irq/16-enp2s0f010:08:270
14879993434,0cyclictest246650irq/16-enp2s0f009:24:531
14879993434,0cyclictest168750irq/16-i91507:35:501
14879993433,0cyclictest246650irq/16-enp2s0f011:47:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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