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2026-10-06 - 23:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Oct 06, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
706324428,8sleep00-21swapper/007:00:480
72762439,8sleep10-21swapper/107:03:031
7538993534,0cyclictest168750irq/16-i91509:54:361
7538993534,0cyclictest168750irq/16-i91509:24:501
7537993534,0cyclictest246650irq/16-enp2s0f010:11:440
7538993433,0cyclictest246650irq/16-enp2s0f008:00:361
7538993433,0cyclictest168750irq/16-i91509:30:301
7538993432,1cyclictest168750irq/16-i91507:12:051
7537993434,0cyclictest246650irq/16-enp2s0f008:48:270
7537993434,0cyclictest246650irq/16-enp2s0f007:16:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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