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2026-06-09 - 00:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Mon Jun 08, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
140642449,8sleep10-21swapper/107:05:191
138792448,8sleep00-21swapper/007:03:210
14333993433,0cyclictest168750irq/16-i91512:21:011
14333993433,0cyclictest168750irq/16-i91509:05:161
14333993433,0cyclictest168750irq/16-i91507:44:051
14333993432,1cyclictest168750irq/16-i91512:00:491
14333993432,1cyclictest168750irq/16-i91510:25:291
14333993432,1cyclictest168750irq/16-i91509:29:371
14333993432,1cyclictest168750irq/16-i91508:38:571
14333993432,1cyclictest168750irq/16-i91507:34:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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