You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-08 - 00:13
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Sun Dec 07, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
295642468,8sleep00-21swapper/007:00:410
294052428,8sleep10-21swapper/106:59:001
29749993534,0cyclictest167950irq/16-i91507:47:231
29748993527,7cyclictest245950irq/16-enp2s0f009:12:090
29749993433,0cyclictest167950irq/16-i91510:54:561
29749993433,0cyclictest167950irq/16-i91510:13:361
29749993432,1cyclictest245950irq/16-enp2s0f009:58:061
29749993432,1cyclictest185550irq/16-nvkm12:01:531
29749993432,1cyclictest167950irq/16-i91511:27:061
29749993432,1cyclictest167950irq/16-i91510:22:011
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional