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2025-11-06 - 00:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Wed Nov 05, 2025 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
281822458,8sleep00-21swapper/007:01:380
2787023721,8sleep10-21swapper/106:58:301
28325993631,1cyclictest167950irq/16-i91511:57:130
28325993532,0cyclictest167950irq/16-i91511:27:190
28325993531,0cyclictest167950irq/16-i91508:45:380
28326993434,0cyclictest167950irq/16-i91509:55:351
28326993432,1cyclictest167950irq/16-i91511:31:141
28326993432,1cyclictest167950irq/16-i91510:39:461
28326993432,1cyclictest167950irq/16-i91509:24:311
28326993432,1cyclictest167950irq/16-i91507:19:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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