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2026-07-07 - 08:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot2.osadl.org (updated Tue Jul 07, 2026 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
735824519,19sleep10-21swapper/119:02:101
747624014,18sleep00-21swapper/019:03:250
7875993433,0cyclictest168750irq/16-i91520:42:081
7875993433,0cyclictest168750irq/16-i91500:23:161
7875993432,1cyclictest168750irq/16-i91523:52:271
7875993432,1cyclictest168750irq/16-i91521:52:221
7875993432,1cyclictest168750irq/16-i91520:08:511
7874993432,1cyclictest246650irq/16-enp2s0f022:01:110
7874993432,1cyclictest246650irq/16-enp2s0f021:53:330
7874993432,1cyclictest246650irq/16-enp2s0f021:18:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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