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2025-09-18 - 05:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot2.osadl.org (updated Thu Sep 18, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181412570,0sleep00-21swapper/021:33:450
57922428,8sleep00-21swapper/019:02:100
5977993534,0cyclictest245950irq/16-enp2s0f022:47:330
5977993534,0cyclictest245950irq/16-enp2s0f021:20:210
580423510,18sleep10-21swapper/119:02:171
5978993432,1cyclictest167950irq/16-i91520:13:381
5978993432,1cyclictest167950irq/16-i91520:03:421
5977993433,0cyclictest245950irq/16-enp2s0f020:28:400
5977993432,1cyclictest245950irq/16-enp2s0f022:08:420
5977993432,1cyclictest245950irq/16-enp2s0f020:54:450
5977993432,1cyclictest245950irq/16-enp2s0f019:48:430
5977993432,1cyclictest245950irq/16-enp2s0f019:14:040
5977993432,1cyclictest245950irq/16-enp2s0f000:13:430
5978993332,0cyclictest245950irq/16-enp2s0f023:42:331
5978993332,0cyclictest245950irq/16-enp2s0f019:43:431
5978993332,0cyclictest167950irq/16-i91523:58:421
5978993332,0cyclictest167950irq/16-i91523:28:411
5978993332,0cyclictest167950irq/16-i91523:13:211
5978993332,0cyclictest167950irq/16-i91523:03:401
5978993332,0cyclictest167950irq/16-i91522:49:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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