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2025-12-03 - 06:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Wed Dec 03, 2025 00:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1325724010,22sleep00-21swapper/018:58:240
1342823519,8sleep10-21swapper/119:00:071
13667993432,1cyclictest185550irq/16-nvkm22:51:411
13667993432,1cyclictest167950irq/16-i91522:23:501
13667993432,1cyclictest167950irq/16-i91521:12:111
13667993432,1cyclictest167950irq/16-i91520:42:121
13666993433,0cyclictest245950irq/16-enp2s0f023:43:240
13666993433,0cyclictest245950irq/16-enp2s0f021:52:200
13666993433,0cyclictest245950irq/16-enp2s0f021:27:310
13666993433,0cyclictest245950irq/16-enp2s0f019:30:440
13666993432,1cyclictest245950irq/16-enp2s0f023:27:140
13666993432,1cyclictest245950irq/16-enp2s0f023:07:090
13666993432,1cyclictest245950irq/16-enp2s0f023:00:200
13666993432,1cyclictest245950irq/16-enp2s0f022:47:140
13666993432,1cyclictest245950irq/16-enp2s0f022:12:130
13666993432,1cyclictest245950irq/16-enp2s0f022:07:180
13666993432,1cyclictest245950irq/16-enp2s0f022:05:150
13666993432,1cyclictest245950irq/16-enp2s0f021:22:130
13666993432,1cyclictest245950irq/16-enp2s0f020:53:280
13666993432,1cyclictest245950irq/16-enp2s0f020:37:210
13666993432,1cyclictest245950irq/16-enp2s0f020:24:230
13666993432,1cyclictest245950irq/16-enp2s0f020:02:190
13666993432,1cyclictest245950irq/16-enp2s0f019:32:380
13666993432,1cyclictest245950irq/16-enp2s0f019:16:580
13667993332,0cyclictest245950irq/16-enp2s0f023:22:231
13667993332,0cyclictest245950irq/16-enp2s0f020:22:151
13667993332,0cyclictest245950irq/16-enp2s0f019:19:101
13667993332,0cyclictest245950irq/16-enp2s0f000:07:251
13667993332,0cyclictest185550irq/16-nvkm20:52:121
13667993332,0cyclictest167950irq/16-i91523:27:091
13667993332,0cyclictest167950irq/16-i91523:17:131
13667993332,0cyclictest167950irq/16-i91523:07:131
13667993332,0cyclictest167950irq/16-i91523:04:021
13667993332,0cyclictest167950irq/16-i91522:37:151
13667993332,0cyclictest167950irq/16-i91521:51:591
13667993332,0cyclictest167950irq/16-i91521:32:381
13667993332,0cyclictest167950irq/16-i91521:22:351
13667993332,0cyclictest167950irq/16-i91521:07:151
13667993332,0cyclictest167950irq/16-i91520:39:071
13667993332,0cyclictest167950irq/16-i91520:32:461
13667993332,0cyclictest167950irq/16-i91520:17:581
13667993332,0cyclictest167950irq/16-i91520:08:111
13667993332,0cyclictest167950irq/16-i91519:09:521
13667993332,0cyclictest167950irq/16-i91519:02:171
13667993332,0cyclictest167950irq/16-i91500:17:221
13667993331,1cyclictest245950irq/16-enp2s0f023:47:141
13667993331,1cyclictest245950irq/16-enp2s0f023:32:171
13667993331,1cyclictest245950irq/16-enp2s0f022:27:171
13667993331,1cyclictest245950irq/16-enp2s0f019:52:111
13667993331,1cyclictest245950irq/16-enp2s0f019:27:171
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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