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2025-10-28 - 02:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Mon Oct 27, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
335125012,8sleep00-21swapper/006:59:570
341824013,20sleep10-21swapper/107:00:401
3678993534,0cyclictest245950irq/16-enp2s0f007:02:590
3679993434,0cyclictest167950irq/16-i91509:25:381
3679993434,0cyclictest167950irq/16-i91509:18:571
3679993434,0cyclictest167950irq/16-i91508:28:291
3679993433,0cyclictest245950irq/16-enp2s0f007:50:191
3679993433,0cyclictest245950irq/16-enp2s0f007:04:531
3679993433,0cyclictest167950irq/16-i91510:37:531
3679993433,0cyclictest167950irq/16-i91510:26:091
3679993433,0cyclictest167950irq/16-i91507:42:541
3679993432,1cyclictest245950irq/16-enp2s0f011:47:551
3679993432,1cyclictest245950irq/16-enp2s0f010:27:591
3679993432,1cyclictest245950irq/16-enp2s0f008:23:001
3679993432,1cyclictest245950irq/16-enp2s0f008:18:021
3679993432,1cyclictest245950irq/16-enp2s0f007:37:581
3679993432,1cyclictest245950irq/16-enp2s0f007:07:531
3679993432,1cyclictest167950irq/16-i91512:07:501
3678993434,0cyclictest245950irq/16-enp2s0f011:56:190
3678993434,0cyclictest245950irq/16-enp2s0f007:49:420
3678993433,0cyclictest245950irq/16-enp2s0f008:18:290
3678993432,1cyclictest245950irq/16-enp2s0f012:03:010
3678993432,1cyclictest245950irq/16-enp2s0f011:00:060
3678993432,1cyclictest245950irq/16-enp2s0f010:17:560
3678993432,1cyclictest245950irq/16-enp2s0f009:47:540
3678993432,1cyclictest245950irq/16-enp2s0f009:20:450
3678993432,1cyclictest245950irq/16-enp2s0f007:39:110
3678993432,1cyclictest167950irq/16-i91511:39:370
3678993432,1cyclictest167950irq/16-i91510:52:520
3678993432,1cyclictest167950irq/16-i91509:39:140
3679993333,0cyclictest167950irq/16-i91510:53:061
3679993333,0cyclictest167950irq/16-i91510:44:171
3679993333,0cyclictest167950irq/16-i91510:08:271
3679993333,0cyclictest167950irq/16-i91508:49:001
3679993333,0cyclictest167950irq/16-i91507:22:531
3679993333,0cyclictest167950irq/16-i91507:15:181
3679993332,0cyclictest245950irq/16-enp2s0f012:22:451
3679993332,0cyclictest245950irq/16-enp2s0f012:17:541
3679993332,0cyclictest245950irq/16-enp2s0f011:57:541
3679993332,0cyclictest245950irq/16-enp2s0f011:52:581
3679993332,0cyclictest245950irq/16-enp2s0f011:37:531
3679993332,0cyclictest245950irq/16-enp2s0f011:25:181
3679993332,0cyclictest245950irq/16-enp2s0f011:16:041
3679993332,0cyclictest245950irq/16-enp2s0f011:07:581
3679993332,0cyclictest245950irq/16-enp2s0f011:02:531
3679993332,0cyclictest245950irq/16-enp2s0f010:34:071
3679993332,0cyclictest245950irq/16-enp2s0f010:17:471
3679993332,0cyclictest245950irq/16-enp2s0f010:03:041
3679993332,0cyclictest245950irq/16-enp2s0f009:33:001
3679993332,0cyclictest245950irq/16-enp2s0f009:27:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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