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2026-06-12 - 21:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Fri Jun 12, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
238012459,29sleep00-21swapper/007:06:100
2380223713,16sleep10-21swapper/107:06:111
23983993534,0cyclictest168750irq/16-i91507:20:481
23982993534,0cyclictest246650irq/16-enp2s0f007:38:210
23983993433,0cyclictest168750irq/16-i91510:14:591
23983993433,0cyclictest168750irq/16-i91508:19:151
23983993432,1cyclictest246650irq/16-enp2s0f011:18:061
23983993432,1cyclictest246650irq/16-enp2s0f009:29:411
23983993432,1cyclictest168750irq/16-i91509:49:311
23983993432,1cyclictest168750irq/16-i91507:29:071
23983993432,0cyclictest168750irq/16-i91510:46:021
23982993433,0cyclictest246650irq/16-enp2s0f012:04:390
23982993433,0cyclictest246650irq/16-enp2s0f011:37:230
23982993432,1cyclictest246650irq/16-enp2s0f010:52:170
23982993432,1cyclictest246650irq/16-enp2s0f010:36:590
23982993432,1cyclictest246650irq/16-enp2s0f010:10:380
23982993431,0cyclictest168750irq/16-i91510:27:390
23983993332,0cyclictest246650irq/16-enp2s0f011:58:111
23983993332,0cyclictest246650irq/16-enp2s0f009:05:271
23983993332,0cyclictest246650irq/16-enp2s0f007:52:551
23983993332,0cyclictest246650irq/16-enp2s0f007:27:181
23983993332,0cyclictest168750irq/16-i91512:34:051
23983993332,0cyclictest168750irq/16-i91512:29:371
23983993332,0cyclictest168750irq/16-i91512:14:041
23983993332,0cyclictest168750irq/16-i91512:09:491
23983993332,0cyclictest168750irq/16-i91512:04:561
23983993332,0cyclictest168750irq/16-i91511:55:071
23983993332,0cyclictest168750irq/16-i91511:52:171
23983993332,0cyclictest168750irq/16-i91511:44:111
23983993332,0cyclictest168750irq/16-i91511:36:441
23983993332,0cyclictest168750irq/16-i91511:24:491
23983993332,0cyclictest168750irq/16-i91511:17:091
23983993332,0cyclictest168750irq/16-i91511:04:131
23983993332,0cyclictest168750irq/16-i91510:59:041
23983993332,0cyclictest168750irq/16-i91510:34:401
23983993332,0cyclictest168750irq/16-i91510:28:281
23983993332,0cyclictest168750irq/16-i91510:07:441
23983993332,0cyclictest168750irq/16-i91510:04:341
23983993332,0cyclictest168750irq/16-i91510:00:551
23983993332,0cyclictest168750irq/16-i91509:34:281
23983993332,0cyclictest168750irq/16-i91509:09:231
23983993332,0cyclictest168750irq/16-i91509:01:291
23983993332,0cyclictest168750irq/16-i91508:48:271
23983993332,0cyclictest168750irq/16-i91508:44:191
23983993332,0cyclictest168750irq/16-i91508:34:171
23983993332,0cyclictest168750irq/16-i91508:17:161
23983993332,0cyclictest168750irq/16-i91508:09:141
23983993332,0cyclictest168750irq/16-i91508:02:261
23983993332,0cyclictest168750irq/16-i91507:59:121
23983993332,0cyclictest168750irq/16-i91507:35:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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