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2025-08-29 - 04:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Fri Aug 29, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41602580,1sleep1221ktimersoftd/100:19:031
75122488,8sleep00-21swapper/019:02:220
72492398,8sleep10-21swapper/118:59:421
7715993634,1cyclictest167950irq/16-i91523:04:011
7715993534,0cyclictest167950irq/16-i91522:34:551
7714993534,0cyclictest245950irq/16-enp2s0f022:37:170
7714993534,0cyclictest245950irq/16-enp2s0f020:26:480
7715993433,0cyclictest167950irq/16-i91522:49:521
7715993433,0cyclictest167950irq/16-i91522:19:051
7715993433,0cyclictest167950irq/16-i91500:01:561
7715993432,1cyclictest167950irq/16-i91523:54:291
7715993432,1cyclictest167950irq/16-i91523:44:301
7715993432,1cyclictest167950irq/16-i91519:38:491
7715993432,1cyclictest167950irq/16-i91519:26:481
7714993434,0cyclictest245950irq/16-enp2s0f023:07:300
7714993434,0cyclictest245950irq/16-enp2s0f000:27:460
7714993433,0cyclictest245950irq/16-enp2s0f023:12:210
7714993433,0cyclictest245950irq/16-enp2s0f021:45:390
7714993433,0cyclictest245950irq/16-enp2s0f019:55:210
7714993432,1cyclictest245950irq/16-enp2s0f023:19:050
7714993432,1cyclictest245950irq/16-enp2s0f022:59:060
7714993432,1cyclictest245950irq/16-enp2s0f022:39:010
7714993432,1cyclictest245950irq/16-enp2s0f021:29:090
7714993432,1cyclictest245950irq/16-enp2s0f021:24:310
7714993432,1cyclictest245950irq/16-enp2s0f021:18:040
7714993432,1cyclictest245950irq/16-enp2s0f020:54:130
7714993432,1cyclictest245950irq/16-enp2s0f020:39:040
7714993432,1cyclictest245950irq/16-enp2s0f020:36:470
7714993432,1cyclictest245950irq/16-enp2s0f000:09:080
7715993332,0cyclictest245950irq/16-enp2s0f023:34:221
7715993332,0cyclictest245950irq/16-enp2s0f022:15:091
7715993332,0cyclictest245950irq/16-enp2s0f021:54:211
7715993332,0cyclictest245950irq/16-enp2s0f021:19:261
7715993332,0cyclictest245950irq/16-enp2s0f020:04:301
7715993332,0cyclictest185550irq/16-nvkm20:31:161
7715993332,0cyclictest167950irq/16-i91523:53:461
7715993332,0cyclictest167950irq/16-i91523:31:231
7715993332,0cyclictest167950irq/16-i91523:24:301
7715993332,0cyclictest167950irq/16-i91523:22:221
7715993332,0cyclictest167950irq/16-i91523:14:511
7715993332,0cyclictest167950irq/16-i91523:11:401
7715993332,0cyclictest167950irq/16-i91522:54:181
7715993332,0cyclictest167950irq/16-i91522:40:531
7715993332,0cyclictest167950irq/16-i91522:32:271
7715993332,0cyclictest167950irq/16-i91522:09:161
7715993332,0cyclictest167950irq/16-i91522:03:591
7715993332,0cyclictest167950irq/16-i91521:59:411
7715993332,0cyclictest167950irq/16-i91521:49:121
7715993332,0cyclictest167950irq/16-i91521:39:101
7715993332,0cyclictest167950irq/16-i91521:34:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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