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2025-11-25 - 19:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Tue Nov 25, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
213392990,0sleep121338-22proc_pri08:47:251
2162124925,11sleep10-21swapper/107:01:191
214182398,23sleep00-21swapper/006:59:140
21759993635,0cyclictest245950irq/16-enp2s0f008:32:210
21759993634,1cyclictest245950irq/16-enp2s0f011:42:270
21760993531,1cyclictest167950irq/16-i91508:42:211
21759993534,0cyclictest245950irq/16-enp2s0f007:48:250
21759993533,1cyclictest245950irq/16-enp2s0f007:32:450
21759993533,1cyclictest245950irq/16-enp2s0f007:14:130
21760993433,0cyclictest167950irq/16-i91511:16:341
21760993432,1cyclictest167950irq/16-i91512:12:251
21760993432,1cyclictest167950irq/16-i91512:10:161
21760993432,1cyclictest167950irq/16-i91510:47:341
21760993432,1cyclictest167950irq/16-i91510:32:201
21760993432,1cyclictest167950irq/16-i91508:32:271
21759993434,0cyclictest245950irq/16-enp2s0f010:17:170
21759993434,0cyclictest245950irq/16-enp2s0f008:04:470
21759993433,0cyclictest245950irq/16-enp2s0f012:27:190
21759993433,0cyclictest245950irq/16-enp2s0f012:04:420
21759993433,0cyclictest245950irq/16-enp2s0f009:14:080
21759993432,1cyclictest245950irq/16-enp2s0f011:57:200
21759993432,1cyclictest245950irq/16-enp2s0f011:12:210
21759993432,1cyclictest245950irq/16-enp2s0f011:07:240
21759993432,1cyclictest245950irq/16-enp2s0f010:47:210
21759993432,1cyclictest245950irq/16-enp2s0f010:37:190
21759993432,1cyclictest245950irq/16-enp2s0f009:47:190
21759993432,1cyclictest245950irq/16-enp2s0f009:42:200
21759993432,1cyclictest245950irq/16-enp2s0f009:37:200
21759993432,1cyclictest245950irq/16-enp2s0f007:37:080
21760993333,0cyclictest167950irq/16-i91508:19:591
21760993332,0cyclictest245950irq/16-enp2s0f008:00:251
21760993332,0cyclictest245950irq/16-enp2s0f007:27:141
21760993332,0cyclictest245950irq/16-enp2s0f007:17:191
21760993332,0cyclictest167950irq/16-i91512:17:431
21760993332,0cyclictest167950irq/16-i91512:03:361
21760993332,0cyclictest167950irq/16-i91511:52:361
21760993332,0cyclictest167950irq/16-i91511:42:201
21760993332,0cyclictest167950irq/16-i91511:26:111
21760993332,0cyclictest167950irq/16-i91511:17:301
21760993332,0cyclictest167950irq/16-i91511:07:231
21760993332,0cyclictest167950irq/16-i91510:37:261
21760993332,0cyclictest167950irq/16-i91510:19:521
21760993332,0cyclictest167950irq/16-i91509:47:341
21760993332,0cyclictest167950irq/16-i91509:38:131
21760993332,0cyclictest167950irq/16-i91509:27:201
21760993332,0cyclictest167950irq/16-i91509:25:571
21760993332,0cyclictest167950irq/16-i91509:16:181
21760993332,0cyclictest167950irq/16-i91509:02:301
21760993332,0cyclictest167950irq/16-i91508:54:121
21760993332,0cyclictest167950irq/16-i91508:27:251
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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