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2025-11-30 - 02:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Sun Nov 30, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
210662468,8sleep00-21swapper/018:58:480
213512378,8sleep10-21swapper/119:01:411
21446993434,0cyclictest167950irq/16-i91523:39:501
21446993433,0cyclictest167950irq/16-i91523:06:041
21446993432,1cyclictest167950irq/16-i91522:42:131
21446993432,1cyclictest167950irq/16-i91521:57:331
21446993432,1cyclictest167950irq/16-i91521:16:411
21446993432,1cyclictest167950irq/16-i91519:12:141
21446993432,1cyclictest167950irq/16-i91500:17:191
21445993433,0cyclictest245950irq/16-enp2s0f023:46:340
21445993433,0cyclictest245950irq/16-enp2s0f023:39:500
21445993433,0cyclictest245950irq/16-enp2s0f019:43:570
21445993432,1cyclictest245950irq/16-enp2s0f023:57:150
21445993432,1cyclictest245950irq/16-enp2s0f023:55:570
21445993432,1cyclictest245950irq/16-enp2s0f019:06:360
21445993432,1cyclictest245950irq/16-enp2s0f000:17:190
21446993332,0cyclictest245950irq/16-enp2s0f021:41:331
21446993332,0cyclictest245950irq/16-enp2s0f021:23:331
21446993332,0cyclictest167950irq/16-i91523:57:331
21446993332,0cyclictest167950irq/16-i91523:52:261
21446993332,0cyclictest167950irq/16-i91523:27:151
21446993332,0cyclictest167950irq/16-i91522:13:341
21446993332,0cyclictest167950irq/16-i91521:54:151
21446993332,0cyclictest167950irq/16-i91521:42:131
21446993332,0cyclictest167950irq/16-i91521:35:241
21446993332,0cyclictest167950irq/16-i91521:17:191
21446993332,0cyclictest167950irq/16-i91520:57:171
21446993332,0cyclictest167950irq/16-i91520:52:211
21446993332,0cyclictest167950irq/16-i91520:35:161
21446993332,0cyclictest167950irq/16-i91520:26:501
21446993332,0cyclictest167950irq/16-i91519:42:381
21446993332,0cyclictest167950irq/16-i91519:41:411
21446993332,0cyclictest167950irq/16-i91519:19:411
21446993332,0cyclictest167950irq/16-i91519:07:171
21446993332,0cyclictest167950irq/16-i91500:22:511
21446993332,0cyclictest167950irq/16-i91500:15:471
21446993331,1cyclictest167950irq/16-i91523:12:191
21446993331,1cyclictest167950irq/16-i91522:52:151
21446993331,1cyclictest167950irq/16-i91522:32:531
21446993331,1cyclictest167950irq/16-i91520:37:221
21446993331,1cyclictest167950irq/16-i91520:12:151
21446993331,1cyclictest167950irq/16-i91520:02:181
21446993331,1cyclictest167950irq/16-i91520:00:361
21446993331,1cyclictest167950irq/16-i91519:27:201
21445993333,0cyclictest245950irq/16-enp2s0f021:49:470
21445993332,0cyclictest245950irq/16-enp2s0f023:47:140
21445993332,0cyclictest245950irq/16-enp2s0f023:32:190
21445993332,0cyclictest245950irq/16-enp2s0f023:27:150
21445993332,0cyclictest245950irq/16-enp2s0f023:22:330
21445993332,0cyclictest245950irq/16-enp2s0f022:57:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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