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2025-12-04 - 03:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Thu Dec 04, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
277872478,8sleep00-21swapper/018:58:210
281142449,8sleep10-21swapper/119:01:441
28198993533,1cyclictest167950irq/16-i91519:12:091
28198993432,1cyclictest167950irq/16-i91522:42:361
28198993432,1cyclictest167950irq/16-i91521:38:251
28198993432,1cyclictest167950irq/16-i91520:29:371
28198993432,1cyclictest167950irq/16-i91519:18:131
28198993432,1cyclictest167950irq/16-i91500:03:201
28197993433,0cyclictest245950irq/16-enp2s0f023:37:110
28197993433,0cyclictest245950irq/16-enp2s0f021:04:520
28197993433,0cyclictest245950irq/16-enp2s0f019:12:090
28197993432,1cyclictest245950irq/16-enp2s0f023:52:160
28197993432,1cyclictest245950irq/16-enp2s0f023:07:120
28197993432,1cyclictest245950irq/16-enp2s0f023:02:130
28197993432,1cyclictest245950irq/16-enp2s0f022:22:110
28197993432,1cyclictest245950irq/16-enp2s0f021:37:160
28197993432,1cyclictest245950irq/16-enp2s0f019:22:130
28197993432,1cyclictest167950irq/16-i91522:11:400
28198993332,0cyclictest245950irq/16-enp2s0f021:16:311
28198993332,0cyclictest167950irq/16-i91523:56:581
28198993332,0cyclictest167950irq/16-i91523:52:101
28198993332,0cyclictest167950irq/16-i91523:49:141
28198993332,0cyclictest167950irq/16-i91523:37:101
28198993332,0cyclictest167950irq/16-i91523:31:581
28198993332,0cyclictest167950irq/16-i91523:15:111
28198993332,0cyclictest167950irq/16-i91523:07:241
28198993332,0cyclictest167950irq/16-i91523:02:091
28198993332,0cyclictest167950irq/16-i91522:36:411
28198993332,0cyclictest167950irq/16-i91522:30:011
28198993332,0cyclictest167950irq/16-i91522:26:451
28198993332,0cyclictest167950irq/16-i91522:17:091
28198993332,0cyclictest167950irq/16-i91522:16:001
28198993332,0cyclictest167950irq/16-i91521:59:021
28198993332,0cyclictest167950irq/16-i91521:32:211
28198993332,0cyclictest167950irq/16-i91521:28:351
28198993332,0cyclictest167950irq/16-i91521:05:481
28198993332,0cyclictest167950irq/16-i91520:24:181
28198993332,0cyclictest167950irq/16-i91520:02:361
28198993332,0cyclictest167950irq/16-i91519:59:481
28198993332,0cyclictest167950irq/16-i91519:52:121
28198993332,0cyclictest167950irq/16-i91519:49:501
28198993332,0cyclictest167950irq/16-i91519:44:481
28198993332,0cyclictest167950irq/16-i91519:41:141
28198993332,0cyclictest167950irq/16-i91519:36:121
28198993332,0cyclictest167950irq/16-i91519:27:101
28198993332,0cyclictest167950irq/16-i91519:10:351
28198993332,0cyclictest167950irq/16-i91500:27:331
28198993332,0cyclictest167950irq/16-i91500:07:121
28198993331,1cyclictest167950irq/16-i91523:42:111
28198993331,1cyclictest167950irq/16-i91523:22:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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