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2025-12-02 - 22:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Tue Dec 02, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
322582438,8sleep00-21swapper/007:00:310
32462993729,7cyclictest245950irq/16-enp2s0f012:29:480
3198023611,17sleep10-21swapper/106:57:401
32462993534,0cyclictest245950irq/16-enp2s0f011:50:320
32462993534,0cyclictest245950irq/16-enp2s0f010:02:030
32463993434,0cyclictest167950irq/16-i91509:42:401
32463993434,0cyclictest167950irq/16-i91509:19:321
32463993432,1cyclictest167950irq/16-i91511:41:551
32463993432,1cyclictest167950irq/16-i91510:44:541
32463993432,1cyclictest167950irq/16-i91510:32:341
32463993432,1cyclictest167950irq/16-i91510:22:181
32463993432,1cyclictest167950irq/16-i91509:27:171
32463993432,1cyclictest167950irq/16-i91508:22:181
32463993432,1cyclictest167950irq/16-i91508:11:211
32462993433,0cyclictest245950irq/16-enp2s0f011:22:120
32462993433,0cyclictest245950irq/16-enp2s0f010:24:090
32462993432,1cyclictest245950irq/16-enp2s0f011:57:140
32462993432,1cyclictest245950irq/16-enp2s0f010:52:150
32462993432,1cyclictest245950irq/16-enp2s0f010:27:160
32462993432,1cyclictest245950irq/16-enp2s0f009:39:420
32462993432,1cyclictest245950irq/16-enp2s0f009:27:130
32462993432,1cyclictest245950irq/16-enp2s0f009:02:120
32462993432,1cyclictest245950irq/16-enp2s0f007:39:440
32463993332,0cyclictest245950irq/16-enp2s0f009:59:591
32463993332,0cyclictest245950irq/16-enp2s0f007:27:191
32463993332,0cyclictest167950irq/16-i91512:28:181
32463993332,0cyclictest167950irq/16-i91511:53:171
32463993332,0cyclictest167950irq/16-i91511:07:181
32463993332,0cyclictest167950irq/16-i91511:02:091
32463993332,0cyclictest167950irq/16-i91510:54:561
32463993332,0cyclictest167950irq/16-i91510:51:171
32463993332,0cyclictest167950irq/16-i91510:38:181
32463993332,0cyclictest167950irq/16-i91510:20:271
32463993332,0cyclictest167950irq/16-i91510:02:161
32463993332,0cyclictest167950irq/16-i91509:35:101
32463993332,0cyclictest167950irq/16-i91507:19:171
32463993331,1cyclictest245950irq/16-enp2s0f009:40:131
32463993331,1cyclictest245950irq/16-enp2s0f009:05:591
32463993331,1cyclictest167950irq/16-i91511:57:161
32463993331,1cyclictest167950irq/16-i91511:42:181
32463993331,1cyclictest167950irq/16-i91509:07:271
32463993331,1cyclictest167950irq/16-i91508:57:151
32463993331,1cyclictest167950irq/16-i91508:37:131
32463993331,1cyclictest167950irq/16-i91508:32:131
32463993331,1cyclictest167950irq/16-i91507:48:341
32463993331,1cyclictest167950irq/16-i91507:42:121
32462993332,0cyclictest245950irq/16-enp2s0f012:17:110
32462993332,0cyclictest245950irq/16-enp2s0f011:52:090
32462993332,0cyclictest245950irq/16-enp2s0f011:41:590
32462993332,0cyclictest245950irq/16-enp2s0f011:38:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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