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2025-11-21 - 05:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Fri Nov 21, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1199524813,8sleep10-21swapper/118:58:461
120932418,8sleep00-21swapper/018:59:430
12395993635,0cyclictest167950irq/16-i91523:31:051
12395993534,0cyclictest167950irq/16-i91523:03:291
12394993534,0cyclictest245950irq/16-enp2s0f023:12:130
12395993434,0cyclictest167950irq/16-i91522:32:111
12395993433,0cyclictest167950irq/16-i91522:32:481
12395993432,1cyclictest185550irq/16-nvkm19:12:231
12395993432,1cyclictest167950irq/16-i91523:49:341
12395993432,1cyclictest167950irq/16-i91519:11:271
12394993434,0cyclictest245950irq/16-enp2s0f021:52:310
12394993433,0cyclictest245950irq/16-enp2s0f023:54:250
12394993433,0cyclictest245950irq/16-enp2s0f022:37:280
12394993433,0cyclictest245950irq/16-enp2s0f022:36:030
12394993433,0cyclictest245950irq/16-enp2s0f022:18:350
12394993433,0cyclictest245950irq/16-enp2s0f020:25:050
12394993433,0cyclictest245950irq/16-enp2s0f019:17:250
12394993433,0cyclictest245950irq/16-enp2s0f019:12:320
12394993433,0cyclictest245950irq/16-enp2s0f000:28:430
12394993432,1cyclictest245950irq/16-enp2s0f022:50:060
12394993432,1cyclictest245950irq/16-enp2s0f022:30:060
12394993432,1cyclictest245950irq/16-enp2s0f022:12:280
12394993432,1cyclictest245950irq/16-enp2s0f021:27:280
12394993432,1cyclictest245950irq/16-enp2s0f021:15:480
12394993432,1cyclictest245950irq/16-enp2s0f020:47:380
12394993432,1cyclictest245950irq/16-enp2s0f019:57:250
12394993432,1cyclictest245950irq/16-enp2s0f019:27:250
12395993332,1cyclictest167950irq/16-i91522:39:191
12395993332,0cyclictest245950irq/16-enp2s0f022:00:301
12395993332,0cyclictest245950irq/16-enp2s0f021:39:111
12395993332,0cyclictest245950irq/16-enp2s0f019:04:171
12395993332,0cyclictest245950irq/16-enp2s0f000:09:091
12395993332,0cyclictest167950irq/16-i91523:58:031
12395993332,0cyclictest167950irq/16-i91523:38:431
12395993332,0cyclictest167950irq/16-i91523:34:061
12395993332,0cyclictest167950irq/16-i91523:08:151
12395993332,0cyclictest167950irq/16-i91522:52:511
12395993332,0cyclictest167950irq/16-i91522:12:511
12395993332,0cyclictest167950irq/16-i91522:02:421
12395993332,0cyclictest167950irq/16-i91521:52:141
12395993332,0cyclictest167950irq/16-i91521:52:121
12395993332,0cyclictest167950irq/16-i91521:42:381
12395993332,0cyclictest167950irq/16-i91521:32:331
12395993332,0cyclictest167950irq/16-i91521:22:231
12395993332,0cyclictest167950irq/16-i91521:07:311
12395993332,0cyclictest167950irq/16-i91520:52:241
12395993332,0cyclictest167950irq/16-i91520:50:031
12395993332,0cyclictest167950irq/16-i91520:37:301
12395993332,0cyclictest167950irq/16-i91520:27:311
12395993332,0cyclictest167950irq/16-i91520:22:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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