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2026-07-11 - 23:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Sat Jul 11, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
99052458,7sleep00-21swapper/007:04:170
97802378,8sleep10-21swapper/107:02:581
10207993433,0cyclictest168750irq/16-i91507:56:541
10207993432,1cyclictest168750irq/16-i91511:25:351
10207993432,1cyclictest168750irq/16-i91508:31:241
10207993432,1cyclictest168750irq/16-i91508:15:041
10206993434,0cyclictest246650irq/16-enp2s0f009:53:290
10206993434,0cyclictest246650irq/16-enp2s0f008:59:470
10206993432,1cyclictest246650irq/16-enp2s0f012:28:090
10206993432,1cyclictest246650irq/16-enp2s0f010:04:340
10206993432,1cyclictest168750irq/16-i91509:40:140
10207993332,0cyclictest246650irq/16-enp2s0f011:34:071
10207993332,0cyclictest246650irq/16-enp2s0f010:37:041
10207993332,0cyclictest246650irq/16-enp2s0f010:07:451
10207993332,0cyclictest246650irq/16-enp2s0f010:05:531
10207993332,0cyclictest246650irq/16-enp2s0f009:50:341
10207993332,0cyclictest246650irq/16-enp2s0f009:07:121
10207993332,0cyclictest246650irq/16-enp2s0f007:24:121
10207993332,0cyclictest168750irq/16-i91512:27:301
10207993332,0cyclictest168750irq/16-i91512:22:091
10207993332,0cyclictest168750irq/16-i91512:14:301
10207993332,0cyclictest168750irq/16-i91512:08:511
10207993332,0cyclictest168750irq/16-i91512:00:461
10207993332,0cyclictest168750irq/16-i91511:53:011
10207993332,0cyclictest168750irq/16-i91511:42:591
10207993332,0cyclictest168750irq/16-i91511:37:011
10207993332,0cyclictest168750irq/16-i91511:15:111
10207993332,0cyclictest168750irq/16-i91511:04:351
10207993332,0cyclictest168750irq/16-i91510:47:001
10207993332,0cyclictest168750irq/16-i91509:02:121
10207993332,0cyclictest168750irq/16-i91508:54:491
10207993332,0cyclictest168750irq/16-i91508:50:091
10207993332,0cyclictest168750irq/16-i91508:25:001
10207993332,0cyclictest168750irq/16-i91508:07:331
10207993332,0cyclictest168750irq/16-i91508:03:101
10207993332,0cyclictest168750irq/16-i91507:07:001
10207993331,1cyclictest168750irq/16-i91510:36:491
10207993331,1cyclictest168750irq/16-i91509:29:031
10207993331,1cyclictest168750irq/16-i91508:45:291
10207993331,1cyclictest168750irq/16-i91507:54:521
10207993331,1cyclictest168750irq/16-i91507:32:351
10206993333,0cyclictest246650irq/16-enp2s0f012:05:550
10206993333,0cyclictest246650irq/16-enp2s0f009:18:430
10206993333,0cyclictest246650irq/16-enp2s0f008:50:580
10206993333,0cyclictest246650irq/16-enp2s0f008:29:340
10206993332,1cyclictest246650irq/16-enp2s0f012:22:260
10206993332,0cyclictest246650irq/16-enp2s0f012:33:040
10206993332,0cyclictest246650irq/16-enp2s0f011:54:310
10206993332,0cyclictest246650irq/16-enp2s0f011:44:350
10206993332,0cyclictest246650irq/16-enp2s0f011:36:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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