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2026-07-24 - 22:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Fri Jul 24, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
151082479,8sleep00-21swapper/007:04:500
15336993732,4cyclictest246650irq/16-enp2s0f007:52:261
15336993731,5cyclictest168750irq/16-i91508:34:181
148572379,8sleep10-21swapper/107:02:131
15336993633,2cyclictest168750irq/16-i91509:37:431
15336993632,3cyclictest168750irq/16-i91509:48:431
15336993631,4cyclictest246650irq/16-enp2s0f011:28:431
15336993631,4cyclictest168750irq/16-i91509:59:011
15336993631,4cyclictest168750irq/16-i91508:58:491
15336993631,4cyclictest168750irq/16-i91507:35:471
15336993532,2cyclictest168750irq/16-i91511:55:221
15336993532,2cyclictest168750irq/16-i91511:47:581
15336993532,2cyclictest168750irq/16-i91510:48:431
15336993532,2cyclictest168750irq/16-i91509:19:201
15336993532,2cyclictest168750irq/16-i91507:24:481
15336993531,4cyclictest246650irq/16-enp2s0f010:36:251
15336993531,3cyclictest246650irq/16-enp2s0f011:13:141
15336993531,3cyclictest168750irq/16-i91508:47:321
15336993531,3cyclictest168750irq/16-i91507:20:141
15336993530,4cyclictest168750irq/16-i91512:34:281
15336993530,4cyclictest168750irq/16-i91512:09:251
15336993530,4cyclictest168750irq/16-i91509:43:141
15336993530,4cyclictest168750irq/16-i91508:18:411
15336993432,2cyclictest168750irq/16-i91510:12:421
15336993432,2cyclictest168750irq/16-i91507:47:041
15336993432,2cyclictest168750irq/16-i91507:08:011
15336993431,2cyclictest246650irq/16-enp2s0f009:33:271
15336993431,2cyclictest246650irq/16-enp2s0f009:10:401
15336993431,2cyclictest168750irq/16-i91512:01:491
15336993431,2cyclictest168750irq/16-i91511:31:361
15336993431,2cyclictest168750irq/16-i91511:26:321
15336993431,2cyclictest168750irq/16-i91511:16:471
15336993431,2cyclictest168750irq/16-i91510:58:121
15336993431,2cyclictest168750irq/16-i91510:11:261
15336993431,2cyclictest168750irq/16-i91509:29:211
15336993431,2cyclictest168750irq/16-i91509:14:561
15336993431,2cyclictest168750irq/16-i91508:54:401
15336993431,2cyclictest168750irq/16-i91508:44:031
15336993431,2cyclictest168750irq/16-i91508:28:181
15336993431,2cyclictest168750irq/16-i91508:22:051
15336993431,2cyclictest168750irq/16-i91508:07:151
15336993431,2cyclictest168750irq/16-i91508:03:151
15336993431,2cyclictest168750irq/16-i91507:41:581
15336993431,2cyclictest168750irq/16-i91507:38:401
15336993430,3cyclictest168750irq/16-i91512:29:011
15336993430,3cyclictest168750irq/16-i91512:24:291
15336993430,3cyclictest168750irq/16-i91511:44:221
15336993430,3cyclictest168750irq/16-i91510:17:201
15336993430,3cyclictest168750irq/16-i91510:06:201
15336993430,3cyclictest168750irq/16-i91507:12:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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