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2025-05-02 - 12:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Fri May 02, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
73722860,0sleep17373-22cstates20:46:221
95872448,28sleep00-21swapper/019:02:440
94682449,8sleep10-21swapper/119:01:311
9975993931,1cyclictest167950irq/16-i91523:51:231
9975993830,1cyclictest167950irq/16-i91519:36:271
9975993731,0cyclictest167950irq/16-i91522:16:201
9975993731,0cyclictest167950irq/16-i91500:16:241
9975993730,1cyclictest167950irq/16-i91521:21:241
9975993634,1cyclictest167950irq/16-i91522:01:221
9975993632,3cyclictest167950irq/16-i91522:46:241
9975993632,3cyclictest167950irq/16-i91522:10:401
9975993631,4cyclictest167950irq/16-i91500:26:231
9975993631,0cyclictest167950irq/16-i91519:55:421
9975993630,1cyclictest167950irq/16-i91522:57:371
9975993630,1cyclictest167950irq/16-i91519:19:411
9975993629,1cyclictest167950irq/16-i91500:11:231
9975993533,2cyclictest167950irq/16-i91519:50:361
9975993533,1cyclictest167950irq/16-i91522:26:201
9975993532,2cyclictest167950irq/16-i91523:34:511
9975993532,2cyclictest167950irq/16-i91522:21:241
9975993532,2cyclictest167950irq/16-i91520:40:331
9975993532,2cyclictest167950irq/16-i91520:23:521
9975993531,0cyclictest167950irq/16-i91523:27:411
9975993531,0cyclictest167950irq/16-i91520:26:191
9975993531,0cyclictest167950irq/16-i91520:26:191
9975993531,0cyclictest167950irq/16-i91520:11:231
9975993531,0cyclictest167950irq/16-i91519:56:221
9975993531,0cyclictest167950irq/16-i91519:41:241
9975993531,0cyclictest167950irq/16-i91519:11:261
9975993531,0cyclictest167950irq/16-i91519:09:541
9974993534,0cyclictest245950irq/16-enp2s0f022:33:100
9975993433,0cyclictest167950irq/16-i91523:20:421
9975993433,0cyclictest167950irq/16-i91521:45:001
9975993433,0cyclictest167950irq/16-i91520:01:241
9975993433,0cyclictest167950irq/16-i91520:01:241
9975993433,0cyclictest167950irq/16-i91519:34:361
9975993432,2cyclictest167950irq/16-i91519:26:131
9975993432,1cyclictest167950irq/16-i91523:46:221
9975993432,1cyclictest167950irq/16-i91521:36:251
9975993431,2cyclictest245950irq/16-enp2s0f023:09:071
9975993431,2cyclictest167950irq/16-i91521:57:001
9975993431,2cyclictest167950irq/16-i91520:32:051
9975993431,0cyclictest167950irq/16-i91523:57:451
9975993431,0cyclictest167950irq/16-i91523:40:451
9975993431,0cyclictest167950irq/16-i91523:01:231
9975993431,0cyclictest167950irq/16-i91522:51:211
9975993431,0cyclictest167950irq/16-i91522:36:191
9975993431,0cyclictest167950irq/16-i91522:32:511
9975993431,0cyclictest167950irq/16-i91522:11:261
9975993431,0cyclictest167950irq/16-i91521:26:551
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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