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2025-11-23 - 02:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Sun Nov 23, 2025 00:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2413324414,22sleep00-21swapper/018:58:010
2325524428,8sleep10-21swapper/118:57:181
24599993831,1cyclictest167950irq/16-i91523:02:271
24599993830,1cyclictest167950irq/16-i91521:17:251
24599993732,4cyclictest167950irq/16-i91500:07:581
24599993633,2cyclictest167950irq/16-i91519:12:031
24599993632,3cyclictest245950irq/16-enp2s0f021:15:511
24599993632,3cyclictest167950irq/16-i91522:07:351
24599993632,3cyclictest167950irq/16-i91521:30:451
24599993631,4cyclictest167950irq/16-i91520:27:151
24599993631,0cyclictest167950irq/16-i91523:17:481
24599993631,0cyclictest167950irq/16-i91522:57:451
24599993631,0cyclictest167950irq/16-i91520:02:101
24599993631,0cyclictest167950irq/16-i91519:57:091
24599993630,0cyclictest167950irq/16-i91523:47:311
24599993532,2cyclictest167950irq/16-i91522:54:351
24599993532,2cyclictest167950irq/16-i91519:21:131
24599993531,0cyclictest245950irq/16-enp2s0f023:32:221
24599993531,0cyclictest245950irq/16-enp2s0f021:32:231
24599993531,0cyclictest167950irq/16-i91522:47:241
24599993531,0cyclictest167950irq/16-i91522:37:261
24599993531,0cyclictest167950irq/16-i91521:53:481
24599993531,0cyclictest167950irq/16-i91521:22:261
24599993531,0cyclictest167950irq/16-i91520:07:041
24599993531,0cyclictest167950irq/16-i91519:27:031
24599993531,0cyclictest167950irq/16-i91500:20:021
24599993530,0cyclictest167950irq/16-i91523:43:421
24599993530,0cyclictest167950irq/16-i91521:41:161
24597993533,1cyclictest245950irq/16-enp2s0f023:52:280
24597993533,1cyclictest245950irq/16-enp2s0f020:15:490
24597993533,1cyclictest245950irq/16-enp2s0f000:19:400
24599993434,0cyclictest167950irq/16-i91523:30:281
24599993431,2cyclictest167950irq/16-i91520:57:271
24599993431,2cyclictest167950irq/16-i91520:47:171
24599993431,0cyclictest167950irq/16-i91523:52:301
24599993431,0cyclictest167950irq/16-i91523:12:151
24599993431,0cyclictest167950irq/16-i91522:43:011
24599993431,0cyclictest167950irq/16-i91522:37:021
24599993431,0cyclictest167950irq/16-i91522:22:401
24599993431,0cyclictest167950irq/16-i91522:18:411
24599993431,0cyclictest167950irq/16-i91522:01:051
24599993431,0cyclictest167950irq/16-i91521:42:381
24599993431,0cyclictest167950irq/16-i91521:05:191
24599993431,0cyclictest167950irq/16-i91520:56:101
24599993431,0cyclictest167950irq/16-i91520:37:251
24599993431,0cyclictest167950irq/16-i91520:12:231
24599993431,0cyclictest167950irq/16-i91520:08:241
24599993431,0cyclictest167950irq/16-i91519:49:571
24599993431,0cyclictest167950irq/16-i91519:43:421
24599993431,0cyclictest167950irq/16-i91519:35:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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