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2025-11-23 - 22:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Sun Nov 23, 2025 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
287202560,0sleep09-21rcu_preempt10:07:090
57612478,8sleep00-21swapper/006:58:360
583524125,8sleep10-21swapper/106:59:191
127372380,0sleep012738-22/usr/sbin/munin07:22:240
6173993433,0cyclictest167950irq/16-i91512:11:291
6173993432,1cyclictest245950irq/16-enp2s0f011:45:511
6173993432,1cyclictest167950irq/16-i91510:54:491
6173993432,1cyclictest167950irq/16-i91507:47:231
6173993432,1cyclictest167950irq/16-i91507:09:111
6172993433,0cyclictest245950irq/16-enp2s0f012:10:400
6172993433,0cyclictest245950irq/16-enp2s0f012:03:470
6172993433,0cyclictest245950irq/16-enp2s0f011:23:580
6172993433,0cyclictest245950irq/16-enp2s0f009:11:520
6172993432,1cyclictest245950irq/16-enp2s0f010:00:480
6172993432,1cyclictest245950irq/16-enp2s0f009:17:250
6172993432,1cyclictest245950irq/16-enp2s0f009:14:420
6172993432,1cyclictest245950irq/16-enp2s0f007:37:460
6172993432,1cyclictest245950irq/16-enp2s0f007:27:270
6173993333,0cyclictest167950irq/16-i91511:56:091
6173993333,0cyclictest167950irq/16-i91510:51:471
6173993333,0cyclictest167950irq/16-i91509:55:251
6173993332,0cyclictest245950irq/16-enp2s0f011:07:221
6173993332,0cyclictest185550irq/16-nvkm10:09:031
6173993332,0cyclictest167950irq/16-i91512:25:061
6173993332,0cyclictest167950irq/16-i91511:57:261
6173993332,0cyclictest167950irq/16-i91511:49:591
6173993332,0cyclictest167950irq/16-i91511:34:561
6173993332,0cyclictest167950irq/16-i91511:16:101
6173993332,0cyclictest167950irq/16-i91511:06:091
6173993332,0cyclictest167950irq/16-i91510:23:471
6173993332,0cyclictest167950irq/16-i91508:52:221
6173993332,0cyclictest167950irq/16-i91508:48:451
6173993332,0cyclictest167950irq/16-i91508:42:201
6173993331,1cyclictest245950irq/16-enp2s0f009:48:251
6173993331,1cyclictest245950irq/16-enp2s0f008:07:271
6173993331,1cyclictest245950irq/16-enp2s0f007:52:291
6173993331,1cyclictest167950irq/16-i91511:26:431
6173993331,1cyclictest167950irq/16-i91509:40:531
6173993331,1cyclictest167950irq/16-i91509:35:531
6173993331,1cyclictest167950irq/16-i91509:26:471
6173993331,1cyclictest167950irq/16-i91509:16:321
6173993331,1cyclictest167950irq/16-i91508:17:211
6173993331,1cyclictest167950irq/16-i91507:57:201
6172993333,0cyclictest245950irq/16-enp2s0f007:57:250
6172993332,1cyclictest245950irq/16-enp2s0f012:27:250
6172993332,0cyclictest245950irq/16-enp2s0f012:22:280
6172993332,0cyclictest245950irq/16-enp2s0f012:17:180
6172993332,0cyclictest245950irq/16-enp2s0f012:12:250
6172993332,0cyclictest245950irq/16-enp2s0f011:47:280
6172993332,0cyclictest245950irq/16-enp2s0f011:42:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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