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2025-12-03 - 19:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Wed Dec 03, 2025 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
160982399,22sleep00-21swapper/006:57:070
173672378,22sleep10-21swapper/107:01:491
17444993531,3cyclictest167950irq/16-i91508:22:101
17443993533,1cyclictest245950irq/16-enp2s0f008:32:140
17444993434,0cyclictest167950irq/16-i91511:25:021
17444993433,0cyclictest245950irq/16-enp2s0f011:57:471
17444993433,0cyclictest167950irq/16-i91512:24:221
17444993433,0cyclictest167950irq/16-i91511:55:271
17444993433,0cyclictest167950irq/16-i91507:35:041
17444993432,1cyclictest221ktimersoftd/110:15:041
17444993432,1cyclictest221ktimersoftd/107:51:571
17444993432,1cyclictest167950irq/16-i91512:04:221
17444993432,1cyclictest167950irq/16-i91511:33:391
17444993432,1cyclictest167950irq/16-i91510:21:361
17444993432,1cyclictest167950irq/16-i91509:42:091
17444993432,1cyclictest167950irq/16-i91507:46:371
17443993433,0cyclictest245950irq/16-enp2s0f011:38:520
17443993433,0cyclictest245950irq/16-enp2s0f011:00:030
17443993433,0cyclictest245950irq/16-enp2s0f009:07:140
17443993433,0cyclictest185550irq/16-nvkm12:10:170
17443993432,1cyclictest245950irq/16-enp2s0f010:52:170
17443993432,1cyclictest245950irq/16-enp2s0f009:36:120
17443993432,1cyclictest245950irq/16-enp2s0f007:52:190
17443993432,1cyclictest167950irq/16-i91511:42:120
17444993333,0cyclictest245950irq/16-enp2s0f010:08:241
17444993333,0cyclictest167950irq/16-i91510:43:191
17444993332,0cyclictest245950irq/16-enp2s0f011:17:121
17444993332,0cyclictest245950irq/16-enp2s0f011:12:151
17444993332,0cyclictest245950irq/16-enp2s0f011:02:201
17444993332,0cyclictest245950irq/16-enp2s0f009:47:121
17444993332,0cyclictest245950irq/16-enp2s0f009:27:201
17444993332,0cyclictest245950irq/16-enp2s0f009:12:271
17444993332,0cyclictest221ktimersoftd/110:23:161
17444993332,0cyclictest167950irq/16-i91512:27:111
17444993332,0cyclictest167950irq/16-i91511:47:161
17444993332,0cyclictest167950irq/16-i91511:28:151
17444993332,0cyclictest167950irq/16-i91511:10:251
17444993332,0cyclictest167950irq/16-i91510:57:101
17444993332,0cyclictest167950irq/16-i91510:53:221
17444993332,0cyclictest167950irq/16-i91510:33:391
17444993332,0cyclictest167950irq/16-i91510:27:431
17444993332,0cyclictest167950irq/16-i91509:37:111
17444993332,0cyclictest167950irq/16-i91509:34:221
17444993332,0cyclictest167950irq/16-i91509:26:021
17444993332,0cyclictest167950irq/16-i91508:57:171
17444993332,0cyclictest167950irq/16-i91508:54:051
17444993332,0cyclictest167950irq/16-i91508:41:031
17444993332,0cyclictest167950irq/16-i91508:29:251
17444993332,0cyclictest167950irq/16-i91508:12:171
17444993332,0cyclictest167950irq/16-i91508:09:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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