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2025-12-06 - 01:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Fri Dec 05, 2025 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
199892610,0sleep10-21swapper/110:17:081
670624512,8sleep10-21swapper/106:57:281
709724124,8sleep00-21swapper/007:01:270
7201993932,6cyclictest245950irq/16-enp2s0f011:52:110
7201993932,6cyclictest245950irq/16-enp2s0f009:42:080
7201993932,6cyclictest245950irq/16-enp2s0f008:01:240
7201993932,6cyclictest245950irq/16-enp2s0f007:36:280
7201993832,5cyclictest245950irq/16-enp2s0f007:39:030
7201993831,6cyclictest245950irq/16-enp2s0f012:27:060
7201993831,6cyclictest245950irq/16-enp2s0f012:01:240
7201993831,6cyclictest245950irq/16-enp2s0f010:52:110
7201993831,6cyclictest245950irq/16-enp2s0f010:47:080
7201993831,6cyclictest245950irq/16-enp2s0f010:02:240
7201993831,6cyclictest245950irq/16-enp2s0f008:15:350
7201993830,7cyclictest245950irq/16-enp2s0f009:57:120
7201993830,7cyclictest245950irq/16-enp2s0f009:02:050
7201993731,5cyclictest245950irq/16-enp2s0f012:22:120
7201993731,5cyclictest245950irq/16-enp2s0f011:24:450
7201993731,5cyclictest245950irq/16-enp2s0f009:54:280
7201993731,5cyclictest245950irq/16-enp2s0f008:24:100
7201993730,6cyclictest245950irq/16-enp2s0f012:07:080
7201993730,6cyclictest245950irq/16-enp2s0f011:37:110
7201993729,7cyclictest245950irq/16-enp2s0f009:37:070
7201993729,7cyclictest245950irq/16-enp2s0f009:27:050
7201993729,7cyclictest245950irq/16-enp2s0f008:47:070
7201993633,2cyclictest245950irq/16-enp2s0f008:04:040
7201993633,2cyclictest245950irq/16-enp2s0f007:26:510
7201993632,3cyclictest245950irq/16-enp2s0f011:33:410
7201993632,3cyclictest245950irq/16-enp2s0f010:35:490
7201993632,3cyclictest245950irq/16-enp2s0f009:00:500
7201993631,4cyclictest245950irq/16-enp2s0f012:17:090
7201993631,4cyclictest245950irq/16-enp2s0f012:03:270
7201993631,4cyclictest245950irq/16-enp2s0f011:27:120
7201993631,4cyclictest245950irq/16-enp2s0f010:12:140
7201993631,4cyclictest245950irq/16-enp2s0f009:14:190
7201993631,4cyclictest245950irq/16-enp2s0f007:48:220
7201993631,4cyclictest167950irq/16-i91507:02:060
7201993630,5cyclictest245950irq/16-enp2s0f012:12:100
7201993630,5cyclictest245950irq/16-enp2s0f011:02:390
7201993630,5cyclictest245950irq/16-enp2s0f010:22:140
7201993630,5cyclictest245950irq/16-enp2s0f008:54:150
7201993630,5cyclictest245950irq/16-enp2s0f008:09:080
7201993630,5cyclictest245950irq/16-enp2s0f007:21:240
7201993629,6cyclictest245950irq/16-enp2s0f008:32:080
7201993532,2cyclictest245950irq/16-enp2s0f011:07:340
7201993532,2cyclictest245950irq/16-enp2s0f010:26:570
7201993532,2cyclictest245950irq/16-enp2s0f007:14:360
7201993532,2cyclictest167950irq/16-i91509:07:110
7201993531,3cyclictest245950irq/16-enp2s0f011:44:590
7201993531,3cyclictest245950irq/16-enp2s0f011:17:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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