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2026-05-29 - 19:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Fri May 29, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
312724011,22sleep00-21swapper/007:04:150
319223923,8sleep10-21swapper/107:04:541
3532993433,0cyclictest168750irq/16-i91510:05:411
3532993432,1cyclictest168750irq/16-i91507:41:551
3532993432,1cyclictest168750irq/16-i91507:32:401
3531993432,1cyclictest246650irq/16-enp2s0f008:59:510
3531993432,1cyclictest246650irq/16-enp2s0f008:46:290
3531993432,1cyclictest246650irq/16-enp2s0f007:19:460
3531993430,0cyclictest168750irq/16-i91509:42:170
3532993333,0cyclictest168750irq/16-i91511:50:311
3532993333,0cyclictest168750irq/16-i91508:01:021
3532993333,0cyclictest168750irq/16-i91507:10:451
3532993332,0cyclictest246650irq/16-enp2s0f012:33:471
3532993332,0cyclictest246650irq/16-enp2s0f011:42:101
3532993332,0cyclictest246650irq/16-enp2s0f010:51:541
3532993332,0cyclictest246650irq/16-enp2s0f010:28:101
3532993332,0cyclictest246650irq/16-enp2s0f009:21:181
3532993332,0cyclictest246650irq/16-enp2s0f009:15:461
3532993332,0cyclictest246650irq/16-enp2s0f008:39:091
3532993332,0cyclictest246650irq/16-enp2s0f008:34:431
3532993332,0cyclictest168750irq/16-i91512:18:321
3532993332,0cyclictest168750irq/16-i91512:08:051
3532993332,0cyclictest168750irq/16-i91512:02:091
3532993332,0cyclictest168750irq/16-i91511:54:461
3532993332,0cyclictest168750irq/16-i91511:43:081
3532993332,0cyclictest168750irq/16-i91511:32:521
3532993332,0cyclictest168750irq/16-i91511:30:121
3532993332,0cyclictest168750irq/16-i91511:19:561
3532993332,0cyclictest168750irq/16-i91511:13:151
3532993332,0cyclictest168750irq/16-i91510:56:191
3532993332,0cyclictest168750irq/16-i91510:45:221
3532993332,0cyclictest168750irq/16-i91510:40:021
3532993332,0cyclictest168750irq/16-i91510:34:151
3532993332,0cyclictest168750irq/16-i91510:23:281
3532993332,0cyclictest168750irq/16-i91509:50:061
3532993332,0cyclictest168750irq/16-i91509:26:031
3532993332,0cyclictest168750irq/16-i91509:11:221
3532993332,0cyclictest168750irq/16-i91509:00:021
3532993332,0cyclictest168750irq/16-i91508:55:011
3532993332,0cyclictest168750irq/16-i91508:50:001
3532993332,0cyclictest168750irq/16-i91508:26:221
3532993332,0cyclictest168750irq/16-i91508:10:041
3532993332,0cyclictest168750irq/16-i91507:55:011
3532993332,0cyclictest168750irq/16-i91507:45:041
3532993331,1cyclictest246650irq/16-enp2s0f007:15:391
3532993331,1cyclictest168750irq/16-i91510:10:311
3532993331,1cyclictest168750irq/16-i91508:44:591
3531993333,0cyclictest246650irq/16-enp2s0f011:48:590
3531993333,0cyclictest246650irq/16-enp2s0f009:26:470
3531993332,0cyclictest246650irq/16-enp2s0f012:36:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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