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2026-08-21 - 23:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Fri Aug 21, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
270462438,28sleep00-21swapper/007:03:160
269552439,8sleep10-21swapper/107:02:191
27374993432,1cyclictest168750irq/16-i91510:58:531
27373993434,0cyclictest246650irq/16-enp2s0f007:31:540
27373993432,1cyclictest246650irq/16-enp2s0f011:40:190
27373993432,1cyclictest246650irq/16-enp2s0f011:25:540
27373993432,1cyclictest246650irq/16-enp2s0f009:46:430
27373993432,1cyclictest246650irq/16-enp2s0f008:38:020
27373993432,1cyclictest246650irq/16-enp2s0f007:24:390
27374993332,0cyclictest246650irq/16-enp2s0f010:26:061
27374993332,0cyclictest246650irq/16-enp2s0f010:18:541
27374993332,0cyclictest246650irq/16-enp2s0f008:47:161
27374993332,0cyclictest246650irq/16-enp2s0f007:38:201
27374993332,0cyclictest168750irq/16-i91512:11:441
27374993332,0cyclictest168750irq/16-i91511:59:061
27374993332,0cyclictest168750irq/16-i91511:46:491
27374993332,0cyclictest168750irq/16-i91511:44:031
27374993332,0cyclictest168750irq/16-i91511:40:501
27374993332,0cyclictest168750irq/16-i91511:17:121
27374993332,0cyclictest168750irq/16-i91511:07:121
27374993332,0cyclictest168750irq/16-i91510:41:211
27374993332,0cyclictest168750irq/16-i91510:39:581
27374993332,0cyclictest168750irq/16-i91510:33:491
27374993332,0cyclictest168750irq/16-i91510:23:431
27374993332,0cyclictest168750irq/16-i91510:03:431
27374993332,0cyclictest168750irq/16-i91509:41:271
27374993332,0cyclictest168750irq/16-i91509:36:191
27374993332,0cyclictest168750irq/16-i91509:26:281
27374993332,0cyclictest168750irq/16-i91509:20:231
27374993332,0cyclictest168750irq/16-i91509:10:071
27374993332,0cyclictest168750irq/16-i91509:06:011
27374993332,0cyclictest168750irq/16-i91508:58:381
27374993332,0cyclictest168750irq/16-i91508:43:281
27374993332,0cyclictest168750irq/16-i91508:33:261
27374993332,0cyclictest168750irq/16-i91508:26:071
27374993332,0cyclictest168750irq/16-i91508:15:361
27374993332,0cyclictest168750irq/16-i91507:47:271
27374993332,0cyclictest168750irq/16-i91507:44:441
27374993332,0cyclictest168750irq/16-i91507:08:111
27374993331,1cyclictest168750irq/16-i91512:24:101
27374993331,1cyclictest168750irq/16-i91512:02:051
27374993331,1cyclictest168750irq/16-i91511:22:251
27374993331,1cyclictest168750irq/16-i91510:52:501
27374993331,1cyclictest168750irq/16-i91510:15:051
27374993331,1cyclictest168750irq/16-i91507:13:121
27373993333,0cyclictest246650irq/16-enp2s0f009:29:420
27373993332,0cyclictest246650irq/16-enp2s0f012:28:330
27373993332,0cyclictest246650irq/16-enp2s0f012:05:040
27373993332,0cyclictest246650irq/16-enp2s0f011:52:070
27373993332,0cyclictest246650irq/16-enp2s0f011:47:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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