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2025-11-11 - 01:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Mon Nov 10, 2025 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
305822580,1sleep00-21swapper/008:27:430
289072580,0sleep128906-22load08:22:411
431224211,23sleep00-21swapper/007:01:010
432123612,16sleep10-21swapper/107:01:061
4509993534,0cyclictest245950irq/16-enp2s0f007:42:480
4509993532,0cyclictest245950irq/16-enp2s0f011:15:070
4510993432,1cyclictest245950irq/16-enp2s0f007:26:441
4510993432,1cyclictest185550irq/16-nvkm11:22:451
4510993432,1cyclictest167950irq/16-i91512:19:021
4510993432,1cyclictest167950irq/16-i91508:40:181
4510993432,1cyclictest167950irq/16-i91507:41:041
4509993433,0cyclictest245950irq/16-enp2s0f011:23:500
4509993433,0cyclictest245950irq/16-enp2s0f008:56:030
4509993432,1cyclictest245950irq/16-enp2s0f012:12:400
4509993432,1cyclictest245950irq/16-enp2s0f011:27:400
4509993432,1cyclictest245950irq/16-enp2s0f011:17:340
4509993432,1cyclictest245950irq/16-enp2s0f010:42:390
4509993432,1cyclictest245950irq/16-enp2s0f010:17:370
4509993432,1cyclictest245950irq/16-enp2s0f010:12:410
4509993432,1cyclictest245950irq/16-enp2s0f009:55:130
4509993432,1cyclictest245950irq/16-enp2s0f007:57:370
4509993432,1cyclictest245950irq/16-enp2s0f007:47:440
4509993432,1cyclictest245950irq/16-enp2s0f007:32:410
4510993333,0cyclictest167950irq/16-i91508:28:591
4510993333,0cyclictest167950irq/16-i91508:08:291
4510993332,0cyclictest245950irq/16-enp2s0f011:43:201
4510993332,0cyclictest245950irq/16-enp2s0f011:12:401
4510993332,0cyclictest245950irq/16-enp2s0f011:07:381
4510993332,0cyclictest245950irq/16-enp2s0f011:00:021
4510993332,0cyclictest245950irq/16-enp2s0f010:12:351
4510993332,0cyclictest245950irq/16-enp2s0f010:05:131
4510993332,0cyclictest245950irq/16-enp2s0f009:33:091
4510993332,0cyclictest245950irq/16-enp2s0f007:52:271
4510993332,0cyclictest167950irq/16-i91512:22:401
4510993332,0cyclictest167950irq/16-i91511:41:031
4510993332,0cyclictest167950irq/16-i91511:36:031
4510993332,0cyclictest167950irq/16-i91511:28:531
4510993332,0cyclictest167950irq/16-i91510:54:231
4510993332,0cyclictest167950irq/16-i91510:22:371
4510993332,0cyclictest167950irq/16-i91509:52:411
4510993332,0cyclictest167950irq/16-i91509:43:451
4510993332,0cyclictest167950irq/16-i91509:38:081
4510993332,0cyclictest167950irq/16-i91509:22:361
4510993332,0cyclictest167950irq/16-i91508:53:271
4510993332,0cyclictest167950irq/16-i91508:50:351
4510993332,0cyclictest167950irq/16-i91508:18:411
4510993332,0cyclictest167950irq/16-i91508:07:121
4510993332,0cyclictest167950irq/16-i91508:07:121
4510993332,0cyclictest167950irq/16-i91507:48:511
4510993332,0cyclictest167950irq/16-i91507:17:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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