You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-15 - 18:08
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Wed Apr 15, 2026 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
80562580,1sleep00-21swapper/007:43:310
32812479,8sleep00-21swapper/007:07:540
320423912,19sleep10-21swapper/107:07:071
3398993534,0cyclictest246650irq/16-enp2s0f012:22:320
3399993433,0cyclictest168750irq/16-i91509:39:401
3399993432,1cyclictest168750irq/16-i91509:50:081
3398993433,0cyclictest246650irq/16-enp2s0f011:58:100
3398993433,0cyclictest246650irq/16-enp2s0f010:30:160
3398993432,1cyclictest246650irq/16-enp2s0f010:02:000
3398993432,1cyclictest246650irq/16-enp2s0f008:07:450
3399993333,0cyclictest168750irq/16-i91511:51:321
3399993333,0cyclictest168750irq/16-i91510:53:071
3399993332,0cyclictest246650irq/16-enp2s0f010:22:321
3399993332,0cyclictest246650irq/16-enp2s0f009:54:431
3399993332,0cyclictest246650irq/16-enp2s0f009:04:461
3399993332,0cyclictest246650irq/16-enp2s0f008:23:541
3399993332,0cyclictest246650irq/16-enp2s0f007:37:171
3399993332,0cyclictest168750irq/16-i91512:37:001
3399993332,0cyclictest168750irq/16-i91512:14:221
3399993332,0cyclictest168750irq/16-i91512:04:591
3399993332,0cyclictest168750irq/16-i91511:45:291
3399993332,0cyclictest168750irq/16-i91511:38:331
3399993332,0cyclictest168750irq/16-i91511:29:291
3399993332,0cyclictest168750irq/16-i91511:27:071
3399993332,0cyclictest168750irq/16-i91511:15:241
3399993332,0cyclictest168750irq/16-i91510:58:561
3399993332,0cyclictest168750irq/16-i91510:34:591
3399993332,0cyclictest168750irq/16-i91510:25:561
3399993332,0cyclictest168750irq/16-i91510:10:241
3399993332,0cyclictest168750irq/16-i91509:25:441
3399993332,0cyclictest168750irq/16-i91509:13:491
3399993332,0cyclictest168750irq/16-i91508:04:491
3399993332,0cyclictest168750irq/16-i91507:55:041
3399993332,0cyclictest168750irq/16-i91507:44:161
3399993332,0cyclictest168750irq/16-i91507:40:001
3399993332,0cyclictest168750irq/16-i91507:29:531
3399993332,0cyclictest168750irq/16-i91507:24:411
3399993332,0cyclictest168750irq/16-i91507:21:031
3399993332,0cyclictest168750irq/16-i91507:12:111
3399993331,1cyclictest168750irq/16-i91512:11:581
3399993331,1cyclictest168750irq/16-i91509:31:241
3398993333,0cyclictest246650irq/16-enp2s0f008:28:410
3398993332,1cyclictest246650irq/16-enp2s0f008:21:250
3398993332,0cyclictest246650irq/16-enp2s0f012:29:520
3398993332,0cyclictest246650irq/16-enp2s0f012:11:290
3398993332,0cyclictest246650irq/16-enp2s0f011:50:300
3398993332,0cyclictest246650irq/16-enp2s0f011:45:290
3398993332,0cyclictest246650irq/16-enp2s0f011:35:390
3398993332,0cyclictest246650irq/16-enp2s0f011:29:420
3398993332,0cyclictest246650irq/16-enp2s0f011:19:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional