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2024-04-20 - 00:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Fri Apr 19, 2024 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2434524313,23sleep00-21swapper/007:05:570
2437024226,8sleep10-21swapper/107:06:141
24584993534,0cyclictest271250irq/16-enp2s0f012:27:520
24584993532,1cyclictest271250irq/16-enp2s0f008:06:400
24585993432,1cyclictest168750irq/16-i91509:38:041
24584993434,0cyclictest271250irq/16-enp2s0f010:12:410
24584993433,0cyclictest271250irq/16-enp2s0f008:19:330
24584993432,1cyclictest271250irq/16-enp2s0f012:36:480
24584993432,1cyclictest271250irq/16-enp2s0f011:33:030
24584993432,1cyclictest271250irq/16-enp2s0f011:18:080
24584993432,1cyclictest271250irq/16-enp2s0f010:28:060
24584993432,1cyclictest271250irq/16-enp2s0f009:59:500
24584993432,1cyclictest271250irq/16-enp2s0f009:38:060
24584993432,1cyclictest271250irq/16-enp2s0f009:13:040
24584993432,1cyclictest271250irq/16-enp2s0f008:23:070
24584993432,1cyclictest271250irq/16-enp2s0f007:48:110
24584993432,1cyclictest271250irq/16-enp2s0f007:12:030
24585993332,0cyclictest271250irq/16-enp2s0f009:33:081
24585993332,0cyclictest271250irq/16-enp2s0f009:19:391
24585993332,0cyclictest271250irq/16-enp2s0f008:15:261
24585993332,0cyclictest168750irq/16-i91512:19:271
24585993332,0cyclictest168750irq/16-i91512:14:541
24585993332,0cyclictest168750irq/16-i91511:57:381
24585993332,0cyclictest168750irq/16-i91511:46:551
24585993332,0cyclictest168750irq/16-i91511:27:591
24585993332,0cyclictest168750irq/16-i91511:24:391
24585993332,0cyclictest168750irq/16-i91511:18:011
24585993332,0cyclictest168750irq/16-i91511:14:351
24585993332,0cyclictest168750irq/16-i91511:09:341
24585993332,0cyclictest168750irq/16-i91511:04:241
24585993332,0cyclictest168750irq/16-i91510:41:591
24585993332,0cyclictest168750irq/16-i91510:06:241
24585993332,0cyclictest168750irq/16-i91509:23:051
24585993332,0cyclictest168750irq/16-i91508:51:001
24585993332,0cyclictest168750irq/16-i91508:33:071
24585993332,0cyclictest168750irq/16-i91508:27:351
24585993332,0cyclictest168750irq/16-i91507:38:041
24585993332,0cyclictest168750irq/16-i91507:33:101
24585993332,0cyclictest168750irq/16-i91507:31:481
24585993332,0cyclictest168750irq/16-i91507:23:001
24585993331,1cyclictest271250irq/16-enp2s0f009:03:071
24585993331,1cyclictest168750irq/16-i91512:28:411
24585993331,1cyclictest168750irq/16-i91512:23:031
24585993331,1cyclictest168750irq/16-i91510:43:021
24585993331,1cyclictest168750irq/16-i91510:11:461
24585993331,1cyclictest168750irq/16-i91509:54:301
24585993331,1cyclictest168750irq/16-i91508:53:101
24584993333,0cyclictest271250irq/16-enp2s0f007:18:090
24584993332,0cyclictest271250irq/16-enp2s0f012:18:020
24584993332,0cyclictest271250irq/16-enp2s0f012:03:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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