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2026-03-31 - 21:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot2.osadl.org (updated Tue Mar 31, 2026 12:43:27)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1211824925,11sleep10-21swapper/107:04:091
12627993433,0cyclictest246650irq/16-enp2s0f011:54:311
12627993433,0cyclictest246650irq/16-enp2s0f011:29:491
12627993433,0cyclictest168750irq/16-i91511:52:221
12627993433,0cyclictest168750irq/16-i91511:19:121
12627993433,0cyclictest168750irq/16-i91509:45:591
12627993433,0cyclictest168750irq/16-i91508:54:561
12627993432,1cyclictest168750irq/16-i91512:31:291
12627993432,1cyclictest168750irq/16-i91511:26:421
12627993432,1cyclictest168750irq/16-i91510:52:331
12627993432,1cyclictest168750irq/16-i91510:02:481
12627993432,1cyclictest168750irq/16-i91507:20:541
12626993432,1cyclictest246650irq/16-enp2s0f010:17:440
12626993432,1cyclictest168750irq/16-i91511:21:410
12627993332,0cyclictest246650irq/16-enp2s0f012:00:151
12627993332,0cyclictest246650irq/16-enp2s0f011:16:401
12627993332,0cyclictest246650irq/16-enp2s0f010:45:311
12627993332,0cyclictest246650irq/16-enp2s0f010:04:511
12627993332,0cyclictest246650irq/16-enp2s0f007:59:431
12627993332,0cyclictest246650irq/16-enp2s0f007:14:371
12627993332,0cyclictest168750irq/16-i91512:20:411
12627993332,0cyclictest168750irq/16-i91512:08:301
12627993332,0cyclictest168750irq/16-i91511:34:081
12627993332,0cyclictest168750irq/16-i91511:07:331
12627993332,0cyclictest168750irq/16-i91510:37:171
12627993332,0cyclictest168750irq/16-i91510:12:291
12627993332,0cyclictest168750irq/16-i91509:56:261
12627993332,0cyclictest168750irq/16-i91509:51:251
12627993332,0cyclictest168750irq/16-i91509:39:201
12627993332,0cyclictest168750irq/16-i91509:38:451
12627993332,0cyclictest168750irq/16-i91509:31:271
12627993332,0cyclictest168750irq/16-i91509:25:031
12627993332,0cyclictest168750irq/16-i91509:13:591
12627993332,0cyclictest168750irq/16-i91509:09:181
12627993332,0cyclictest168750irq/16-i91508:49:021
12627993332,0cyclictest168750irq/16-i91508:45:521
12627993332,0cyclictest168750irq/16-i91508:25:081
12627993332,0cyclictest168750irq/16-i91508:14:591
12627993332,0cyclictest168750irq/16-i91508:08:551
12627993332,0cyclictest168750irq/16-i91508:06:021
12627993332,0cyclictest168750irq/16-i91507:39:551
12627993332,0cyclictest168750irq/16-i91507:11:451
12627993331,1cyclictest246650irq/16-enp2s0f009:20:141
12627993331,1cyclictest168750irq/16-i91509:06:161
12627993331,1cyclictest168750irq/16-i91508:34:411
12626993333,0cyclictest246650irq/16-enp2s0f008:51:010
12626993333,0cyclictest168750irq/16-i91512:09:070
12626993332,0cyclictest246650irq/16-enp2s0f012:32:470
12626993332,0cyclictest246650irq/16-enp2s0f012:07:140
12626993332,0cyclictest246650irq/16-enp2s0f011:43:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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