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2025-12-18 - 10:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot3.osadl.org (updated Thu Dec 18, 2025 01:33:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,7913
"cycles":100000000,7912
"load":"idle",7911
"condition":{7910
"clock":"2200"7908
"family":"x86",7907
"vendor":"Intel",7906
"processor":{7904
"dataset":"2024-01-08T16:38:52+01:00"7902
"origin":"2024-01-08T12:43:22+01:00",7901
"timestamps":{7900
"granularity":"microseconds"7898
1222:51:237896
14,22:51:117895
24,22:51:117894
13,22:51:117893
36,22:51:117892
33,22:51:117891
22,22:51:117890
14,22:51:117889
"maxima":[7888
022:51:117885
0,22:51:117884
0,22:51:117883
0,22:51:117882
0,22:51:117881
0,22:51:117880
0,22:51:117879
0,22:51:117878
0,22:51:117877
0,22:51:117876
0,22:51:117875
0,22:51:117874
0,22:51:117873
0,22:51:117872
0,22:51:117871
0,22:51:117870
0,22:51:117869
0,22:51:117868
0,22:51:117867
0,22:51:117866
0,22:51:117865
0,22:51:117864
0,22:51:117863
0,22:51:117862
0,22:51:117861
0,22:51:117860
0,22:51:117859
0,22:51:117858
0,22:51:117857
0,22:51:117856
0,22:51:117855
0,22:51:117854
0,22:51:117853
0,22:51:117852
0,22:51:117851
0,22:51:117850
0,22:51:117849
0,22:51:117848
0,22:51:117847
0,22:51:117846
0,22:51:117845
0,22:51:117844
0,22:51:117843
0,22:51:117842
0,22:51:117841
0,22:51:117840
0,22:51:117839
0,22:51:117838
0,22:51:117837
0,22:51:117836
0,22:51:117835
0,22:51:117834
0,22:51:117833
0,22:51:117832
0,22:51:117831
0,22:51:117830
0,22:51:117829
0,22:51:117828
0,22:51:117827
0,22:51:117826
0,22:51:117825
0,22:51:117824
0,22:51:117823
0,22:51:117822
0,22:51:117821
0,22:51:117820
0,22:51:117819
0,22:51:117818
0,22:51:117817
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0,22:51:117814
0,22:51:117813
0,22:51:117812
0,22:51:117811
0,22:51:117810
0,22:51:117809
0,22:51:117808
0,22:51:117807
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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