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2026-01-07 - 16:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot3.osadl.org (updated Wed Jan 07, 2026 13:33:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,7913
"cycles":100000000,7912
"load":"idle",7911
"condition":{7910
"clock":"2200"7908
"family":"x86",7907
"vendor":"Intel",7906
"processor":{7904
"dataset":"2024-01-08T16:38:52+01:00"7902
"origin":"2024-01-08T12:43:22+01:00",7901
"timestamps":{7900
"granularity":"microseconds"7898
1215:57:397896
14,15:57:277895
24,15:57:277894
13,15:57:277893
36,15:57:277892
33,15:57:277891
22,15:57:277890
14,15:57:277889
"maxima":[7888
015:57:277885
0,15:57:277884
0,15:57:277883
0,15:57:277882
0,15:57:277881
0,15:57:277880
0,15:57:277879
0,15:57:277878
0,15:57:277877
0,15:57:277876
0,15:57:277875
0,15:57:277874
0,15:57:277873
0,15:57:277872
0,15:57:277871
0,15:57:277870
0,15:57:277869
0,15:57:277868
0,15:57:277867
0,15:57:277866
0,15:57:277865
0,15:57:277864
0,15:57:277863
0,15:57:277862
0,15:57:277861
0,15:57:277860
0,15:57:277859
0,15:57:277858
0,15:57:277857
0,15:57:277856
0,15:57:277855
0,15:57:277854
0,15:57:277853
0,15:57:277852
0,15:57:277851
0,15:57:277850
0,15:57:277849
0,15:57:277848
0,15:57:277847
0,15:57:277846
0,15:57:277845
0,15:57:277844
0,15:57:277843
0,15:57:277842
0,15:57:277841
0,15:57:277840
0,15:57:277839
0,15:57:277838
0,15:57:277837
0,15:57:277836
0,15:57:277835
0,15:57:277834
0,15:57:277833
0,15:57:277832
0,15:57:277831
0,15:57:277830
0,15:57:277829
0,15:57:277828
0,15:57:277827
0,15:57:277826
0,15:57:277825
0,15:57:277824
0,15:57:277823
0,15:57:277822
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0,15:57:277819
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0,15:57:277811
0,15:57:277810
0,15:57:277809
0,15:57:277808
0,15:57:277807
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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