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2025-07-19 - 06:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sat Jul 19, 2025 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2671499112305804,5415cyclictest20348-21kworker/0:100:03:220
2671499104755404,5019cyclictest17056-21kworker/0:119:30:300
2671499102395113,5112cyclictest20348-21kworker/0:123:58:380
2671499101855300,4874cyclictest20348-21kworker/0:123:35:280
2671499100105213,4793cyclictest2295-21kworker/0:223:12:430
267149999255259,4655cyclictest17056-21kworker/0:119:24:100
267149999065248,4647cyclictest17056-21kworker/0:120:19:380
267149998165197,4608cyclictest9921-21kworker/0:221:16:210
267149997825089,4683cyclictest20348-21kworker/0:123:48:350
267149997785080,4687cyclictest20599-21kworker/0:022:40:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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