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2025-11-23 - 02:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sun Nov 23, 2025 00:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1116999109645738,5175cyclictest3451-21kworker/0:200:19:030
1116999104565495,4946cyclictest2869-21kworker/0:021:26:490
111699997515080,4660cyclictest6820-21kworker/0:220:41:530
111699996545034,4609cyclictest17248-21kworker/0:122:59:360
111699996375030,4603cyclictest6820-21kworker/0:219:52:430
111699996155114,4490cyclictest6820-21kworker/0:220:34:100
111699993914800,4580cyclictest30428-21kworker/0:022:25:170
111699993024772,4519cyclictest6820-21kworker/0:221:08:420
111699992134731,4471cyclictest15204-21kworker/0:221:51:050
111699992044729,4471cyclictest6820-21kworker/0:220:11:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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