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2025-09-13 - 10:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sat Sep 13, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2254499110955891,5190cyclictest31342-21kworker/0:220:31:070
2254499106295419,5168cyclictest26450-21kworker/0:021:44:310
2254499102425204,5027cyclictest32160-21kworker/0:123:04:590
2254499101875192,4983cyclictest4431-21kworker/0:100:12:470
225449999745256,4707cyclictest4431-21kworker/0:100:00:410
225449999445256,4676cyclictest26450-21kworker/0:021:15:300
225449999435241,4691cyclictest32160-21kworker/0:123:08:410
225449998045187,4606cyclictest26450-21kworker/0:020:56:190
225449997625061,4690cyclictest26450-21kworker/0:021:30:270
225449997055138,4556cyclictest26450-21kworker/0:022:33:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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