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2025-07-14 - 23:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Mon Jul 14, 2025 12:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1249499103385242,5085cyclictest4957-21kworker/0:009:40:020
124949999675202,4751cyclictest8175-21kworker/0:208:26:060
124949998175171,4641cyclictest8175-21kworker/0:208:52:070
124949997965162,4624cyclictest24949-21kworker/0:008:07:020
124949992934704,4584cyclictest14462-21kworker/0:012:00:430
124949992364702,4530cyclictest25730-21kworker/0:010:10:170
124949991874657,4518cyclictest3914-21kworker/0:211:03:330
124949991144626,4477cyclictest14462-21kworker/0:012:15:480
124949990874621,4462cyclictest8175-21kworker/0:208:56:210
124949990734711,4351cyclictest24949-21kworker/0:007:43:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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