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2026-01-07 - 16:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Wed Jan 07, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
980599100245222,4750cyclictest31490-21kworker/0:207:57:300
98059999185194,4713cyclictest4893-21kworker/0:110:56:180
98059998474948,4884cyclictest10039-21kworker/0:009:54:410
98059998325153,4675cyclictest27276-21kworker/0:112:18:060
98059997415111,4619cyclictest12239-21kworker/0:011:58:200
98059995074997,4505cyclictest31490-21kworker/0:208:55:540
98059993534730,4613cyclictest10039-21kworker/0:010:05:340
98059993474831,4505cyclictest6482-21kworker/0:211:48:130
98059993024788,4503cyclictest27276-21kworker/0:112:32:100
98059991724634,4527cyclictest10039-21kworker/0:009:56:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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