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2025-11-03 - 11:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Mon Nov 03, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
183299105515442,5066cyclictest12038-21kworker/0:121:01:040
183299104965378,5114cyclictest25372-21kworker/0:023:29:100
18329999025263,4627cyclictest14489-21kworker/0:221:06:400
18329998245222,4591cyclictest2153-21kworker/0:020:06:160
18329996365029,4596cyclictest8414-21kworker/0:223:16:580
18329996335125,4497cyclictest2153-21kworker/0:020:18:200
18329994504852,4587cyclictest8414-21kworker/0:223:12:530
18329993904715,4664cyclictest2337-21kworker/0:022:48:030
18329993704810,4549cyclictest31705-21kworker/0:000:39:160
18329992854662,4618cyclictest2153-21kworker/0:019:35:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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