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2024-02-29 - 20:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Thu Feb 29, 2024 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3168299105315405,5103cyclictest31512-21kworker/0:007:22:200
3168299104805402,5075cyclictest31512-21kworker/0:009:13:000
3168299104625498,4961cyclictest31512-21kworker/0:007:56:560
3168299104425488,4951cyclictest24161-21kworker/0:210:34:090
316829998445277,4564cyclictest19481-21kworker/0:011:59:120
316829997975249,4545cyclictest24161-21kworker/0:210:27:550
316829997475232,4512cyclictest31512-21kworker/0:008:36:050
316829997365227,4506cyclictest19481-21kworker/0:012:10:450
316829996835189,4491cyclictest19481-21kworker/0:011:53:110
316829996585187,4468cyclictest31512-21kworker/0:007:19:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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