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2026-07-22 - 04:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Wed Jul 22, 2026 00:45:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
65839992604643,4604cyclictest10426-21kworker/0:123:26:580
65839990594665,4384cyclictest27220-21kworker/0:019:15:590
65839989924522,4456cyclictest23981-21kworker/0:100:01:110
65839984434230,4199cyclictest6767-21kworker/0:200:30:310
65839981284053,4061cyclictest27220-21kworker/0:019:14:130
65839976593940,3697cyclictest21060-21kworker/0:223:45:180
65839973963872,3464cyclictest21060-21kworker/0:223:43:240
65839972713818,3393cyclictest23981-21kworker/0:123:59:120
65839972383806,3380cyclictest1601-21kworker/0:100:13:330
65839971413749,3333cyclictest10426-21kworker/0:123:25:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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