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2025-05-09 - 06:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Fri May 09, 2025 00:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2408599108315548,5279cyclictest4079-21kworker/0:022:19:590
240859999915202,4778cyclictest14314-21kworker/0:000:21:250
240859998694873,4982cyclictest18458-21kworker/0:123:38:320
240859997985115,4671cyclictest4079-21kworker/0:022:08:100
240859997425064,4667cyclictest14314-21kworker/0:000:33:260
240859996045118,4475cyclictest13446-21kworker/0:019:24:020
240859996015109,4481cyclictest13446-21kworker/0:020:28:400
240859995925010,4571cyclictest11999-21kworker/0:223:23:560
240859994194839,4569cyclictest31670-21kworker/0:000:09:030
240859993114680,4626cyclictest4079-21kworker/0:022:28:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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