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2026-03-09 - 07:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Mon Mar 09, 2026 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
595299109425452,5476cyclictest10700-21kworker/0:021:38:030
595299105305239,5277cyclictest10700-21kworker/0:020:56:280
59529987474668,4069cyclictest23087-21kworker/0:119:19:170
59529986394607,4021cyclictest23087-21kworker/0:119:23:210
59529986154267,4297cyclictest10700-21kworker/0:020:52:470
59529982184295,3909cyclictest32501-21kworker/0:220:41:510
59529980594092,3943cyclictest8596-21kworker/0:122:06:340
59529979504135,3792cyclictest23087-21kworker/0:119:14:160
59529979394306,3582cyclictest23087-21kworker/0:119:32:080
59529978613991,3856cyclictest32501-21kworker/0:220:25:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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