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2023-03-31 - 12:24

x86 Intel Celeron M @1500 MHz, Linux 5.15.32-rt39 (Profile)

Latency plot of system in rack #6, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Fri Mar 31, 2023 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1719799105005358,5138cyclictest30351-21kworker/0:022:12:210
171979999085239,4658cyclictest13662-21kworker/0:219:43:410
171979998545216,4634cyclictest4963-21kworker/0:020:28:550
171979998145177,4626cyclictest31388-21kworker/0:123:21:520
171979997555165,4578cyclictest4963-21kworker/0:020:51:210
171979997385139,4588cyclictest29073-21kworker/0:221:22:190
171979995885083,4501cyclictest4963-21kworker/0:020:37:560
171979992934740,4538cyclictest13662-21kworker/0:219:24:370
171979992864641,4633cyclictest29073-21kworker/0:221:17:330
171979991944702,4481cyclictest31388-21kworker/0:123:12:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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