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2026-02-21 - 20:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sat Feb 21, 2026 12:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1676899107125480,5221cyclictest7821-21kworker/0:109:36:420
167689997655094,4660cyclictest15771-21kworker/0:011:06:060
167689993714802,4565cyclictest10194-21kworker/0:210:37:110
167689993294651,4635cyclictest10229-21kworker/0:008:52:450
167689992674757,4499cyclictest7821-21kworker/0:109:48:480
167689991744590,4569cyclictest15771-21kworker/0:010:51:290
167689990674516,4500cyclictest10229-21kworker/0:008:47:350
167689990214646,4371cyclictest10229-21kworker/0:007:23:040
167689989614594,4356cyclictest7821-21kworker/0:109:31:090
167689988594558,4296cyclictest10229-21kworker/0:008:13:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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