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2026-04-23 - 15:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Thu Apr 23, 2026 12:44:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2239299110745619,5441cyclictest6946-21kworker/0:011:32:150
223929992984768,4526cyclictest17060-21kworker/0:211:54:530
223929989474759,4137cyclictest22722-21kworker/0:107:31:300
223929987324500,4221cyclictest1078-21kworker/0:208:32:410
223929986974482,4204cyclictest1078-21kworker/0:208:49:150
223929986724610,3975cyclictest27723-21kworker/0:211:07:570
223929982534147,4067cyclictest1078-21kworker/0:209:29:020
223929981944045,4134cyclictest1078-21kworker/0:208:03:030
223929981804178,3960cyclictest22722-21kworker/0:107:14:190
223929980834343,3688cyclictest1078-21kworker/0:208:36:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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