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2026-09-19 - 22:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sat Sep 19, 2026 12:45:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1955999104825379,5093cyclictest2349-21kworker/0:208:11:150
1955999102225234,4974cyclictest28719-21kworker/0:211:25:250
195599997585200,4548cyclictest18484-21kworker/0:108:46:350
195599988694436,4420cyclictest18484-21kworker/0:109:06:520
195599987864533,4249cyclictest2349-21kworker/0:208:04:310
195599987794475,4254cyclictest4740-21kworker/0:011:46:280
195599982154120,4081cyclictest31030-21kworker/0:007:17:540
195599981444461,3669cyclictest4740-21kworker/0:012:01:540
195599981184246,3822cyclictest2349-21kworker/0:208:16:560
195599980844355,3715cyclictest30659-21kworker/0:007:37:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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