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2024-04-25 - 21:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Thu Apr 25, 2024 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2666299113796015,5361cyclictest21438-21kworker/0:011:25:000
2666299112675965,5299cyclictest21438-21kworker/0:010:44:250
2666299112395942,5294cyclictest3081-21kworker/0:109:54:570
2666299110575862,5192cyclictest27346-21kworker/0:208:40:470
2666299110195842,5174cyclictest21438-21kworker/0:011:03:070
2666299104915382,5106cyclictest27346-21kworker/0:209:19:230
2666299103805529,4848cyclictest7150-21kworker/0:210:16:420
2666299102055216,4974cyclictest26514-21kworker/0:107:37:540
266629998795261,4615cyclictest22349-21kworker/0:212:31:570
266629998255231,4591cyclictest22349-21kworker/0:212:05:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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