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2026-06-06 - 19:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sat Jun 06, 2026 00:44:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
268119997845111,4662cyclictest5682-21kworker/0:119:43:170
268119996495142,4496cyclictest5682-21kworker/0:119:53:580
268119996165026,4579cyclictest6727-21kworker/0:019:28:070
268119994614933,4513cyclictest20844-21kworker/0:021:21:580
268119992954785,4506cyclictest5682-21kworker/0:119:59:160
268119991284702,4421cyclictest20844-21kworker/0:020:41:090
268119990544661,4382cyclictest21288-21kworker/0:221:38:490
268119989594595,4353cyclictest14132-21kworker/0:023:00:330
268119989254599,4322cyclictest27308-21kworker/0:022:02:110
268119988754614,4247cyclictest20844-21kworker/0:021:10:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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