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2025-12-07 - 04:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Sun Dec 07, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2541899120516230,5770cyclictest28797-21kworker/0:119:25:340
2541899114005928,5462cyclictest22399-21kworker/0:121:01:470
2541899108415446,5391cyclictest22399-21kworker/0:121:13:120
2541899104095237,5157cyclictest28797-21kworker/0:119:51:330
254189999215289,4621cyclictest22399-21kworker/0:120:31:150
254189997435203,4529cyclictest22399-21kworker/0:120:46:380
254189997235091,4621cyclictest31094-21kworker/0:122:51:400
254189996885173,4504cyclictest22399-21kworker/0:120:54:100
254189993724816,4545cyclictest26102-21kworker/0:022:09:570
254189993324818,4509cyclictest17413-21kworker/0:000:25:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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