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2026-07-22 - 01:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot5.osadl.org (updated Tue Jul 21, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
595199100395364,4664cyclictest22050-21kworker/0:107:43:370
59519998735182,4681cyclictest22050-21kworker/0:108:51:050
59519995455018,4517cyclictest22050-21kworker/0:108:19:260
59519990274669,4354cyclictest22050-21kworker/0:107:49:370
59519990174568,4439cyclictest22050-21kworker/0:108:31:380
59519990094570,4435cyclictest22050-21kworker/0:108:44:470
59519989874652,4324cyclictest22050-21kworker/0:107:24:070
59519988934509,4381cyclictest22050-21kworker/0:108:25:230
59519984344230,4154cyclictest22050-21kworker/0:108:23:490
59519983754336,4025cyclictest20429-21kworker/0:209:11:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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