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2026-02-06 - 12:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack6slot5.osadl.org (updated Fri Feb 06, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2807199100155332,4672cyclictest9987-21kworker/0:120:19:190
280719997845236,4545cyclictest10098-21kworker/0:019:13:000
280719997415198,4539cyclictest9987-21kworker/0:119:49:550
280719997385095,4632cyclictest3118-21kworker/0:219:28:160
280719996615059,4598cyclictest3118-21kworker/0:219:33:070
280719994184707,4659cyclictest3118-21kworker/0:219:42:210
280719990354661,4363cyclictest10098-21kworker/0:019:19:510
280719989234606,4306cyclictest27019-21kworker/0:220:52:510
280719988494747,4090cyclictest9987-21kworker/0:119:56:280
280719987314707,4013cyclictest27019-21kworker/0:220:35:420
280719987094696,4002cyclictest3431-21kworker/0:021:00:580
280719986844464,4206cyclictest18432-21kworker/0:123:54:230
280719986694394,4261cyclictest10098-21kworker/0:019:22:130
280719984264247,4164cyclictest17395-21kworker/0:221:33:320
280719984134236,4125cyclictest27019-21kworker/0:220:42:300
280719983944381,3999cyclictest9987-21kworker/0:120:02:130
280719983024157,4093cyclictest3118-21kworker/0:219:36:540
280719981134071,4019cyclictest22477-21kworker/0:222:54:380
280719981124342,3719cyclictest3549-21kworker/0:023:23:350
280719980284438,3567cyclictest4723-21kworker/0:222:15:270
280719979954325,3655cyclictest12090-21kworker/0:123:39:150
280719979694272,3654cyclictest9987-21kworker/0:120:26:200
280719979644197,3752cyclictest28376-21kworker/0:023:10:260
280719979054169,3713cyclictest4723-21kworker/0:222:29:160
280719978844136,3696cyclictest24705-21kworker/0:000:24:530
280719978723931,3890cyclictest9987-21kworker/0:119:54:520
280719977883908,3828cyclictest27019-21kworker/0:220:34:070
280719977274177,3535cyclictest22732-21kworker/0:121:47:250
280719974533922,3480cyclictest9987-21kworker/0:120:09:340
280719973543891,3448cyclictest22732-21kworker/0:121:58:580
280719973043842,3411cyclictest3431-21kworker/0:020:59:230
280719972893854,3420cyclictest4723-21kworker/0:222:13:250
280719972623745,3502cyclictest28376-21kworker/0:023:07:340
280719967373651,3005cyclictest15968-21kworker/0:022:39:400
280719966663576,3079cyclictest3431-21kworker/0:021:09:250
280719966063597,2995cyclictest3431-21kworker/0:021:18:530
280719966063512,3079cyclictest24705-21kworker/0:000:39:440
280719965513388,3139cyclictest24705-21kworker/0:000:26:540
280719964163453,2959cyclictest9987-21kworker/0:120:11:090
280719963403289,3036cyclictest3549-21kworker/0:023:25:280
280719962983449,2798cyclictest24705-21kworker/0:000:07:470
280719962553419,2784cyclictest22732-21kworker/0:121:44:170
280719962453137,3093cyclictest24705-21kworker/0:000:10:320
280719943894332,44cyclictest3431-21kworker/0:021:20:520
280719941402495,1621cyclictest22732-21kworker/0:122:00:580
280719925582440,104cyclictest15968-21kworker/0:022:41:360
278922866185,203sleep00-21swapper19:09:090
28071995481,533cyclictest3495-21ssh23:18:050
280719948554,256cyclictest11-21ksoftirqd/022:59:300
280719947133,438cyclictest0-21swapper21:54:590
280719945887,357cyclictest345450irq/10-yenta21:27:360
28071994512,435cyclictest22185-21ssh22:49:360
28071994505,430cyclictest8698-21diskmemload00:00:380
28071994501,388cyclictest29065-21ssh23:04:100
280719944180,348cyclictest4404-21ssh22:09:040
28071994365,371cyclictest10771-21ssh23:33:490
28071994361,374cyclictest8698-21diskmemload00:33:280
28071994361,374cyclictest22181-21ssh21:37:030
28071994361,374cyclictest16318-21ssh22:34:530
28071994360,374cyclictest8698-21diskmemload22:21:560
28071994251,248cyclictest22364-21ssh23:58:030
280719942338,88cyclictest11-21ksoftirqd/021:11:070
280719940340,349cyclictest32072-21latency_hist00:20:050
280719939734,350cyclictest15242-21ssh23:42:020
280719938731,356cyclictest0-21swapper20:48:400
280719937932,347cyclictest0-21swapper23:48:340
280719934434,310cyclictest0-21swapper20:20:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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