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2026-09-15 - 04:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Sep 15, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
140189910702453407,53526cyclictest0-21swapper23:39:060
140189910692353386,53474cyclictest134850irq/9-eth023:51:200
140189910668153393,53199cyclictest13986-21cyclictest00:36:330
140189910665153444,53115cyclictest0-21swapper21:32:300
140189910661053447,53163cyclictest0-21swapper22:12:410
140189910660453409,53103cyclictest9-21ksoftirqd/023:44:170
140189910660353469,53134cyclictest0-21swapper20:46:560
140189910660353354,53214cyclictest24853-21ssh22:24:240
140189910658953434,53155cyclictest0-21swapper19:27:540
140189910655553391,53099cyclictest0-21swapper22:35:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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