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2026-08-27 - 05:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Aug 27, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6359910705053414,53571cyclictest0-21swapper20:32:590
6359910682653458,53303cyclictest27352-21ssh22:43:160
6359910653053449,53081cyclictest0-21swapper20:13:530
6359910651653476,53040cyclictest0-21swapper20:55:350
6359910651653475,53041cyclictest0-21swapper19:25:390
6359910650953457,53052cyclictest0-21swapper00:23:150
6359910649753467,53030cyclictest0-21swapper22:37:550
6359910648953468,53021cyclictest0-21swapper23:15:060
6359910648453461,53023cyclictest0-21swapper22:30:430
6359910648153458,53023cyclictest0-21swapper21:08:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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