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2026-02-28 - 00:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Feb 27, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5189910900154553,54423cyclictest1741-21hald12:09:340
5189910772553401,54238cyclictest20576-21munin-node11:35:140
5189910681053455,53264cyclictest0-21swapper11:05:550
5189910675753353,53391cyclictest0-21swapper07:10:580
5189910673153412,53223cyclictest11668-21ssh11:21:100
5189910665253385,53177cyclictest134850irq/9-eth010:44:490
5189910657153384,53122cyclictest0-21swapper08:54:270
5189910655353391,53070cyclictest0-21swapper09:05:310
5189910650853476,53032cyclictest0-21swapper12:10:140
5189910649253426,53066cyclictest0-21swapper12:29:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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