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2026-08-22 - 02:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Aug 21, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
237829910709853427,53606cyclictest9-21ksoftirqd/011:16:240
237829910696753447,53520cyclictest0-21swapper09:56:010
237829910683053396,53372cyclictest9-21ksoftirqd/012:16:110
237829910669853385,53248cyclictest0-21swapper12:31:150
237829910669753470,53163cyclictest9-21ksoftirqd/007:38:210
237829910669353468,53134cyclictest0-21swapper08:10:300
237829910652653481,53045cyclictest0-21swapper08:40:090
237829910651653388,53128cyclictest0-21swapper08:17:020
237829910650653474,53032cyclictest0-21swapper11:24:060
237829910649153409,53082cyclictest0-21swapper10:04:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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