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2025-11-07 - 15:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Nov 07, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
65299910722253468,53657cyclictest1013-21ssh10:08:390
65299910671353435,53278cyclictest0-21swapper08:12:450
65299910662253448,53174cyclictest0-21swapper09:58:160
65299910660053477,53032cyclictest0-21swapper11:04:050
65299910658253406,53084cyclictest0-21swapper07:31:230
65299910658053464,53116cyclictest0-21swapper08:30:100
65299910657153402,53078cyclictest0-21swapper07:48:280
65299910656353397,53103cyclictest9-21ksoftirqd/010:51:410
65299910655553481,53074cyclictest0-21swapper08:15:160
65299910655253479,53073cyclictest0-21swapper07:10:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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