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2026-05-22 - 16:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri May 22, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33579910667653421,53189cyclictest0-21swapper20:44:440
33579910666553473,53101cyclictest0-21swapper22:02:060
33579910661853302,53301cyclictest8369-21ssh23:45:360
33579910656053385,53110cyclictest21487-21kworker/0:121:10:510
33579910652053477,53043cyclictest0-21swapper22:05:570
33579910651253403,53109cyclictest0-21swapper19:49:180
33579910650453469,53035cyclictest0-21swapper19:35:240
33579910647953465,53014cyclictest0-21swapper23:40:440
33579910646853456,53012cyclictest0-21swapper23:56:190
33579910643453395,53039cyclictest0-21swapper20:50:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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