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2026-07-25 - 17:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Jul 25, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243969910736253462,53804cyclictest2099-21runrttasks08:09:160
243969910725953421,53742cyclictest9343-21diskmemload11:03:260
243969910707253418,53556cyclictest26041-21ssh12:34:530
243969910685953426,53312cyclictest9343-21diskmemload12:03:140
243969910660653478,53128cyclictest0-21swapper08:38:040
243969910659053421,53103cyclictest0-21swapper10:07:100
243969910654453418,53034cyclictest0-21swapper07:24:030
243969910653753414,53032cyclictest0-21swapper08:15:280
243969910653353384,53084cyclictest0-21swapper10:24:150
243969910650853473,53035cyclictest0-21swapper09:49:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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