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2026-06-25 - 15:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Jun 25, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
271809910726353450,53691cyclictest28356-21ssh11:53:520
271809910695953384,53483cyclictest0-21swapper09:27:000
271809910677253462,53221cyclictest9-21ksoftirqd/009:42:540
271809910675153472,53189cyclictest9-21ksoftirqd/007:29:060
271809910673753467,53270cyclictest0-21swapper09:24:390
271809910665253475,53177cyclictest0-21swapper12:16:080
271809910659753433,53164cyclictest0-21swapper12:37:350
271809910654153404,53137cyclictest0-21swapper09:03:430
271809910651553475,53040cyclictest0-21swapper11:48:500
271809910651253435,53077cyclictest0-21swapper11:39:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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