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2026-06-06 - 02:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Jun 06, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
227779910655853395,53163cyclictest0-21swapper19:28:350
227779910655853394,53099cyclictest0-21swapper23:40:580
227779910650753473,53034cyclictest0-21swapper23:16:510
227779910650353477,53026cyclictest0-21swapper00:28:220
227779910650253428,53074cyclictest0-21swapper19:54:330
227779910649753412,53085cyclictest0-21swapper20:52:090
227779910649353437,53056cyclictest0-21swapper22:29:570
227779910649153438,53053cyclictest0-21swapper00:32:530
227779910649053467,53023cyclictest0-21swapper23:14:100
227779910647253414,53058cyclictest0-21swapper21:25:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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