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2025-12-06 - 08:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Dec 06, 2025 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25479910671253412,53300cyclictest0-21swapper20:54:010
25479910659753475,53122cyclictest0-21swapper23:35:070
25479910656253408,53058cyclictest13422-21ssh00:20:100
25479910656253394,53103cyclictest0-21swapper23:30:460
25479910655853472,53086cyclictest0-21swapper21:03:430
25479910654253412,53040cyclictest0-21swapper19:50:320
25479910651553420,53032cyclictest3950irq/9-acpi22:36:500
25479910651453479,53035cyclictest0-21swapper23:18:220
25479910650253469,53033cyclictest0-21swapper23:07:090
25479910649553468,53027cyclictest0-21swapper00:19:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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