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2026-04-07 - 20:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Apr 07, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
216309910695053386,53479cyclictest0-21swapper12:03:120
216309910690953402,53412cyclictest2099-21runrttasks10:15:310
216309910680153475,53326cyclictest0-21swapper09:08:520
216309910664253396,53246cyclictest0-21swapper08:39:430
216309910661653449,53167cyclictest0-21swapper11:48:380
216309910661453380,53144cyclictest9-21ksoftirqd/011:15:480
216309910660153474,53127cyclictest0-21swapper12:30:300
216309910659753398,53109cyclictest9-21ksoftirqd/011:21:500
216309910657753407,53104cyclictest0-21swapper08:11:050
216309910657353404,53105cyclictest9-21ksoftirqd/010:57:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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