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2026-08-09 - 14:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Aug 09, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
301339910724353474,53671cyclictest28138-21ssh22:37:560
301339910669753470,53137cyclictest9-21ksoftirqd/022:55:410
301339910667053467,53203cyclictest0-21swapper19:27:010
301339910658653467,53119cyclictest0-21swapper19:56:290
301339910656253382,53089cyclictest0-21swapper21:55:340
301339910654853387,53095cyclictest0-21swapper22:48:190
301339910653453384,53084cyclictest0-21swapper19:34:130
301339910650253468,53034cyclictest0-21swapper22:33:150
301339910646953411,53058cyclictest0-21swapper00:39:310
301339910645853473,52985cyclictest0-21swapper19:19:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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