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2026-03-25 - 12:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Mar 25, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
316689910704453445,53533cyclictest300862sleep019:38:530
316689910666253472,53190cyclictest0-21swapper23:34:510
316689910656753393,53076cyclictest20480-21runrttasks20:33:490
316689910654153384,53091cyclictest0-21swapper23:12:050
316689910652253483,53039cyclictest0-21swapper21:50:110
316689910651353418,53095cyclictest0-21swapper23:27:390
316689910650953474,53035cyclictest0-21swapper22:07:560
316689910650853468,53040cyclictest0-21swapper22:44:370
316689910650153476,53025cyclictest0-21swapper23:17:060
316689910649953470,53029cyclictest0-21swapper00:26:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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