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2026-03-15 - 07:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Mar 15, 2026 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2179599209928105447,104479cyclictest0-21swapper23:56:200
217959910702853401,53537cyclictest7317-1kworker/u3:222:15:100
217959910672053439,53281cyclictest0-21swapper21:47:220
217959910666653389,53186cyclictest9-21ksoftirqd/022:34:460
217959910665253411,53176cyclictest0-21swapper00:34:200
217959910664353457,53186cyclictest0-21swapper22:09:590
217959910662253478,53144cyclictest0-21swapper19:43:070
217959910660653433,53173cyclictest0-21swapper22:03:370
217959910656053459,53101cyclictest0-21swapper21:39:000
217959910655753426,53131cyclictest0-21swapper21:58:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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