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2026-06-24 - 14:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Jun 24, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
255149910699553407,53492cyclictest24330-21ssh11:53:470
255149910669753399,53204cyclictest0-21swapper08:54:460
255149910667253388,53192cyclictest0-21swapper08:16:350
255149910662353413,53119cyclictest10-21rcuc/009:26:350
255149910654153447,53094cyclictest0-21swapper11:39:330
255149910653953428,53045cyclictest0-21swapper10:24:110
255149910651153429,53082cyclictest0-21swapper08:20:260
255149910650853473,53035cyclictest0-21swapper12:18:240
255149910650753476,53031cyclictest0-21swapper11:19:170
255149910650353469,53034cyclictest0-21swapper08:39:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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