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2026-03-24 - 10:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Mar 24, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
87539910760353474,54008cyclictest20668-21ssh23:26:240
87539910713053441,53568cyclictest13350-21ssh00:02:340
87539910674953413,53245cyclictest0-21swapper20:36:250
87539910670653407,53299cyclictest0-21swapper22:21:450
87539910653553395,53073cyclictest0-21swapper20:21:310
87539910651253433,53079cyclictest0-21swapper22:12:530
87539910649053409,53081cyclictest0-21swapper21:47:050
87539910648853468,53020cyclictest0-21swapper20:58:410
87539910646653412,53054cyclictest0-21swapper21:16:260
87539910645153452,52999cyclictest0-21swapper22:34:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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