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2026-08-11 - 18:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Aug 11, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2473699209885105398,104485cyclictest0-21swapper07:55:160
247369910758053457,54032cyclictest12022-21kworker/u2:009:18:100
247369910691253466,53350cyclictest20432-21ssh11:48:340
247369910689953391,53412cyclictest1907-21snmpd12:06:590
247369910684653481,53300cyclictest134850irq/9-eth007:41:220
247369910683753393,53381cyclictest3950irq/9-acpi11:31:390
247369910673453403,53331cyclictest0-21swapper11:04:110
247369910670953326,53360cyclictest18315-21ssh09:21:310
247369910659553426,53105cyclictest9-21ksoftirqd/012:12:100
247369910654753388,53094cyclictest0-21swapper09:31:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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