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2026-05-03 - 15:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun May 03, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231159910712353461,53540cyclictest25515-21ssh11:11:020
231159910670953432,53277cyclictest0-21swapper08:46:100
231159910666153413,53158cyclictest0-21swapper08:42:290
231159910662253479,53143cyclictest0-21swapper07:26:170
231159910661453412,53138cyclictest9-21ksoftirqd/011:30:580
231159910656353450,53113cyclictest0-21swapper07:21:060
231159910654153452,53089cyclictest0-21swapper11:22:550
231159910650153423,53078cyclictest0-21swapper09:09:070
231159910649453464,53030cyclictest0-21swapper12:21:420
231159910649053479,53011cyclictest0-21swapper08:14:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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