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2026-06-22 - 12:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Jun 22, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
287959910711553459,53560cyclictest11343-21diskmemload23:32:440
287959910693253463,53469cyclictest0-21swapper23:40:260
287959910690453472,53432cyclictest11331-21ssh21:56:260
287959910660053400,53103cyclictest22957-21ssh00:38:130
287959910659853409,53189cyclictest0-21swapper21:13:440
287959910659253396,53105cyclictest9-21ksoftirqd/023:47:280
287959910656953382,53099cyclictest9-21ksoftirqd/022:40:290
287959910655953391,53101cyclictest0-21swapper23:26:520
287959910655353463,53090cyclictest0-21swapper19:59:120
287959910652553471,53054cyclictest0-21swapper22:12:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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