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2026-02-09 - 16:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Feb 09, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165309910703753391,53582cyclictest147692sleep011:05:590
165309910678353459,53324cyclictest0-21swapper07:59:360
165309910668253445,53237cyclictest0-21swapper12:19:010
165309910666953424,53154cyclictest28031-21kworker/0:011:26:150
165309910652153461,52968cyclictest0-21swapper08:13:000
165309910650453474,53030cyclictest0-21swapper10:48:450
165309910649653477,53019cyclictest0-21swapper11:51:330
165309910649453394,53100cyclictest0-21swapper09:06:550
165309910649353469,53024cyclictest0-21swapper09:00:330
165309910649353409,53084cyclictest0-21swapper08:48:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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