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2026-08-20 - 23:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Aug 20, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1812099209854105356,104496cyclictest0-21swapper09:10:230
181209910741453458,53857cyclictest2099-21runrttasks07:28:530
181209910666353416,53157cyclictest0-21swapper08:34:020
181209910660053402,53133cyclictest0-21swapper08:47:460
181209910657653401,53084cyclictest0-21swapper12:31:310
181209910653953442,53097cyclictest0-21swapper11:27:320
181209910652053402,53026cyclictest0-21swapper12:02:120
181209910651153472,53039cyclictest0-21swapper12:20:470
181209910650053468,53032cyclictest0-21swapper08:35:020
181209910649353468,53025cyclictest0-21swapper10:33:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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