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2026-01-31 - 15:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Jan 31, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
61279910688353441,53345cyclictest6742-21ssh09:32:190
61279910680453441,53275cyclictest3950irq/9-acpi09:22:570
61279910672453387,53274cyclictest134850irq/9-eth012:34:120
61279910667853471,53162cyclictest3950irq/9-acpi07:24:530
61279910666053470,53190cyclictest0-21swapper11:26:220
61279910664153461,53180cyclictest0-21swapper11:31:140
61279910662453453,53171cyclictest0-21swapper08:45:460
61279910658453433,53151cyclictest0-21swapper10:37:580
61279910655853443,53051cyclictest134850irq/9-eth009:13:440
61279910654753407,53140cyclictest0-21swapper08:27:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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