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2026-03-01 - 01:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Feb 28, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1149299210530105348,105180cyclictest3471-21kworker/0:210:09:140
1149299209956105453,104501cyclictest21315-21ssh11:22:050
114929910687553461,53414cyclictest0-21swapper08:02:070
114929910676453432,53244cyclictest9-21ksoftirqd/008:17:520
114929910673853407,53265cyclictest0-21swapper07:36:300
114929910667253449,53159cyclictest11491-21cyclictest12:25:430
114929910654653405,53141cyclictest0-21swapper08:52:320
114929910653753436,53101cyclictest0-21swapper08:42:190
114929910648853465,53023cyclictest0-21swapper07:57:360
114929910648353472,53011cyclictest0-21swapper09:56:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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