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2026-05-20 - 03:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed May 20, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
297679910716553436,53633cyclictest14893-21ssh21:10:010
297679910694653468,53478cyclictest0-21swapper00:17:250
297679910687453435,53345cyclictest0-21swapper23:23:000
297679910679753397,53304cyclictest14786-21diskmemload22:12:090
297679910669453421,53182cyclictest29760-21cyclictest20:28:290
297679910660953389,53130cyclictest9-21ksoftirqd/019:44:470
297679910657353440,53133cyclictest0-21swapper19:56:000
297679910655353392,53071cyclictest0-21swapper22:25:330
297679910654053470,53070cyclictest0-21swapper00:28:590
297679910653753470,53067cyclictest0-21swapper22:37:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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