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2026-08-28 - 06:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Aug 28, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
189919910694653383,53478cyclictest0-21swapper22:51:140
189919910675253456,53296cyclictest0-21swapper23:31:350
189919910674353436,53307cyclictest0-21swapper23:29:250
189919910664353384,53194cyclictest0-21swapper20:46:280
189919910653853410,53035cyclictest0-21swapper23:06:580
189919910647153441,53030cyclictest0-21swapper19:18:120
189919910646053435,53025cyclictest0-21swapper19:50:420
189919910645453445,53009cyclictest0-21swapper20:53:500
189919910644653446,53000cyclictest0-21swapper23:55:020
189919910644253400,53042cyclictest0-21swapper20:44:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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