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2026-06-04 - 01:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Jun 03, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
43159910702753465,53463cyclictest2099-21runrttasks07:48:340
43159910675753448,53309cyclictest0-21swapper11:20:350
43159910668553419,53266cyclictest0-21swapper10:21:280
43159910664553424,53155cyclictest0-21swapper07:12:230
43159910657853462,53116cyclictest0-21swapper09:23:210
43159910649153469,53022cyclictest0-21swapper07:42:120
43159910649053468,53022cyclictest0-21swapper11:54:350
43159910648053403,53077cyclictest0-21swapper12:10:390
43159910647253400,53072cyclictest0-21swapper12:29:450
43159910627653473,52803cyclictest0-21swapper07:37:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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