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2026-07-11 - 07:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Jul 11, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
102729910718553476,53609cyclictest7589-21ssh22:25:490
102729910703153410,53530cyclictest0-21swapper00:04:170
102729910702353459,53564cyclictest22053-21ssh00:23:330
102729910670553443,53170cyclictest0-21swapper19:21:050
102729910669353452,53241cyclictest0-21swapper23:09:010
102729910658053407,53173cyclictest0-21swapper19:41:310
102729910651353479,53034cyclictest0-21swapper20:38:080
102729910648853474,53014cyclictest0-21swapper20:19:520
102729910646153410,53051cyclictest0-21swapper21:48:280
102729910643753479,52893cyclictest9-21ksoftirqd/022:17:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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