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2026-03-29 - 03:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Mar 29, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2388899210860105405,105453cyclictest0-21swapper22:52:280
238889910713553423,53590cyclictest10762-21rm00:22:240
238889910680553467,53338cyclictest0-21swapper19:51:560
238889910670953454,53164cyclictest9-21ksoftirqd/000:37:380
238889910658153391,53125cyclictest0-21swapper21:53:110
238889910651253390,53057cyclictest0-21swapper00:16:520
238889910650853435,53073cyclictest0-21swapper20:00:080
238889910650053472,53028cyclictest0-21swapper21:09:480
238889910649653472,53024cyclictest0-21swapper20:52:430
238889910649353465,53028cyclictest0-21swapper21:39:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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