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2026-02-24 - 22:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Feb 24, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
216759910678453405,53290cyclictest134850irq/9-eth010:22:380
216759910674053392,53260cyclictest134850irq/9-eth010:55:580
216759910663353456,53177cyclictest0-21swapper12:21:430
216759910661853472,53146cyclictest0-21swapper10:19:070
216759910658753399,53098cyclictest9-21ksoftirqd/009:49:490
216759910651153476,53035cyclictest0-21swapper07:59:470
216759910650953455,53054cyclictest0-21swapper08:18:330
216759910650453474,53030cyclictest0-21swapper07:34:400
216759910647653456,53020cyclictest0-21swapper12:35:270
216759910646553455,53010cyclictest0-21swapper10:32:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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