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2026-07-03 - 01:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Jul 02, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
241619910766153496,54041cyclictest10410-21ssh11:31:410
241619910718553431,53631cyclictest3954-21ssh09:48:510
241619910697853426,53461cyclictest0-21swapper10:15:090
241619910687253419,53363cyclictest24160-21cyclictest08:33:290
241619910668653448,53238cyclictest0-21swapper08:51:340
241619910664453427,53217cyclictest0-21swapper10:52:390
241619910663453416,53174cyclictest5350irq/9-uhci_hcd:11:21:480
241619910663353462,53107cyclictest9-21ksoftirqd/011:19:370
241619910657753393,53184cyclictest0-21swapper12:08:510
241619910651953401,53118cyclictest0-21swapper08:58:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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