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2026-03-11 - 04:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Mar 11, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
264079910702053415,53538cyclictest0-21swapper19:11:180
264079910696353457,53414cyclictest9-21ksoftirqd/022:00:470
264079910690853478,53308cyclictest112272sleep021:09:420
264079910687653408,53402cyclictest3950irq/9-acpi23:26:520
264079910685653438,53296cyclictest403-21ssh22:29:250
264079910665053393,53164cyclictest0-21swapper00:19:070
264079910663253429,53113cyclictest9-21ksoftirqd/022:47:500
264079910658553422,53099cyclictest0-21swapper00:39:230
264079910652053436,53084cyclictest0-21swapper21:30:080
264079910650453473,53031cyclictest0-21swapper21:35:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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