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2026-04-17 - 16:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Apr 17, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
187399910737053469,53806cyclictest3674-21diskmemload11:19:470
187399910722853456,53675cyclictest1907-21snmpd08:14:240
187399910697453400,53574cyclictest0-21swapper07:28:010
187399910684553399,53382cyclictest90502sleep008:04:510
187399910682953413,53323cyclictest0-21swapper08:48:040
187399910658453471,53113cyclictest0-21swapper09:17:520
187399910655453405,53149cyclictest0-21swapper08:30:390
187399910652553434,53091cyclictest0-21swapper11:06:040
187399910651253474,53038cyclictest0-21swapper08:55:060
187399910650753449,53058cyclictest0-21swapper12:38:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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