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2026-03-20 - 02:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Mar 20, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
226499910736953424,53848cyclictest22995-21ssh00:13:180
226499910685553459,53300cyclictest28178-21diskmemload23:38:580
226499910660653479,53037cyclictest0-21swapper00:08:070
226499910660153475,53126cyclictest0-21swapper20:37:560
226499910659053470,53029cyclictest0-21swapper00:18:500
226499910658653433,53153cyclictest0-21swapper22:11:430
226499910657353403,53103cyclictest0-21swapper00:32:240
226499910654553389,53066cyclictest0-21swapper21:16:070
226499910653753457,53080cyclictest0-21swapper19:41:200
226499910653053437,53093cyclictest0-21swapper21:09:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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