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2026-05-14 - 20:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu May 14, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41329910721453395,53721cyclictest20031-21diskmemload11:29:000
41329910714453471,53551cyclictest32651-21ssh10:12:380
41329910710053479,53497cyclictest10328-21ssh12:01:090
41329910696453420,53453cyclictest0-21swapper07:37:330
41329910669953415,53284cyclictest0-21swapper10:25:020
41329910664353470,53109cyclictest9-21ksoftirqd/010:37:350
41329910650453446,52993cyclictest10-21rcuc/007:43:250
41329910647053409,53061cyclictest0-21swapper08:52:450
41329910646353442,53021cyclictest0-21swapper09:35:570
41329910642353432,52991cyclictest0-21swapper09:26:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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