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2026-07-01 - 23:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Jul 01, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165119910722153471,53659cyclictest9-21ksoftirqd/012:20:400
165119910699653452,53544cyclictest0-21swapper11:49:010
165119910676753399,53272cyclictest1325-21diskmemload11:59:340
165119910676453435,53232cyclictest8437-21ssh10:06:510
165119910676453419,53280cyclictest5350irq/9-uhci_hcd:10:36:300
165119910668453424,53195cyclictest0-21swapper07:44:400
165119910667853475,53138cyclictest140350irq/7-b4308:22:010
165119910658953390,53134cyclictest9-21ksoftirqd/009:50:060
165119910656753386,53088cyclictest0-21swapper08:18:100
165119910655053477,53073cyclictest0-21swapper09:29:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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