You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-24 - 03:06
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Aug 24, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
316219910678253440,53342cyclictest0-21swapper20:23:310
316219910673353473,53260cyclictest0-21swapper23:01:270
316219910670153397,53213cyclictest31610-21cyclictest21:08:140
316219910659853471,53127cyclictest0-21swapper20:37:550
316219910658453477,53107cyclictest0-21swapper00:23:200
316219910656353467,53032cyclictest134850irq/9-eth019:58:040
316219910655153420,53040cyclictest0-21swapper19:47:510
316219910648553464,53021cyclictest0-21swapper20:58:520
316219910642953448,52890cyclictest31610-21cyclictest19:28:350
316219910640253444,52958cyclictest0-21swapper00:28:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional