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2026-04-24 - 15:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Apr 24, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23099910696153423,53445cyclictest0-21swapper09:24:180
23099910687153462,53409cyclictest24023-21ssh10:52:330
23099910674153409,53267cyclictest0-21swapper12:12:060
23099910668353446,53145cyclictest0-21swapper09:03:020
23099910664753419,53138cyclictest9-21ksoftirqd/008:32:330
23099910661153402,53117cyclictest0-21swapper07:57:430
23099910659053469,53121cyclictest0-21swapper12:34:230
23099910656453398,53103cyclictest9-21ksoftirqd/011:24:020
23099910655853394,53073cyclictest0-21swapper10:48:220
23099910654153381,53095cyclictest0-21swapper12:29:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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