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2025-11-29 - 01:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Nov 28, 2025 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
273299910672953465,53173cyclictest27324-21cyclictest10:37:190
273299910658753453,53042cyclictest0-21swapper07:58:530
273299910657353478,53095cyclictest0-21swapper08:58:410
273299910655253413,53048cyclictest0-21swapper07:36:170
273299910651753387,53130cyclictest0-21swapper08:32:030
273299910649353469,53024cyclictest0-21swapper07:13:500
273299910647753402,53075cyclictest0-21swapper07:28:450
273299910646053395,53065cyclictest0-21swapper12:20:590
273299910645753447,53010cyclictest0-21swapper07:15:110
273299910644453461,52983cyclictest0-21swapper08:13:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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