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2026-05-07 - 11:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu May 07, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
93659910739053404,53890cyclictest19944-21ssh22:45:160
93659910722353412,53811cyclictest0-21swapper21:45:390
93659910672553458,53267cyclictest0-21swapper20:06:510
93659910650553475,53030cyclictest0-21swapper00:08:000
93659910647553454,53021cyclictest0-21swapper22:25:110
93659910645753466,52991cyclictest0-21swapper22:31:120
93659910645153475,52976cyclictest0-21swapper20:42:310
93659910645053399,53051cyclictest0-21swapper22:38:240
93659910644753449,52998cyclictest0-21swapper23:24:180
93659910643453470,52964cyclictest0-21swapper20:16:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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