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2026-07-27 - 19:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Jul 27, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117389910759353452,54016cyclictest8942-21ssh11:46:490
117389910704553467,53514cyclictest5350irq/9-uhci_hcd:10:12:420
117389910669353451,53153cyclictest11737-21cyclictest11:56:210
117389910668453461,53131cyclictest0-21swapper08:08:360
117389910662353429,53104cyclictest9-21ksoftirqd/010:39:090
117389910655353389,53099cyclictest0-21swapper11:31:040
117389910654853388,53094cyclictest0-21swapper09:05:220
117389910654853386,53096cyclictest0-21swapper08:28:520
117389910654453419,53032cyclictest0-21swapper07:38:370
117389910653753465,53072cyclictest0-21swapper09:12:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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