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2026-03-26 - 10:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Mar 26, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
270889910673053470,53260cyclictest0-21swapper00:07:050
270889910667153403,53146cyclictest21835-21ssh21:54:370
270889910663953467,53172cyclictest0-21swapper22:56:250
270889910663953467,53172cyclictest0-21swapper22:20:040
270889910662653461,53165cyclictest0-21swapper19:26:240
270889910654653389,53092cyclictest0-21swapper22:19:040
270889910652253471,53051cyclictest0-21swapper21:21:380
270889910650853471,53037cyclictest0-21swapper00:31:320
270889910650453468,53036cyclictest0-21swapper21:33:210
270889910650253464,53038cyclictest0-21swapper22:37:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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