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2026-06-15 - 09:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Jun 14, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
37969910668353435,53181cyclictest11931-21kworker/0:307:33:230
37969910657053461,53109cyclictest0-21swapper08:03:110
37969910655653416,53049cyclictest0-21swapper10:03:060
37969910651953476,53043cyclictest0-21swapper08:05:520
37969910651153472,53039cyclictest0-21swapper11:22:190
37969910649253467,53025cyclictest0-21swapper12:29:380
37969910647953423,52968cyclictest3795-21cyclictest08:41:530
37969910647653415,53061cyclictest0-21swapper07:16:080
37969910646353468,52995cyclictest0-21swapper11:56:490
37969910645753395,53062cyclictest0-21swapper10:42:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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