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2025-12-12 - 04:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Dec 12, 2025 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
321019910671753460,53193cyclictest133750irq/9-eth022:40:300
321019910666953463,53142cyclictest9-21ksoftirqd/022:46:020
321019910661853395,53156cyclictest0-21swapper19:59:340
321019910661153470,53141cyclictest0-21swapper20:09:570
321019910660053379,53156cyclictest0-21swapper19:35:570
321019910656153472,52996cyclictest9-21ksoftirqd/021:26:590
321019910649753473,52933cyclictest0-21swapper20:39:250
321019910649253484,53008cyclictest0-21swapper00:27:310
321019910646953412,53057cyclictest0-21swapper21:21:380
321019910645453404,53050cyclictest0-21swapper20:23:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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