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2026-08-13 - 20:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Aug 13, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7779910703553411,53532cyclictest0-21swapper12:22:330
7779910699553457,53446cyclictest0-21swapper09:09:380
7779910696553449,53451cyclictest134850irq/9-eth011:17:140
7779910673953459,53280cyclictest0-21swapper08:41:100
7779910673053476,53254cyclictest0-21swapper07:35:410
7779910665753423,53234cyclictest0-21swapper12:13:110
7779910663153393,53173cyclictest3950irq/9-acpi11:31:190
7779910652053478,53042cyclictest0-21swapper09:35:350
7779910650953474,53035cyclictest0-21swapper08:11:510
7779910650853431,53077cyclictest0-21swapper09:25:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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