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2026-07-04 - 03:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Jul 04, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
130839910696953388,53518cyclictest134850irq/9-eth022:20:530
130839910674553417,53238cyclictest5350irq/9-uhci_hcd:23:52:090
130839910671153552,53157cyclictest1741-21hald00:18:370
130839910667453474,53102cyclictest2099-21runrttasks19:28:330
130839910661953406,53150cyclictest13072-21cyclictest22:11:100
130839910659653474,53122cyclictest0-21swapper00:25:590
130839910658753421,53100cyclictest0-21swapper20:23:090
130839910654753463,53084cyclictest0-21swapper19:50:090
130839910654653387,53092cyclictest0-21swapper22:08:190
130839910651653479,53037cyclictest0-21swapper19:45:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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