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2026-02-13 - 18:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Feb 13, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122759910723553333,53837cyclictest26875-21kworker/0:010:42:120
122759910721053463,53682cyclictest5350irq/9-uhci_hcd:11:04:580
122759910683053479,53351cyclictest0-21swapper10:08:020
122759910668953455,53234cyclictest0-21swapper08:20:310
122759910667953466,53122cyclictest0-21swapper09:22:590
122759910666453438,53226cyclictest0-21swapper11:10:100
122759910662053422,53107cyclictest9-21ksoftirqd/012:35:450
122759910658653418,53104cyclictest9-21ksoftirqd/007:40:190
122759910658553452,53041cyclictest0-21swapper09:12:560
122759910658253420,53097cyclictest0-21swapper12:30:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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