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2026-06-05 - 02:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Jun 05, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
157589910719853466,53633cyclictest16782-21ssh23:09:240
157589910714253410,53635cyclictest597-21diskmemload00:35:290
157589910685353398,53359cyclictest597-21diskmemload22:09:370
157589910684453464,53290cyclictest12991-21kworker/0:000:10:520
157589910671253444,53205cyclictest134850irq/9-eth000:22:550
157589910657453475,53099cyclictest0-21swapper19:40:340
157589910655153449,53102cyclictest0-21swapper20:52:350
157589910652853483,53045cyclictest0-21swapper00:00:290
157589910652653480,53046cyclictest0-21swapper23:37:220
157589910650553470,53035cyclictest0-21swapper21:21:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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