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2026-01-31 - 03:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Jan 31, 2026 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
276949910719653460,53640cyclictest8476-21ssh23:32:160
276949910698753470,53420cyclictest395-21ssh00:08:570
276949910691653474,53318cyclictest28079-21ssh23:14:110
276949910689253403,53489cyclictest0-21swapper19:59:350
276949910678353392,53301cyclictest0-21swapper20:20:010
276949910671453391,53233cyclictest0-21swapper22:22:060
276949910668653484,53202cyclictest0-21swapper00:25:020
276949910666853475,53193cyclictest0-21swapper00:22:110
276949910663353463,53079cyclictest9-21ksoftirqd/022:18:550
276949910662653390,53172cyclictest23340-21kworker/0:200:00:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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