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2026-08-07 - 07:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Aug 07, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
43889910754753459,54088cyclictest0-21swapper19:31:320
43889910731753412,53809cyclictest2118-21ssh23:51:070
43889910695453419,53443cyclictest0-21swapper21:57:140
43889910667953422,53166cyclictest0-21swapper19:24:400
43889910659953412,53122cyclictest9-21ksoftirqd/023:18:080
43889910656953398,53105cyclictest0-21swapper00:15:440
43889910656553442,53123cyclictest0-21swapper23:21:290
43889910655153452,53099cyclictest0-21swapper22:41:170
43889910654953403,53146cyclictest0-21swapper21:25:050
43889910652853396,53132cyclictest0-21swapper22:59:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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