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2025-12-08 - 00:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Dec 07, 2025 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
314339910705253417,53569cyclictest0-21swapper12:25:440
314339910668353446,53237cyclictest0-21swapper09:42:070
314339910667953439,53240cyclictest0-21swapper10:11:250
314339910667553477,53132cyclictest0-21swapper12:36:070
314339910664853465,53120cyclictest9-21ksoftirqd/007:43:430
314339910652653477,53049cyclictest0-21swapper07:35:300
314339910652553478,53047cyclictest0-21swapper09:28:130
314339910651153473,53038cyclictest0-21swapper10:23:590
314339910650253404,53001cyclictest1911-21snmpd07:16:450
314339910650153469,53032cyclictest0-21swapper10:39:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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