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2025-12-07 - 10:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Dec 07, 2025 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
237329910761253463,54050cyclictest3728-21ssh23:56:280
237329910697253434,53446cyclictest0-21swapper21:40:090
237329910680353379,53335cyclictest5350irq/9-uhci_hcd:00:13:030
237329910675153413,53247cyclictest0-21swapper19:27:510
237329910673153465,53177cyclictest9-21ksoftirqd/019:54:580
237329910668253471,53122cyclictest9-21ksoftirqd/021:18:120
237329910663353423,53210cyclictest0-21swapper22:46:380
237329910658453389,53104cyclictest0-21swapper23:01:520
237329910655453425,53129cyclictest0-21swapper23:24:490
237329910649853474,53024cyclictest0-21swapper22:08:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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