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2026-09-10 - 18:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Sep 10, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
289629910684753397,53386cyclictest134850irq/9-eth011:51:320
289629910669153427,53172cyclictest0-21swapper07:33:480
289629910667753414,53174cyclictest3950irq/9-acpi11:07:000
289629910663353432,53102cyclictest1907-21snmpd08:47:400
289629910661553468,53081cyclictest134850irq/9-eth012:30:340
289629910658253420,53069cyclictest0-21swapper08:44:190
289629910655753394,53098cyclictest0-21swapper07:11:520
289629910655153407,53144cyclictest0-21swapper07:44:310
289629910654353445,53098cyclictest0-21swapper09:17:080
289629910651453476,53038cyclictest0-21swapper09:31:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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