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2026-06-12 - 08:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Jun 12, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27189910706953476,53593cyclictest0-21swapper20:50:380
27189910683453364,53457cyclictest0-21swapper22:56:240
27189910678353446,53337cyclictest0-21swapper23:52:200
27189910675353465,53224cyclictest9-21ksoftirqd/022:35:280
27189910674853412,53244cyclictest0-21swapper20:29:320
27189910669453430,53200cyclictest2519-21cyclictest22:27:360
27189910659253394,53198cyclictest0-21swapper00:15:570
27189910658853411,53177cyclictest0-21swapper20:38:040
27189910649153413,53078cyclictest0-21swapper22:09:110
27189910648253404,53078cyclictest0-21swapper21:37:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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