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2025-11-17 - 20:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Nov 17, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30239910686653388,53385cyclictest0-21swapper08:59:370
30239910671153474,53140cyclictest20133-21diskmemload11:07:540
30239910661353476,53137cyclictest0-21swapper08:21:260
30239910655453466,53088cyclictest0-21swapper10:16:500
30239910655053389,53069cyclictest0-21swapper11:35:320
30239910652053476,53044cyclictest0-21swapper08:48:440
30239910650453470,53034cyclictest0-21swapper07:23:300
30239910650053413,53022cyclictest128932sleep007:33:130
30239910649453470,53024cyclictest0-21swapper09:04:290
30239910648653430,53056cyclictest0-21swapper07:13:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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