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2026-05-16 - 11:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat May 16, 2026 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
193969910665253443,53144cyclictest0-21swapper21:41:410
193969910665253431,53156cyclictest9-21ksoftirqd/019:26:420
193969910663153460,53171cyclictest0-21swapper00:37:220
193969910660853466,53142cyclictest0-21swapper20:29:200
193969910651653470,53046cyclictest0-21swapper19:43:570
193969910649753472,53025cyclictest0-21swapper23:41:360
193969910649153457,53034cyclictest0-21swapper20:02:330
193969910646853412,53056cyclictest0-21swapper22:36:370
193969910645653446,53010cyclictest0-21swapper00:25:080
193969910642653442,52984cyclictest0-21swapper20:19:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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