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2026-08-05 - 04:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Aug 04, 2026 12:43:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
148249910695453423,53531cyclictest0-21swapper11:41:070
148249910677753386,53327cyclictest134850irq/9-eth011:56:310
148249910665453476,53178cyclictest0-21swapper12:05:040
148249910664953470,53179cyclictest0-21swapper12:37:330
148249910664753425,53222cyclictest0-21swapper12:11:460
148249910660553474,53009cyclictest32164-21diskmemload12:23:090
148249910659453483,53048cyclictest9-21ksoftirqd/007:16:510
148249910658553475,53048cyclictest9-21ksoftirqd/009:44:530
148249910658053436,53144cyclictest0-21swapper11:34:150
148249910652253479,53043cyclictest0-21swapper08:43:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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