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2026-03-19 - 17:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Mar 19, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2442099210870105407,105461cyclictest0-21swapper11:21:160
244209910703653411,53531cyclictest0-21swapper09:19:110
244209910695453416,53447cyclictest0-21swapper09:44:580
244209910681753470,53347cyclictest0-21swapper07:56:570
244209910675153476,53275cyclictest0-21swapper12:31:560
244209910652053481,53039cyclictest0-21swapper11:25:470
244209910649653439,53057cyclictest0-21swapper07:54:360
244209910647953478,53001cyclictest0-21swapper11:42:120
244209910647853466,53012cyclictest0-21swapper10:10:050
244209910646653411,53055cyclictest0-21swapper09:05:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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