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2026-08-30 - 06:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Aug 30, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180279910681253468,53281cyclictest3950irq/9-acpi22:05:500
180279910669553433,53199cyclictest9-21ksoftirqd/022:19:440
180279910655353386,53167cyclictest0-21swapper00:39:250
180279910654253386,53092cyclictest0-21swapper22:43:310
180279910653753413,53030cyclictest0-21swapper22:54:550
180279910653453456,53078cyclictest0-21swapper19:45:000
180279910650753471,53036cyclictest0-21swapper20:36:550
180279910649153407,53020cyclictest134850irq/9-eth022:48:030
180279910649053428,53062cyclictest0-21swapper20:33:340
180279910648753467,53020cyclictest0-21swapper20:59:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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