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2026-04-11 - 17:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Apr 11, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
294499910711553476,53574cyclictest20329-21rm09:17:530
294499910683653329,53487cyclictest0-21swapper09:21:450
294499910660953463,53083cyclictest3950irq/9-acpi11:09:060
294499910657053471,53099cyclictest0-21swapper07:42:360
294499910652553481,53044cyclictest0-21swapper07:28:020
294499910651353475,53038cyclictest0-21swapper10:31:350
294499910650253469,53033cyclictest0-21swapper10:25:130
294499910650153474,53027cyclictest0-21swapper11:34:030
294499910650153448,53053cyclictest0-21swapper09:53:240
294499910647753461,53016cyclictest0-21swapper08:54:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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