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2026-05-13 - 01:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue May 12, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
143599910702653463,53474cyclictest9-21ksoftirqd/012:28:180
143599910698353415,53476cyclictest0-21swapper07:53:280
143599910683753360,53464cyclictest0-21swapper07:56:590
143599910670653451,53163cyclictest9-21ksoftirqd/010:36:350
143599910668653464,53132cyclictest9-21ksoftirqd/010:08:170
143599910667253456,53126cyclictest9-21ksoftirqd/010:45:480
143599910659953255,53321cyclictest12827-21ssh11:01:020
143599910648853483,53005cyclictest0-21swapper10:02:250
143599910645953449,53010cyclictest0-21swapper12:33:590
143599910645953408,53051cyclictest0-21swapper11:59:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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