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2026-08-18 - 20:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Aug 18, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15559910676153452,53211cyclictest2099-21runrttasks09:35:500
15559910672453399,53325cyclictest0-21swapper11:37:450
15559910670253464,53140cyclictest13040-21ssh09:48:340
15559910660553464,53141cyclictest0-21swapper12:17:370
15559910658353460,53123cyclictest0-21swapper08:47:060
15559910658153424,53157cyclictest0-21swapper11:08:170
15559910653553447,53088cyclictest0-21swapper08:00:120
15559910653253465,52946cyclictest18970-21diskmemload10:49:510
15559910652853393,53135cyclictest0-21swapper12:09:140
15559910651353475,53038cyclictest0-21swapper11:13:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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