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2026-06-23 - 12:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Jun 23, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
59209910716953428,53643cyclictest14144-21ssh23:22:160
59209910705353414,53548cyclictest0-21swapper20:05:490
59209910702653414,53521cyclictest9-21ksoftirqd/022:00:120
59209910672053490,53140cyclictest0-21swapper22:42:340
59209910671553424,53199cyclictest0-21swapper21:11:280
59209910670053429,53205cyclictest0-21swapper21:40:360
59209910658853436,53152cyclictest0-21swapper00:21:230
59209910657253448,53033cyclictest0-21swapper21:56:310
59209910655153384,53076cyclictest0-21swapper22:14:160
59209910654953417,53132cyclictest0-21swapper23:43:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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