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2026-04-22 - 02:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Apr 22, 2026 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
324999910674053429,53311cyclictest0-21swapper21:13:080
324999910671353417,53173cyclictest13898-21diskmemload23:28:570
324999910668653465,53098cyclictest12720-21ssh22:43:040
324999910668353433,53250cyclictest0-21swapper23:33:280
324999910666853477,53191cyclictest0-21swapper00:37:270
324999910664453389,53255cyclictest0-21swapper19:34:490
324999910661453384,53165cyclictest0-21swapper19:24:560
324999910660253478,53058cyclictest0-21swapper23:53:240
324999910658253388,53102cyclictest0-21swapper21:59:210
324999910656453421,53143cyclictest0-21swapper21:43:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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