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2026-08-10 - 15:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Aug 10, 2026 12:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20699910622353474,52749cyclictest0-21swapper07:47:490
20699910614053062,53076cyclictest0-21swapper07:19:310
20699910604552977,53066cyclictest0-21swapper08:22:390
20699910603652950,53084cyclictest0-21swapper12:10:550
20699910601652972,53042cyclictest0-21swapper08:05:140
20699910595852913,53043cyclictest0-21swapper10:58:540
20699910587053045,52822cyclictest15139-21ssh11:12:580
20699910562453016,52606cyclictest29029-21diskmemload12:15:470
20699910516953065,52102cyclictest0-21swapper09:30:290
20699910516353059,52102cyclictest0-21swapper11:28:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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