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2026-03-16 - 20:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Mar 16, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
305949910739753436,53839cyclictest15423-21diskmemload10:53:440
305949910710753483,53534cyclictest9-21ksoftirqd/009:56:270
305949910670753428,53279cyclictest0-21swapper07:41:480
305949910667253418,53161cyclictest0-21swapper07:27:140
305949910656553453,53112cyclictest0-21swapper08:46:170
305949910656053416,53144cyclictest0-21swapper07:20:520
305949910655453476,52981cyclictest2099-21runrttasks08:26:010
305949910654953473,53076cyclictest0-21swapper07:18:220
305949910654753443,53104cyclictest0-21swapper10:35:180
305949910654253375,53104cyclictest9-21ksoftirqd/011:28:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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