You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-23 - 14:40
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Apr 23, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1765699209878105395,104481cyclictest0-21swapper07:49:160
1765699209787105310,104475cyclictest0-21swapper12:07:100
176569910613253059,53071cyclictest0-21swapper07:24:290
176569910611653024,53090cyclictest0-21swapper10:34:230
176569910610853025,53081cyclictest0-21swapper11:27:090
176569910609253011,53079cyclictest0-21swapper08:35:390
176569910607753004,53071cyclictest0-21swapper11:10:040
176569910607152963,53106cyclictest0-21swapper08:13:230
176569910606852971,53095cyclictest0-21swapper10:49:280
176569910606352973,53088cyclictest0-21swapper11:41:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional