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2026-05-11 - 23:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon May 11, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
101319910754653465,53958cyclictest9646-21ssh11:52:020
101319910751153480,53910cyclictest15546-21ssh11:14:010
101319910725153446,53709cyclictest30376-21ssh11:35:170
101319910715653474,53616cyclictest134850irq/9-eth009:55:090
101319910700853468,53443cyclictest1120-21ssh12:27:220
101319910680753440,53275cyclictest9-21ksoftirqd/009:16:370
101319910675253407,53278cyclictest11-21rcu_preempt11:08:100
101319910674453470,53185cyclictest10127-21cyclictest07:20:340
101319910670153391,53247cyclictest9-21ksoftirqd/010:06:320
101319910669153463,53164cyclictest9-21ksoftirqd/008:13:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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