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2026-05-20 - 16:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed May 20, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
53449910741253409,53906cyclictest31047-21ssh10:54:490
53449910717953397,53718cyclictest20093-21kworker/0:109:17:210
53449910712953453,53580cyclictest13279-21ssh11:15:150
53449910712953448,53616cyclictest134850irq/9-eth011:11:340
53449910704053452,53491cyclictest54042sleep010:16:280
53449910694253476,53376cyclictest12493-21kworker/u2:010:37:440
53449910680853432,53278cyclictest13323-21ssh12:01:580
53449910676253463,53299cyclictest0-21swapper07:29:400
53449910666753402,53175cyclictest0-21swapper11:09:330
53449910654653435,53111cyclictest0-21swapper08:36:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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