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2026-04-10 - 04:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Apr 10, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24739910695453412,53450cyclictest0-21swapper23:06:330
24739910672553458,53169cyclictest24608-21ssh00:28:060
24739910667053387,53192cyclictest0-21swapper21:13:500
24739910666453477,53187cyclictest0-21swapper23:30:090
24739910665053468,53182cyclictest0-21swapper23:13:450
24739910654753454,53093cyclictest0-21swapper22:42:160
24739910653553382,53088cyclictest0-21swapper21:55:320
24739910650053474,53026cyclictest0-21swapper23:54:570
24739910648953406,53083cyclictest0-21swapper21:50:010
24739910648453475,53009cyclictest0-21swapper00:06:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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