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2026-05-23 - 18:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat May 23, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
317809910699053440,53459cyclictest0-21swapper10:11:210
317809910679453399,53274cyclictest13191-21ssh11:28:030
317809910672153475,53150cyclictest16869-21ssh11:33:450
317809910662753429,53133cyclictest9-21ksoftirqd/008:17:480
317809910660553426,53116cyclictest10-21rcuc/008:29:520
317809910658853415,53108cyclictest0-21swapper08:10:360
317809910656153453,53108cyclictest0-21swapper09:27:380
317809910655953394,53100cyclictest0-21swapper12:29:210
317809910653653429,53043cyclictest134850irq/9-eth008:40:250
317809910653453458,53076cyclictest0-21swapper09:16:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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