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2026-03-15 - 20:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Mar 15, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
33619910736853465,53806cyclictest11683-21ssh11:18:360
33619910665753467,53190cyclictest0-21swapper11:20:470
33619910661253394,53126cyclictest0-21swapper11:46:140
33619910654653390,53091cyclictest0-21swapper10:34:230
33619910650653476,53030cyclictest0-21swapper11:03:020
33619910649853466,53032cyclictest0-21swapper11:54:160
33619910647653475,53001cyclictest0-21swapper10:58:500
33619910645653405,53051cyclictest0-21swapper12:17:430
33619910645053404,53046cyclictest0-21swapper12:24:150
33619910644753442,53005cyclictest0-21swapper11:06:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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