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2026-09-23 - 20:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Sep 23, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2846099210384105357,105025cyclictest25848-21sh11:40:530
284609910728953400,53790cyclictest29518-21diskmemload11:01:020
284609910708553420,53573cyclictest0-21swapper08:13:540
284609910700153438,53463cyclictest9425-21ssh09:49:010
284609910682753380,53385cyclictest3950irq/9-acpi12:19:140
284609910677053458,53312cyclictest0-21swapper11:21:180
284609910668053399,53281cyclictest0-21swapper08:09:120
284609910664753391,53165cyclictest0-21swapper08:58:060
284609910661253424,53092cyclictest7992-21ssh10:31:030
284609910656253380,53090cyclictest0-21swapper10:23:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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