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2026-08-02 - 00:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Aug 01, 2026 12:43:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
126469910715853451,53641cyclictest161542sleep007:16:560
126469910698653393,53528cyclictest9-21ksoftirqd/012:25:550
126469910686353401,53365cyclictest21110-21ssh12:06:090
126469910678853353,53420cyclictest24667-21sh12:11:310
126469910671753432,53285cyclictest0-21swapper09:07:280
126469910668353445,53238cyclictest0-21swapper10:38:340
126469910661653456,53160cyclictest0-21swapper10:21:490
126469910657453437,53137cyclictest0-21swapper11:55:460
126469910652153431,53090cyclictest0-21swapper07:10:540
126469910651153473,53038cyclictest0-21swapper07:35:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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