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2026-02-10 - 17:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Feb 10, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
288909910716353446,53621cyclictest13903-21diskmemload10:04:470
288909910712153427,53598cyclictest2099-21runrttasks12:02:310
288909910706453434,53507cyclictest25393-21ssh12:35:300
288909910671653431,53189cyclictest2099-21runrttasks07:53:390
288909910669953470,53163cyclictest0-21swapper08:26:080
288909910667253453,53219cyclictest0-21swapper11:55:590
288909910650053450,53050cyclictest0-21swapper07:27:410
288909910649353473,53020cyclictest0-21swapper09:45:410
288909910647653459,53017cyclictest0-21swapper09:25:050
288909910646153450,53011cyclictest0-21swapper07:20:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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