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2026-01-27 - 02:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Jan 27, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
51849910697053420,53459cyclictest0-21swapper21:59:100
51849910687453470,53337cyclictest3950irq/9-acpi21:44:160
51849910680353475,53328cyclictest0-21swapper00:34:550
51849910675253379,53307cyclictest0-21swapper21:37:540
51849910664153387,53186cyclictest0-21swapper21:19:090
51849910651653428,53088cyclictest0-21swapper20:09:190
51849910651553478,53037cyclictest0-21swapper19:57:150
51849910651553476,53039cyclictest0-21swapper00:01:260
51849910651153473,53038cyclictest0-21swapper20:38:570
51849910650553475,53030cyclictest0-21swapper20:30:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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