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2026-05-21 - 16:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu May 21, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
190949910730853430,53789cyclictest19090-21cyclictest10:09:410
190949910723653485,53654cyclictest21530-21ssh11:54:110
190949910693453484,53387cyclictest134850irq/9-eth009:23:580
190949910667253447,53225cyclictest0-21swapper07:36:570
190949910661953403,53216cyclictest0-21swapper12:24:400
190949910658753474,53113cyclictest0-21swapper08:55:290
190949910658153400,53181cyclictest0-21swapper08:49:280
190949910654753388,53094cyclictest0-21swapper07:11:090
190949910653153434,53097cyclictest0-21swapper07:24:030
190949910651253474,53038cyclictest0-21swapper12:35:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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