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2026-07-22 - 16:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Jul 22, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11219910696453421,53451cyclictest0-21swapper11:06:320
11219910668753463,53224cyclictest0-21swapper08:43:010
11219910666653479,53187cyclictest0-21swapper07:24:490
11219910657553391,53092cyclictest0-21swapper08:49:130
11219910656453467,53097cyclictest0-21swapper07:44:140
11219910655053451,53099cyclictest0-21swapper08:25:360
11219910655053390,53095cyclictest0-21swapper09:24:230
11219910652953482,53047cyclictest0-21swapper09:45:590
11219910650753472,53035cyclictest0-21swapper08:51:240
11219910645653451,53005cyclictest0-21swapper12:10:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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