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2026-05-31 - 22:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun May 31, 2026 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
265199910671253460,53161cyclictest0-21swapper08:41:440
265199910660753470,53137cyclictest0-21swapper09:38:410
265199910653253381,53086cyclictest0-21swapper08:38:540
265199910651153472,53039cyclictest0-21swapper09:49:040
265199910650953476,53033cyclictest0-21swapper07:26:330
265199910649853466,53032cyclictest0-21swapper11:33:140
265199910647353401,53072cyclictest0-21swapper07:35:350
265199910644553472,52973cyclictest0-21swapper07:17:100
265199910642753478,52949cyclictest0-21swapper09:02:000
265199910640253452,52886cyclictest26518-21cyclictest08:33:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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