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2026-07-19 - 12:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Jul 19, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1899299210776105323,105451cyclictest0-21swapper23:36:190
189929910692153393,53463cyclictest21925-1kworker/u3:100:17:210
189929910676353383,53316cyclictest9-21ksoftirqd/021:04:550
189929910665853466,53127cyclictest0-21swapper22:50:560
189929910662253412,53210cyclictest0-21swapper21:42:560
189929910654053385,53090cyclictest0-21swapper22:32:300
189929910649953414,53085cyclictest0-21swapper20:22:530
189929910647253414,53058cyclictest0-21swapper23:17:540
189929910645053447,53003cyclictest0-21swapper22:15:260
189929910642853432,52996cyclictest0-21swapper19:52:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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