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2026-08-08 - 11:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Aug 08, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
47389910671853463,53255cyclictest0-21swapper21:13:470
47389910663653459,53114cyclictest9-21ksoftirqd/021:00:430
47389910661953397,53202cyclictest2277-21Xorg20:39:070
47389910655453448,53106cyclictest0-21swapper20:10:590
47389910654953392,53157cyclictest0-21swapper21:38:040
47389910650353471,53032cyclictest0-21swapper21:07:350
47389910649953471,53028cyclictest0-21swapper19:55:540
47389910649953417,53018cyclictest9-21ksoftirqd/023:07:300
47389910648553464,53021cyclictest0-21swapper00:21:010
47389910647453458,53016cyclictest0-21swapper22:43:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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