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2026-04-03 - 18:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Apr 03, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
88159910722453389,53770cyclictest18545-21kworker/0:207:49:500
88159910699353449,53452cyclictest134850irq/9-eth012:34:020
88159910674853447,53301cyclictest0-21swapper07:55:010
88159910673653453,53220cyclictest9-21ksoftirqd/008:37:130
88159910665353461,53128cyclictest9-21ksoftirqd/012:22:380
88159910654553416,53038cyclictest0-21swapper11:04:260
88159910654253442,53100cyclictest0-21swapper08:46:460
88159910650153473,53028cyclictest0-21swapper09:18:050
88159910649553467,53028cyclictest0-21swapper08:24:100
88159910649353389,53042cyclictest8813-21cyclictest08:00:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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