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2026-07-13 - 08:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Jul 13, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243499910714553419,53605cyclictest11936-21ssh23:36:390
243499910674853411,53270cyclictest0-21swapper19:55:050
243499910664853455,53104cyclictest9-21ksoftirqd/021:36:240
243499910663853411,53164cyclictest3950irq/9-acpi00:17:510
243499910662953383,53224cyclictest0-21swapper21:58:010
243499910661553467,53057cyclictest0-21swapper23:53:440
243499910656153392,53078cyclictest0-21swapper22:52:060
243499910654653403,53143cyclictest0-21swapper20:36:170
243499910653953384,53065cyclictest0-21swapper21:14:380
243499910650853476,53032cyclictest0-21swapper22:37:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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