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2026-04-29 - 09:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Apr 29, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
173339910697553410,53468cyclictest1907-21snmpd20:04:420
173339910675253416,53245cyclictest0-21swapper20:20:360
173339910649953467,53032cyclictest0-21swapper20:48:140
173339910649753471,53026cyclictest0-21swapper19:37:140
173339910643653396,53040cyclictest0-21swapper20:36:210
173339910642853392,53036cyclictest0-21swapper20:53:560
173339910641253429,52983cyclictest0-21swapper20:55:060
173339910622453475,52749cyclictest0-21swapper20:33:100
173339910621653472,52744cyclictest0-21swapper21:02:380
173339910620253436,52766cyclictest0-21swapper19:33:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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