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2025-08-27 - 02:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Aug 26, 2025 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
143319910714453477,53575cyclictest9-21ksoftirqd/009:41:480
143319910709853474,53536cyclictest3950irq/9-acpi09:59:030
143319910694253424,53426cyclictest0-21swapper08:17:230
143319910677053459,53311cyclictest0-21swapper11:35:000
143319910663353458,53175cyclictest0-21swapper12:25:050
143319910659653470,53126cyclictest0-21swapper09:16:300
143319910657153405,53102cyclictest9-21ksoftirqd/012:32:570
143319910650453470,53034cyclictest0-21swapper10:41:150
143319910650153443,53058cyclictest0-21swapper11:16:050
143319910649053465,53025cyclictest0-21swapper11:56:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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