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2026-05-07 - 18:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu May 07, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
100449910720753453,53656cyclictest1993-21lldpd07:44:420
100449910712553472,53555cyclictest7335-21ssh11:47:320
100449910693453481,53356cyclictest27343-21diskmemload10:10:540
100449910677753412,53365cyclictest0-21swapper11:28:060
100449910677653386,53377cyclictest134850irq/9-eth010:52:360
100449910671253448,53264cyclictest0-21swapper08:14:400
100449910669053448,53242cyclictest0-21swapper10:03:420
100449910659053449,53044cyclictest29369-21ssh09:11:570
100449910655253442,53110cyclictest0-21swapper11:58:250
100449910652253480,53042cyclictest0-21swapper07:20:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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