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2026-04-20 - 01:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Apr 19, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
320179910665153396,53190cyclictest0-21swapper11:30:500
320179910655453475,53079cyclictest0-21swapper12:23:350
320179910650853473,53035cyclictest0-21swapper09:05:590
320179910650853432,53076cyclictest0-21swapper09:46:400
320179910650553418,53087cyclictest0-21swapper10:02:350
320179910649753464,53033cyclictest0-21swapper07:34:420
320179910647353419,52990cyclictest3950irq/9-acpi11:46:150
320179910645953407,53052cyclictest0-21swapper07:45:050
320179910645453464,52990cyclictest0-21swapper12:13:430
320179910644353399,53044cyclictest0-21swapper12:26:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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