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2026-01-12 - 18:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Jan 12, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
135929910729253471,53724cyclictest9729-21ssh11:00:440
135929910705053458,53526cyclictest134850irq/9-eth010:28:550
135929910698753418,53569cyclictest0-21swapper10:48:400
135929910684853430,53418cyclictest2099-21runrttasks07:17:300
135929910667553420,53161cyclictest0-21swapper09:01:190
135929910664553468,53113cyclictest30898-21kworker/0:209:17:540
135929910661253399,53125cyclictest3950irq/9-acpi11:16:080
135929910660853476,53132cyclictest0-21swapper11:10:370
135929910659753457,53077cyclictest9-21ksoftirqd/010:39:480
135929910659153429,53105cyclictest0-21swapper08:15:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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