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2026-02-20 - 19:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Feb 20, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
286479910711453461,53531cyclictest8639-21ssh10:38:240
286479910704953418,53539cyclictest0-21swapper09:20:010
286479910684453389,53391cyclictest134850irq/9-eth009:47:190
286479910680553415,53390cyclictest0-21swapper08:51:230
286479910672453426,53209cyclictest9-21ksoftirqd/009:06:170
286479910670753456,53251cyclictest0-21swapper07:48:150
286479910660453460,53052cyclictest0-21swapper08:08:300
286479910656553381,53091cyclictest0-21swapper12:29:260
286479910655453464,53090cyclictest0-21swapper11:55:460
286479910654953389,53070cyclictest0-21swapper09:15:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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