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2026-06-16 - 09:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Jun 16, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
441799210908105438,105465cyclictest0-21swapper00:20:280
44179910757853456,54024cyclictest2099-21runrttasks20:37:140
44179910728553411,53781cyclictest0-21swapper23:43:070
44179910726853479,53692cyclictest2099-21runrttasks20:09:360
44179910703753415,53530cyclictest0-21swapper23:14:290
44179910703353380,53565cyclictest134850irq/9-eth000:14:560
44179910687553428,53383cyclictest9-21ksoftirqd/022:47:110
44179910681153343,53455cyclictest0-21swapper23:52:200
44179910671653443,53273cyclictest0-21swapper19:54:510
44179910666853436,53143cyclictest9-21ksoftirqd/022:03:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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