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2026-07-06 - 04:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Jul 06, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
188519910702553475,53550cyclictest0-21swapper20:55:080
188519910658653421,53100cyclictest0-21swapper22:32:060
188519910649153468,53023cyclictest0-21swapper21:47:430
188519910648553479,53006cyclictest0-21swapper19:16:390
188519910644553401,53044cyclictest0-21swapper19:14:290
188519910643953470,52969cyclictest0-21swapper19:36:150
188519910643253439,52993cyclictest0-21swapper21:09:120
188519910641753432,52985cyclictest0-21swapper20:08:240
188519910628853417,52807cyclictest9-21ksoftirqd/019:57:110
188519910624053471,52769cyclictest0-21swapper20:19:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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