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2026-06-28 - 20:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Jun 28, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
56819910906654734,54329cyclictest1741-21hald08:00:000
56819910733253473,53761cyclictest22919-21diskmemload10:59:110
56819910684053382,53395cyclictest9-21ksoftirqd/009:23:540
56819910683853418,53420cyclictest0-21swapper07:32:520
56819910666853462,53154cyclictest134850irq/9-eth010:34:540
56819910663253395,53173cyclictest9-21ksoftirqd/010:29:030
56819910658653401,53090cyclictest24086-21munin-node11:35:220
56819910657753457,53028cyclictest0-21swapper11:51:060
56819910657053447,53031cyclictest0-21swapper12:35:390
56819910656253400,53099cyclictest9-21ksoftirqd/011:43:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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