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2025-12-04 - 15:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Dec 04, 2025 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
185149910679453445,53258cyclictest18497-21cyclictest08:33:120
185149910667853423,53166cyclictest0-21swapper07:19:310
185149910667053469,53078cyclictest17793-21ssh10:15:120
185149910665653430,53163cyclictest18497-21cyclictest10:22:140
185149910658353463,53120cyclictest0-21swapper07:32:550
185149910657453473,53101cyclictest0-21swapper08:42:450
185149910652453483,53041cyclictest0-21swapper10:57:040
185149910652353480,53043cyclictest0-21swapper10:10:400
185149910651653475,53041cyclictest0-21swapper09:30:590
185149910651553475,53040cyclictest0-21swapper12:12:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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