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2026-03-27 - 20:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Mar 27, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13829910693753427,53419cyclictest0-21swapper07:38:200
13829910663553462,53108cyclictest9-21ksoftirqd/010:44:240
13829910663553417,53196cyclictest9907-21ssh09:43:560
13829910654553429,53116cyclictest0-21swapper07:18:040
13829910653353394,53139cyclictest0-21swapper08:52:010
13829910653153381,53085cyclictest0-21swapper12:00:250
13829910650253419,52986cyclictest26306-21ssh11:41:400
13829910649053422,53068cyclictest0-21swapper11:20:240
13829910646453470,52994cyclictest0-21swapper09:00:540
13829910646153439,53022cyclictest0-21swapper12:39:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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