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2026-01-09 - 04:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Jan 09, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
234899910706153425,53570cyclictest50072sleep022:36:350
234899910666453429,53235cyclictest0-21swapper21:27:350
234899910661853435,53183cyclictest0-21swapper20:25:070
234899910659353429,53164cyclictest0-21swapper21:18:330
234899910649153473,53018cyclictest0-21swapper23:33:010
234899910645453465,52989cyclictest0-21swapper19:41:150
234899910644953440,53009cyclictest0-21swapper21:13:410
234899910643353440,52993cyclictest0-21swapper00:19:550
234899910637753446,52868cyclictest23483-21cyclictest20:02:310
234899910624353465,52778cyclictest0-21swapper19:55:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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