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2026-03-20 - 16:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Mar 20, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
289499910669853429,53269cyclictest0-21swapper08:52:380
289499910667253459,53213cyclictest0-21swapper11:39:560
289499910659653470,53126cyclictest0-21swapper09:59:070
289499910655053390,53095cyclictest0-21swapper10:36:280
289499910654653448,53098cyclictest0-21swapper09:24:270
289499910651153474,53037cyclictest0-21swapper12:35:020
289499910645853445,53013cyclictest0-21swapper11:32:440
289499910644753400,53047cyclictest0-21swapper10:27:350
289499910644253441,53001cyclictest0-21swapper08:42:150
289499910642353430,52993cyclictest0-21swapper12:30:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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