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2026-07-26 - 19:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Jul 26, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
294399910725953460,53704cyclictest14459-21diskmemload10:16:380
294399910708353474,53513cyclictest2099-21runrttasks09:20:420
294399910665353381,53180cyclictest0-21swapper12:31:470
294399910664953419,53138cyclictest0-21swapper11:54:460
294399910655853471,53087cyclictest0-21swapper10:58:300
294399910644753462,52985cyclictest0-21swapper11:48:140
294399910644453465,52979cyclictest0-21swapper10:36:130
294399910643853442,52996cyclictest0-21swapper12:29:260
294399910643753395,53042cyclictest0-21swapper10:40:050
294399910643253394,53038cyclictest0-21swapper10:21:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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