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2025-12-30 - 15:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Dec 30, 2025 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158339910704353416,53536cyclictest0-21swapper08:47:540
158339910696053441,53455cyclictest3950irq/9-acpi10:49:490
158339910677953470,53309cyclictest0-21swapper11:32:210
158339910657353440,53040cyclictest0-21swapper12:02:500
158339910655053434,53052cyclictest9-21ksoftirqd/012:32:580
158339910652453416,53042cyclictest0-21swapper07:35:230
158339910652053476,53044cyclictest0-21swapper09:28:350
158339910651253474,53038cyclictest0-21swapper10:00:350
158339910649753471,53026cyclictest0-21swapper08:15:540
158339910648553461,53024cyclictest0-21swapper10:39:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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