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2026-08-31 - 07:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Aug 31, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
286259910675953408,53260cyclictest0-21swapper23:33:000
286259910669853432,53175cyclictest28618-21cyclictest21:22:030
286259910667653420,53165cyclictest0-21swapper00:20:440
286259910665153398,53131cyclictest9299-21ssh21:59:440
286259910664753383,53201cyclictest3950irq/9-acpi21:43:290
286259910658253471,53111cyclictest0-21swapper19:31:510
286259910657353463,53110cyclictest0-21swapper20:58:260
286259910654953394,53092cyclictest9-21ksoftirqd/022:32:130
286259910654953387,53096cyclictest0-21swapper22:25:110
286259910653053426,53104cyclictest0-21swapper22:58:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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