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2026-04-07 - 05:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Apr 07, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
142929910726653385,53792cyclictest7305-21rm00:38:350
142929910660853429,53088cyclictest0-21swapper00:13:480
142929910659653414,53182cyclictest0-21swapper00:04:150
142929910654353375,53101cyclictest0-21swapper22:02:100
142929910648553458,53027cyclictest0-21swapper22:23:160
142929910647953462,53017cyclictest0-21swapper20:05:560
142929910647853455,53023cyclictest0-21swapper20:12:180
142929910646653447,53019cyclictest0-21swapper22:46:020
142929910646053447,53013cyclictest0-21swapper21:12:050
142929910644153398,53043cyclictest0-21swapper23:59:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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