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2026-03-13 - 20:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Mar 13, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
215799910673453441,53293cyclictest0-21swapper10:33:540
215799910670753476,53231cyclictest0-21swapper12:06:000
215799910667053380,53227cyclictest3950irq/9-acpi11:32:400
215799910664053470,53170cyclictest0-21swapper11:51:060
215799910663753423,53214cyclictest0-21swapper10:21:000
215799910658853465,53123cyclictest0-21swapper12:25:360
215799910654853386,53097cyclictest0-21swapper09:28:250
215799910653653406,53064cyclictest0-21swapper12:19:140
215799910651253474,53038cyclictest0-21swapper08:31:280
215799910651253474,53038cyclictest0-21swapper07:41:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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