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2026-01-16 - 00:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Jan 15, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179649910693453462,53472cyclictest4275-21ssh09:10:360
179649910676653453,53216cyclictest29570-21ssh09:49:280
179649910670953459,53153cyclictest2877-21diskmemload11:54:240
179649910658053390,53097cyclictest0-21swapper09:59:200
179649910655653451,53105cyclictest0-21swapper09:06:050
179649910654253386,53090cyclictest0-21swapper11:38:590
179649910649853467,53031cyclictest0-21swapper09:21:500
179649910649453465,53029cyclictest0-21swapper11:09:210
179649910647553456,53019cyclictest0-21swapper11:14:420
179649910647153461,53010cyclictest0-21swapper12:23:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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