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2026-07-10 - 06:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Jul 10, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
244819910699353423,53473cyclictest31687-21ssh23:16:380
244819910680953432,53285cyclictest9-21ksoftirqd/022:39:580
244819910679853423,53277cyclictest20062-21sh22:12:000
244819910665853472,53122cyclictest134850irq/9-eth021:21:550
244819910664053421,53128cyclictest9-21ksoftirqd/021:16:440
244819910663253443,53098cyclictest9-21ksoftirqd/023:43:460
244819910661553393,53132cyclictest9-21ksoftirqd/021:57:160
244819910659953476,53123cyclictest0-21swapper20:26:090
244819910654453386,53093cyclictest0-21swapper20:11:050
244819910653153399,53132cyclictest0-21swapper20:23:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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