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2026-05-18 - 01:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun May 17, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
290799910739653459,53841cyclictest29420-21ssh11:07:180
290799910679053402,53388cyclictest0-21swapper07:51:020
290799910675353433,53255cyclictest9-21ksoftirqd/010:43:410
290799910673053442,53224cyclictest9-21ksoftirqd/010:32:580
290799910662653458,53103cyclictest9-21ksoftirqd/012:27:110
290799910658453466,53118cyclictest0-21swapper07:23:340
290799910654753447,53100cyclictest0-21swapper08:01:040
290799910653753383,53089cyclictest0-21swapper07:35:470
290799910653553381,53088cyclictest0-21swapper07:28:250
290799910650453421,53083cyclictest0-21swapper08:31:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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