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2026-08-16 - 20:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Aug 16, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
292029910736153413,53852cyclictest14227-21diskmemload09:48:340
292029910706653455,53520cyclictest0-21swapper10:42:090
292029910702653472,53457cyclictest6429-21ssh12:08:440
292029910670453463,53241cyclictest0-21swapper08:25:500
292029910667053475,53195cyclictest0-21swapper11:33:240
292029910666653475,53191cyclictest0-21swapper12:19:270
292029910665353391,53203cyclictest0-21swapper09:37:410
292029910663853411,53134cyclictest0-21swapper12:28:300
292029910660553459,53053cyclictest0-21swapper11:42:170
292029910659053473,53051cyclictest0-21swapper10:18:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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