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2026-08-06 - 05:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Aug 06, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
185139910702953409,53529cyclictest0-21swapper21:01:030
185139910692853414,53418cyclictest12124-21ssh21:21:490
185139910687753467,53410cyclictest0-21swapper22:01:110
185139910676153428,53236cyclictest1687-21ssh23:30:260
185139910668253420,53198cyclictest0-21swapper20:10:390
185139910664553464,53181cyclictest0-21swapper20:50:300
185139910658353412,53080cyclictest0-21swapper00:39:460
185139910658053393,53093cyclictest0-21swapper21:46:460
185139910656953457,53112cyclictest0-21swapper21:38:240
185139910655953451,53045cyclictest3950irq/9-acpi22:48:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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