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2026-04-26 - 13:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Apr 26, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
287469910697153414,53461cyclictest12846-21diskmemload23:25:450
287469910683553392,53353cyclictest28738-21cyclictest19:47:020
287469910675253414,53247cyclictest0-21swapper23:17:430
287469910669253485,53111cyclictest14539-21ssh21:59:000
287469910667153451,53220cyclictest0-21swapper19:58:250
287469910666953449,53220cyclictest0-21swapper00:21:510
287469910656353429,53069cyclictest0-21swapper00:00:350
287469910655953457,53011cyclictest9-21ksoftirqd/021:51:180
287469910655253393,53095cyclictest9-21ksoftirqd/023:54:440
287469910652953429,53004cyclictest32305-21ssh23:58:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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