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2026-03-02 - 16:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Mar 02, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3223099209812105330,104480cyclictest0-21swapper10:19:460
322309910726653481,53686cyclictest17046-21diskmemload10:41:530
322309910692553373,53532cyclictest0-21swapper09:10:160
322309910667953373,53281cyclictest19284-21ssh11:36:490
322309910666153435,53226cyclictest0-21swapper08:15:000
322309910664853448,53200cyclictest0-21swapper09:25:010
322309910656453384,53086cyclictest0-21swapper09:49:480
322309910655953395,53099cyclictest0-21swapper07:15:530
322309910653653411,53125cyclictest0-21swapper08:41:580
322309910650353471,53032cyclictest0-21swapper09:20:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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