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2026-04-18 - 16:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Apr 18, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7379910696453418,53454cyclictest0-21swapper11:09:190
7379910674453407,53270cyclictest0-21swapper07:38:290
7379910670653432,53153cyclictest32059-21ssh11:54:220
7379910668853492,53196cyclictest0-21swapper12:27:020
7379910659153407,53184cyclictest0-21swapper09:33:320
7379910657453409,53101cyclictest9-21ksoftirqd/009:38:430
7379910654553400,53082cyclictest134850irq/9-eth010:36:100
7379910653553373,53097cyclictest9-21ksoftirqd/008:58:220
7379910652453436,53088cyclictest0-21swapper12:10:570
7379910651853432,53086cyclictest0-21swapper07:59:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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