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2026-03-09 - 03:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Mar 09, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
245319910712853459,53547cyclictest27949-21diskmemload23:56:000
245319910672553483,53242cyclictest0-21swapper23:02:050
245319910670153449,53186cyclictest0-21swapper20:20:590
245319910668553464,53098cyclictest27949-21diskmemload23:14:390
245319910657153455,53116cyclictest0-21swapper00:18:570
245319910654453389,53092cyclictest0-21swapper22:13:210
245319910653353443,53090cyclictest0-21swapper19:50:500
245319910651253470,53042cyclictest0-21swapper20:11:060
245319910649053468,53022cyclictest0-21swapper20:45:560
245319910649053463,53027cyclictest0-21swapper00:36:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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