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2026-03-23 - 08:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Mar 23, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
63209910717453422,53752cyclictest0-21swapper22:30:030
63209910697853414,53473cyclictest0-21swapper21:14:410
63209910676853476,53201cyclictest0-21swapper23:17:170
63209910672853458,53270cyclictest0-21swapper21:52:020
63209910672353458,53265cyclictest0-21swapper00:37:300
63209910669453385,53218cyclictest0-21swapper23:53:270
63209910650553471,53034cyclictest0-21swapper19:53:580
63209910649853451,53047cyclictest0-21swapper20:39:210
63209910648953463,53026cyclictest0-21swapper21:24:440
63209910647053477,52993cyclictest0-21swapper23:37:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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