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2026-05-17 - 12:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun May 17, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
242529910700853419,53493cyclictest4516-21ssh21:48:480
242529910690053424,53412cyclictest9-21ksoftirqd/000:16:310
242529910684453446,53398cyclictest0-21swapper21:18:190
242529910659153428,53100cyclictest9-21ksoftirqd/000:32:050
242529910653853440,53098cyclictest0-21swapper21:04:350
242529910651453476,53038cyclictest0-21swapper20:34:270
242529910650853472,53036cyclictest0-21swapper23:11:020
242529910648653491,52905cyclictest9-21ksoftirqd/000:25:330
242529910645853467,52991cyclictest0-21swapper20:43:390
242529910637953447,52869cyclictest24245-21cyclictest20:01:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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