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2026-07-09 - 07:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Jul 09, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
185459910744253410,53910cyclictest12559-21ssh22:08:140
185459910696653466,53410cyclictest18534-21cyclictest23:11:220
185459910690553458,53356cyclictest28269-21kworker/u2:000:04:270
185459910687953402,53413cyclictest134850irq/9-eth022:57:480
185459910683653473,53363cyclictest0-21swapper00:36:160
185459910670553452,53253cyclictest0-21swapper22:53:070
185459910667453446,53137cyclictest10-21rcuc/020:46:000
185459910654553421,53124cyclictest0-21swapper19:54:450
185459910648453420,53064cyclictest0-21swapper00:26:030
185459910648353464,53019cyclictest0-21swapper23:22:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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