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2025-12-03 - 01:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Dec 02, 2025 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1952999209797105333,104462cyclictest0-21swapper07:11:390
195299910697953447,53466cyclictest0-21swapper08:36:230
195299910650553422,53083cyclictest0-21swapper07:20:120
195299910650353471,53032cyclictest0-21swapper07:52:410
195299910632253478,52844cyclictest0-21swapper08:53:490
195299910631153427,52821cyclictest24985-21kworker/0:107:26:230
195299910622253474,52748cyclictest0-21swapper09:25:480
195299910616953407,52762cyclictest0-21swapper07:36:460
195299910614353439,52704cyclictest0-21swapper09:09:030
195299910614253434,52708cyclictest0-21swapper08:30:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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