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2025-11-24 - 21:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Nov 24, 2025 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304219910715653475,53590cyclictest0-21swapper09:59:490
304219910667853393,53220cyclictest0-21swapper07:32:360
304219910666053475,53185cyclictest0-21swapper11:53:210
304219910664153467,53174cyclictest0-21swapper08:35:040
304219910659353384,53146cyclictest9-21ksoftirqd/008:10:570
304219910654153398,53143cyclictest0-21swapper12:29:320
304219910653653414,53122cyclictest0-21swapper12:32:030
304219910652753436,53091cyclictest0-21swapper10:29:070
304219910652453471,53053cyclictest0-21swapper09:52:170
304219910651853437,53081cyclictest0-21swapper11:12:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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