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2026-06-03 - 00:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Jun 02, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
242309910732553438,53765cyclictest18973-21diskmemload12:26:490
242309910722953460,53672cyclictest16952-21rm11:28:320
242309910712053458,53598cyclictest3950irq/9-acpi10:19:020
242309910692653458,53404cyclictest9-21ksoftirqd/011:33:440
242309910687253445,53335cyclictest0-21swapper09:18:450
242309910674853468,53280cyclictest0-21swapper12:34:010
242309910671453479,53145cyclictest9-21ksoftirqd/007:26:330
242309910671453425,53289cyclictest0-21swapper10:44:500
242309910670853469,53239cyclictest0-21swapper08:47:360
242309910667553420,53189cyclictest0-21swapper08:59:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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