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2026-08-03 - 06:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Aug 03, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
109229910735053420,53807cyclictest31507-21ssh22:17:400
109229910703453413,53530cyclictest0-21swapper23:11:060
109229910686053454,53406cyclictest0-21swapper20:08:030
109229910661653393,53131cyclictest9-21ksoftirqd/021:18:330
109229910653253394,53138cyclictest0-21swapper20:43:330
109229910649053464,53026cyclictest0-21swapper22:14:090
109229910648853463,53025cyclictest0-21swapper22:45:480
109229910648553459,53026cyclictest0-21swapper21:50:430
109229910648153458,53023cyclictest0-21swapper00:04:410
109229910647253412,53060cyclictest0-21swapper20:11:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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