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2026-04-09 - 11:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Apr 09, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
270149910749853471,53929cyclictest9098-21ssh23:41:480
270149910660753480,53127cyclictest0-21swapper20:43:270
270149910657953465,53114cyclictest0-21swapper22:16:130
270149910654753390,53092cyclictest0-21swapper23:39:570
270149910652453481,53043cyclictest0-21swapper19:28:050
270149910651353475,53038cyclictest0-21swapper21:45:040
270149910650353451,53052cyclictest0-21swapper22:29:270
270149910648453459,53025cyclictest0-21swapper23:06:280
270149910645453428,53026cyclictest0-21swapper23:50:400
270149910644653399,53047cyclictest0-21swapper19:51:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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