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2026-01-11 - 16:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Jan 11, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
100039910716553475,53595cyclictest28287-21ssh09:59:210
100039910689853447,53451cyclictest0-21swapper11:44:020
100039910661553431,53184cyclictest0-21swapper09:48:580
100039910661253414,53107cyclictest0-21swapper09:32:040
100039910660553481,53058cyclictest0-21swapper12:30:150
100039910655353404,53149cyclictest0-21swapper07:45:330
100039910655353396,53094cyclictest9-21ksoftirqd/010:17:060
100039910649453475,53019cyclictest0-21swapper07:24:470
100039910648953427,53062cyclictest0-21swapper09:00:340
100039910647253455,53017cyclictest0-21swapper10:56:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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