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2026-08-23 - 02:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Aug 23, 2026 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
92049910728853478,53713cyclictest26552-21diskmemload23:23:580
92049910702253427,53531cyclictest3950irq/9-acpi22:13:280
92049910677753424,53289cyclictest0-21swapper22:58:410
92049910661053455,53155cyclictest0-21swapper22:29:430
92049910659353411,53117cyclictest30430-21kworker/u2:022:16:390
92049910656953434,53135cyclictest0-21swapper20:35:000
92049910656453415,53149cyclictest0-21swapper00:28:570
92049910654553414,53042cyclictest0-21swapper21:54:020
92049910650553429,53076cyclictest0-21swapper22:02:550
92049910644953405,53044cyclictest0-21swapper22:52:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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