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2026-07-08 - 06:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Jul 08, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
175299910749353458,53939cyclictest15252-21ssh21:27:570
175299910724153456,53688cyclictest4111-21ssh21:11:020
175299910673553406,53264cyclictest0-21swapper19:49:390
175299910670753428,53279cyclictest0-21swapper19:41:260
175299910665353404,53249cyclictest0-21swapper20:50:060
175299910664153465,53113cyclictest17528-21cyclictest22:43:590
175299910659953475,53124cyclictest0-21swapper00:18:560
175299910658353452,53066cyclictest9-21ksoftirqd/019:14:090
175299910656753445,53030cyclictest0-21swapper00:03:220
175299910650353474,53029cyclictest0-21swapper19:59:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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