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2026-01-30 - 02:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Jan 30, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
68099910703353407,53534cyclictest0-21swapper20:52:360
68099910702753411,53524cyclictest0-21swapper21:49:020
68099910680553433,53276cyclictest2099-21runrttasks21:21:440
68099910676953440,53237cyclictest9-21ksoftirqd/019:49:070
68099910663653420,53216cyclictest0-21swapper22:21:010
68099910658053383,53108cyclictest9-21ksoftirqd/022:19:210
68099910657353437,53136cyclictest0-21swapper00:38:110
68099910655953454,53105cyclictest0-21swapper21:50:520
68099910655153391,53095cyclictest0-21swapper22:04:260
68099910650253468,53034cyclictest0-21swapper22:51:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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