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2026-06-27 - 22:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Jun 27, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
288859910706653412,53561cyclictest0-21swapper11:28:050
288859910670853461,53247cyclictest0-21swapper10:31:380
288859910668053479,53076cyclictest20769-21ssh09:19:480
288859910666453461,53113cyclictest9-21ksoftirqd/007:33:170
288859910650453473,53031cyclictest0-21swapper09:47:260
288859910649553411,53084cyclictest0-21swapper11:51:310
288859910648353463,53020cyclictest0-21swapper08:41:060
288859910647353407,53066cyclictest0-21swapper10:46:430
288859910646853456,53012cyclictest0-21swapper11:31:560
288859910645553427,53028cyclictest0-21swapper11:56:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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