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2026-08-15 - 20:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Aug 15, 2026 12:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
231579910713853453,53587cyclictest20517-21ssh09:27:230
231579910707953471,53545cyclictest3950irq/9-acpi09:54:100
231579910672953470,53169cyclictest23156-21cyclictest08:56:340
231579910661953476,53143cyclictest0-21swapper11:23:460
231579910660853391,53154cyclictest9-21ksoftirqd/011:41:010
231579910659253448,53144cyclictest0-21swapper12:26:340
231579910647353461,53012cyclictest0-21swapper12:12:100
231579910644953441,53008cyclictest0-21swapper12:30:050
231579910643953395,53044cyclictest0-21swapper08:42:500
231579910636853478,52890cyclictest0-21swapper11:11:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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