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2026-03-29 - 17:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Mar 29, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
265369910732453427,53772cyclictest3257-21ssh10:33:430
265369910727653433,53750cyclictest0-21swapper09:18:110
265369910696453423,53477cyclictest8979-21ssh12:19:130
265369910687953461,53322cyclictest11475-21diskmemload12:32:370
265369910684353433,53314cyclictest21226-21ssh10:11:360
265369910675953409,53261cyclictest26535-21cyclictest08:35:390
265369910658253419,53066cyclictest6551-21ssh10:38:340
265369910656353428,53044cyclictest0-21swapper09:49:500
265369910654253411,53040cyclictest0-21swapper10:00:430
265369910652553433,53092cyclictest0-21swapper11:21:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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