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2026-07-18 - 10:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Jul 18, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2789699210581105318,105261cyclictest18583-21ssh21:29:370
278969910685553419,53372cyclictest27664-21ssh22:29:550
278969910669353456,53237cyclictest0-21swapper20:39:030
278969910665453392,53262cyclictest0-21swapper00:01:410
278969910662853464,53100cyclictest9-21ksoftirqd/021:30:280
278969910661553451,53067cyclictest14032-21ssh21:22:150
278969910659453484,53110cyclictest0-21swapper20:49:260
278969910659153407,53184cyclictest0-21swapper23:00:540
278969910656953397,53172cyclictest0-21swapper00:37:010
278969910656453395,53169cyclictest0-21swapper21:52:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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