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2026-09-17 - 08:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Sep 17, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158629910706953412,53592cyclictest0-21swapper20:59:500
158629910671053454,53256cyclictest0-21swapper00:31:110
158629910668453461,53133cyclictest9-21ksoftirqd/021:48:440
158629910665153461,53125cyclictest9-21ksoftirqd/020:24:500
158629910661353439,53174cyclictest0-21swapper00:23:290
158629910660353473,53130cyclictest0-21swapper00:18:370
158629910658853466,53122cyclictest0-21swapper21:24:370
158629910658053424,53156cyclictest0-21swapper20:47:460
158629910651653475,53041cyclictest0-21swapper22:33:370
158629910651053421,53089cyclictest0-21swapper20:39:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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