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2026-09-03 - 09:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Sep 03, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
284779910703553453,53517cyclictest134850irq/9-eth021:58:380
284779910696453401,53500cyclictest9-21ksoftirqd/019:23:030
284779910681853400,53323cyclictest9569-21ssh22:39:200
284779910677353450,53323cyclictest0-21swapper19:12:000
284779910664753474,53173cyclictest0-21swapper00:12:370
284779910658653407,53115cyclictest9-21ksoftirqd/000:30:220
284779910657253471,53101cyclictest0-21swapper21:33:210
284779910654953402,53147cyclictest0-21swapper20:22:500
284779910654653388,53067cyclictest0-21swapper00:24:100
284779910653153445,53086cyclictest0-21swapper23:06:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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