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2025-12-26 - 09:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Dec 26, 2025 00:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
286519910678553396,53295cyclictest0-21swapper23:32:240
286519910677053458,53246cyclictest0-21swapper00:31:410
286519910666253417,53245cyclictest0-21swapper20:08:360
286519910663153414,53121cyclictest1741-21hald20:53:290
286519910662653461,53165cyclictest0-21swapper22:48:420
286519910657553389,53096cyclictest0-21swapper20:27:410
286519910654853408,53140cyclictest0-21swapper00:10:350
286519910654253402,53140cyclictest0-21swapper22:06:300
286519910653953384,53091cyclictest0-21swapper21:56:370
286519910653453415,53119cyclictest0-21swapper20:45:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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