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2026-02-06 - 14:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Feb 06, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
214219910749353452,53941cyclictest2099-21runrttasks11:52:180
214219910699153424,53475cyclictest0-21swapper11:25:310
214219910694653475,53346cyclictest12274-21ssh10:50:210
214219910685853445,53325cyclictest3950irq/9-acpi12:12:340
214219910680853410,53276cyclictest3156-21ssh09:51:240
214219910673953392,53256cyclictest9-21ksoftirqd/009:36:490
214219910671753473,53244cyclictest0-21swapper07:30:230
214219910667153451,53220cyclictest0-21swapper08:35:120
214219910666453449,53215cyclictest0-21swapper12:38:120
214219910664853477,53080cyclictest0-21swapper12:25:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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