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2026-03-31 - 07:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Mar 31, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
323149910691953412,53384cyclictest172612sleep020:32:400
323149910671353263,53437cyclictest0-21swapper19:30:520
323149910670253472,53139cyclictest0-21swapper00:04:410
323149910667453394,53280cyclictest0-21swapper20:42:030
323149910653353443,53090cyclictest0-21swapper00:21:460
323149910652553440,53085cyclictest0-21swapper19:22:500
323149910652053440,53080cyclictest0-21swapper20:54:160
323149910651653477,53039cyclictest0-21swapper21:27:160
323149910644353443,53000cyclictest0-21swapper22:29:240
323149910636453427,52937cyclictest0-21swapper20:08:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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