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2026-03-05 - 17:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Mar 05, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
77339910706653470,53506cyclictest9-21ksoftirqd/008:35:410
77339910680253425,53281cyclictest3429-21rtkit-daemon10:15:100
77339910674653454,53195cyclictest2099-21runrttasks09:09:110
77339910666553457,53141cyclictest0-21swapper08:51:150
77339910658753468,53119cyclictest0-21swapper10:23:020
77339910658053463,53117cyclictest0-21swapper09:37:290
77339910655553454,53101cyclictest0-21swapper12:10:530
77339910655053388,53096cyclictest0-21swapper08:10:440
77339910654153474,53067cyclictest0-21swapper08:34:000
77339910653453379,53090cyclictest0-21swapper08:16:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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