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2026-09-02 - 08:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Sep 02, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2957299210875105406,105467cyclictest0-21swapper21:29:550
2957299210155105379,104774cyclictest25139-21ssh22:50:580
2957299209824105328,104494cyclictest0-21swapper22:18:190
295729910751053416,53998cyclictest1907-21snmpd20:23:160
295729910651953417,53038cyclictest9-21ksoftirqd/000:30:570
295729910618353474,52709cyclictest0-21swapper19:53:170
295729910615353398,52755cyclictest0-21swapper19:28:500
295729910612453425,52699cyclictest0-21swapper21:06:580
295729910610353032,53069cyclictest0-21swapper22:27:010
295729910608853006,53080cyclictest0-21swapper22:36:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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