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2026-04-20 - 13:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Apr 20, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19509910990055080,54818cyclictest1741-21hald19:20:360
19509910690053452,53357cyclictest0-21swapper21:05:060
19509910669353451,53242cyclictest0-21swapper23:12:520
19509910666053471,53125cyclictest9-21ksoftirqd/023:07:210
19509910651053459,53051cyclictest0-21swapper23:21:050
19509910650053470,53030cyclictest0-21swapper20:29:250
19509910648653423,53063cyclictest0-21swapper21:28:320
19509910647653448,53028cyclictest0-21swapper00:21:320
19509910645853467,52991cyclictest0-21swapper22:58:080
19509910644753394,52991cyclictest1941-21cyclictest20:33:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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