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2026-06-08 - 03:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Jun 08, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41499910668853408,53280cyclictest0-21swapper19:15:510
41499910664153388,53160cyclictest0-21swapper22:04:200
41499910660353458,53145cyclictest0-21swapper00:36:440
41499910655753321,53236cyclictest0-21swapper23:26:330
41499910652553480,53045cyclictest0-21swapper22:26:360
41499910650853473,53035cyclictest0-21swapper23:30:040
41499910649553437,53058cyclictest0-21swapper20:01:240
41499910647753456,53021cyclictest0-21swapper22:46:320
41499910643353445,52988cyclictest0-21swapper23:06:580
41499910626253414,52783cyclictest0-21swapper19:47:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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