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2026-03-18 - 13:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Mar 18, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
260559910732953458,53779cyclictest0-21swapper22:05:020
260559910704453481,53471cyclictest9-21ksoftirqd/023:16:220
260559910703253440,53497cyclictest7536-21ssh00:12:590
260559910684453419,53360cyclictest15068-1kworker/u3:223:35:280
260559910680853417,53269cyclictest23865-21ssh00:37:060
260559910669953434,53199cyclictest26047-21cyclictest23:06:400
260559910659553471,53124cyclictest0-21swapper22:45:440
260559910658553419,53102cyclictest9-21ksoftirqd/021:19:390
260559910653453384,53061cyclictest32292-21kworker/0:200:04:360
260559910651153449,53062cyclictest0-21swapper20:30:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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