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2026-01-07 - 17:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Jan 07, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2482699210835105371,105462cyclictest0-21swapper10:11:560
2482699209875105379,104494cyclictest0-21swapper08:30:570
248269910711653394,53601cyclictest31938-21ssh10:28:110
248269910695753434,53523cyclictest0-21swapper12:03:080
248269910686853436,53340cyclictest0-21swapper12:08:090
248269910685153392,53424cyclictest26307-21ssh11:06:120
248269910676453474,53199cyclictest0-21swapper08:52:530
248269910666553394,53183cyclictest3950irq/9-acpi09:50:000
248269910664753418,53163cyclictest0-21swapper07:49:250
248269910664053418,53222cyclictest0-21swapper10:03:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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