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2026-01-26 - 01:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Jan 25, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121459910686053393,53404cyclictest12133-21cyclictest11:06:580
121459910680153392,53314cyclictest5658-21ssh12:34:030
121459910667453413,53197cyclictest30320-21kworker/0:010:57:550
121459910667453401,53273cyclictest0-21swapper07:15:010
121459910656453396,53078cyclictest0-21swapper12:38:140
121459910651653476,53040cyclictest0-21swapper10:02:190
121459910650153471,53030cyclictest0-21swapper08:49:080
121459910648953476,53013cyclictest0-21swapper09:16:260
121459910648753459,53028cyclictest0-21swapper09:27:190
121459910646153408,53053cyclictest0-21swapper10:43:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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