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2026-05-25 - 08:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon May 25, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
219889910733553396,53814cyclictest27806-21ssh00:34:250
219889910715853434,53602cyclictest18332-21diskmemload00:04:360
219889910682553439,53386cyclictest0-21swapper20:51:000
219889910667853470,53160cyclictest3950irq/9-acpi21:56:490
219889910663453509,53125cyclictest0-21swapper20:57:320
219889910663153453,53178cyclictest18332-21diskmemload00:38:060
219889910661053472,53138cyclictest0-21swapper22:32:390
219889910659653477,53028cyclictest0-21swapper00:24:520
219889910659453469,53125cyclictest0-21swapper20:32:550
219889910658753480,53107cyclictest0-21swapper22:19:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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