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2026-01-10 - 20:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Jan 10, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
211569910699853423,53484cyclictest0-21swapper11:12:180
211569910678653468,53318cyclictest0-21swapper10:48:510
211569910674753406,53275cyclictest11-21rcu_preempt08:00:220
211569910672553461,53201cyclictest9-21ksoftirqd/012:05:030
211569910653753431,53106cyclictest0-21swapper10:05:280
211569910652453437,53022cyclictest16750-21ssh11:46:270
211569910650053467,53033cyclictest0-21swapper10:54:220
211569910648553477,53008cyclictest0-21swapper11:06:360
211569910648153401,53080cyclictest0-21swapper07:10:080
211569910647653448,53028cyclictest0-21swapper09:11:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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