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2026-07-20 - 12:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Jul 20, 2026 00:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
257009910687553476,53399cyclictest0-21swapper21:27:170
257009910676953459,53213cyclictest6881-21ssh22:50:410
257009910676053483,53188cyclictest0-21swapper22:14:200
257009910674253479,53263cyclictest0-21swapper21:06:000
257009910673653477,53259cyclictest0-21swapper22:03:270
257009910672253447,53210cyclictest9-21ksoftirqd/022:34:360
257009910666253475,53121cyclictest0-21swapper23:17:480
257009910664853475,53173cyclictest0-21swapper20:17:570
257009910657553385,53099cyclictest0-21swapper00:35:310
257009910654653449,53097cyclictest0-21swapper23:13:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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