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2026-08-19 - 21:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Aug 19, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
82839910755353475,53980cyclictest13534-21ssh09:38:260
82839910698953442,53483cyclictest134850irq/9-eth011:38:400
82839910664853392,53165cyclictest0-21swapper10:43:240
82839910662153387,53168cyclictest134850irq/9-eth007:40:220
82839910657853442,53040cyclictest1907-21snmpd07:48:340
82839910654853470,53078cyclictest0-21swapper07:27:480
82839910652553465,53060cyclictest0-21swapper08:54:530
82839910651553404,53018cyclictest0-21swapper08:59:450
82839910650753396,53111cyclictest0-21swapper09:32:540
82839910650253468,53034cyclictest0-21swapper10:20:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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