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2026-03-19 - 02:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Mar 19, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
94219910665253456,53196cyclictest0-21swapper19:58:000
94219910661453410,53114cyclictest9-21ksoftirqd/023:44:250
94219910657653462,53114cyclictest0-21swapper22:42:270
94219910653953477,53062cyclictest0-21swapper23:07:250
94219910653653474,52970cyclictest9-21ksoftirqd/023:21:590
94219910649353475,53018cyclictest0-21swapper21:59:050
94219910648853473,53015cyclictest0-21swapper21:26:150
94219910647153439,53032cyclictest0-21swapper19:32:330
94219910644553402,53043cyclictest0-21swapper00:09:320
94219910643653436,53000cyclictest0-21swapper00:35:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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