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2026-07-17 - 09:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Jul 17, 2026 00:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
72019910666553481,53184cyclictest0-21swapper00:38:270
72019910664053466,53174cyclictest0-21swapper21:31:230
72019910660653386,53157cyclictest9-21ksoftirqd/020:19:020
72019910660353384,53156cyclictest9-21ksoftirqd/023:47:520
72019910659653469,53036cyclictest9-21ksoftirqd/022:31:500
72019910659153407,53184cyclictest0-21swapper19:52:140
72019910658153471,53046cyclictest9-21ksoftirqd/023:00:290
72019910652153482,53039cyclictest0-21swapper23:56:050
72019910651753470,53047cyclictest0-21swapper22:59:280
72019910651453404,53110cyclictest0-21swapper23:32:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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