You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-03 - 09:07
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun May 03, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246159910704553402,53520cyclictest14981-21ssh22:29:330
246159910673453386,53283cyclictest0-21swapper22:00:540
246159910658953435,53062cyclictest0-21swapper19:57:290
246159910657153460,53111cyclictest0-21swapper23:22:380
246159910656053419,53020cyclictest8493-21ssh21:33:570
246159910652053477,53043cyclictest0-21swapper22:24:110
246159910650453470,53034cyclictest0-21swapper22:42:570
246159910649453470,53024cyclictest0-21swapper22:18:290
246159910648853466,53022cyclictest0-21swapper22:11:070
246159910647353459,53014cyclictest0-21swapper23:53:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional