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2026-07-30 - 19:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Jul 30, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184709910725953465,53697cyclictest7694-21ssh10:01:030
184709910704353429,53548cyclictest0-21swapper08:33:380
184709910671853459,53259cyclictest0-21swapper10:53:280
184709910670253474,53138cyclictest9-21ksoftirqd/007:49:250
184709910665653427,53229cyclictest0-21swapper08:39:100
184709910656553409,53065cyclictest0-21swapper07:29:190
184709910656353481,53082cyclictest0-21swapper10:46:560
184709910655153389,53097cyclictest0-21swapper09:29:040
184709910653553455,53080cyclictest0-21swapper08:15:430
184709910651053470,53040cyclictest0-21swapper09:52:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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