You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-12 - 19:08
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Aug 12, 2026 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180169910674153407,53269cyclictest0-21swapper09:32:190
180169910663953419,53130cyclictest9-21ksoftirqd/010:46:510
180169910650753475,53032cyclictest0-21swapper07:37:460
180169910649753445,53052cyclictest0-21swapper07:46:390
180169910644253441,53001cyclictest0-21swapper09:01:300
180169910640953428,52981cyclictest0-21swapper07:58:520
180169910625953451,52808cyclictest0-21swapper09:05:010
180169910620653443,52763cyclictest0-21swapper08:15:470
180169910619853462,52736cyclictest0-21swapper07:21:220
180169910618453455,52729cyclictest0-21swapper08:49:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional