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2026-07-05 - 03:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Jul 05, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
289019910716653417,53653cyclictest27092-21ssh21:28:220
289019910702153405,53524cyclictest0-21swapper20:38:080
289019910698853474,53451cyclictest9-21ksoftirqd/019:11:030
289019910672953465,53264cyclictest0-21swapper21:12:280
289019910665953466,53129cyclictest9-21ksoftirqd/000:32:460
289019910665753462,53131cyclictest9-21ksoftirqd/022:53:270
289019910657753463,53114cyclictest0-21swapper19:54:450
289019910644253440,53002cyclictest0-21swapper22:28:500
289019910643253458,52974cyclictest0-21swapper20:40:590
289019910621453470,52744cyclictest0-21swapper20:03:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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