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2026-09-08 - 13:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Sep 08, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184629910675653412,53344cyclictest0-21swapper19:49:150
184629910674853413,53244cyclictest0-21swapper22:31:520
184629910674153410,53240cyclictest0-21swapper23:58:570
184629910665253478,53174cyclictest0-21swapper00:31:170
184629910663753479,53158cyclictest0-21swapper19:57:580
184629910660953446,53099cyclictest9-21ksoftirqd/020:49:330
184629910659253469,53123cyclictest0-21swapper21:54:310
184629910654853417,53038cyclictest0-21swapper21:56:220
184629910654053462,53078cyclictest0-21swapper19:36:120
184629910653153476,53055cyclictest0-21swapper23:02:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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