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2026-02-23 - 20:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Feb 23, 2026 12:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
83129910707753478,53501cyclictest2272-21munin-node08:51:170
83129910666053467,53193cyclictest0-21swapper12:33:410
83129910663953471,53168cyclictest0-21swapper09:39:310
83129910661653461,53155cyclictest0-21swapper08:34:020
83129910659653387,53145cyclictest9-21ksoftirqd/007:37:460
83129910652253375,53057cyclictest0-21swapper11:03:550
83129910651553471,53044cyclictest0-21swapper07:17:000
83129910651053471,53039cyclictest0-21swapper11:09:070
83129910648153465,53016cyclictest0-21swapper10:25:040
83129910647253457,53015cyclictest0-21swapper12:24:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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