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2026-06-21 - 12:05
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Jun 21, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
88999910667253395,53188cyclictest8891-21cyclictest21:37:150
88999910664953380,53147cyclictest0-21swapper22:47:260
88999910657953396,53118cyclictest0-21swapper23:16:140
88999910657753413,53072cyclictest0-21swapper00:01:370
88999910657553474,53101cyclictest0-21swapper20:09:400
88999910647753459,53018cyclictest0-21swapper20:31:060
88999910647653401,53075cyclictest0-21swapper20:12:410
88999910646753414,53053cyclictest0-21swapper22:54:180
88999910645553446,53009cyclictest0-21swapper20:51:320
88999910644953450,52999cyclictest0-21swapper22:59:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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