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2026-06-30 - 22:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Jun 30, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
232189910689453414,53389cyclictest9-21ksoftirqd/009:44:100
232189910680253337,53445cyclictest0-21swapper08:04:510
232189910679653448,53252cyclictest32382-21diskmemload09:26:250
232189910671453384,53241cyclictest27847-21kworker/0:209:03:180
232189910669453452,53176cyclictest134850irq/9-eth009:36:370
232189910667753384,53201cyclictest11-21rcu_preempt12:28:270
232189910656353386,53114cyclictest3950irq/9-acpi08:54:350
232189910654453396,53148cyclictest0-21swapper08:09:520
232189910653653384,53062cyclictest0-21swapper08:46:330
232189910651453466,53048cyclictest0-21swapper11:42:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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