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2026-06-17 - 09:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Jun 17, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
210059910613253039,53091cyclictest0-21swapper21:57:320
210059910613053042,53086cyclictest0-21swapper21:47:090
210059910611653025,53089cyclictest0-21swapper00:03:080
210059910609453014,53078cyclictest0-21swapper20:29:360
210059910607653003,53071cyclictest0-21swapper20:17:430
210059910605552969,53084cyclictest0-21swapper21:33:150
210059910601652930,53084cyclictest0-21swapper21:23:120
210059910581952921,52896cyclictest31844-21ssh23:57:560
210059910559752926,52669cyclictest5600-21ssh22:37:030
210059910547452993,52479cyclictest3950irq/9-acpi23:43:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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