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2026-08-29 - 06:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Aug 29, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
109409910717053486,53586cyclictest2785-21ssh22:31:030
109409910699253462,53465cyclictest134850irq/9-eth023:29:500
109409910697653475,53435cyclictest0-21swapper22:22:000
109409910696253420,53451cyclictest0-21swapper21:58:230
109409910684853476,53372cyclictest0-21swapper21:42:190
109409910680953389,53357cyclictest134850irq/9-eth023:12:350
109409910673253456,53180cyclictest16712-21automount23:37:220
109409910667053387,53192cyclictest0-21swapper19:46:450
109409910658753392,53128cyclictest0-21swapper19:57:280
109409910655553477,53078cyclictest0-21swapper00:26:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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