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2026-04-15 - 13:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Apr 15, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
43609910691953468,53352cyclictest30222-21ssh00:31:410
43609910689753471,53331cyclictest21652-21diskmemload22:29:260
43609910665653429,53136cyclictest10-21rcuc/023:59:120
43609910661053431,53090cyclictest9-21ksoftirqd/023:48:190
43609910659153447,53144cyclictest0-21swapper22:21:240
43609910655653471,53085cyclictest0-21swapper22:35:480
43609910653753398,53139cyclictest0-21swapper20:47:370
43609910653553425,53110cyclictest0-21swapper23:10:080
43609910650453473,53031cyclictest0-21swapper21:59:470
43609910649953468,53031cyclictest0-21swapper22:57:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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