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2026-05-29 - 21:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri May 29, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
172159910697353460,53449cyclictest5350irq/9-uhci_hcd:09:36:500
172159910675753457,53300cyclictest0-21swapper11:59:010
172159910664553428,53217cyclictest0-21swapper12:27:400
172159910661253416,53074cyclictest22926-21ssh12:16:260
172159910659453424,53074cyclictest2272-21munin-node08:30:210
172159910659353425,53103cyclictest0-21swapper10:37:180
172159910656853413,53155cyclictest0-21swapper08:43:350
172159910655553392,53099cyclictest9-21ksoftirqd/007:20:210
172159910652153393,53128cyclictest0-21swapper11:41:160
172159910651953477,53042cyclictest0-21swapper07:58:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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