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2026-05-02 - 11:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat May 02, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
82839910680053409,53300cyclictest0-21swapper20:26:320
82839910674353466,53277cyclictest0-21swapper23:46:400
82839910669953383,53252cyclictest9-21ksoftirqd/020:35:350
82839910667653420,53165cyclictest0-21swapper23:38:080
82839910659353465,53128cyclictest0-21swapper00:26:420
82839910658553387,53132cyclictest0-21swapper22:33:290
82839910654253386,53066cyclictest0-21swapper21:59:390
82839910651153475,53036cyclictest0-21swapper19:42:100
82839910650153469,53032cyclictest0-21swapper23:01:170
82839910649253470,53022cyclictest0-21swapper21:49:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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