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2025-12-09 - 16:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Dec 09, 2025 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
238989910717753425,53752cyclictest0-21swapper09:27:520
238989910677853453,53325cyclictest0-21swapper09:56:000
238989910655453446,53108cyclictest0-21swapper08:12:200
238989910652353478,53045cyclictest0-21swapper10:10:550
238989910650153470,53031cyclictest0-21swapper12:20:520
238989910649653378,53054cyclictest3950irq/9-acpi08:24:340
238989910648653465,53021cyclictest0-21swapper10:48:350
238989910644853440,53008cyclictest0-21swapper09:42:470
238989910643453440,52994cyclictest0-21swapper09:17:590
238989910637453462,52847cyclictest9-21ksoftirqd/007:50:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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