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2026-03-13 - 13:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Mar 13, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
137339910678853479,53245cyclictest9-21ksoftirqd/019:33:340
137339910672453387,53243cyclictest19949-21diskmemload22:23:130
137339910667553457,53218cyclictest0-21swapper21:01:400
137339910656753453,53114cyclictest0-21swapper20:51:470
137339910656653412,53064cyclictest10388-21rm00:06:130
137339910655953455,53104cyclictest0-21swapper21:05:410
137339910655153460,53091cyclictest0-21swapper00:33:410
137339910652653467,53059cyclictest0-21swapper20:55:080
137339910650753400,53016cyclictest11-21rcu_preempt22:10:090
137339910649453469,53025cyclictest0-21swapper23:19:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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