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2026-03-06 - 23:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Mar 06, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
172369910678553462,53259cyclictest9-21ksoftirqd/008:24:220
172369910676553376,53376cyclictest0-21swapper07:35:580
172369910670953456,53190cyclictest17235-21cyclictest10:30:490
172369910651953439,53080cyclictest0-21swapper07:10:410
172369910649553426,53069cyclictest0-21swapper11:02:280
172369910647253416,52992cyclictest11-21rcu_preempt08:03:060
172369910644253444,52998cyclictest0-21swapper09:59:400
172369910643153395,53036cyclictest0-21swapper10:09:430
172369910640253458,52881cyclictest17235-21cyclictest09:13:270
172369910635053435,52824cyclictest0-21swapper09:05:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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