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2026-06-14 - 08:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sun Jun 14, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
289569910688453473,53314cyclictest2099-21runrttasks23:40:270
289569910675953439,53253cyclictest0-21swapper20:19:490
289569910653653403,53068cyclictest0-21swapper20:52:180
289569910653353378,53090cyclictest0-21swapper23:58:120
289569910648453404,53080cyclictest0-21swapper19:56:020
289569910647253460,53012cyclictest0-21swapper00:30:410
289569910646653452,53014cyclictest0-21swapper21:14:040
289569910644653437,53009cyclictest0-21swapper21:05:320
289569910643053432,52998cyclictest0-21swapper23:25:220
289569910642853381,52954cyclictest0-21swapper20:56:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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