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2026-06-09 - 17:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue Jun 09, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
209139910700553452,53553cyclictest0-21swapper11:11:210
209139910676453459,53305cyclictest0-21swapper10:58:580
209139910674153445,53296cyclictest0-21swapper08:54:220
209139910672653468,53195cyclictest20905-21cyclictest10:15:050
209139910669153431,53169cyclictest0-21swapper07:46:020
209139910661053474,53136cyclictest0-21swapper11:45:410
209139910657653378,53133cyclictest9-21ksoftirqd/008:45:390
209139910653753452,52996cyclictest20905-21cyclictest08:25:440
209139910653553450,53085cyclictest0-21swapper07:18:440
209139910653053433,53097cyclictest0-21swapper09:29:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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