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2026-07-23 - 16:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Thu Jul 23, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
43379910716153483,53588cyclictest23450-21kworker/u2:312:08:350
43379910682453430,53272cyclictest14105-21ssh10:27:360
43379910660253469,53133cyclictest0-21swapper07:41:380
43379910656953454,53115cyclictest0-21swapper08:01:240
43379910656653460,53106cyclictest0-21swapper10:48:520
43379910655853391,53102cyclictest0-21swapper12:38:140
43379910655353390,53097cyclictest0-21swapper09:55:370
43379910654753419,53062cyclictest0-21swapper08:54:490
43379910652253472,53050cyclictest0-21swapper11:56:320
43379910652053432,53088cyclictest0-21swapper07:35:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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