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2026-05-06 - 01:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue May 05, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
278769910688553413,53381cyclictest0-21swapper07:36:000
278769910688453432,53387cyclictest134850irq/9-eth012:23:020
278769910676453383,53291cyclictest0-21swapper11:32:480
278769910676253400,53240cyclictest10188-21ssh11:04:200
278769910671353390,53258cyclictest0-21swapper10:36:320
278769910660753476,53131cyclictest0-21swapper08:48:200
278769910655653393,53098cyclictest0-21swapper08:45:000
278769910654253384,53093cyclictest0-21swapper12:11:290
278769910654053384,53091cyclictest0-21swapper11:46:520
278769910646753395,52982cyclictest10-21rcuc/011:13:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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