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2026-05-09 - 20:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat May 09, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
127779910674453410,53242cyclictest0-21swapper09:04:040
127779910671753477,53145cyclictest7675-21ssh10:11:340
127779910671653478,53171cyclictest0-21swapper09:45:060
127779910666953454,53215cyclictest0-21swapper11:46:010
127779910661253391,53156cyclictest0-21swapper09:08:050
127779910648853435,53053cyclictest0-21swapper11:00:180
127779910648653432,53054cyclictest0-21swapper09:21:290
127779910648653418,53068cyclictest0-21swapper11:56:240
127779910647653455,53021cyclictest0-21swapper12:09:480
127779910646353454,53009cyclictest0-21swapper12:36:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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