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2026-06-02 - 00:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Jun 01, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
253339910751453433,53959cyclictest3377-21ssh12:05:280
253339910717953412,53646cyclictest4644-21ssh10:35:020
253339910675053414,53245cyclictest0-21swapper10:51:470
253339910665853441,53217cyclictest0-21swapper10:07:140
253339910664053380,53196cyclictest12076-21kworker/0:110:12:050
253339910663653472,53164cyclictest0-21swapper09:10:480
253339910659153385,53134cyclictest309452sleep007:22:260
253339910653153444,53087cyclictest0-21swapper12:29:050
253339910652153481,53040cyclictest0-21swapper10:19:170
253339910650753418,53089cyclictest0-21swapper11:51:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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