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2026-09-16 - 07:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Sep 16, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
308679910731353424,53767cyclictest13473-21ssh23:49:140
308679910676053470,53201cyclictest134850irq/9-eth021:34:450
308679910673553471,53264cyclictest0-21swapper22:44:250
308679910668853448,53240cyclictest0-21swapper22:15:470
308679910667953465,53124cyclictest9-21ksoftirqd/000:12:210
308679910664353410,53233cyclictest0-21swapper21:56:010
308679910662753426,53137cyclictest9-21ksoftirqd/021:06:470
308679910659753405,53192cyclictest0-21swapper21:47:390
308679910655553405,53150cyclictest0-21swapper20:04:390
308679910650453431,53073cyclictest0-21swapper23:03:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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