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2026-01-05 - 02:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Mon Jan 05, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
126979910685653462,53301cyclictest9-21ksoftirqd/021:32:480
126979910681853459,53293cyclictest0-21swapper21:20:540
126979910670653468,53238cyclictest0-21swapper00:21:560
126979910670253475,53138cyclictest9-21ksoftirqd/021:11:520
126979910665453385,53269cyclictest0-21swapper20:05:430
126979910664653476,53106cyclictest9-21ksoftirqd/022:21:420
126979910658553409,53176cyclictest0-21swapper23:00:130
126979910658353426,53066cyclictest0-21swapper20:18:060
126979910654353387,53156cyclictest0-21swapper20:26:490
126979910652153474,53047cyclictest0-21swapper21:05:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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