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2026-05-06 - 22:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed May 06, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
167219910679053468,53232cyclictest9-21ksoftirqd/011:31:220
167219910668253407,53275cyclictest0-21swapper08:14:560
167219910660853479,53038cyclictest0-21swapper07:26:320
167219910660653390,53153cyclictest9-21ksoftirqd/011:27:510
167219910655353461,53092cyclictest0-21swapper08:22:380
167219910654353387,53091cyclictest0-21swapper10:51:510
167219910654253453,53089cyclictest0-21swapper07:58:010
167219910650553470,53035cyclictest0-21swapper11:44:560
167219910650053468,53032cyclictest0-21swapper10:48:200
167219910647953417,53062cyclictest0-21swapper07:52:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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