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2025-11-30 - 01:23
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Nov 29, 2025 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
837199209928105423,104503cyclictest0-21swapper11:36:210
83719910726453464,53703cyclictest22764-21ssh11:18:060
83719910708853455,53633cyclictest0-21swapper09:02:160
83719910674553471,53274cyclictest0-21swapper11:41:420
83719910669653447,53249cyclictest0-21swapper10:46:260
83719910665653475,53181cyclictest0-21swapper09:07:580
83719910659353457,53136cyclictest0-21swapper08:04:000
83719910651253479,53033cyclictest0-21swapper09:38:570
83719910651253445,53067cyclictest0-21swapper10:06:250
83719910644453400,53044cyclictest0-21swapper08:20:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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