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2026-07-24 - 16:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Fri Jul 24, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
232319910686953433,53436cyclictest0-21swapper08:09:010
232319910680953462,53250cyclictest20180-21ssh12:34:580
232319910669653473,53101cyclictest10084-21rm09:11:290
232319910668553452,53233cyclictest0-21swapper08:39:000
232319910660953414,53195cyclictest0-21swapper11:05:020
232319910653753398,53139cyclictest0-21swapper10:10:360
232319910650453415,53089cyclictest0-21swapper11:43:530
232319910649153469,53022cyclictest0-21swapper11:48:440
232319910648253464,53018cyclictest0-21swapper11:33:400
232319910647853448,53030cyclictest0-21swapper12:12:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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