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2026-07-15 - 09:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Wed Jul 15, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
278959910710253452,53529cyclictest28083-21ssh23:51:230
278959910704053403,53573cyclictest4129-21kworker/u2:121:53:190
278959910701353472,53445cyclictest12949-21diskmemload22:33:010
278959910671853478,53240cyclictest0-21swapper19:16:540
278959910671453473,53241cyclictest0-21swapper22:06:530
278959910671353411,53239cyclictest27888-21cyclictest19:32:490
278959910664353405,53147cyclictest0-21swapper19:57:260
278959910655553443,53013cyclictest12949-21diskmemload00:00:360
278959910652953397,53132cyclictest0-21swapper22:23:380
278959910651853474,53044cyclictest0-21swapper21:47:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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