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2026-06-13 - 08:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Sat Jun 13, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
314689910733353422,53814cyclictest15690-21diskmemload00:22:240
314689910718253448,53610cyclictest28748-21rm00:33:470
314689910710953470,53519cyclictest3465-21rm21:38:060
314689910676653394,53251cyclictest19622-21ssh23:34:300
314689910659753450,53147cyclictest0-21swapper21:07:280
314689910653753402,53135cyclictest0-21swapper20:16:530
314689910650353474,53029cyclictest0-21swapper21:34:350
314689910649353445,53048cyclictest0-21swapper21:02:360
314689910648153460,53021cyclictest0-21swapper20:25:460
314689910647753460,53017cyclictest0-21swapper00:37:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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