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2026-05-05 - 05:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 10 highest latencies:
System rack6slot6 (updated Tue May 05, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299689910715253445,53612cyclictest7726-21ssh00:06:000
299689910711953479,53543cyclictest9-21ksoftirqd/022:31:530
299689910703953413,53534cyclictest0-21swapper23:34:410
299689910696153422,53447cyclictest0-21swapper23:59:480
299689910674853474,53274cyclictest0-21swapper00:21:350
299689910671653402,53251cyclictest29583-21kworker/0:100:04:500
299689910669253464,53228cyclictest0-21swapper23:43:030
299689910668153421,53169cyclictest0-21swapper20:41:310
299689910655753481,53076cyclictest0-21swapper19:39:430
299689910650753486,53021cyclictest0-21swapper21:56:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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