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2026-01-24 - 00:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 100 highest latencies:
System rack6slot6 (updated Fri Jan 23, 2026 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
187969910746753417,53927cyclictest6448-21ssh09:57:180
187969910691053400,53415cyclictest12295-21ssh11:43:490
187969910672853440,53288cyclictest0-21swapper08:45:270
187969910667253447,53225cyclictest0-21swapper07:36:380
187969910661853422,53196cyclictest0-21swapper09:52:070
187969910655853407,53151cyclictest0-21swapper08:41:160
187969910653053398,53132cyclictest0-21swapper10:58:560
187969910645953476,52894cyclictest9-21ksoftirqd/010:21:250
187969910645753448,53009cyclictest0-21swapper09:01:320
187969910639853476,52831cyclictest0-21swapper07:51:420
187969910633553405,52864cyclictest0-21swapper12:30:520
187969910626253467,52795cyclictest0-21swapper08:32:240
187969910625553462,52793cyclictest0-21swapper07:20:330
187969910622053476,52744cyclictest0-21swapper08:28:530
187969910621253469,52743cyclictest0-21swapper07:27:150
187969910617953453,52726cyclictest0-21swapper12:14:180
187969910616853401,52767cyclictest0-21swapper07:18:120
187969910616253403,52759cyclictest0-21swapper10:14:330
187969910615753400,52757cyclictest0-21swapper07:44:200
187969910615053399,52751cyclictest0-21swapper10:19:450
187969910608152994,53085cyclictest0-21swapper09:20:580
187969910556453006,52553cyclictest18792-21cyclictest11:05:380
187969910517953048,52129cyclictest0-21swapper10:02:400
187969910511953018,52099cyclictest0-21swapper11:12:500
187969910509152980,52110cyclictest0-21swapper09:27:300
187969910500052904,52094cyclictest0-21swapper10:43:310
18796995313624,53112cyclictest0-21swapper08:00:040
18796995278225,52757cyclictest0-21swapper08:09:070
18796995277126,52745cyclictest0-21swapper08:51:090
187969926141091,1396cyclictest2099-21runrttasks10:09:520
187969925031079,1297cyclictest29007-21ssh12:06:050
187969924681088,1281cyclictest3900-21ssh11:31:250
187969924371094,1248cyclictest134850irq/9-eth012:18:090
187969923841031,1255cyclictest6224-21ssh10:45:220
187969923561046,1207cyclictest3800-21diskmemload11:46:090
187969922081041,1145cyclictest0-21swapper11:54:420
18796992202999,1186cyclictest2099-21runrttasks08:14:080
187969922021048,1027cyclictest5880-21rm09:11:550
187969921281042,994cyclictest5350irq/9-uhci_hcd:10:32:380
187969921001041,994cyclictest3950irq/9-acpi11:16:510
187969920641078,888cyclictest9009-21ssh09:15:560
187969920531022,965cyclictest3950irq/9-acpi12:20:090
18796992039987,1016cyclictest0-21swapper11:02:370
18796991995978,981cyclictest307-21ssh10:36:190
18796991988973,977cyclictest29087-21ssh10:29:170
187969919811031,915cyclictest0-21swapper08:20:200
18796991974951,989cyclictest0-21swapper07:58:340
187969919381033,810cyclictest0-21swapper10:52:140
187969919341035,806cyclictest0-21swapper09:42:340
187969918841086,671cyclictest23419-21ssh11:59:230
187969918631067,673cyclictest0-21swapper08:35:450
187969918031093,642cyclictest3950irq/9-acpi12:25:210
187969917821006,683cyclictest0-21swapper08:55:100
187969917351044,654cyclictest7268-21ssh11:35:560
187969917041032,607cyclictest10-21rcuc/009:47:550
187969916901071,619cyclictest0-21swapper12:01:440
187969916891023,572cyclictest0-21swapper11:20:420
187969916761093,583cyclictest0-21swapper12:37:240
187969916721091,581cyclictest0-21swapper11:26:140
187969916471086,469cyclictest21568-21ssh09:34:110
187969916121084,436cyclictest9-21ksoftirqd/009:08:040
187969916091083,435cyclictest9-21ksoftirqd/008:16:290
187969915811082,433cyclictest0-21swapper07:34:170
187969915081013,428cyclictest0-21swapper07:45:200
187969914691089,380cyclictest0-21swapper07:10:400
187969914321080,352cyclictest0-21swapper09:39:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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