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2026-02-23 - 02:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 100 highest latencies:
System rack6slot6 (updated Mon Feb 23, 2026 00:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
69809910740853428,53881cyclictest1907-21snmpd23:04:380
69809910730953395,53817cyclictest10728-21ssh21:57:390
69809910677853487,53201cyclictest6972-21cyclictest22:52:350
69809910672153442,53279cyclictest0-21swapper21:20:580
69809910668653387,53208cyclictest0-21swapper23:26:550
69809910661653379,53146cyclictest9-21ksoftirqd/021:49:370
69809910660853478,53064cyclictest0-21swapper20:31:040
69809910659953473,53060cyclictest0-21swapper21:06:340
69809910657153453,53118cyclictest0-21swapper20:42:470
69809910655453415,53139cyclictest0-21swapper00:21:400
69809910653553404,53131cyclictest0-21swapper23:18:520
69809910646653468,52998cyclictest0-21swapper00:39:360
69809910645553406,53049cyclictest0-21swapper22:26:170
69809910645253445,53007cyclictest0-21swapper23:40:390
69809910644053466,52974cyclictest0-21swapper20:55:510
69809910643553440,52995cyclictest0-21swapper22:45:330
69809910643553398,53037cyclictest0-21swapper19:32:270
69809910643353449,52984cyclictest0-21swapper21:36:230
69809910641853432,52986cyclictest0-21swapper23:07:390
69809910631053407,52903cyclictest0-21swapper21:15:070
69809910625753388,52804cyclictest0-21swapper20:21:410
69809910625353418,52835cyclictest0-21swapper21:02:330
69809910624053379,52796cyclictest0-21swapper19:36:580
69809910623153476,52755cyclictest0-21swapper19:53:130
69809910622253473,52749cyclictest0-21swapper19:49:420
69809910621753472,52745cyclictest0-21swapper20:29:130
69809910621453422,52792cyclictest0-21swapper00:00:440
69809910620353468,52735cyclictest0-21swapper20:37:560
69809910618653460,52726cyclictest0-21swapper20:14:090
69809910614753450,52697cyclictest0-21swapper00:09:470
69809910611153421,52690cyclictest0-21swapper20:00:550
69809910602053072,52946cyclictest24936-21ssh22:18:550
69809910594853111,52827cyclictest5328-21ssh22:37:000
69809910592553397,52528cyclictest0-21swapper21:12:560
69809910562052970,52647cyclictest22536-21ssh21:27:300
69809910519753079,52116cyclictest0-21swapper23:12:510
69809910517453060,52112cyclictest0-21swapper23:32:460
6980995397053374,505cyclictest0-21swapper00:30:030
6980995393553407,528cyclictest0-21swapper22:43:320
6980995382653433,393cyclictest0-21swapper20:53:200
6980995377253437,335cyclictest0-21swapper00:26:320
6980995371227,53590cyclictest134850irq/9-eth023:36:170
6980995355026,0cyclictest0-21swapper22:11:530
6980995354325,0cyclictest0-21swapper21:51:070
6980995347025,0cyclictest0-21swapper00:15:490
6980995327826,53158cyclictest0-21swapper19:59:050
6980995326027,53166cyclictest0-21swapper19:40:500
6980995307427,53047cyclictest0-21swapper22:59:270
6980995306927,52950cyclictest0-21swapper20:06:270
69809923171083,1185cyclictest10166-21diskmemload23:22:330
69809921301019,959cyclictest25726-21ssh21:32:010
69809920721025,1012cyclictest0-21swapper23:52:520
69809920261094,932cyclictest0-21swapper23:56:430
69809920081090,822cyclictest27668-21ssh22:22:260
6980991999981,1018cyclictest0-21swapper23:48:210
6980991928927,967cyclictest0-21swapper00:10:270
6980991909917,968cyclictest0-21swapper22:31:290
6980991888895,978cyclictest0-21swapper20:49:490
69809918811044,740cyclictest10166-21diskmemload22:06:520
69809918201020,764cyclictest14988-21ssh22:04:310
69809915941094,500cyclictest0-21swapper19:24:150
69809915401092,357cyclictest0-21swapper19:29:460
69809914151030,385cyclictest0-21swapper21:42:040
69809914101074,336cyclictest0-21swapper20:15:290
6980991121622,496cyclictest4228-21wc19:16:530
6980991104612,488cyclictest30100-21wc19:14:020
698099560552,6cyclictest6884-21latency_hist19:10:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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