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2025-11-29 - 19:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 100 highest latencies:
System rack6slot6 (updated Sat Nov 29, 2025 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
837199209928105423,104503cyclictest0-21swapper11:36:210
83719910726453464,53703cyclictest22764-21ssh11:18:060
83719910708853455,53633cyclictest0-21swapper09:02:160
83719910674553471,53274cyclictest0-21swapper11:41:420
83719910669653447,53249cyclictest0-21swapper10:46:260
83719910665653475,53181cyclictest0-21swapper09:07:580
83719910659353457,53136cyclictest0-21swapper08:04:000
83719910651253479,53033cyclictest0-21swapper09:38:570
83719910651253445,53067cyclictest0-21swapper10:06:250
83719910644453400,53044cyclictest0-21swapper08:20:040
83719910644153446,52995cyclictest0-21swapper07:18:370
83719910641653433,52983cyclictest0-21swapper12:16:320
83719910635453459,52832cyclictest9-21ksoftirqd/008:32:480
83719910628853435,52853cyclictest0-21swapper07:22:380
83719910627953384,52895cyclictest0-21swapper08:52:540
83719910623653387,52805cyclictest0-21swapper08:09:510
83719910620353464,52739cyclictest0-21swapper09:32:050
83719910619353463,52730cyclictest0-21swapper08:29:070
83719910619153428,52763cyclictest0-21swapper07:35:110
83719910617653412,52764cyclictest0-21swapper08:12:220
83719910616353449,52714cyclictest0-21swapper10:44:060
83719910614853398,52750cyclictest0-21swapper07:52:560
83719910612253038,53082cyclictest0-21swapper09:28:340
83719910600352918,53083cyclictest0-21swapper09:16:200
83719910529053017,52271cyclictest25536-21diskmemload10:32:020
83719910528153055,52226cyclictest0-21swapper07:43:240
83719910516053030,52129cyclictest0-21swapper10:02:040
83719910513853053,52083cyclictest0-21swapper08:37:090
83719910504452942,52100cyclictest25118-21ssh10:36:340
83719910503452903,52129cyclictest0-21swapper10:29:520
83719910501652920,52094cyclictest0-21swapper09:41:480
83719910497752918,52054cyclictest0-21swapper10:59:200
8371995383253413,328cyclictest0-21swapper11:24:070
8371995362127,53527cyclictest0-21swapper07:30:200
8371995346527,53400cyclictest25536-21diskmemload11:58:270
8371995334727,53199cyclictest0-21swapper07:49:050
8371995303925,53014cyclictest0-21swapper10:22:300
83719924921086,1283cyclictest1460650ssh11:06:220
83719923081094,1088cyclictest12256-21ssh12:31:370
83719922621028,1142cyclictest9-21ksoftirqd/012:08:000
83719922011093,1041cyclictest3950irq/9-acpi09:46:490
83719921631023,1015cyclictest4863-21ssh10:53:380
83719921341025,1073cyclictest23816-21ssh12:03:590
83719921111014,1060cyclictest15520-21ssh12:35:480
83719920931037,1022cyclictest0-21swapper11:14:140
83719920881036,1018cyclictest0-21swapper12:11:010
83719919651031,814cyclictest0-21swapper08:41:500
8371991935934,968cyclictest28349-21ssh09:13:200
83719919181094,731cyclictest0-21swapper11:02:210
83719919091039,777cyclictest0-21swapper07:58:180
8371991904926,954cyclictest0-21swapper08:16:230
83719917371092,645cyclictest0-21swapper08:48:320
8371991730950,759cyclictest3950irq/9-acpi10:11:160
83719917011094,607cyclictest0-21swapper08:57:050
8371991693852,827cyclictest133750irq/9-eth009:23:020
83719916861011,610cyclictest5350irq/9-uhci_hcd:12:29:560
83719916731039,569cyclictest133750irq/9-eth011:50:350
8371991642813,826cyclictest0-21swapper09:51:100
8371991637992,608cyclictest11242-21ssh10:18:080
83719916101086,458cyclictest0-21swapper11:47:040
83719915921079,448cyclictest9-21ksoftirqd/007:13:550
8371991522752,766cyclictest0-21swapper11:26:380
8371991512769,738cyclictest584-21ssh11:31:490
83719915071020,450cyclictest28063-21ssh09:56:220
83719914961010,422cyclictest0-21swapper12:23:240
83719914441089,355cyclictest0-21swapper07:27:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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