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2026-03-05 - 10:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6 (updated Thu Mar 05, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71119910701553477,53443cyclictest1622-21ssh23:26:030
71119910668353409,53274cyclictest0-21swapper22:45:010
71119910659653475,53121cyclictest0-21swapper22:29:160
71119910656653418,53148cyclictest2790-21gnome-settings-21:49:450
71119910653853384,53088cyclictest0-21swapper19:44:090
71119910653153398,53133cyclictest0-21swapper21:57:370
71119910650253464,53038cyclictest0-21swapper22:20:540
71119910649653460,53036cyclictest0-21swapper19:45:590
71119910647353455,53018cyclictest0-21swapper22:54:030
71119910647353414,53059cyclictest0-21swapper00:25:100
71119910645553448,53007cyclictest0-21swapper20:28:210
71119910645053403,53047cyclictest0-21swapper22:13:420
71119910644453399,53045cyclictest0-21swapper21:40:520
71119910641553429,52986cyclictest0-21swapper00:02:130
71119910638353475,52818cyclictest9-21ksoftirqd/021:17:560
71119910624953471,52778cyclictest0-21swapper19:34:160
71119910621853476,52742cyclictest0-21swapper20:39:550
71119910621853459,52759cyclictest0-21swapper20:24:100
71119910614553441,52704cyclictest0-21swapper20:04:040
71119910604153387,52647cyclictest10226-21kworker/0:020:11:060
71119910511753018,52097cyclictest0-21swapper21:26:480
7111995352224,0cyclictest0-21swapper22:35:280
7111995324727,53154cyclictest0-21swapper20:18:490
7111995309825,53073cyclictest0-21swapper23:08:580
7111995277925,52754cyclictest0-21swapper20:40:550
71119924581080,1254cyclictest1196-21ssh00:13:460
71119922851097,1091cyclictest29032-21ssh23:19:510
71119922641081,1084cyclictest19550-21ssh22:17:230
71119921791090,995cyclictest134850irq/9-eth021:10:440
71119921711056,1024cyclictest9-21ksoftirqd/023:37:360
71119920921067,960cyclictest134850irq/9-eth000:33:220
71119920831051,909cyclictest22401-21ssh21:34:500
71119920651021,1009cyclictest0-21swapper23:03:260
71119920571019,1000cyclictest8552-21ssh00:24:390
71119920421091,886cyclictest9408-21rm22:02:280
7111992033987,1010cyclictest0-21swapper21:35:510
7111992002990,975cyclictest17766-21ssh00:37:330
71119919961035,867cyclictest0-21swapper19:28:540
71119919771025,858cyclictest0-21swapper19:55:420
7111991966946,1020cyclictest0-21swapper22:44:100
71119919531095,858cyclictest0-21swapper23:11:580
71119919451026,860cyclictest0-21swapper19:38:370
71119919091026,791cyclictest3950irq/9-acpi22:56:140
71119918911030,763cyclictest2099-21runrttasks23:44:580
7111991870887,970cyclictest14398-21kworker/0:223:24:120
71119918231061,670cyclictest0-21swapper20:45:260
71119917891079,617cyclictest134850irq/9-eth023:33:150
71119917541093,661cyclictest0-21swapper22:34:280
71119917351090,645cyclictest0-21swapper20:55:290
71119917331089,644cyclictest0-21swapper23:59:320
71119917261084,642cyclictest0-21swapper21:51:450
71119917181047,575cyclictest2099-21runrttasks21:04:120
71119917181034,618cyclictest3950irq/9-acpi21:06:320
71119916071066,541cyclictest0-21swapper22:05:490
71119915961083,450cyclictest7100-21kworker/0:223:51:300
71119915491078,381cyclictest0-21swapper20:34:530
7111991524792,721cyclictest16264-21taskset23:47:590
71119914921093,399cyclictest0-21swapper00:15:570
71119914551094,361cyclictest0-21swapper19:54:320
71119914371082,355cyclictest0-21swapper20:52:580
71119914251089,336cyclictest0-21swapper20:07:050
71119913951053,342cyclictest0-21swapper21:23:170
71119913551051,304cyclictest0-21swapper00:08:450
7111991157619,533cyclictest17440-21hwlatdetect-tra19:24:530
7111991124602,518cyclictest12860-21hwlatdetect-tra19:12:500
7111991122603,515cyclictest24543-21hwlatdetect-tra19:15:400
209025912,38sleep02386-21wc19:07:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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