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2026-03-01 - 23:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6 (updated Sun Mar 01, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6569910697053429,53449cyclictest9-21ksoftirqd/012:24:380
6569910683053387,53354cyclictest245172sleep010:49:500
6569910682353421,53305cyclictest17989-21diskmemload12:01:310
6569910666653392,53210cyclictest134850irq/9-eth008:15:560
6569910654853389,53068cyclictest0-21swapper08:07:230
6569910654053385,53090cyclictest0-21swapper10:59:430
6569910649053462,53028cyclictest0-21swapper11:57:400
6569910646253465,52997cyclictest0-21swapper07:24:210
6569910643353436,52997cyclictest0-21swapper08:38:320
6569910643153435,52996cyclictest0-21swapper08:27:490
6569910642853431,52997cyclictest0-21swapper12:19:360
6569910634253461,52881cyclictest0-21swapper07:28:020
6569910632053434,52821cyclictest0-21swapper08:53:270
6569910631453411,52841cyclictest9-21ksoftirqd/008:56:580
6569910625153440,52811cyclictest0-21swapper12:09:230
6569910623653436,52800cyclictest0-21swapper09:45:020
6569910622353475,52748cyclictest0-21swapper08:12:550
6569910621253472,52740cyclictest0-21swapper08:32:510
6569910620553466,52739cyclictest0-21swapper07:43:170
6569910619453459,52735cyclictest0-21swapper07:54:300
6569910617253453,52719cyclictest0-21swapper10:28:240
6569910617153406,52765cyclictest0-21swapper09:03:100
6569910614753437,52710cyclictest0-21swapper07:46:270
6569910614753056,53089cyclictest0-21swapper11:44:460
6569910613553433,52702cyclictest0-21swapper09:20:450
6569910610453063,53039cyclictest22110-21ssh11:30:420
6569910592652961,52962cyclictest1741-21hald11:36:040
6569910577853271,52507cyclictest0-21swapper11:25:310
6569910576652988,52776cyclictest11482-21ssh11:15:380
6569910539153137,52254cyclictest0-21swapper09:26:060
6569910518053071,52107cyclictest0-21swapper10:54:320
6569910513653049,52085cyclictest0-21swapper11:20:090
6569910513253036,52094cyclictest0-21swapper09:43:310
6569910509652997,52098cyclictest0-21swapper09:13:320
6569910507352967,52104cyclictest0-21swapper10:07:180
6569910505752957,52098cyclictest0-21swapper10:40:380
6569910505352957,52094cyclictest0-21swapper10:37:070
6569910505152968,52082cyclictest0-21swapper07:14:080
6569910504552948,52095cyclictest0-21swapper11:49:170
6569910501652891,52123cyclictest0-21swapper10:11:390
656995377325,0cyclictest0-21swapper12:34:000
656995347225,53447cyclictest0-21swapper11:03:540
656995341526,53389cyclictest0-21swapper09:37:390
656995324726,0cyclictest0-21swapper08:02:320
656995323425,53117cyclictest0-21swapper11:07:350
656995318025,53155cyclictest0-21swapper08:21:380
65699531188,53108cyclictest0-21swapper09:59:160
656995307625,53051cyclictest0-21swapper08:45:040
656995304225,52926cyclictest0-21swapper07:59:310
656995278025,52755cyclictest0-21swapper12:37:510
6569924711053,1293cyclictest1741-21hald08:42:340
6569921661044,1031cyclictest3950irq/9-acpi09:15:330
6569920491005,1024cyclictest0-21swapper12:27:080
6569919401080,737cyclictest17989-21diskmemload10:18:110
6569917291005,627cyclictest178282sleep009:09:110
656991567726,833cyclictest0-21swapper10:21:220
656991547716,823cyclictest0-21swapper10:02:160
65699152427,1372cyclictest1907-21snmpd07:33:540
6569914571094,363cyclictest0-21swapper11:53:490
6569914331052,381cyclictest0-21swapper09:33:180
6569914281080,348cyclictest0-21swapper12:14:350
656991325624,698cyclictest0-21swapper09:54:340
656991295933,342cyclictest3950irq/9-acpi11:14:570
656991241597,642cyclictest0-21swapper10:31:450
6569911401024,116cyclictest0-21swapper07:19:400
656991072452,618cyclictest0-21swapper07:35:140
30979255085,238sleep00-21swapper07:05:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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