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2026-01-29 - 11:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6 (updated Thu Jan 29, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
269329910978755240,54544cyclictest1741-21hald22:28:390
269329910704053418,53529cyclictest0-21swapper00:29:430
269329910687753460,53417cyclictest0-21swapper22:22:270
269329910670553424,53268cyclictest0-21swapper21:05:350
269329910669953469,53230cyclictest0-21swapper00:21:010
269329910656053455,53105cyclictest0-21swapper19:41:510
269329910654853390,53066cyclictest0-21swapper00:32:240
269329910652553393,53132cyclictest0-21swapper22:04:320
269329910647153456,53015cyclictest0-21swapper23:23:540
269329910642853430,52998cyclictest0-21swapper19:48:320
269329910630053467,52833cyclictest0-21swapper19:29:370
269329910630053453,52783cyclictest9-21ksoftirqd/020:34:360
269329910624253453,52789cyclictest0-21swapper20:16:100
269329910622753463,52764cyclictest0-21swapper20:14:200
269329910622153473,52748cyclictest0-21swapper20:21:020
269329910621753475,52742cyclictest0-21swapper19:59:060
269329910621453425,52789cyclictest0-21swapper20:43:080
269329910620753453,52718cyclictest0-21swapper21:02:540
269329910619653464,52732cyclictest0-21swapper22:06:220
269329910618053381,52784cyclictest31811-21ssh21:25:000
269329910595153411,52540cyclictest0-21swapper00:36:050
269329910514653050,52094cyclictest0-21swapper23:17:230
26932995396653377,499cyclictest0-21swapper23:13:110
26932995396453375,498cyclictest0-21swapper21:30:520
26932995359925,53474cyclictest1574-21ssh23:03:190
26932995353925,342cyclictest14049-21kworker/0:022:34:500
26932995351924,0cyclictest0-21swapper21:15:380
26932995347525,0cyclictest0-21swapper20:25:330
26932995334453276,45cyclictest7957-21ssh21:36:130
26932995322425,0cyclictest0-21swapper20:01:560
26932995309527,53068cyclictest0-21swapper19:30:470
26932995307128,53043cyclictest0-21swapper22:45:130
26932995278125,52756cyclictest0-21swapper20:39:370
26932995211010,52098cyclictest0-21swapper22:53:560
269329924071092,1220cyclictest3950irq/9-acpi23:39:090
269329922161019,1197cyclictest3357-21rm23:53:530
269329921381091,981cyclictest5350irq/9-uhci_hcd:22:39:420
269329920821035,1010cyclictest382-21ssh22:14:040
269329920811093,891cyclictest19956-21rm00:18:300
269329920721026,1011cyclictest0-21swapper20:51:510
269329920641003,1025cyclictest0-21swapper20:49:500
269329920451012,996cyclictest5483-21ssh23:09:100
269329920441002,1009cyclictest0-21swapper21:40:550
26932992033995,1017cyclictest0-21swapper23:45:310
26932992016979,1003cyclictest0-21swapper20:07:580
26932991999986,977cyclictest19540-21ssh21:54:290
269329919821014,846cyclictest0-21swapper23:26:550
269329919811029,859cyclictest0-21swapper19:54:540
26932991974952,988cyclictest0-21swapper19:36:490
269329919741102,805cyclictest3950irq/9-acpi22:40:520
269329919481023,904cyclictest0-21swapper00:07:070
269329919291036,772cyclictest0-21swapper21:13:470
26932991906914,969cyclictest0-21swapper00:14:590
269329918921078,691cyclictest8666-21ssh00:00:450
269329918741038,777cyclictest0-21swapper23:59:550
26932991840949,856cyclictest0-21swapper21:55:490
269329918041004,706cyclictest0-21swapper21:49:270
269329917791039,650cyclictest0-21swapper22:58:070
26932991739964,740cyclictest21666-21diskmemload22:19:260
269329917391090,649cyclictest0-21swapper21:27:010
269329916641051,613cyclictest0-21swapper23:33:170
269329916271038,497cyclictest0-21swapper19:24:250
26932991569988,547cyclictest3950irq/9-acpi23:43:200
26932991155623,529cyclictest12537-21wc19:18:240
26932991141616,522cyclictest7490-21hwlatdetect-tra19:11:020
26932991007909,79cyclictest0-21swapper20:57:220
2693299727614,110cyclictest27000-21hwlatdetect-tra19:10:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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