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2026-02-27 - 10:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6 (updated Fri Feb 27, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
305089910732353452,53774cyclictest2099-21runrttasks20:00:040
305089910692053430,53425cyclictest134850irq/9-eth000:07:050
305089910662553468,53094cyclictest30501-21cyclictest20:59:110
305089910662453421,53130cyclictest134850irq/9-eth022:34:090
305089910658753450,53073cyclictest9-21ksoftirqd/022:56:050
305089910657453443,53067cyclictest9-21ksoftirqd/023:32:150
305089910652053483,53037cyclictest0-21swapper21:56:280
305089910651453465,53049cyclictest0-21swapper00:36:440
305089910650353454,53049cyclictest0-21swapper19:32:060
305089910649053458,53032cyclictest0-21swapper00:11:270
305089910648753446,53041cyclictest0-21swapper00:32:430
305089910648253459,53023cyclictest0-21swapper21:12:050
305089910646753467,53000cyclictest0-21swapper22:06:510
305089910646553439,53026cyclictest0-21swapper22:23:050
305089910645553452,53003cyclictest0-21swapper00:26:310
305089910644253397,53045cyclictest0-21swapper20:15:390
305089910643553187,53238cyclictest0-21swapper23:59:230
305089910643153439,52992cyclictest0-21swapper21:20:070
305089910642553390,53035cyclictest0-21swapper21:48:050
305089910639253423,52955cyclictest30501-21cyclictest19:41:090
305089910631553452,52863cyclictest0-21swapper20:29:030
305089910630053428,52781cyclictest0-21swapper19:59:540
305089910623953481,52758cyclictest0-21swapper20:07:060
305089910623053436,52794cyclictest0-21swapper21:53:370
305089910621153451,52724cyclictest0-21swapper20:44:270
305089910618653415,52771cyclictest0-21swapper21:06:230
305089910615753446,52711cyclictest0-21swapper21:04:430
305089910614453393,52751cyclictest0-21swapper20:24:110
305089910613953035,53102cyclictest0-21swapper22:27:070
305089910580553287,52518cyclictest0-21swapper23:27:440
305089910568352986,52695cyclictest26570-21ssh22:35:390
30508995417031,54014cyclictest14209-21ssh22:18:340
30508995383329,53705cyclictest32179-21ssh00:18:490
30508995359426,53475cyclictest0-21swapper21:34:420
30508995353327,53414cyclictest0-21swapper20:14:180
30508995345927,384cyclictest0-21swapper21:29:200
30508995340727,53380cyclictest0-21swapper22:52:140
30508995309424,311cyclictest0-21swapper19:29:460
30508995308326,53057cyclictest0-21swapper22:46:320
30508995308024,53056cyclictest0-21swapper22:12:420
30508995304025,53015cyclictest0-21swapper20:32:040
30508995302727,52909cyclictest0-21swapper21:18:370
30508995292152899,21cyclictest0-21swapper23:39:380
305089924871095,1292cyclictest8676-21ssh23:44:590
305089923731087,1191cyclictest3950irq/9-acpi23:48:200
305089922741048,1156cyclictest134850irq/9-eth000:22:500
305089922341018,1216cyclictest18494-21ssh23:10:590
305089922251011,1214cyclictest2099-21runrttasks23:00:460
305089921401056,989cyclictest9-21ksoftirqd/023:17:410
30508992011993,980cyclictest16455-21ssh23:08:590
305089919591020,845cyclictest0-21swapper00:02:440
305089919571037,915cyclictest0-21swapper21:44:440
305089919501092,791cyclictest3950irq/9-acpi21:36:120
305089919441026,859cyclictest0-21swapper19:39:180
305089917561094,662cyclictest0-21swapper22:40:510
305089917501099,651cyclictest0-21swapper19:53:020
305089917321095,546cyclictest30501-21cyclictest20:35:240
305089916171096,425cyclictest4108-21ssh22:04:000
305089916051093,422cyclictest9-21ksoftirqd/020:51:290
305089915581053,462cyclictest9-21ksoftirqd/020:48:180
305089915421040,411cyclictest0-21swapper23:54:220
305089914791102,377cyclictest0-21swapper23:24:230
30508991453985,402cyclictest0-21swapper19:23:440
305089914511089,362cyclictest0-21swapper19:49:010
30508991141613,525cyclictest13105-21hwlatdetect-tra19:15:510
30508991077578,496cyclictest16444-21grep19:13:410
2119821910,2sleep021199-21hwlatdetect-tra19:05:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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