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2026-01-13 - 03:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Tue Jan 13, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
274289910663553468,53167cyclictest0-21swapper20:32:590
274289910656053395,53100cyclictest0-21swapper19:50:260
274289910655453465,53089cyclictest0-21swapper20:51:040
274289910653953455,53084cyclictest0-21swapper20:58:260
274289910651353460,53053cyclictest0-21swapper20:13:430
274289910651053473,53037cyclictest0-21swapper22:01:540
274289910649753471,53026cyclictest0-21swapper21:02:170
274289910649553466,53029cyclictest0-21swapper19:19:170
274289910647553429,53046cyclictest0-21swapper21:05:480
274289910646353453,53010cyclictest0-21swapper19:40:440
274289910645753444,53013cyclictest0-21swapper20:35:190
274289910644853447,53001cyclictest0-21swapper20:26:070
274289910643653397,53039cyclictest0-21swapper19:22:080
274289910643053473,52867cyclictest9-21ksoftirqd/021:21:330
274289910641653464,52888cyclictest9-21ksoftirqd/023:59:480
274289910640453421,52983cyclictest0-21swapper21:32:360
274289910622153477,52744cyclictest0-21swapper19:33:320
274289910619153462,52729cyclictest0-21swapper22:34:140
274289910618953458,52731cyclictest0-21swapper23:05:530
274289910618253458,52724cyclictest0-21swapper00:14:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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