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2026-01-24 - 19:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sat Jan 24, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
56399910701653432,53463cyclictest13952-21munin-node07:30:210
56399910694753475,53408cyclictest3950irq/9-acpi10:03:050
56399910673953395,53279cyclictest18245-21kworker/0:211:29:400
56399910673053472,53258cyclictest0-21swapper09:27:040
56399910670353462,53241cyclictest0-21swapper08:52:140
56399910669253390,53236cyclictest0-21swapper10:28:120
56399910663353425,53208cyclictest0-21swapper09:56:030
56399910656253430,53066cyclictest0-21swapper12:20:140
56399910654053475,53065cyclictest0-21swapper09:41:080
56399910652853444,53084cyclictest0-21swapper07:18:270
56399910651853476,53042cyclictest0-21swapper11:43:340
56399910650853429,53079cyclictest0-21swapper08:14:230
56399910650553474,53031cyclictest0-21swapper10:23:510
56399910645953447,53012cyclictest0-21swapper10:57:200
56399910643953442,52997cyclictest0-21swapper07:45:450
56399910643153439,52992cyclictest0-21swapper11:47:250
56399910632453416,52908cyclictest0-21swapper07:37:130
56399910626853394,52808cyclictest0-21swapper08:18:450
56399910624553472,52773cyclictest0-21swapper07:54:580
56399910621253472,52740cyclictest0-21swapper07:58:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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