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2026-02-14 - 10:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sat Feb 14, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
269459910701053469,53418cyclictest25395-21ssh00:26:590
269459910689453456,53374cyclictest26933-21cyclictest21:39:210
269459910676453419,53223cyclictest1741-21hald20:55:390
269459910674653396,53286cyclictest5350irq/9-uhci_hcd:23:03:150
269459910672953469,53196cyclictest26933-21cyclictest22:06:490
269459910661753451,53166cyclictest0-21swapper21:50:340
269459910656353402,53095cyclictest0-21swapper22:54:230
269459910656053421,53139cyclictest0-21swapper19:57:120
269459910654453428,53116cyclictest0-21swapper00:03:230
269459910650953473,53036cyclictest0-21swapper23:07:570
269459910650953473,53036cyclictest0-21swapper21:47:340
269459910650253466,53036cyclictest0-21swapper23:27:520
269459910647553459,53016cyclictest0-21swapper21:29:180
269459910647053450,53020cyclictest0-21swapper00:09:340
269459910645253484,52968cyclictest0-21swapper00:24:290
269459910645253464,52894cyclictest0-21swapper20:49:070
269459910643753440,52997cyclictest0-21swapper23:52:400
269459910643553435,53000cyclictest0-21swapper21:04:210
269459910641453428,52986cyclictest0-21swapper20:20:280
269459910637753474,52903cyclictest0-21swapper23:16:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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