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2026-01-24 - 00:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Fri Jan 23, 2026 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
187969910746753417,53927cyclictest6448-21ssh09:57:180
187969910691053400,53415cyclictest12295-21ssh11:43:490
187969910672853440,53288cyclictest0-21swapper08:45:270
187969910667253447,53225cyclictest0-21swapper07:36:380
187969910661853422,53196cyclictest0-21swapper09:52:070
187969910655853407,53151cyclictest0-21swapper08:41:160
187969910653053398,53132cyclictest0-21swapper10:58:560
187969910645953476,52894cyclictest9-21ksoftirqd/010:21:250
187969910645753448,53009cyclictest0-21swapper09:01:320
187969910639853476,52831cyclictest0-21swapper07:51:420
187969910633553405,52864cyclictest0-21swapper12:30:520
187969910626253467,52795cyclictest0-21swapper08:32:240
187969910625553462,52793cyclictest0-21swapper07:20:330
187969910622053476,52744cyclictest0-21swapper08:28:530
187969910621253469,52743cyclictest0-21swapper07:27:150
187969910617953453,52726cyclictest0-21swapper12:14:180
187969910616853401,52767cyclictest0-21swapper07:18:120
187969910616253403,52759cyclictest0-21swapper10:14:330
187969910615753400,52757cyclictest0-21swapper07:44:200
187969910615053399,52751cyclictest0-21swapper10:19:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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