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2026-01-21 - 08:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Wed Jan 21, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41109910750153478,53926cyclictest21413-21diskmemload22:22:180
41109910674653412,53243cyclictest0-21swapper00:03:280
41109910674053408,53241cyclictest0-21swapper21:53:100
41109910665053394,53166cyclictest0-21swapper23:59:360
41109910656853463,53039cyclictest0-21swapper19:47:140
41109910653953459,53049cyclictest28086-21kworker/0:220:19:530
41109910650353475,53028cyclictest0-21swapper21:13:490
41109910647353414,53059cyclictest0-21swapper23:17:040
41109910646953454,53015cyclictest0-21swapper22:25:090
41109910646453450,53014cyclictest0-21swapper22:10:050
41109910642653378,52983cyclictest11-21rcu_preempt23:49:030
41109910638753439,52883cyclictest0-21swapper20:28:560
41109910629453424,52804cyclictest9-21ksoftirqd/021:07:570
41109910624353456,52787cyclictest0-21swapper19:17:150
41109910622453476,52748cyclictest0-21swapper21:03:160
41109910621853401,52817cyclictest0-21swapper20:53:530
41109910621453469,52745cyclictest0-21swapper19:52:550
41109910620853449,52759cyclictest0-21swapper20:37:280
41109910619653460,52736cyclictest0-21swapper20:14:010
41109910619553460,52735cyclictest0-21swapper00:07:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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