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2026-01-16 - 09:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Fri Jan 16, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38409910721653417,53701cyclictest18869-21ssh00:13:160
38409910679153469,53322cyclictest0-21swapper21:53:560
38409910669753457,53240cyclictest0-21swapper22:30:370
38409910667053467,53112cyclictest9-21ksoftirqd/000:05:040
38409910665553469,53186cyclictest0-21swapper22:01:590
38409910662653476,53150cyclictest0-21swapper23:15:500
38409910660153476,53125cyclictest0-21swapper22:23:250
38409910659453406,53188cyclictest0-21swapper00:15:070
38409910649153469,53022cyclictest0-21swapper23:03:060
38409910647153446,53025cyclictest0-21swapper21:59:580
38409910645553461,52994cyclictest0-21swapper21:11:440
38409910644153475,52966cyclictest0-21swapper19:40:480
38409910643353438,52995cyclictest0-21swapper21:20:470
38409910642553445,52980cyclictest0-21swapper21:29:090
38409910642153388,53033cyclictest0-21swapper21:34:510
38409910623953378,52796cyclictest0-21swapper00:02:430
38409910623053393,52815cyclictest31880-21ssh22:11:010
38409910620253466,52736cyclictest0-21swapper19:20:320
38409910619953464,52735cyclictest0-21swapper21:06:030
38409910617153406,52765cyclictest0-21swapper20:56:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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