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2026-08-19 - 10:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Wed Aug 19, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
160089910665753414,53152cyclictest0-21swapper20:30:090
160089910647353428,53045cyclictest0-21swapper20:24:170
160089910644553398,53047cyclictest0-21swapper19:36:030
160089910642853436,52992cyclictest0-21swapper20:43:530
160089910641853415,52912cyclictest0-21swapper19:34:530
160089910640253475,52862cyclictest5350irq/9-uhci_hcd:00:11:520
160089910627053394,52811cyclictest0-21swapper21:03:480
160089910621953473,52746cyclictest0-21swapper20:04:210
160089910621453469,52745cyclictest0-21swapper20:28:480
160089910621053473,52737cyclictest0-21swapper20:57:360
160089910620753479,52728cyclictest0-21swapper19:56:190
160089910619653465,52731cyclictest0-21swapper20:15:540
160089910616653451,52715cyclictest0-21swapper22:25:320
160089910615853442,52716cyclictest0-21swapper21:06:390
160089910615753442,52715cyclictest0-21swapper23:19:270
160089910615153398,52753cyclictest0-21swapper19:46:060
160089910613153387,52744cyclictest0-21swapper19:10:060
160089910613053431,52699cyclictest0-21swapper21:16:220
160089910613053050,53078cyclictest0-21swapper23:51:270
160089910611553420,52695cyclictest0-21swapper19:18:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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