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2026-01-30 - 16:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Fri Jan 30, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
83739910680553353,53439cyclictest0-21swapper09:13:290
83739910677453467,53210cyclictest9-21ksoftirqd/010:10:460
83739910674153435,53183cyclictest1907-21snmpd09:40:570
83739910672253428,53294cyclictest0-21swapper11:46:230
83739910669453461,53233cyclictest0-21swapper07:50:250
83739910667153388,53219cyclictest9-21ksoftirqd/010:28:110
83739910666653447,53219cyclictest0-21swapper08:03:590
83739910666553448,53217cyclictest0-21swapper08:42:100
83739910663153469,53098cyclictest9-21ksoftirqd/010:40:440
83739910656553443,53059cyclictest134850irq/9-eth010:21:290
83739910652453426,53098cyclictest0-21swapper09:30:440
83739910651953474,53045cyclictest0-21swapper08:35:080
83739910647953471,53008cyclictest0-21swapper09:23:420
83739910646853451,53017cyclictest0-21swapper08:10:110
83739910645753406,53051cyclictest0-21swapper07:44:330
83739910642453431,52993cyclictest0-21swapper11:28:080
83739910642153422,52999cyclictest0-21swapper07:58:580
83739910641053466,52944cyclictest0-21swapper09:06:470
83739910639253403,52953cyclictest28132-21taskset10:47:160
83739910637853469,52845cyclictest9-21ksoftirqd/007:31:500
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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