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2026-02-02 - 20:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Mon Feb 02, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246669910713353413,53629cyclictest0-21swapper10:12:000
246669910699753466,53435cyclictest3429-21rtkit-daemon11:12:180
246669910667353402,53271cyclictest0-21swapper09:05:010
246669910664553433,53148cyclictest26586-21kworker/0:008:32:420
246669910663153413,53218cyclictest0-21swapper11:43:270
246669910659553397,53107cyclictest0-21swapper11:16:190
246669910654653403,53143cyclictest0-21swapper09:56:060
246669910654153450,53000cyclictest0-21swapper09:02:300
246669910649253469,53023cyclictest0-21swapper07:25:020
246669910649053466,53024cyclictest0-21swapper12:29:500
246669910647653461,53015cyclictest0-21swapper10:32:460
246669910647253414,53058cyclictest0-21swapper10:47:310
246669910646153422,53039cyclictest0-21swapper10:55:030
246669910646053468,52992cyclictest0-21swapper08:50:270
246669910646053449,53011cyclictest0-21swapper12:37:320
246669910644053438,53002cyclictest0-21swapper07:46:280
246669910642653432,52994cyclictest0-21swapper07:57:520
246669910638253399,52983cyclictest0-21swapper08:57:390
246669910628153386,52803cyclictest0-21swapper07:20:410
246669910623453462,52772cyclictest0-21swapper08:40:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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