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2026-02-10 - 07:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Tue Feb 10, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
56069910675753415,53251cyclictest0-21swapper19:10:090
56069910675053453,53297cyclictest0-21swapper22:27:460
56069910659553330,53230cyclictest2138-21sh22:13:520
56069910652353479,53044cyclictest0-21swapper00:34:420
56069910646953412,53057cyclictest0-21swapper22:18:430
56069910645453404,53050cyclictest0-21swapper22:03:090
56069910644153396,53045cyclictest0-21swapper20:40:250
56069910643953397,53042cyclictest0-21swapper19:29:140
56069910641553424,52991cyclictest0-21swapper22:23:350
56069910640053422,52978cyclictest0-21swapper00:25:100
56069910640053419,52981cyclictest0-21swapper00:38:240
56069910638953435,52954cyclictest0-21swapper21:03:320
56069910630653417,52889cyclictest0-21swapper22:53:430
56069910630253431,52805cyclictest0-21swapper20:57:000
56069910626253477,52785cyclictest0-21swapper19:39:370
56069910625953389,52805cyclictest0-21swapper21:28:190
56069910622453476,52748cyclictest0-21swapper19:58:330
56069910620153422,52779cyclictest0-21swapper21:51:150
56069910619653465,52731cyclictest0-21swapper19:24:530
56069910614953398,52751cyclictest0-21swapper00:20:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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