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2026-02-28 - 08:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sat Feb 28, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62109910681453403,53348cyclictest6203-21cyclictest23:07:130
62109910678653482,53240cyclictest2063649kworker/u2:100:00:280
62109910671553385,53235cyclictest0-21swapper21:14:510
62109910670053400,53237cyclictest9-21ksoftirqd/022:18:590
62109910669353439,53254cyclictest0-21swapper19:34:020
62109910665353416,53145cyclictest0-21swapper23:54:570
62109910659753468,53111cyclictest9-21ksoftirqd/022:33:330
62109910650953402,53107cyclictest0-21swapper00:11:320
62109910649953475,53024cyclictest0-21swapper22:23:100
62109910649953471,53028cyclictest0-21swapper21:21:020
62109910648253471,53011cyclictest0-21swapper20:05:310
62109910648153465,53016cyclictest0-21swapper00:24:350
62109910647553457,53018cyclictest0-21swapper22:13:580
62109910647253415,53057cyclictest0-21swapper21:03:070
62109910646153473,52896cyclictest0-21swapper20:57:360
62109910635253386,52877cyclictest10-21rcuc/022:26:310
62109910632953487,52751cyclictest0-21swapper20:02:000
62109910632653468,52744cyclictest0-21swapper23:10:340
62109910632453414,52817cyclictest0-21swapper21:19:220
62109910629653458,52719cyclictest0-21swapper23:40:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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