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2026-02-03 - 21:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Tue Feb 03, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
325089910668253426,53190cyclictest0-21swapper07:46:330
325089910667053445,53225cyclictest0-21swapper08:22:540
325089910662353470,53153cyclictest0-21swapper10:10:350
325089910656953471,53034cyclictest134850irq/9-eth012:16:110
325089910651753412,53039cyclictest0-21swapper09:50:090
325089910650153472,53029cyclictest0-21swapper12:23:530
325089910645253445,53007cyclictest0-21swapper10:00:520
325089910645153445,53006cyclictest0-21swapper09:37:250
325089910644253434,53008cyclictest0-21swapper09:30:130
325089910644153401,53040cyclictest0-21swapper11:12:330
325089910641753463,52891cyclictest9-21ksoftirqd/008:00:470
325089910641453426,52988cyclictest0-21swapper12:25:030
325089910636953469,52834cyclictest0-21swapper08:45:400
325089910631153477,52834cyclictest0-21swapper10:38:530
325089910622853423,52805cyclictest0-21swapper11:49:530
325089910622053415,52770cyclictest0-21swapper08:41:190
325089910619953468,52731cyclictest0-21swapper08:09:000
325089910618853461,52727cyclictest0-21swapper07:50:440
325089910618053454,52726cyclictest0-21swapper10:06:030
325089910616953450,52719cyclictest0-21swapper08:19:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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