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2026-01-29 - 15:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Thu Jan 29, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
302729910740853405,53907cyclictest1907-21snmpd07:55:120
302729910692253477,53348cyclictest28747-21ssh10:15:420
302729910680553413,53392cyclictest0-21swapper10:28:360
302729910674053466,53274cyclictest0-21swapper09:51:250
302729910668353390,53230cyclictest30217-21cyclictest09:42:430
302729910667353404,53269cyclictest0-21swapper12:29:010
302729910663953429,53210cyclictest0-21swapper07:38:070
302729910663053429,53201cyclictest0-21swapper12:13:060
302729910657753402,53175cyclictest0-21swapper09:48:040
302729910654453387,53092cyclictest0-21swapper12:20:080
302729910653853384,53088cyclictest0-21swapper11:27:030
302729910651053478,53032cyclictest0-21swapper08:07:150
302729910646453411,53053cyclictest0-21swapper09:22:570
302729910645253405,53047cyclictest0-21swapper07:30:550
302729910644053477,52963cyclictest0-21swapper11:39:160
302729910643553395,53040cyclictest0-21swapper12:39:540
302729910642853415,53013cyclictest0-21swapper08:58:100
302729910640953400,52944cyclictest5350irq/9-uhci_hcd:12:01:130
302729910630353410,52893cyclictest0-21swapper08:12:470
302729910622353476,52747cyclictest0-21swapper08:22:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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