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2026-02-19 - 16:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Thu Feb 19, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
315919910734853485,53800cyclictest31587-21cyclictest11:30:540
315919910715253444,53610cyclictest2099-21runrttasks08:05:050
315919910705953428,53535cyclictest18182-21ssh11:37:060
315919910675353419,53236cyclictest3950irq/9-acpi10:23:250
315919910671753454,53198cyclictest0-21swapper08:01:240
315919910659153423,53103cyclictest9-21ksoftirqd/010:19:430
315919910657653416,53097cyclictest9-21ksoftirqd/011:29:030
315919910655953394,53101cyclictest0-21swapper09:40:420
315919910653953384,53089cyclictest0-21swapper10:06:300
315919910651053474,53036cyclictest0-21swapper08:46:470
315919910650653475,53031cyclictest0-21swapper07:57:330
315919910650653472,53034cyclictest0-21swapper12:28:210
315919910649953468,53031cyclictest0-21swapper07:27:340
315919910647953462,53017cyclictest0-21swapper11:21:210
315919910647753463,53014cyclictest0-21swapper09:36:010
315919910646953452,53017cyclictest0-21swapper10:13:220
315919910646453453,53011cyclictest0-21swapper11:08:580
315919910645553469,52921cyclictest5350irq/9-uhci_hcd:10:26:350
315919910645153465,52986cyclictest0-21swapper07:33:160
315919910645153445,53006cyclictest0-21swapper09:03:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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