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2026-02-18 - 14:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Wed Feb 18, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
114879910671653435,53281cyclictest0-21swapper10:08:350
114879910667053474,53196cyclictest0-21swapper08:26:360
114879910661153414,53197cyclictest0-21swapper11:22:070
114879910660953477,53132cyclictest0-21swapper10:47:270
114879910660453417,53187cyclictest0-21swapper09:33:250
114879910658353428,53155cyclictest0-21swapper11:16:350
114879910658053406,53082cyclictest0-21swapper09:21:420
114879910657853422,53059cyclictest9-21ksoftirqd/010:19:390
114879910654753388,53092cyclictest0-21swapper12:30:260
114879910648553466,53019cyclictest0-21swapper11:28:490
114879910647353459,53014cyclictest0-21swapper09:37:160
114879910646853457,53011cyclictest0-21swapper11:13:440
114879910646853414,53054cyclictest0-21swapper07:59:480
114879910646153453,53008cyclictest0-21swapper09:56:020
114879910644453452,52992cyclictest0-21swapper11:57:570
114879910631153462,52737cyclictest0-21swapper08:07:310
114879910629053459,52751cyclictest0-21swapper07:15:260
114879910626953455,52727cyclictest0-21swapper12:28:160
114879910626653389,52813cyclictest0-21swapper08:42:210
114879910626053388,52808cyclictest9-21ksoftirqd/007:31:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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