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2026-01-22 - 20:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Thu Jan 22, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
56939910716553465,53545cyclictest22920-21diskmemload11:30:100
56939910661653477,53139cyclictest0-21swapper09:35:070
56939910659153427,53164cyclictest0-21swapper08:44:220
56939910654953443,53106cyclictest0-21swapper07:24:590
56939910654853421,53035cyclictest0-21swapper07:33:320
56939910650053468,53032cyclictest0-21swapper07:44:150
56939910649153465,53026cyclictest0-21swapper12:22:250
56939910647653417,53059cyclictest0-21swapper10:08:160
56939910647053456,53014cyclictest0-21swapper12:25:560
56939910645753447,53010cyclictest0-21swapper08:21:360
56939910645453404,53050cyclictest0-21swapper07:51:070
56939910645253445,53007cyclictest0-21swapper09:30:460
56939910643953448,52895cyclictest2099-21runrttasks07:13:260
56939910643053433,52997cyclictest0-21swapper09:06:490
56939910643053432,52998cyclictest0-21swapper12:19:140
56939910633553419,52826cyclictest9-21ksoftirqd/007:37:530
56939910631053457,52761cyclictest0-21swapper08:33:590
56939910625753386,52806cyclictest0-21swapper08:37:300
56939910625553386,52804cyclictest0-21swapper11:54:170
56939910620553473,52732cyclictest0-21swapper08:28:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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