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2026-02-25 - 16:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Wed Feb 25, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
243429910692953385,53479cyclictest9-21ksoftirqd/010:33:260
243429910689753420,53380cyclictest16469-21ssh10:55:530
243429910667253461,53129cyclictest0-21swapper07:58:120
243429910666153474,53096cyclictest0-21swapper07:52:300
243429910664053382,53167cyclictest9-21ksoftirqd/011:19:090
243429910660553480,53033cyclictest0-21swapper11:26:110
243429910658453451,53041cyclictest0-21swapper08:58:190
243429910657853420,53038cyclictest0-21swapper12:28:390
243429910655353388,53075cyclictest0-21swapper11:33:540
243429910655253390,53096cyclictest0-21swapper07:49:090
243429910653153402,53129cyclictest0-21swapper10:06:590
243429910652153478,53043cyclictest0-21swapper10:45:500
243429910651453476,53038cyclictest0-21swapper07:15:390
243429910650353470,53033cyclictest0-21swapper11:50:180
243429910649053468,53022cyclictest0-21swapper07:32:240
243429910647653459,53017cyclictest0-21swapper09:53:550
243429910647653456,53020cyclictest0-21swapper07:29:130
243429910647153472,52999cyclictest0-21swapper08:24:390
243429910647053413,53057cyclictest0-21swapper11:47:280
243429910646753447,53020cyclictest0-21swapper09:01:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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