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2026-02-26 - 17:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Thu Feb 26, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
253479910708853449,53543cyclictest9-21ksoftirqd/010:14:160
253479910705153477,53477cyclictest2099-21runrttasks12:06:180
253479910675953480,53279cyclictest0-21swapper11:03:300
253479910675153463,53225cyclictest9-21ksoftirqd/008:07:590
253479910671353389,53233cyclictest0-21swapper08:40:590
253479910668853479,53145cyclictest23603-21kworker/0:007:19:150
253479910659353467,53126cyclictest0-21swapper10:01:120
253479910658753423,53164cyclictest0-21swapper08:22:130
253479910655453402,53152cyclictest0-21swapper08:27:050
253479910650853433,53075cyclictest0-21swapper07:39:210
253479910647253457,53015cyclictest0-21swapper09:18:090
253479910647253415,53057cyclictest0-21swapper12:15:100
253479910645953472,52987cyclictest0-21swapper09:09:470
253479910641853432,52986cyclictest0-21swapper10:20:070
253479910639953422,52977cyclictest0-21swapper08:31:160
253479910635353455,52834cyclictest9-21ksoftirqd/008:14:410
253479910628653072,53204cyclictest0-21swapper10:05:530
253479910623453482,52752cyclictest0-21swapper08:59:240
253479910623153483,52748cyclictest0-21swapper10:18:570
253479910622053433,52787cyclictest0-21swapper09:03:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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