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2026-02-22 - 02:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sat Feb 21, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
293879910730253396,53786cyclictest2099-21runrttasks11:59:220
293879910697753425,53459cyclictest0-21swapper09:41:220
293879910680453467,53245cyclictest9-21ksoftirqd/007:33:350
293879910678153382,53386cyclictest0-21swapper12:39:130
293879910663953389,53159cyclictest0-21swapper08:39:440
293879910663553425,53210cyclictest0-21swapper07:46:390
293879910658053447,53133cyclictest0-21swapper11:33:340
293879910650853403,53105cyclictest0-21swapper08:54:490
293879910648353464,53019cyclictest0-21swapper11:19:200
293879910648253460,53022cyclictest0-21swapper10:03:180
293879910647653472,52938cyclictest134850irq/9-eth011:48:490
293879910647653466,53010cyclictest0-21swapper09:21:060
293879910647553460,53015cyclictest0-21swapper08:01:230
293879910646753413,53054cyclictest0-21swapper10:39:190
293879910645153480,52971cyclictest0-21swapper12:24:590
293879910645153452,52999cyclictest0-21swapper10:43:200
293879910644653441,53005cyclictest0-21swapper09:28:080
293879910644353399,53044cyclictest0-21swapper11:09:170
293879910631553399,52852cyclictest9-21ksoftirqd/007:50:500
293879910626353390,52807cyclictest0-21swapper10:54:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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