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2026-03-10 - 22:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Tue Mar 10, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
117049910718153476,53609cyclictest17004-21ssh12:04:150
117049910711153443,53571cyclictest11361-21rm09:30:310
117049910684153456,53295cyclictest11685-21cyclictest07:43:400
117049910680453408,53305cyclictest9-21ksoftirqd/007:56:340
117049910669553454,53241cyclictest0-21swapper07:45:000
117049910667453390,53192cyclictest0-21swapper08:48:090
117049910667253435,53146cyclictest9-21ksoftirqd/012:15:080
117049910663853436,53138cyclictest9-21ksoftirqd/011:27:140
117049910659453406,53098cyclictest9-21ksoftirqd/010:18:250
117049910656053450,53110cyclictest0-21swapper07:10:400
117049910652253470,53052cyclictest0-21swapper11:18:220
117049910649653472,53024cyclictest0-21swapper07:38:180
117049910648853462,53026cyclictest0-21swapper09:44:050
117049910647853462,53016cyclictest0-21swapper09:24:390
117049910647753454,53023cyclictest0-21swapper07:34:570
117049910647153468,53003cyclictest0-21swapper10:00:500
117049910646553468,52997cyclictest0-21swapper09:14:260
117049910645153474,52912cyclictest27986-21rm11:31:360
117049910644953442,53007cyclictest0-21swapper08:06:060
117049910642753390,53037cyclictest0-21swapper10:24:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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