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2026-08-31 - 15:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Mon Aug 31, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17179910676853430,53275cyclictest134850irq/9-eth010:09:540
17179910667753484,53071cyclictest28847-21ssh10:10:440
17179910667453470,53140cyclictest134850irq/9-eth008:51:310
17179910666653386,53189cyclictest0-21swapper07:37:500
17179910656953381,53098cyclictest9-21ksoftirqd/009:48:280
17179910655553433,53122cyclictest0-21swapper07:18:450
17179910654153403,53138cyclictest0-21swapper12:38:270
17179910651053429,53081cyclictest0-21swapper10:16:260
17179910649953472,53027cyclictest0-21swapper10:39:430
17179910649453466,53028cyclictest0-21swapper09:34:240
17179910648453460,53024cyclictest0-21swapper09:57:200
17179910648453459,52932cyclictest1907-21snmpd07:52:140
17179910646753438,53029cyclictest0-21swapper11:07:510
17179910646353446,53017cyclictest0-21swapper12:26:130
17179910642553435,52990cyclictest0-21swapper08:30:050
17179910640353419,52984cyclictest0-21swapper09:24:110
17179910639653401,52995cyclictest0-21swapper10:00:010
17179910629353386,52814cyclictest0-21swapper07:31:180
17179910626253387,52810cyclictest0-21swapper08:17:420
17179910623353452,52781cyclictest0-21swapper07:27:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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