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2026-03-16 - 04:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Mon Mar 16, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
142919910686453431,53336cyclictest9-21ksoftirqd/021:22:400
142919910666153477,53184cyclictest0-21swapper20:35:060
142919910664253469,53173cyclictest0-21swapper21:03:040
142919910662253479,53052cyclictest9-21ksoftirqd/021:46:370
142919910658353477,53043cyclictest9-21ksoftirqd/020:55:020
142919910651953482,53037cyclictest0-21swapper22:00:010
142919910648653420,53066cyclictest0-21swapper21:40:050
142919910648453473,53011cyclictest0-21swapper21:38:550
142919910647853461,53017cyclictest0-21swapper21:58:400
142919910646753410,53057cyclictest0-21swapper22:48:050
142919910646653411,53055cyclictest0-21swapper20:07:480
142919910643853396,53042cyclictest0-21swapper19:51:340
142919910642053413,52918cyclictest10-21rcuc/021:52:490
142919910639953427,52972cyclictest0-21swapper00:29:540
142919910638653388,52935cyclictest9-21ksoftirqd/019:31:280
142919910633653480,52795cyclictest14281-21cyclictest20:24:530
142919910632653480,52846cyclictest0-21swapper22:53:260
142919910626853449,52708cyclictest0-21swapper23:59:550
142919910626553449,52707cyclictest0-21swapper20:53:520
142919910623153483,52748cyclictest0-21swapper19:35:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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