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2026-01-19 - 23:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Mon Jan 19, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
188859910671853436,53282cyclictest0-21swapper11:36:070
188859910667253440,53232cyclictest0-21swapper09:49:070
188859910662553465,53160cyclictest0-21swapper11:45:000
188859910651153473,53038cyclictest0-21swapper10:04:410
188859910651053473,53037cyclictest0-21swapper08:35:350
188859910649453447,53047cyclictest0-21swapper07:51:330
188859910648653463,53023cyclictest0-21swapper07:55:240
188859910648353450,53033cyclictest0-21swapper07:22:340
188859910647953418,53061cyclictest0-21swapper07:31:170
188859910647653289,53172cyclictest3888-21diskmemload10:25:570
188859910646753411,53056cyclictest0-21swapper08:46:290
188859910646353435,53028cyclictest0-21swapper07:10:410
188859910641553428,52987cyclictest0-21swapper10:48:140
188859910640153475,52926cyclictest0-21swapper08:21:520
188859910631753404,52821cyclictest0-21swapper08:17:400
188859910629753394,52811cyclictest0-21swapper07:29:570
188859910623153467,52764cyclictest0-21swapper12:25:020
188859910621353476,52737cyclictest0-21swapper08:53:510
188859910621253473,52739cyclictest0-21swapper11:56:330
188859910620753465,52742cyclictest0-21swapper11:31:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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