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2026-01-23 - 03:02
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Fri Jan 23, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2048699210761105294,105462cyclictest0-21swapper22:59:390
2048699210688105346,105339cyclictest2099-21runrttasks21:15:090
204869910721053470,53650cyclictest5350irq/9-uhci_hcd:21:49:080
204869910673853400,53249cyclictest16233-21kworker/0:100:27:340
204869910657053452,53118cyclictest0-21swapper22:45:350
204869910654153435,53106cyclictest0-21swapper20:30:060
204869910651053428,53082cyclictest0-21swapper23:02:500
204869910650553471,53034cyclictest0-21swapper21:30:530
204869910650353470,53033cyclictest0-21swapper22:43:040
204869910649853472,53026cyclictest0-21swapper23:33:280
204869910648253463,53019cyclictest0-21swapper19:30:180
204869910647153454,53017cyclictest0-21swapper00:33:060
204869910644653400,53046cyclictest0-21swapper20:59:440
204869910644053434,53006cyclictest0-21swapper22:51:260
204869910643853442,52996cyclictest0-21swapper00:20:520
204869910640653427,52979cyclictest0-21swapper23:13:130
204869910635353390,52897cyclictest0-21swapper21:39:050
204869910633353441,52892cyclictest0-21swapper20:46:000
204869910633353417,52916cyclictest0-21swapper23:07:010
204869910630053409,52828cyclictest20479-21cyclictest20:43:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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