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2025-11-18 - 23:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Tue Nov 18, 2025 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19699910712653412,53623cyclictest0-21swapper08:56:510
19699910705453449,53508cyclictest1911-21snmpd07:56:240
19699910672053436,53284cyclictest0-21swapper10:09:020
19699910664653456,53127cyclictest3950irq/9-acpi10:23:160
19699910661253478,53134cyclictest0-21swapper08:54:410
19699910660753428,53113cyclictest0-21swapper12:36:450
19699910659653409,53095cyclictest9-21ksoftirqd/011:24:240
19699910653753469,53068cyclictest0-21swapper11:54:530
19699910652653465,53061cyclictest0-21swapper09:03:330
19699910652253448,53074cyclictest0-21swapper07:26:250
19699910651453476,53038cyclictest0-21swapper12:03:350
19699910650853391,53021cyclictest2103-21runrttasks08:11:180
19699910650153468,53033cyclictest0-21swapper10:18:150
19699910648453459,53025cyclictest0-21swapper10:44:120
19699910647753452,53025cyclictest0-21swapper11:43:190
19699910647753414,53063cyclictest0-21swapper10:56:260
19699910645753446,53011cyclictest0-21swapper08:16:100
19699910643253393,53039cyclictest0-21swapper09:05:440
19699910641953452,52904cyclictest1968-21cyclictest08:29:240
19699910638353430,52858cyclictest19197-21diskmemload09:48:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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