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2026-02-22 - 14:46
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sun Feb 22, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32329910742553406,53923cyclictest2790-21gnome-settings-10:33:220
32329910717753467,53587cyclictest29444-21ssh10:55:380
32329910695753445,53422cyclictest2650-21kworker/0:011:53:350
32329910680653466,53340cyclictest0-21swapper12:28:450
32329910673553474,53261cyclictest0-21swapper12:13:110
32329910673453389,53250cyclictest731-21ssh11:01:200
32329910655853452,53106cyclictest0-21swapper09:24:520
32329910650653430,53076cyclictest0-21swapper10:14:060
32329910648453465,53019cyclictest0-21swapper09:11:480
32329910647853414,53064cyclictest0-21swapper10:53:180
32329910647153462,53009cyclictest0-21swapper10:00:520
32329910645953442,53017cyclictest0-21swapper12:19:320
32329910645053403,53047cyclictest0-21swapper10:15:570
32329910641653428,52923cyclictest3950irq/9-acpi10:20:480
32329910639953418,52981cyclictest0-21swapper08:31:370
32329910639053430,52960cyclictest0-21swapper08:08:000
32329910638353477,52842cyclictest0-21swapper07:14:350
32329910638253392,52990cyclictest0-21swapper11:39:310
32329910626453390,52809cyclictest0-21swapper10:05:040
32329910626353392,52805cyclictest0-21swapper07:57:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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