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2026-03-08 - 11:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sun Mar 08, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
60139910686953405,53369cyclictest2099-21runrttasks20:16:320
60139910662253425,53105cyclictest0-21swapper20:40:090
60139910656353458,53105cyclictest0-21swapper21:18:100
60139910654553387,53093cyclictest0-21swapper22:23:090
60139910653753446,53091cyclictest0-21swapper22:10:450
60139910649653421,53075cyclictest0-21swapper22:07:140
60139910649253431,53061cyclictest0-21swapper19:52:150
60139910647953388,53091cyclictest0-21swapper19:22:170
60139910647553456,53019cyclictest0-21swapper23:39:410
60139910646453471,52993cyclictest0-21swapper21:36:150
60139910645953409,53050cyclictest0-21swapper21:45:280
60139910643953443,52996cyclictest0-21swapper00:15:410
60139910643653397,53039cyclictest0-21swapper23:41:010
60139910643253434,52998cyclictest0-21swapper20:20:030
60139910642253391,53031cyclictest0-21swapper22:29:310
60139910634553426,52919cyclictest0-21swapper19:34:000
60139910630253471,52831cyclictest0-21swapper22:58:590
60139910630153414,52822cyclictest9-21ksoftirqd/020:50:320
60139910625353412,52750cyclictest0-21swapper19:47:540
60139910625253387,52801cyclictest0-21swapper21:06:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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