You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-21 - 04:31
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Fri Nov 21, 2025 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
16779910698253456,53526cyclictest0-21swapper19:58:120
16779910670653408,53275cyclictest24131-21sh21:31:190
16779910665553392,53198cyclictest0-21swapper19:39:560
16779910664153389,53187cyclictest0-21swapper22:34:470
16779910657553410,53165cyclictest0-21swapper20:49:260
16779910648353460,53023cyclictest0-21swapper20:38:330
16779910645353395,53058cyclictest0-21swapper21:50:540
16779910641953455,52964cyclictest0-21swapper21:14:240
16779910640153419,52982cyclictest0-21swapper22:08:490
16779910629353394,52807cyclictest0-21swapper20:09:150
16779910627153388,52819cyclictest0-21swapper19:45:580
16779910621653455,52761cyclictest0-21swapper19:40:070
16779910619653466,52730cyclictest0-21swapper20:29:410
16779910618453413,52771cyclictest0-21swapper20:04:440
16779910613253458,52674cyclictest0-21swapper22:35:070
16779910611753344,52773cyclictest0-21swapper22:47:410
16779910611053416,52694cyclictest0-21swapper22:55:030
16779910579053246,52544cyclictest0-21swapper21:16:040
16779910520353080,52121cyclictest0-21swapper21:47:330
16779910503952940,52094cyclictest0-21swapper22:53:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional