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2026-02-17 - 14:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Tue Feb 17, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32509910739753448,53826cyclictest25898-21ssh09:17:060
32509910723053468,53671cyclictest18299-21ssh09:54:470
32509910706753455,53515cyclictest6140-21ssh10:24:450
32509910697753426,53486cyclictest9-21ksoftirqd/012:01:030
32509910688153462,53321cyclictest2099-21runrttasks08:31:330
32509910676553446,53227cyclictest134850irq/9-eth009:32:500
32509910667953427,53160cyclictest0-21swapper08:28:120
32509910660253405,53103cyclictest0-21swapper08:53:590
32509910660253402,53136cyclictest9-21ksoftirqd/011:40:570
32509910651053475,53035cyclictest0-21swapper10:18:440
32509910650353474,53029cyclictest0-21swapper11:39:570
32509910648653458,53028cyclictest0-21swapper10:58:150
32509910648053467,53013cyclictest0-21swapper11:04:070
32509910647753411,52973cyclictest0-21swapper07:14:000
32509910646053407,53053cyclictest0-21swapper07:37:270
32509910645753407,53050cyclictest0-21swapper08:42:060
32509910645753405,53052cyclictest0-21swapper10:09:310
32509910644653441,53005cyclictest0-21swapper11:28:440
32509910644053437,52937cyclictest0-21swapper09:08:430
32509910643453391,53043cyclictest0-21swapper09:24:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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