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2026-01-15 - 08:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Thu Jan 15, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
220879910671353449,53264cyclictest0-21swapper00:24:450
220879910667153468,53113cyclictest9-21ksoftirqd/023:53:060
220879910665253452,53200cyclictest0-21swapper00:04:090
220879910661753419,53198cyclictest0-21swapper22:04:450
220879910659153422,53169cyclictest0-21swapper21:28:340
220879910654553400,53145cyclictest0-21swapper21:38:370
220879910652653472,53054cyclictest0-21swapper00:28:560
220879910651553479,53036cyclictest0-21swapper21:41:480
220879910650253467,53035cyclictest0-21swapper22:05:350
220879910648753461,53026cyclictest0-21swapper22:20:090
220879910648553466,53019cyclictest0-21swapper22:12:270
220879910647553462,53013cyclictest0-21swapper21:19:520
220879910645253449,53003cyclictest0-21swapper20:38:100
220879910644253429,53013cyclictest0-21swapper22:37:040
220879910637553438,52937cyclictest0-21swapper19:58:380
220879910632553400,52834cyclictest0-21swapper19:45:040
220879910621853472,52746cyclictest0-21swapper19:43:040
220879910620053454,52746cyclictest0-21swapper21:05:480
220879910618053457,52723cyclictest0-21swapper19:37:220
220879910611353421,52692cyclictest0-21swapper23:39:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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