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2026-02-01 - 06:48
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sun Feb 01, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
241629910661753419,53131cyclictest0-21swapper00:18:550
241629910649353467,53026cyclictest0-21swapper21:57:240
241629910647253400,53072cyclictest0-21swapper22:55:110
241629910645853448,53010cyclictest0-21swapper21:11:510
241629910645653409,52957cyclictest134850irq/9-eth000:31:180
241629910645053443,53007cyclictest0-21swapper21:09:200
241629910642253431,52991cyclictest0-21swapper23:17:370
241629910640453421,52983cyclictest0-21swapper19:32:420
241629910629853426,52808cyclictest9-21ksoftirqd/020:36:110
241629910626653423,52750cyclictest0-21swapper20:43:230
241629910623253417,52751cyclictest0-21swapper20:11:430
241629910622353458,52765cyclictest0-21swapper19:49:170
241629910620153459,52742cyclictest0-21swapper20:28:280
241629910618353401,52782cyclictest0-21swapper20:32:500
241629910617253453,52719cyclictest0-21swapper19:56:190
241629910615853445,52713cyclictest0-21swapper20:21:260
241629910613153388,52743cyclictest0-21swapper00:02:200
241629910608253001,53079cyclictest0-21swapper22:39:460
241629910520653080,52124cyclictest0-21swapper23:12:150
241629910519753085,52110cyclictest0-21swapper19:42:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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