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2026-03-01 - 18:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sun Mar 01, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6569910697053429,53449cyclictest9-21ksoftirqd/012:24:380
6569910683053387,53354cyclictest245172sleep010:49:500
6569910682353421,53305cyclictest17989-21diskmemload12:01:310
6569910666653392,53210cyclictest134850irq/9-eth008:15:560
6569910654853389,53068cyclictest0-21swapper08:07:230
6569910654053385,53090cyclictest0-21swapper10:59:430
6569910649053462,53028cyclictest0-21swapper11:57:400
6569910646253465,52997cyclictest0-21swapper07:24:210
6569910643353436,52997cyclictest0-21swapper08:38:320
6569910643153435,52996cyclictest0-21swapper08:27:490
6569910642853431,52997cyclictest0-21swapper12:19:360
6569910634253461,52881cyclictest0-21swapper07:28:020
6569910632053434,52821cyclictest0-21swapper08:53:270
6569910631453411,52841cyclictest9-21ksoftirqd/008:56:580
6569910625153440,52811cyclictest0-21swapper12:09:230
6569910623653436,52800cyclictest0-21swapper09:45:020
6569910622353475,52748cyclictest0-21swapper08:12:550
6569910621253472,52740cyclictest0-21swapper08:32:510
6569910620553466,52739cyclictest0-21swapper07:43:170
6569910619453459,52735cyclictest0-21swapper07:54:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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