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2026-02-11 - 07:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Wed Feb 11, 2026 00:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
178409910659253473,53119cyclictest0-21swapper22:10:560
178409910644653401,53045cyclictest0-21swapper20:45:510
178409910638453400,52984cyclictest0-21swapper19:47:550
178409910621753476,52741cyclictest0-21swapper20:28:060
178409910614453060,53082cyclictest0-21swapper22:45:260
178409910614153057,53082cyclictest0-21swapper19:57:070
178409910611553053,53060cyclictest0-21swapper22:36:130
178409910611353034,53077cyclictest0-21swapper00:28:150
178409910609753003,53092cyclictest0-21swapper21:19:510
178409910604352945,53096cyclictest0-21swapper21:38:060
178409910603852959,53077cyclictest0-21swapper23:54:460
178409910601653000,53014cyclictest16577-21ssh21:32:550
178409910600952929,53078cyclictest21851-21kworker/0:219:26:390
178409910547553189,52276cyclictest0-21swapper21:28:040
178409910516453059,52103cyclictest0-21swapper23:07:020
178409910515553050,52100cyclictest0-21swapper21:57:120
178409910515153044,52105cyclictest0-21swapper22:55:490
178409910513352976,52154cyclictest25449-21ssh22:30:110
178409910512953029,52098cyclictest0-21swapper19:36:310
178409910511953022,52095cyclictest0-21swapper00:01:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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