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2026-02-15 - 23:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sun Feb 15, 2026 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3239899209926105452,104472cyclictest0-21swapper08:13:590
3239899209883105409,104472cyclictest0-21swapper07:26:450
3239899209816105328,104486cyclictest0-21swapper08:49:090
3239899209804105330,104472cyclictest0-21swapper12:09:070
323989910612653052,53072cyclictest0-21swapper12:19:090
323989910611753031,53084cyclictest0-21swapper08:28:230
323989910609553018,53075cyclictest0-21swapper08:33:340
323989910606952979,53088cyclictest0-21swapper10:06:010
323989910604252968,53072cyclictest0-21swapper08:16:190
323989910602652946,53078cyclictest0-21swapper08:08:270
323989910600452911,53087cyclictest0-21swapper12:39:350
323989910600252911,53089cyclictest0-21swapper11:12:400
323989910599252917,53073cyclictest0-21swapper07:21:040
323989910592152969,52950cyclictest30761-21ssh10:12:230
323989910573453068,52663cyclictest12425-21ssh10:31:380
323989910547653041,52432cyclictest19909-21seq09:12:260
323989910545552932,52521cyclictest8953-21ssh11:56:430
323989910542452920,52501cyclictest6785-21ssh11:09:490
323989910529252977,52312cyclictest17573-21diskmemload09:47:260
323989910515353046,52105cyclictest0-21swapper07:17:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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