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2026-02-05 - 12:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Thu Feb 05, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2769299210831105361,105468cyclictest0-21swapper23:13:150
276929910665953382,53186cyclictest0-21swapper22:20:200
276929910654753386,53096cyclictest0-21swapper23:28:390
276929910651053473,53037cyclictest0-21swapper22:46:470
276929910645053403,53047cyclictest0-21swapper21:24:240
276929910639853472,52835cyclictest0-21swapper22:03:450
276929910639553451,52944cyclictest0-21swapper23:20:470
276929910639053449,52941cyclictest0-21swapper19:46:350
276929910634953428,52921cyclictest0-21swapper20:56:250
276929910634653461,52820cyclictest9-21ksoftirqd/020:07:410
276929910624953385,52799cyclictest0-21swapper21:06:590
276929910623753442,52795cyclictest0-21swapper21:03:170
276929910621553412,52766cyclictest0-21swapper21:41:180
276929910620553466,52739cyclictest0-21swapper00:16:230
276929910557353017,52550cyclictest19345-21ssh22:14:280
276929910500352918,52083cyclictest0-21swapper19:57:490
2769299531258,9cyclictest0-21swapper21:59:540
27692995278127,52754cyclictest0-21swapper19:27:000
276929924991077,1300cyclictest17987-21rm00:32:180
276929924781081,1273cyclictest14546-21ssh22:54:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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