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2026-02-27 - 07:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Fri Feb 27, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
305089910732353452,53774cyclictest2099-21runrttasks20:00:040
305089910692053430,53425cyclictest134850irq/9-eth000:07:050
305089910662553468,53094cyclictest30501-21cyclictest20:59:110
305089910662453421,53130cyclictest134850irq/9-eth022:34:090
305089910658753450,53073cyclictest9-21ksoftirqd/022:56:050
305089910657453443,53067cyclictest9-21ksoftirqd/023:32:150
305089910652053483,53037cyclictest0-21swapper21:56:280
305089910651453465,53049cyclictest0-21swapper00:36:440
305089910650353454,53049cyclictest0-21swapper19:32:060
305089910649053458,53032cyclictest0-21swapper00:11:270
305089910648753446,53041cyclictest0-21swapper00:32:430
305089910648253459,53023cyclictest0-21swapper21:12:050
305089910646753467,53000cyclictest0-21swapper22:06:510
305089910646553439,53026cyclictest0-21swapper22:23:050
305089910645553452,53003cyclictest0-21swapper00:26:310
305089910644253397,53045cyclictest0-21swapper20:15:390
305089910643553187,53238cyclictest0-21swapper23:59:230
305089910643153439,52992cyclictest0-21swapper21:20:070
305089910642553390,53035cyclictest0-21swapper21:48:050
305089910639253423,52955cyclictest30501-21cyclictest19:41:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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