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2026-01-20 - 19:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Tue Jan 20, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122029910708753482,53541cyclictest12193-21cyclictest09:16:520
122029910684153451,53294cyclictest25471-21ssh10:32:240
122029910677053473,53233cyclictest12193-21cyclictest08:05:520
122029910676053414,53346cyclictest0-21swapper09:12:210
122029910675253453,53299cyclictest0-21swapper12:11:120
122029910670953430,53279cyclictest0-21swapper08:53:050
122029910667653422,53188cyclictest0-21swapper10:50:090
122029910665653422,53234cyclictest0-21swapper11:29:300
122029910650453473,53031cyclictest0-21swapper08:30:390
122029910649753413,53084cyclictest0-21swapper09:41:290
122029910648253464,53018cyclictest0-21swapper07:56:590
122029910648253461,53021cyclictest0-21swapper09:24:440
122029910647853403,53075cyclictest0-21swapper09:47:510
122029910647553398,53077cyclictest0-21swapper11:15:360
122029910647453458,53016cyclictest0-21swapper10:15:390
122029910647153453,53018cyclictest0-21swapper10:01:350
122029910646453474,52990cyclictest0-21swapper07:39:340
122029910644953452,52997cyclictest0-21swapper11:35:420
122029910644553442,53003cyclictest0-21swapper11:50:060
122029910635453471,52883cyclictest0-21swapper07:28:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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