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2026-03-02 - 21:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Mon Mar 02, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3223099209812105330,104480cyclictest0-21swapper10:19:460
322309910726653481,53686cyclictest17046-21diskmemload10:41:530
322309910692553373,53532cyclictest0-21swapper09:10:160
322309910667953373,53281cyclictest19284-21ssh11:36:490
322309910666153435,53226cyclictest0-21swapper08:15:000
322309910664853448,53200cyclictest0-21swapper09:25:010
322309910656453384,53086cyclictest0-21swapper09:49:480
322309910655953395,53099cyclictest0-21swapper07:15:530
322309910653653411,53125cyclictest0-21swapper08:41:580
322309910650353471,53032cyclictest0-21swapper09:20:290
322309910647853459,53019cyclictest0-21swapper12:04:170
322309910645853476,52982cyclictest0-21swapper11:43:410
322309910645853453,53005cyclictest0-21swapper12:38:060
322309910645553404,53051cyclictest0-21swapper10:51:260
322309910643853397,53041cyclictest0-21swapper08:12:500
322309910642753451,52976cyclictest0-21swapper10:03:320
322309910641853426,52992cyclictest0-21swapper11:51:530
322309910640453422,52982cyclictest0-21swapper10:28:190
322309910630553424,52816cyclictest0-21swapper08:07:480
322309910623953298,52929cyclictest3950irq/9-acpi09:35:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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