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2026-01-16 - 16:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Fri Jan 16, 2026 12:43:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
320169910722053478,53742cyclictest0-21swapper10:39:070
320169910673353474,53192cyclictest0-21swapper11:27:210
320169910670553443,53262cyclictest0-21swapper11:49:370
320169910668753429,53193cyclictest9-21ksoftirqd/011:32:520
320169910665353476,53177cyclictest0-21swapper10:27:530
320169910663753467,53170cyclictest0-21swapper08:46:540
320169910663653470,53166cyclictest0-21swapper11:08:150
320169910658353463,53120cyclictest0-21swapper12:29:590
320169910657053473,53006cyclictest0-21swapper12:24:070
320169910651953391,53035cyclictest0-21swapper08:17:060
320169910651353415,53033cyclictest0-21swapper07:56:200
320169910651053470,53040cyclictest0-21swapper10:21:120
320169910647153412,53059cyclictest0-21swapper10:59:330
320169910646353411,53052cyclictest0-21swapper11:03:240
320169910645153428,53023cyclictest0-21swapper08:32:100
320169910644753451,52996cyclictest0-21swapper08:12:040
320169910643453442,52992cyclictest0-21swapper09:28:460
320169910643353393,53040cyclictest0-21swapper12:39:520
320169910642453431,52993cyclictest0-21swapper07:26:510
320169910641953431,52988cyclictest0-21swapper09:17:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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