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2026-01-20 - 12:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Tue Jan 20, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
256419910729553456,53743cyclictest30601-21ssh00:05:330
256419910699253466,53430cyclictest31211-21runrttasks21:08:520
256419910681953396,53359cyclictest9-21ksoftirqd/020:51:580
256419910670153455,53246cyclictest0-21swapper23:37:250
256419910668253461,53130cyclictest6210-1kworker/u3:022:49:110
256419910662053419,53201cyclictest0-21swapper22:05:390
256419910649853470,53028cyclictest0-21swapper21:55:360
256419910646153466,52995cyclictest0-21swapper19:53:010
256419910644753412,52971cyclictest9-21ksoftirqd/019:41:570
256419910644353444,52999cyclictest0-21swapper19:56:220
256419910642753432,52995cyclictest0-21swapper22:22:440
256419910642253404,53018cyclictest0-21swapper20:27:510
256419910640853455,52953cyclictest0-21swapper23:21:010
256419910636153405,52864cyclictest0-21swapper19:48:590
256419910634253424,52918cyclictest0-21swapper20:37:330
256419910620853468,52740cyclictest0-21swapper22:01:580
256419910619953460,52739cyclictest0-21swapper20:43:350
256419910619253458,52734cyclictest0-21swapper19:38:160
256419910618653414,52772cyclictest0-21swapper19:32:350
256419910618453454,52730cyclictest0-21swapper19:28:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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