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2026-02-24 - 03:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Tue Feb 24, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318659910725053420,53740cyclictest16896-21rm00:20:550
318659910719853432,53669cyclictest1828-21hald-addon-acpi20:02:100
318659910696553420,53453cyclictest0-21swapper20:50:240
318659910689553405,53490cyclictest0-21swapper21:43:500
318659910678053439,53277cyclictest134850irq/9-eth023:21:180
318659910676153413,53226cyclictest22682-21ssh21:23:540
318659910667753418,53194cyclictest134850irq/9-eth023:12:050
318659910666253413,53186cyclictest3950irq/9-acpi22:33:040
318659910665753446,53211cyclictest0-21swapper21:53:120
318659910659753411,53186cyclictest0-21swapper20:26:480
318659910652353441,53082cyclictest0-21swapper22:48:080
318659910652153477,53044cyclictest0-21swapper21:14:010
318659910651053478,53032cyclictest0-21swapper21:17:420
318659910646953473,52996cyclictest0-21swapper22:06:260
318659910646053464,52996cyclictest0-21swapper00:03:500
318659910645753393,53000cyclictest10-21rcuc/019:24:400
318659910642453457,52967cyclictest0-21swapper19:31:010
318659910624853383,52800cyclictest0-21swapper00:38:100
318659910623753387,52807cyclictest0-21swapper21:07:190
318659910618853417,52771cyclictest0-21swapper20:49:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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