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2026-03-05 - 01:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Wed Mar 04, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
50369910690153443,53368cyclictest462-21rm10:14:040
50369910672353398,53325cyclictest0-21swapper08:53:010
50369910670853430,53278cyclictest0-21swapper07:14:330
50369910664853463,53121cyclictest5350irq/9-uhci_hcd:10:41:020
50369910658953394,53103cyclictest0-21swapper10:33:300
50369910655353388,53101cyclictest9-21ksoftirqd/012:21:110
50369910655253454,53098cyclictest0-21swapper08:19:010
50369910655153390,53096cyclictest0-21swapper10:06:020
50369910653753384,53061cyclictest0-21swapper08:56:320
50369910651553477,53038cyclictest0-21swapper07:20:140
50369910649753476,53021cyclictest0-21swapper08:00:160
50369910649653470,53026cyclictest0-21swapper09:08:250
50369910649053423,53067cyclictest0-21swapper09:46:570
50369910647153412,53059cyclictest0-21swapper09:35:430
50369910646453454,53010cyclictest0-21swapper08:47:290
50369910646453435,53029cyclictest0-21swapper11:03:090
50369910644453398,53046cyclictest0-21swapper11:12:210
50369910643553393,53042cyclictest0-21swapper10:18:160
50369910642253432,52990cyclictest0-21swapper10:24:370
50369910633153451,52817cyclictest5035-21cyclictest09:51:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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