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2026-02-19 - 10:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Thu Feb 19, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165769910740453483,53800cyclictest5200-21munin-node19:50:130
165769910700653466,53540cyclictest0-21swapper21:34:530
165769910686753410,53367cyclictest12475-21kworker/u2:123:42:000
165769910668453426,53167cyclictest11-21rcu_preempt00:34:150
165769910667053388,53190cyclictest0-21swapper20:28:440
165769910656553385,53060cyclictest0-21swapper21:37:540
165769910656453395,53078cyclictest0-21swapper20:15:300
165769910654653386,53097cyclictest9-21ksoftirqd/020:50:300
165769910652853376,53089cyclictest9-21ksoftirqd/000:21:510
165769910652253482,53040cyclictest0-21swapper00:04:160
165769910652053417,53037cyclictest0-21swapper20:42:080
165769910648453471,53013cyclictest0-21swapper23:00:380
165769910645553444,53011cyclictest0-21swapper21:01:340
165769910644853443,53005cyclictest0-21swapper21:51:280
165769910644653451,52995cyclictest0-21swapper20:33:250
165769910643453394,53040cyclictest0-21swapper21:16:280
165769910642953432,52997cyclictest0-21swapper00:16:300
165769910642853437,52991cyclictest0-21swapper23:06:200
165769910639753445,52952cyclictest0-21swapper19:39:000
165769910635653464,52829cyclictest3950irq/9-acpi00:35:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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