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2026-03-04 - 09:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Wed Mar 04, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
181989910735053480,53773cyclictest25411-21ssh21:41:180
181989910697553428,53450cyclictest3167-21diskmemload21:39:070
181989910697053423,53456cyclictest0-21swapper20:20:140
181989910682553425,53279cyclictest15670-21munin-node23:50:250
181989910682253412,53410cyclictest5238-21ssh22:46:160
181989910676453480,53221cyclictest18192-21cyclictest19:17:360
181989910654253384,53092cyclictest0-21swapper21:18:110
181989910648853431,53057cyclictest0-21swapper19:26:090
181989910647353413,53060cyclictest0-21swapper00:19:130
181989910645653402,53054cyclictest0-21swapper00:00:280
181989910643353439,52994cyclictest0-21swapper23:40:420
181989910641853427,52991cyclictest0-21swapper23:25:280
181989910627153390,52816cyclictest0-21swapper21:06:580
181989910626253391,52805cyclictest0-21swapper19:37:220
181989910623553448,52787cyclictest0-21swapper20:37:090
181989910621153468,52743cyclictest0-21swapper19:52:360
181989910620753467,52740cyclictest0-21swapper22:22:500
181989910618053411,52769cyclictest0-21swapper20:47:120
181989910612453425,52699cyclictest0-21swapper19:11:550
181989910607352988,53083cyclictest0-21swapper00:12:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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