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2025-11-20 - 20:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Thu Nov 20, 2025 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
195199910614753062,53083cyclictest0-21swapper08:57:110
195199910614353396,52747cyclictest0-21swapper08:00:550
195199910614253052,53088cyclictest0-21swapper11:07:590
195199910612853050,53076cyclictest0-21swapper09:49:560
195199910612053038,53080cyclictest0-21swapper10:43:220
195199910610553027,53073cyclictest0-21swapper10:48:130
195199910608153006,53073cyclictest0-21swapper10:33:290
195199910605752966,53089cyclictest0-21swapper12:29:320
195199910601352936,53075cyclictest0-21swapper08:39:060
195199910600252940,53060cyclictest0-21swapper11:04:480
195199910598852932,53054cyclictest0-21swapper07:46:210
195199910592353072,52849cyclictest8058-21ssh09:14:260
195199910568353053,52628cyclictest21637-21ssh11:39:380
195199910546053041,52417cyclictest17940-21ssh10:51:440
195199910538153091,52280cyclictest0-21swapper11:22:430
195199910537053152,52218cyclictest0-21swapper08:27:030
195199910516553051,52112cyclictest0-21swapper09:26:300
195199910516153061,52098cyclictest0-21swapper07:54:030
195199910516053052,52107cyclictest0-21swapper11:59:440
195199910515553057,52096cyclictest0-21swapper10:20:150
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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