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2026-02-07 - 07:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sat Feb 07, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
277059910713053471,53570cyclictest50602sleep021:21:420
277059910679253396,53275cyclictest21216-21ssh23:22:470
277059910675853417,53247cyclictest0-21swapper20:04:200
277059910668953417,53207cyclictest0-21swapper21:28:140
277059910668153392,53196cyclictest0-21swapper20:11:020
277059910667053419,53157cyclictest0-21swapper00:40:000
277059910662753450,53087cyclictest89942sleep020:20:250
277059910659053418,53107cyclictest0-21swapper21:34:260
277059910656353440,53032cyclictest0-21swapper00:32:570
277059910655653457,53099cyclictest0-21swapper19:30:200
277059910649453435,53059cyclictest0-21swapper22:36:440
277059910649253467,53025cyclictest0-21swapper21:10:390
277059910648653419,53067cyclictest0-21swapper21:58:030
277059910648453457,53027cyclictest0-21swapper22:24:410
277059910647153438,53033cyclictest0-21swapper00:20:540
277059910646153448,53013cyclictest0-21swapper00:01:180
277059910645953465,52994cyclictest0-21swapper20:19:450
277059910644153440,53001cyclictest0-21swapper22:29:320
277059910643353396,53037cyclictest0-21swapper19:21:380
277059910642953432,52997cyclictest0-21swapper00:27:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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