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2026-01-26 - 14:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Mon Jan 26, 2026 12:43:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
162129910684953431,53418cyclictest0-21swapper11:48:350
162129910665453400,53162cyclictest0-21swapper07:37:220
162129910661653479,53016cyclictest1405-21ssh12:22:240
162129910658353442,53141cyclictest0-21swapper07:50:260
162129910656553472,53001cyclictest0-21swapper09:35:460
162129910651053404,53106cyclictest0-21swapper08:19:140
162129910649453425,53069cyclictest0-21swapper08:35:190
162129910649153468,53023cyclictest0-21swapper11:08:430
162129910647653419,52962cyclictest1027-21diskmemload09:17:210
162129910645753471,52986cyclictest0-21swapper08:42:510
162129910643553455,52915cyclictest32531-21kworker/0:008:22:450
162129910641153429,52982cyclictest0-21swapper07:25:090
162129910640253436,52966cyclictest0-21swapper09:14:400
162129910638053475,52837cyclictest3950irq/9-acpi07:41:130
162129910637853464,52823cyclictest0-21swapper11:10:340
162129910634653403,52879cyclictest26482-21kworker/0:008:53:340
162129910632353391,52868cyclictest9-21ksoftirqd/010:11:470
162129910631653388,52864cyclictest9-21ksoftirqd/007:30:100
162129910628253473,52720cyclictest3950irq/9-acpi11:40:020
162129910624253379,52798cyclictest0-21swapper11:31:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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