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2026-01-14 - 19:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Wed Jan 14, 2026 12:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
70049910684853401,53383cyclictest134850irq/9-eth011:04:450
70049910674953415,53243cyclictest0-21swapper08:08:140
70049910673253407,53235cyclictest0-21swapper08:57:080
70049910665753463,53129cyclictest9-21ksoftirqd/008:54:170
70049910663153434,53108cyclictest9-21ksoftirqd/012:05:020
70049910660853474,53134cyclictest0-21swapper11:37:540
70049910656453472,53092cyclictest0-21swapper07:36:040
70049910650953472,53037cyclictest0-21swapper09:19:540
70049910648153459,53022cyclictest0-21swapper07:23:510
70049910647553416,52994cyclictest3950irq/9-acpi11:54:290
70049910646853412,52994cyclictest9-21ksoftirqd/008:23:280
70049910646853397,53071cyclictest0-21swapper08:41:130
70049910645653472,52984cyclictest0-21swapper07:31:330
70049910644353399,53044cyclictest0-21swapper10:45:490
70049910641453417,52997cyclictest0-21swapper10:17:010
70049910634953399,52950cyclictest0-21swapper08:02:420
70049910627753384,52801cyclictest0-21swapper08:11:050
70049910627353453,52820cyclictest0-21swapper11:59:100
70049910625553445,52810cyclictest0-21swapper08:36:120
70049910621853472,52746cyclictest0-21swapper07:14:280
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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