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2026-02-25 - 03:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Wed Feb 25, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3899910697053423,53455cyclictest0-21swapper23:58:430
3899910686453381,53393cyclictest9-21ksoftirqd/023:08:390
3899910669353446,53247cyclictest0-21swapper00:15:280
3899910662453431,53130cyclictest9-21ksoftirqd/020:53:200
3899910659953368,53231cyclictest0-21swapper21:30:010
3899910658953400,53189cyclictest0-21swapper20:41:470
3899910657953469,53012cyclictest17968-21ssh23:32:360
3899910655953414,53145cyclictest0-21swapper21:23:290
3899910650953396,53113cyclictest0-21swapper20:01:250
3899910648953461,53028cyclictest0-21swapper23:54:120
3899910647853415,53063cyclictest0-21swapper21:29:300
3899910643453433,53001cyclictest0-21swapper21:15:360
3899910642753431,52996cyclictest0-21swapper22:42:520
3899910641153423,52988cyclictest0-21swapper19:46:410
3899910631453428,52823cyclictest3950irq/9-acpi22:32:490
3899910627553459,52816cyclictest0-21swapper20:55:310
3899910625953386,52807cyclictest0-21swapper21:01:120
3899910624853374,52810cyclictest9-21ksoftirqd/020:46:080
3899910620953471,52738cyclictest0-21swapper20:08:470
3899910617653448,52728cyclictest0-21swapper21:09:450
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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