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2026-02-02 - 08:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Mon Feb 02, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
154849910683553419,53416cyclictest0-21swapper00:02:150
154849910669453438,53132cyclictest3120-21ssh23:51:420
154849910664553471,53174cyclictest0-21swapper21:01:430
154849910664153390,53161cyclictest0-21swapper22:26:070
154849910656353452,53111cyclictest0-21swapper19:31:570
154849910655153391,53096cyclictest0-21swapper23:59:340
154849910654853442,53106cyclictest0-21swapper20:57:010
154849910654453385,53093cyclictest0-21swapper00:07:360
154849910654153382,53068cyclictest0-21swapper23:42:090
154849910652153432,53089cyclictest0-21swapper00:26:420
154849910651653477,53039cyclictest0-21swapper22:32:090
154849910651253388,53124cyclictest0-21swapper20:19:410
154849910645053456,52994cyclictest0-21swapper23:25:440
154849910644053447,52993cyclictest0-21swapper22:12:530
154849910639253403,52896cyclictest0-21swapper19:24:450
154849910633353416,52853cyclictest9-21ksoftirqd/022:01:200
154849910632653450,52876cyclictest0-21swapper23:18:020
154849910627853478,52760cyclictest0-21swapper20:36:150
154849910626853421,52847cyclictest0-21swapper19:51:430
154849910623053477,52753cyclictest0-21swapper22:47:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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