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2026-01-24 - 06:36
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sat Jan 24, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
307839910737653475,53810cyclictest134850irq/9-eth000:12:340
307839910693953435,53408cyclictest6457-21ssh21:17:040
307839910679153479,53312cyclictest0-21swapper23:45:570
307839910676353457,53306cyclictest0-21swapper21:12:230
307839910673053402,53263cyclictest11-21rcu_preempt19:34:140
307839910671953476,53243cyclictest0-21swapper23:30:020
307839910663553470,53098cyclictest0-21swapper23:56:500
307839910663353395,53148cyclictest9-21ksoftirqd/022:10:490
307839910655853393,53100cyclictest0-21swapper21:34:590
307839910652553465,53060cyclictest0-21swapper23:11:270
307839910651553463,53052cyclictest0-21swapper23:16:180
307839910647853401,53077cyclictest0-21swapper22:53:320
307839910646553410,53055cyclictest0-21swapper22:26:140
307839910646453456,53008cyclictest0-21swapper23:07:260
307839910646253450,53012cyclictest0-21swapper22:39:380
307839910646053443,52929cyclictest3950irq/9-acpi23:52:490
307839910644753421,52961cyclictest9-21ksoftirqd/000:22:270
307839910642653464,52841cyclictest15513-21ssh22:18:220
307839910639753446,52951cyclictest0-21swapper19:28:230
307839910637453470,52813cyclictest9-21ksoftirqd/022:32:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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