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2026-01-18 - 02:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sun Jan 18, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1201499209948105449,104497cyclictest0-21swapper22:30:570
1201499209775105286,104487cyclictest0-21swapper19:27:340
120149910669553468,53136cyclictest9-21ksoftirqd/000:05:240
120149910664553459,53124cyclictest9-21ksoftirqd/020:14:170
120149910655353459,53094cyclictest0-21swapper20:15:580
120149910650553423,53082cyclictest0-21swapper20:55:590
120149910649253469,53023cyclictest0-21swapper22:28:360
120149910646753456,53011cyclictest0-21swapper22:42:100
120149910646453410,53054cyclictest0-21swapper23:35:050
120149910646053474,52986cyclictest0-21swapper19:49:100
120149910645853447,53011cyclictest0-21swapper19:15:200
120149910645553444,53011cyclictest0-21swapper21:32:100
120149910642453389,53035cyclictest0-21swapper23:28:330
120149910640453420,52984cyclictest0-21swapper23:15:290
120149910640253409,52993cyclictest0-21swapper23:04:360
120149910620853297,52896cyclictest19173-21ssh00:02:030
120149910616953431,52738cyclictest0-21swapper21:09:030
120149910615753438,52719cyclictest0-21swapper20:04:140
120149910614253439,52703cyclictest0-21swapper20:50:580
120149910613053056,53072cyclictest0-21swapper20:35:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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