You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-17 - 05:21
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Sat Jan 17, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
274769910705353427,53530cyclictest2493-21ssh23:31:590
274769910704853474,53509cyclictest9-21ksoftirqd/020:05:000
274769910699553461,53534cyclictest0-21swapper00:39:090
274769910698253454,53528cyclictest0-21swapper23:25:070
274769910688553441,53344cyclictest2277-21Xorg20:12:120
274769910675453455,53299cyclictest0-21swapper22:35:530
274769910655753393,53099cyclictest0-21swapper22:21:090
274769910655753392,53100cyclictest0-21swapper00:18:330
274769910655453387,53100cyclictest0-21swapper23:22:470
274769910655153389,53096cyclictest0-21swapper20:35:290
274769910654753382,53102cyclictest10-21rcuc/021:36:260
274769910654153386,53090cyclictest0-21swapper22:12:160
274769910653353374,53094cyclictest9-21ksoftirqd/021:18:210
274769910652053478,53042cyclictest0-21swapper21:53:110
274769910651253454,53058cyclictest0-21swapper19:54:470
274769910651053474,53036cyclictest0-21swapper00:24:450
274769910650553473,53032cyclictest0-21swapper23:56:570
274769910649253459,53033cyclictest0-21swapper21:44:180
274769910645153404,53047cyclictest0-21swapper20:50:530
274769910645053447,53003cyclictest0-21swapper22:17:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional