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2026-02-17 - 00:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Mon Feb 16, 2026 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
273709910743453473,53839cyclictest7107-21ssh10:37:250
273709910695553415,53448cyclictest0-21swapper09:36:170
273709910686953423,53414cyclictest0-21swapper07:16:070
273709910683453467,53245cyclictest12337-21diskmemload10:29:120
273709910681753448,53369cyclictest0-21swapper12:09:010
273709910667853475,53203cyclictest0-21swapper11:24:280
273709910666753471,53196cyclictest0-21swapper07:27:300
273709910663153454,53177cyclictest0-21swapper08:00:100
273709910659953476,53032cyclictest0-21swapper07:42:450
273709910657053464,53106cyclictest0-21swapper07:37:330
273709910656953389,53085cyclictest2099-21runrttasks07:59:190
273709910646653456,53010cyclictest0-21swapper10:16:490
273709910644453397,53047cyclictest0-21swapper12:39:000
273709910643253393,53039cyclictest0-21swapper08:40:410
273709910642853433,52995cyclictest0-21swapper08:50:440
273709910634353388,52891cyclictest9-21ksoftirqd/011:34:410
273709910625153384,52802cyclictest0-21swapper08:33:290
273709910619253459,52733cyclictest0-21swapper09:02:070
273709910616753450,52717cyclictest0-21swapper08:07:020
273709910614553443,52702cyclictest0-21swapper08:18:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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