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2026-01-14 - 05:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 20 highest latencies:
System rack6slot6 (updated Wed Jan 14, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
222429910695653442,53514cyclictest0-21swapper22:28:270
222429910670853388,53228cyclictest0-21swapper00:19:190
222429910665253384,53203cyclictest0-21swapper21:28:390
222429910660353475,53128cyclictest0-21swapper23:31:350
222429910654753447,53100cyclictest0-21swapper23:10:490
222429910652753393,53102cyclictest0-21swapper19:15:210
222429910649853467,53031cyclictest0-21swapper00:38:540
222429910647353412,53061cyclictest0-21swapper23:45:590
222429910646753396,53071cyclictest0-21swapper23:07:280
222429910646253451,53011cyclictest0-21swapper23:25:030
222429910642253434,52988cyclictest0-21swapper23:53:310
222429910642253433,52989cyclictest0-21swapper22:51:030
222429910635953304,53032cyclictest1453-21ssh21:48:550
222429910629853452,52782cyclictest9-21ksoftirqd/020:45:070
222429910626853393,52811cyclictest0-21swapper19:49:510
222429910626453390,52809cyclictest0-21swapper19:41:590
222429910625653419,52746cyclictest0-21swapper20:34:440
222429910623653475,52761cyclictest0-21swapper21:01:120
222429910623453420,52748cyclictest0-21swapper20:51:090
222429910620353469,52734cyclictest0-21swapper20:16:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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