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2026-05-28 - 02:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 376 highest latencies:
System rack6slot6 (updated Thu May 28, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23099910698253416,53498cyclictest0-21swapper20:23:370
23099910686953466,53311cyclictest0-21swapper23:29:210
23099910673453465,53172cyclictest12809-21ssh00:20:050
23099910666653399,53267cyclictest0-21swapper19:30:120
23099910665453395,53168cyclictest0-21swapper19:40:350
23099910660753472,53043cyclictest0-21swapper20:58:570
23099910657453430,53144cyclictest0-21swapper19:59:500
23099910656453480,53084cyclictest0-21swapper21:00:380
23099910654253494,53048cyclictest0-21swapper00:11:530
23099910651753432,53085cyclictest0-21swapper21:08:500
23099910651053471,53039cyclictest0-21swapper00:05:310
23099910650753476,53031cyclictest0-21swapper22:26:120
23099910650653472,53034cyclictest0-21swapper21:56:340
23099910650453471,53033cyclictest0-21swapper23:55:380
23099910649553471,53024cyclictest0-21swapper21:45:510
23099910649153468,53023cyclictest0-21swapper22:39:360
23099910648853463,53025cyclictest0-21swapper00:28:180
23099910648053461,53019cyclictest0-21swapper23:15:570
23099910645053442,53008cyclictest0-21swapper22:01:350
23099910644353401,53042cyclictest0-21swapper23:08:040
23099910643753398,53039cyclictest0-21swapper22:22:110
23099910643653439,52997cyclictest0-21swapper23:12:560
23099910643253394,53038cyclictest0-21swapper23:49:360
23099910641553462,52953cyclictest0-21swapper20:04:010
23099910629153467,52824cyclictest0-21swapper20:49:140
23099910628553467,52818cyclictest0-21swapper19:47:170
23099910627453424,52759cyclictest0-21swapper20:06:120
23099910621653471,52745cyclictest0-21swapper23:43:250
23099910621053467,52743cyclictest0-21swapper20:28:490
23099910619453461,52733cyclictest0-21swapper20:52:550
23099910615353400,52753cyclictest0-21swapper20:41:120
23099910615053396,52754cyclictest0-21swapper22:17:500
23099910614853436,52712cyclictest0-21swapper21:21:540
23099910604452957,53082cyclictest0-21swapper23:32:310
23099910507952976,52101cyclictest0-21swapper21:34:270
2309995416232,54005cyclictest16027-21ssh22:49:290
2309995348327,411cyclictest0-21swapper23:38:230
2309995344928,53324cyclictest0-21swapper00:15:340
2309995325924,0cyclictest0-21swapper20:19:460
2309995321625,0cyclictest0-21swapper21:40:090
2309995315225,0cyclictest0-21swapper19:53:180
2309995307727,53050cyclictest0-21swapper19:26:100
2309995306627,53039cyclictest0-21swapper21:10:100
23099951012874,2223cyclictest1741-21hald22:09:380
23099926031091,1413cyclictest5781-21ssh23:20:480
23099925901086,1404cyclictest13183-21diskmemload21:54:030
23099923711105,1260cyclictest0-21swapper00:34:190
23099923621092,1146cyclictest13183-21diskmemload00:35:300
23099923511089,1106cyclictest5500-21ssh22:33:340
23099922961097,1107cyclictest9-21ksoftirqd/022:55:110
23099922071021,1062cyclictest18819-21ssh22:53:100
23099921621054,1015cyclictest9-21ksoftirqd/021:27:050
23099920551008,1027cyclictest0-21swapper19:23:200
2309992034977,1023cyclictest0-21swapper20:39:420
23099919941034,864cyclictest0-21swapper20:31:290
23099919701023,853cyclictest0-21swapper23:50:170
23099919641082,791cyclictest0-21swapper19:35:330
2309991955967,953cyclictest0-21swapper20:12:040
23099919451026,885cyclictest237812sleep022:12:280
2309991785861,908cyclictest12483-21ssh22:44:070
2309991764953,787cyclictest488-21ssh21:38:490
23099917061074,632cyclictest0-21swapper23:02:530
23099916961064,540cyclictest0-21swapper21:15:320
2309991642940,665cyclictest1720-21ssh00:03:300
2309991243615,623cyclictest8327-21hwlatdetect-tra19:12:470
2309991218607,607cyclictest30015-21wc19:16:380
1977922300,2sleep019780-21latency19:05:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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