You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-20 - 04:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Fri Feb 20, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
47759910676253444,53221cyclictest12829-21ssh21:43:510
47759910659953391,53117cyclictest9-21ksoftirqd/000:37:310
47759910658553472,53113cyclictest9-21ksoftirqd/019:39:050
47759910655753385,53105cyclictest0-21swapper20:15:350
47759910652953405,53033cyclictest0-21swapper21:48:320
47759910652753482,53045cyclictest0-21swapper22:17:300
47759910651053475,53035cyclictest0-21swapper00:29:180
47759910650353467,53036cyclictest0-21swapper22:08:280
47759910649653466,53030cyclictest0-21swapper23:14:370
47759910648653465,53021cyclictest0-21swapper23:16:170
47759910648353425,53058cyclictest0-21swapper23:32:020
47759910644553445,53000cyclictest0-21swapper19:23:300
47759910644153399,53042cyclictest0-21swapper19:17:080
47759910644153398,53043cyclictest0-21swapper22:57:120
47759910642453431,52993cyclictest0-21swapper22:26:330
47759910641153424,52987cyclictest0-21swapper00:14:540
47759910635753415,52850cyclictest0-21swapper21:33:180
47759910633353473,52748cyclictest0-21swapper20:58:380
47759910623553369,52802cyclictest9-21ksoftirqd/021:09:110
47759910622453475,52749cyclictest0-21swapper20:07:330
47759910621553470,52745cyclictest0-21swapper19:55:590
47759910619753462,52735cyclictest0-21swapper20:46:540
47759910619153457,52734cyclictest0-21swapper19:31:120
47759910618353458,52725cyclictest0-21swapper20:11:440
47759910617353407,52766cyclictest0-21swapper21:18:530
47759910616853446,52722cyclictest0-21swapper19:40:350
47759910616153443,52718cyclictest0-21swapper20:29:590
47759910612953425,52704cyclictest0-21swapper20:34:410
47759910585553337,52518cyclictest0-21swapper20:41:230
4775995374653414,241cyclictest0-21swapper22:22:420
4775995370326,53585cyclictest0-21swapper23:23:190
4775995356653390,176cyclictest0-21swapper20:21:470
4775995333826,53312cyclictest0-21swapper23:00:530
4775995321926,438cyclictest0-21swapper21:02:090
4775995303325,53008cyclictest0-21swapper23:36:430
4775995277927,52752cyclictest0-21swapper21:53:230
4775995277626,52750cyclictest0-21swapper20:52:560
4775995276824,52744cyclictest0-21swapper00:17:150
47759952032670,2530cyclictest1741-21hald22:53:210
47759922461096,1051cyclictest2099-21runrttasks21:12:520
47759922311011,1126cyclictest14237-21rm00:09:220
47759921891006,1090cyclictest134850irq/9-eth021:56:340
47759921281058,942cyclictest2277-21Xorg20:04:020
47759920641032,999cyclictest0-21swapper22:45:580
47759920561039,979cyclictest17579-21sh22:38:560
47759920381047,899cyclictest5350irq/9-uhci_hcd:21:39:290
47759920221089,804cyclictest348-21ssh22:13:290
47759919921035,865cyclictest0-21swapper23:54:080
4775991944938,971cyclictest0-21swapper00:32:490
4775991932979,915cyclictest30423-21ssh21:21:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional