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2026-02-18 - 00:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Tue Feb 17, 2026 12:43:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32509910739753448,53826cyclictest25898-21ssh09:17:060
32509910723053468,53671cyclictest18299-21ssh09:54:470
32509910706753455,53515cyclictest6140-21ssh10:24:450
32509910697753426,53486cyclictest9-21ksoftirqd/012:01:030
32509910688153462,53321cyclictest2099-21runrttasks08:31:330
32509910676553446,53227cyclictest134850irq/9-eth009:32:500
32509910667953427,53160cyclictest0-21swapper08:28:120
32509910660253405,53103cyclictest0-21swapper08:53:590
32509910660253402,53136cyclictest9-21ksoftirqd/011:40:570
32509910651053475,53035cyclictest0-21swapper10:18:440
32509910650353474,53029cyclictest0-21swapper11:39:570
32509910648653458,53028cyclictest0-21swapper10:58:150
32509910648053467,53013cyclictest0-21swapper11:04:070
32509910647753411,52973cyclictest0-21swapper07:14:000
32509910646053407,53053cyclictest0-21swapper07:37:270
32509910645753407,53050cyclictest0-21swapper08:42:060
32509910645753405,53052cyclictest0-21swapper10:09:310
32509910644653441,53005cyclictest0-21swapper11:28:440
32509910644053437,52937cyclictest0-21swapper09:08:430
32509910643453391,53043cyclictest0-21swapper09:24:080
32509910642853436,52992cyclictest0-21swapper07:22:130
32509910638353329,52993cyclictest23950-21ssh12:26:400
32509910629553393,52810cyclictest0-21swapper07:34:360
32509910622653476,52750cyclictest0-21swapper08:20:090
32509910622453479,52745cyclictest0-21swapper08:15:580
32509910622453474,52750cyclictest0-21swapper09:59:080
32509910622053474,52746cyclictest0-21swapper08:59:510
32509910620553470,52735cyclictest0-21swapper08:08:460
32509910620153473,52728cyclictest0-21swapper12:10:060
32509910619753469,52728cyclictest0-21swapper10:27:260
32509910617653414,52762cyclictest0-21swapper10:46:320
32509910617353458,52715cyclictest0-21swapper07:46:200
32509910617253408,52764cyclictest0-21swapper08:11:070
32509910616653405,52761cyclictest0-21swapper08:46:370
32509910615753401,52756cyclictest0-21swapper12:05:040
32509910613653440,52696cyclictest0-21swapper09:45:040
32509910507052982,52087cyclictest0-21swapper10:34:480
32509910494452892,52050cyclictest0-21swapper12:33:420
3250995387253434,438cyclictest0-21swapper08:02:440
3250995385853419,439cyclictest0-21swapper09:11:140
3250995384653407,439cyclictest0-21swapper10:52:430
3250995383353400,433cyclictest0-21swapper11:54:410
3250995370827,53587cyclictest0-21swapper11:12:390
3250995366630,0cyclictest0-21swapper11:23:320
3250995359953425,174cyclictest0-21swapper07:29:250
3250995355527,0cyclictest0-21swapper10:44:210
3250995353953388,151cyclictest0-21swapper12:36:230
3250995353228,53504cyclictest0-21swapper09:26:180
3250995333826,53312cyclictest0-21swapper12:24:300
3250995308125,52963cyclictest0-21swapper07:51:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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