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2026-02-13 - 19:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Fri Feb 13, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
122759910723553333,53837cyclictest26875-21kworker/0:010:42:120
122759910721053463,53682cyclictest5350irq/9-uhci_hcd:11:04:580
122759910683053479,53351cyclictest0-21swapper10:08:020
122759910668953455,53234cyclictest0-21swapper08:20:310
122759910667953466,53122cyclictest0-21swapper09:22:590
122759910666453438,53226cyclictest0-21swapper11:10:100
122759910662053422,53107cyclictest9-21ksoftirqd/012:35:450
122759910658653418,53104cyclictest9-21ksoftirqd/007:40:190
122759910658553452,53041cyclictest0-21swapper09:12:560
122759910658253420,53097cyclictest0-21swapper12:30:030
122759910657153472,53099cyclictest0-21swapper08:10:480
122759910657153412,53095cyclictest9-21ksoftirqd/011:48:210
122759910654753404,53143cyclictest0-21swapper07:17:130
122759910654753401,53146cyclictest0-21swapper08:18:200
122759910652253421,53037cyclictest0-21swapper09:46:060
122759910650753474,53033cyclictest0-21swapper07:10:410
122759910649553468,53027cyclictest0-21swapper11:07:390
122759910645953452,53007cyclictest0-21swapper08:37:360
122759910645253445,53007cyclictest0-21swapper12:14:390
122759910645153404,53047cyclictest0-21swapper09:02:130
122759910644953444,53005cyclictest0-21swapper09:40:440
122759910644153439,53002cyclictest0-21swapper12:16:390
122759910632653418,52844cyclictest9-21ksoftirqd/007:31:370
122759910630553426,52814cyclictest0-21swapper07:37:290
122759910622953477,52752cyclictest0-21swapper07:56:040
122759910622053477,52743cyclictest0-21swapper12:24:110
122759910621853474,52744cyclictest0-21swapper09:07:350
122759910621653476,52740cyclictest0-21swapper11:58:440
122759910621353459,52754cyclictest0-21swapper07:51:430
122759910619653466,52730cyclictest0-21swapper08:43:380
122759910615153443,52708cyclictest0-21swapper07:21:340
122759910609353045,53046cyclictest3706-21ssh10:50:040
122759910520452900,52302cyclictest19996-21ssh10:26:370
12275995405732,53898cyclictest2790-21gnome-settings-09:32:320
12275995392628,53798cyclictest31093-21ssh11:28:150
12275995355924,53441cyclictest0-21swapper09:54:280
12275995352927,0cyclictest0-21swapper11:44:500
12275995348124,53332cyclictest29500-21diskmemload10:56:360
12275995332026,0cyclictest0-21swapper09:25:500
12275995313927,53112cyclictest0-21swapper10:14:340
12275995312625,53101cyclictest0-21swapper07:46:410
12275995309527,53068cyclictest0-21swapper12:04:050
12275995302326,52905cyclictest0-21swapper11:31:160
12275995302225,52997cyclictest0-21swapper10:04:510
122759945322604,1924cyclictest1741-21hald08:46:390
122759925431087,1332cyclictest26646-21ssh10:35:400
122759925231060,1337cyclictest2937-21ssh10:48:440
122759924651057,1314cyclictest17100-21rm11:54:330
122759924541040,1288cyclictest1993-21lldpd08:03:360
122759923731099,1152cyclictest27282-21ssh11:22:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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