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2026-02-26 - 12:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Thu Feb 26, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
276459910740853462,53821cyclictest2099-21runrttasks22:20:100
276459910733353476,53760cyclictest22260-21ssh21:49:210
276459910705153460,53501cyclictest9-21ksoftirqd/021:30:560
276459910694953415,53443cyclictest0-21swapper23:02:320
276459910690353394,53414cyclictest27784-21diskmemload22:06:560
276459910677953431,53252cyclictest3261-21gnome-power-man20:08:120
276459910665853432,53137cyclictest134850irq/9-eth000:38:300
276459910665053459,53191cyclictest0-21swapper00:14:030
276459910665053432,53218cyclictest0-21swapper20:40:210
276459910662553425,53110cyclictest9-21ksoftirqd/022:27:020
276459910660153391,53116cyclictest0-21swapper00:24:560
276459910659453416,53088cyclictest9-21ksoftirqd/000:27:260
276459910657153412,53094cyclictest9-21ksoftirqd/020:26:270
276459910653153483,53048cyclictest0-21swapper19:55:280
276459910651053478,53032cyclictest0-21swapper23:51:160
276459910649553427,53068cyclictest0-21swapper19:30:410
276459910648553418,53067cyclictest0-21swapper22:56:500
276459910647953460,53019cyclictest0-21swapper21:36:170
276459910647853459,53019cyclictest0-21swapper21:14:310
276459910646953474,52995cyclictest0-21swapper20:22:560
276459910646453450,53014cyclictest0-21swapper22:40:060
276459910645053436,53014cyclictest0-21swapper20:58:460
276459910644653442,53004cyclictest0-21swapper20:31:390
276459910644153398,53043cyclictest0-21swapper23:36:220
276459910644053438,53002cyclictest0-21swapper19:39:030
276459910642953394,53035cyclictest0-21swapper19:42:550
276459910642853254,53161cyclictest20465-21ssh23:21:170
276459910640853426,52982cyclictest0-21swapper23:41:530
276459910640653424,52982cyclictest0-21swapper20:03:510
276459910633853419,52919cyclictest0-21swapper20:38:000
276459910631153389,52831cyclictest0-21swapper22:39:560
276459910629853421,52814cyclictest9-21ksoftirqd/020:10:020
276459910625953416,52751cyclictest0-21swapper00:33:480
276459910622153475,52746cyclictest0-21swapper20:52:450
276459910617753455,52722cyclictest0-21swapper21:22:230
276459910617053446,52724cyclictest0-21swapper22:03:250
276459910616253404,52758cyclictest0-21swapper19:28:400
276459910502852917,52106cyclictest0-21swapper21:40:380
276459910494252881,52059cyclictest0-21swapper23:48:250
27645995380128,175cyclictest0-21swapper21:03:580
27645995368127,53533cyclictest0-21swapper20:19:250
27645995358525,0cyclictest0-21swapper22:19:100
27645995345926,53433cyclictest0-21swapper21:50:410
27645995333127,53304cyclictest0-21swapper23:28:500
27645995324230,201cyclictest0-21swapper22:34:340
276459950052640,2361cyclictest1741-21hald21:55:030
276459924691091,1282cyclictest134850irq/9-eth000:19:440
276459924301012,1323cyclictest28790-1kworker/u3:023:56:580
276459923511086,1138cyclictest27784-21diskmemload21:16:520
276459920961092,911cyclictest134850irq/9-eth022:12:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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