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2026-07-06 - 06:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Mon Jul 06, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
188519910702553475,53550cyclictest0-21swapper20:55:080
188519910658653421,53100cyclictest0-21swapper22:32:060
188519910649153468,53023cyclictest0-21swapper21:47:430
188519910648553479,53006cyclictest0-21swapper19:16:390
188519910644553401,53044cyclictest0-21swapper19:14:290
188519910643953470,52969cyclictest0-21swapper19:36:150
188519910643253439,52993cyclictest0-21swapper21:09:120
188519910641753432,52985cyclictest0-21swapper20:08:240
188519910628853417,52807cyclictest9-21ksoftirqd/019:57:110
188519910624053471,52769cyclictest0-21swapper20:19:580
188519910619453463,52731cyclictest0-21swapper20:52:270
188519910619253459,52733cyclictest0-21swapper20:26:090
188519910618953429,52760cyclictest0-21swapper20:24:390
188519910616353446,52717cyclictest0-21swapper21:56:560
188519910615253444,52708cyclictest0-21swapper19:49:290
188519910614553440,52705cyclictest0-21swapper20:49:460
188519910614253449,52693cyclictest0-21swapper21:24:060
188519910612653040,53084cyclictest0-21swapper21:41:110
188519910607552990,53083cyclictest0-21swapper00:36:520
188519910606452988,53071cyclictest0-21swapper00:13:050
188519910561353014,52596cyclictest890-21sh00:01:520
188519910541353144,52269cyclictest0-21swapper23:18:190
188519910530153057,52241cyclictest4402-21ssh22:38:380
188519910520953086,52121cyclictest0-21swapper22:06:080
188519910518053061,52118cyclictest9-21ksoftirqd/022:49:010
188519910516453065,52097cyclictest0-21swapper20:33:420
188519910514853057,52089cyclictest0-21swapper22:21:230
188519910513553029,52104cyclictest0-21swapper00:30:300
188519910512553019,52104cyclictest0-21swapper22:58:430
188519910511953026,52088cyclictest0-21swapper23:14:580
188519910510753001,52104cyclictest0-21swapper21:18:140
188519910507053007,52061cyclictest0-21swapper22:27:140
188519910504452946,52096cyclictest0-21swapper21:10:420
188519910504252935,52102cyclictest0-21swapper23:59:110
188519910500252915,52085cyclictest0-21swapper22:12:300
18851995352827,0cyclictest0-21swapper22:17:110
18851995336924,53345cyclictest0-21swapper20:43:140
18851995325326,439cyclictest0-21swapper21:26:570
18851995320725,0cyclictest0-21swapper21:34:090
1885199531088,53098cyclictest0-21swapper19:44:270
1885199531028,53092cyclictest0-21swapper21:53:040
18851995305624,53032cyclictest0-21swapper19:23:110
18851995296925,52944cyclictest0-21swapper19:26:020
188519924081064,1223cyclictest129242sleep020:12:250
188519920671092,909cyclictest3950irq/9-acpi22:02:470
188519919871032,862cyclictest0-21swapper23:24:210
188519919851068,849cyclictest3950irq/9-acpi19:52:500
18851991978981,964cyclictest0-21swapper21:39:100
188519919761027,855cyclictest0-21swapper20:38:530
188519919501076,782cyclictest0-21swapper20:03:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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