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2026-01-12 - 15:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Mon Jan 12, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
135929910729253471,53724cyclictest9729-21ssh11:00:440
135929910705053458,53526cyclictest134850irq/9-eth010:28:550
135929910698753418,53569cyclictest0-21swapper10:48:400
135929910684853430,53418cyclictest2099-21runrttasks07:17:300
135929910667553420,53161cyclictest0-21swapper09:01:190
135929910664553468,53113cyclictest30898-21kworker/0:209:17:540
135929910661253399,53125cyclictest3950irq/9-acpi11:16:080
135929910660853476,53132cyclictest0-21swapper11:10:370
135929910659753457,53077cyclictest9-21ksoftirqd/010:39:480
135929910659153429,53105cyclictest0-21swapper08:15:060
135929910657753464,53113cyclictest0-21swapper07:57:510
135929910657353413,53069cyclictest0-21swapper08:40:540
135929910651653476,53040cyclictest0-21swapper12:30:400
135929910651253474,53038cyclictest0-21swapper09:46:430
135929910650353473,53030cyclictest0-21swapper09:30:380
135929910642453430,52994cyclictest0-21swapper11:48:580
135929910638953466,52832cyclictest0-21swapper08:51:170
135929910627253453,52819cyclictest0-21swapper10:01:570
135929910625953461,52798cyclictest0-21swapper08:11:450
135929910624953383,52801cyclictest0-21swapper07:32:140
135929910622353459,52728cyclictest0-21swapper08:21:280
135929910622153477,52744cyclictest0-21swapper08:26:390
135929910622153474,52747cyclictest0-21swapper07:46:380
135929910621853468,52750cyclictest0-21swapper12:25:480
135929910621453469,52745cyclictest0-21swapper10:20:420
135929910618153411,52770cyclictest0-21swapper09:20:350
135929910618053453,52727cyclictest0-21swapper07:37:250
135929910617453453,52721cyclictest0-21swapper08:05:330
135929910616653446,52720cyclictest0-21swapper07:14:090
135929910615653400,52756cyclictest0-21swapper10:14:510
135929910611053418,52692cyclictest0-21swapper08:01:120
135929910520452944,52257cyclictest22390-21ssh10:32:060
135929910511353007,52104cyclictest0-21swapper09:59:460
13592995424853375,814cyclictest0-21swapper10:50:210
13592995386253402,395cyclictest0-21swapper10:59:330
13592995352825,53410cyclictest0-21swapper11:34:340
13592995350924,0cyclictest0-21swapper07:41:570
13592995342625,53309cyclictest0-21swapper12:19:060
13592995319330,296cyclictest13583-21cyclictest08:58:190
13592995312526,53099cyclictest0-21swapper07:22:310
13592995303624,52921cyclictest0-21swapper08:38:030
13592995294252929,11cyclictest134850irq/9-eth011:06:360
1359299521208,52110cyclictest0-21swapper11:35:040
135929925321081,1326cyclictest30886-21diskmemload11:55:300
135929925061052,1330cyclictest23360-21ssh11:21:000
135929922391088,1084cyclictest13583-21cyclictest09:05:410
135929921031090,883cyclictest11919-21ssh09:29:380
135929920701022,1013cyclictest0-21swapper12:03:020
135929920661023,1009cyclictest0-21swapper08:49:360
135929920631004,1024cyclictest0-21swapper09:39:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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