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2025-12-27 - 05:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Sat Dec 27, 2025 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
130999910697653427,53458cyclictest0-21swapper21:43:180
130999910673253474,53258cyclictest0-21swapper00:30:260
130999910671353432,53281cyclictest0-21swapper22:31:220
130999910664353477,53166cyclictest0-21swapper23:19:460
130999910663753451,53186cyclictest0-21swapper22:44:250
130999910663653384,53186cyclictest0-21swapper20:33:080
130999910660553459,53082cyclictest9-21ksoftirqd/020:56:440
130999910656553455,53110cyclictest0-21swapper23:46:330
130999910654853444,53104cyclictest0-21swapper20:17:530
130999910654153412,53038cyclictest0-21swapper22:08:150
130999910653053481,53049cyclictest0-21swapper20:25:250
130999910652853421,53107cyclictest0-21swapper20:22:040
130999910652153483,53038cyclictest0-21swapper20:51:430
130999910649053452,53038cyclictest0-21swapper23:14:140
130999910648053447,53033cyclictest0-21swapper22:02:330
130999910646853452,53016cyclictest0-21swapper19:30:190
130999910646753411,53056cyclictest0-21swapper23:35:300
130999910646753411,53056cyclictest0-21swapper21:12:390
130999910646553448,53017cyclictest0-21swapper19:54:160
130999910643553395,53040cyclictest0-21swapper21:22:220
130999910643453395,53039cyclictest0-21swapper23:03:510
130999910642153434,52987cyclictest0-21swapper22:13:360
130999910640553420,52985cyclictest0-21swapper00:11:510
130999910639853389,52944cyclictest0-21swapper19:27:390
130999910623953439,52734cyclictest0-21swapper22:25:100
130999910622353433,52790cyclictest0-21swapper22:46:160
130999910622253479,52743cyclictest0-21swapper00:15:420
130999910622153477,52744cyclictest0-21swapper20:45:110
130999910621653429,52787cyclictest0-21swapper20:41:300
130999910618853443,52709cyclictest0-21swapper19:42:430
130999910615053396,52754cyclictest0-21swapper21:08:080
130999910614353435,52708cyclictest0-21swapper23:09:330
130999910614353392,52751cyclictest0-21swapper20:10:410
130999910613253429,52703cyclictest0-21swapper21:04:370
130999910613153020,53109cyclictest0-21swapper23:21:460
130999910612353424,52699cyclictest0-21swapper21:35:460
130999910589453262,52609cyclictest16900-21ssh22:56:490
130999910583653266,52557cyclictest0-21swapper21:15:200
13099995361727,0cyclictest0-21swapper00:39:590
13099995353025,0cyclictest0-21swapper21:56:210
13099995342727,53400cyclictest0-21swapper00:04:490
13099995330125,53183cyclictest0-21swapper20:08:400
13099995301327,52895cyclictest0-21swapper19:57:570
130999922721091,1055cyclictest8600-21diskmemload22:38:240
130999921941053,1039cyclictest25678-21ssh23:57:560
130999921391029,989cyclictest8600-21diskmemload23:44:430
130999920811038,1022cyclictest0-21swapper19:36:110
13099991995940,1040cyclictest0-21swapper00:09:200
130999919611019,850cyclictest0-21swapper20:38:490
130999919431008,915cyclictest0-21swapper20:02:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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