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2026-01-25 - 20:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Sun Jan 25, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
121459910686053393,53404cyclictest12133-21cyclictest11:06:580
121459910680153392,53314cyclictest5658-21ssh12:34:030
121459910667453413,53197cyclictest30320-21kworker/0:010:57:550
121459910667453401,53273cyclictest0-21swapper07:15:010
121459910656453396,53078cyclictest0-21swapper12:38:140
121459910651653476,53040cyclictest0-21swapper10:02:190
121459910650153471,53030cyclictest0-21swapper08:49:080
121459910648953476,53013cyclictest0-21swapper09:16:260
121459910648753459,53028cyclictest0-21swapper09:27:190
121459910646153408,53053cyclictest0-21swapper10:43:510
121459910644753402,53045cyclictest0-21swapper07:35:370
121459910644653441,53005cyclictest0-21swapper11:14:000
121459910644553476,52969cyclictest0-21swapper09:10:540
121459910643553398,53037cyclictest0-21swapper07:56:530
121459910642453468,52956cyclictest0-21swapper07:52:520
121459910642353434,52989cyclictest0-21swapper11:16:410
121459910640753444,52963cyclictest0-21swapper08:31:530
121459910638053470,52844cyclictest0-21swapper09:54:270
121459910629453468,52826cyclictest0-21swapper12:03:540
121459910626453391,52808cyclictest0-21swapper07:11:000
121459910626153474,52747cyclictest0-21swapper11:01:160
121459910625053470,52780cyclictest0-21swapper09:02:020
121459910624353411,52832cyclictest0-21swapper08:55:500
121459910623353479,52754cyclictest0-21swapper08:51:590
121459910620553465,52740cyclictest0-21swapper07:31:360
121459910619853466,52732cyclictest0-21swapper08:25:410
121459910619053463,52727cyclictest0-21swapper08:08:060
121459910618153452,52729cyclictest0-21swapper11:35:060
121459910617753412,52765cyclictest0-21swapper10:30:470
121459910617053483,52596cyclictest0-21swapper08:14:080
121459910615853443,52715cyclictest0-21swapper09:59:480
121459910614053433,52707cyclictest0-21swapper09:43:040
121459910612653435,52691cyclictest0-21swapper07:24:140
121459910535553063,52289cyclictest10173-21runrttasks08:21:500
121459910523053017,52211cyclictest19936-21ssh12:06:350
12145995387053407,463cyclictest0-21swapper08:37:050
12145995385453388,466cyclictest0-21swapper12:22:400
12145995384353406,437cyclictest0-21swapper12:10:560
12145995354029,53511cyclictest0-21swapper11:34:360
12145995339526,53369cyclictest0-21swapper09:30:200
12145995333827,53311cyclictest0-21swapper11:40:380
12145995333529,588cyclictest0-21swapper07:44:290
12145995328629,53164cyclictest0-21swapper09:06:530
12145995324327,53150cyclictest0-21swapper07:47:400
121459924761072,1278cyclictest10122-21ssh10:16:030
121459924431092,1221cyclictest29397-21diskmemload10:22:150
121459923221067,1158cyclictest13171-21kworker/0:011:56:420
121459922431092,1023cyclictest1994-21sendmail07:26:140
121459922411044,1077cyclictest3950irq/9-acpi11:49:000
121459922231001,1128cyclictest15272-21kworker/0:010:36:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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