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2026-02-19 - 21:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Thu Feb 19, 2026 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
315919910734853485,53800cyclictest31587-21cyclictest11:30:540
315919910715253444,53610cyclictest2099-21runrttasks08:05:050
315919910705953428,53535cyclictest18182-21ssh11:37:060
315919910675353419,53236cyclictest3950irq/9-acpi10:23:250
315919910671753454,53198cyclictest0-21swapper08:01:240
315919910659153423,53103cyclictest9-21ksoftirqd/010:19:430
315919910657653416,53097cyclictest9-21ksoftirqd/011:29:030
315919910655953394,53101cyclictest0-21swapper09:40:420
315919910653953384,53089cyclictest0-21swapper10:06:300
315919910651053474,53036cyclictest0-21swapper08:46:470
315919910650653475,53031cyclictest0-21swapper07:57:330
315919910650653472,53034cyclictest0-21swapper12:28:210
315919910649953468,53031cyclictest0-21swapper07:27:340
315919910647953462,53017cyclictest0-21swapper11:21:210
315919910647753463,53014cyclictest0-21swapper09:36:010
315919910646953452,53017cyclictest0-21swapper10:13:220
315919910646453453,53011cyclictest0-21swapper11:08:580
315919910645553469,52921cyclictest5350irq/9-uhci_hcd:10:26:350
315919910645153465,52986cyclictest0-21swapper07:33:160
315919910645153445,53006cyclictest0-21swapper09:03:320
315919910644653446,53000cyclictest0-21swapper07:12:200
315919910644153438,53003cyclictest0-21swapper12:21:080
315919910643753457,52884cyclictest6874-21ssh12:09:350
315919910643553436,52999cyclictest0-21swapper09:51:350
315919910630053421,52811cyclictest0-21swapper11:14:390
315919910629653421,52812cyclictest9-21ksoftirqd/008:36:340
315919910629153416,52810cyclictest9-21ksoftirqd/007:18:010
315919910622253434,52788cyclictest0-21swapper08:33:230
315919910621453475,52739cyclictest0-21swapper08:24:500
315919910621053467,52743cyclictest0-21swapper12:14:160
315919910620453437,52767cyclictest0-21swapper07:45:490
315919910620253436,52766cyclictest0-21swapper08:41:550
315919910618853417,52771cyclictest0-21swapper08:28:110
315919910618053415,52765cyclictest0-21swapper09:06:530
315919910617653410,52766cyclictest0-21swapper08:53:590
315919910615253053,53097cyclictest0-21swapper10:37:290
315919910614953441,52708cyclictest0-21swapper07:20:020
315919910614553394,52751cyclictest0-21swapper08:56:190
315919910610353419,52684cyclictest0-21swapper08:12:370
315919910581553005,52808cyclictest2780-21ssh12:02:530
315919910577952976,52800cyclictest812-21sh09:34:510
31591995377427,0cyclictest0-21swapper10:31:470
31591995346626,53440cyclictest0-21swapper12:33:020
31591995340424,53380cyclictest0-21swapper09:46:340
31591995320327,384cyclictest0-21swapper07:38:370
31591995313027,53010cyclictest0-21swapper11:42:570
31591995307026,52950cyclictest0-21swapper11:53:200
31591995305727,52963cyclictest3950irq/9-acpi11:58:420
31591995301927,52899cyclictest0-21swapper09:17:560
315919924721060,1284cyclictest2099-21runrttasks10:48:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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