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2025-11-30 - 23:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Sun Nov 30, 2025 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3214799210248105303,104943cyclictest8164-21ssh11:11:390
321479910705753465,53528cyclictest3950irq/9-acpi10:39:290
321479910675753416,53272cyclictest0-21swapper07:54:020
321479910672253436,53286cyclictest0-21swapper11:21:110
321479910671353456,53194cyclictest32140-21cyclictest12:37:530
321479910662553373,53164cyclictest3950irq/9-acpi09:16:250
321479910650053471,53029cyclictest0-21swapper09:21:570
321479910649253463,53029cyclictest0-21swapper08:10:460
321479910648653465,53021cyclictest0-21swapper12:20:480
321479910648553416,52973cyclictest4335-21diskmemload11:51:100
321479910646353455,53008cyclictest0-21swapper12:11:560
321479910644753400,53047cyclictest0-21swapper11:32:250
321479910643853397,53041cyclictest0-21swapper11:57:420
321479910643853396,53042cyclictest0-21swapper11:44:280
321479910643153435,52996cyclictest0-21swapper11:28:030
321479910640153378,53023cyclictest0-21swapper10:34:280
321479910637653424,52888cyclictest32140-21cyclictest08:36:140
321479910634053419,52856cyclictest133750irq/9-eth009:12:440
321479910631453471,52843cyclictest0-21swapper09:08:130
321479910629953394,52842cyclictest9-21ksoftirqd/009:48:140
321479910628353436,52847cyclictest0-21swapper10:20:040
321479910625053402,52848cyclictest0-21swapper07:14:400
321479910624753383,52800cyclictest9-21ksoftirqd/007:15:510
321479910621553477,52738cyclictest0-21swapper08:31:520
321479910621353472,52741cyclictest0-21swapper08:41:450
321479910621153475,52736cyclictest0-21swapper10:41:100
321479910620353468,52735cyclictest0-21swapper12:33:020
321479910620353468,52735cyclictest0-21swapper07:28:440
321479910618853464,52724cyclictest0-21swapper08:49:380
321479910618553479,52706cyclictest0-21swapper07:39:580
321479910618553416,52769cyclictest0-21swapper09:39:220
321479910617553409,52766cyclictest0-21swapper07:59:030
321479910616653404,52762cyclictest0-21swapper08:58:000
321479910616353451,52712cyclictest0-21swapper09:04:320
321479910584253303,52539cyclictest0-21swapper10:57:040
321479910515053055,52090cyclictest0-21swapper11:03:360
32147995403553441,497cyclictest29586-21ssh12:26:300
32147995389053425,465cyclictest0-21swapper09:54:560
32147995384253444,398cyclictest0-21swapper10:01:480
32147995383153392,439cyclictest0-21swapper10:14:420
32147995358953438,151cyclictest0-21swapper08:03:440
32147995358653409,177cyclictest0-21swapper07:41:080
32147995355653405,151cyclictest0-21swapper08:25:310
32147995346653364,81cyclictest30175-21ssh09:27:390
32147995340531,53250cyclictest15873-21ssh12:07:450
32147995305625,53031cyclictest0-21swapper07:49:500
32147995304025,53015cyclictest0-21swapper08:08:060
32147995298126,52864cyclictest0-21swapper08:21:190
32147995297025,0cyclictest3950irq/9-acpi11:38:560
32147995294852926,21cyclictest0-21swapper09:31:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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