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2026-02-08 - 14:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Sun Feb 08, 2026 12:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
529999209916105434,104480cyclictest0-21swapper12:10:530
52999910731753465,53729cyclictest31922-21rm10:10:090
52999910729353472,53724cyclictest3261-21gnome-power-man08:51:060
52999910668153425,53165cyclictest0-21swapper07:21:100
52999910663553432,53112cyclictest9-21ksoftirqd/008:59:180
52999910659253435,53060cyclictest2099-21runrttasks08:04:520
52999910654553384,53071cyclictest0-21swapper11:56:490
52999910654153441,53100cyclictest0-21swapper08:32:100
52999910653253437,53095cyclictest0-21swapper12:24:070
52999910651953455,53064cyclictest0-21swapper07:47:070
52999910650753442,53065cyclictest0-21swapper09:58:450
52999910649953425,53074cyclictest0-21swapper10:43:480
52999910649853469,53029cyclictest0-21swapper09:32:180
52999910648853448,53040cyclictest0-21swapper07:25:010
52999910644853428,53020cyclictest0-21swapper11:37:540
52999910644653402,53044cyclictest0-21swapper08:18:260
52999910644653401,53045cyclictest0-21swapper09:13:020
52999910643453395,53039cyclictest0-21swapper09:27:560
52999910642653437,52989cyclictest0-21swapper10:56:420
52999910640353474,52865cyclictest3950irq/9-acpi12:01:510
52999910639853452,52946cyclictest0-21swapper07:59:010
52999910639853422,52976cyclictest0-21swapper11:10:360
52999910639153437,52866cyclictest5280-21cyclictest08:08:240
52999910632053432,52799cyclictest3950irq/9-acpi11:03:240
52999910631153441,52870cyclictest0-21swapper08:40:030
52999910627153379,52827cyclictest0-21swapper10:35:060
52999910624653409,52744cyclictest0-21swapper11:32:020
52999910615453398,52756cyclictest0-21swapper11:25:100
52999910612453425,52699cyclictest0-21swapper07:18:390
52999910612153427,52694cyclictest0-21swapper08:29:500
52999910606552999,53064cyclictest0-21swapper07:11:570
52999910605752967,53088cyclictest0-21swapper11:47:570
52999910584953322,52527cyclictest0-21swapper10:05:570
52999910534753071,52273cyclictest5839-21ssh12:39:120
52999910520852906,52301cyclictest9-21ksoftirqd/010:20:110
52999910517153051,52118cyclictest0-21swapper11:44:060
52999910517053062,52103cyclictest0-21swapper10:15:200
52999910511453011,52101cyclictest0-21swapper12:31:390
52999910509553000,52093cyclictest0-21swapper09:35:590
52999910500352907,52094cyclictest0-21swapper12:19:560
5299995356153429,41cyclictest0-21swapper08:23:580
5299995355826,487cyclictest0-21swapper10:28:240
5299995327226,489cyclictest0-21swapper08:49:550
5299995321627,0cyclictest0-21swapper07:40:560
5299995313227,53105cyclictest0-21swapper08:39:220
5299995312926,53103cyclictest0-21swapper09:02:290
529999531019,53090cyclictest0-21swapper09:44:310
52999924071098,1183cyclictest1994-21sendmail07:52:290
52999923351077,1160cyclictest20749-21ssh09:53:440
52999921651079,963cyclictest9-21ksoftirqd/012:06:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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