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2026-06-01 - 08:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Mon Jun 01, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14469910697153428,53421cyclictest9862-21ssh23:19:570
14469910665553380,53210cyclictest9-21ksoftirqd/023:36:220
14469910661253456,53156cyclictest1439-21cyclictest00:25:360
14469910658753468,53119cyclictest0-21swapper20:04:310
14469910655653391,53099cyclictest0-21swapper21:39:390
14469910655053391,53069cyclictest0-21swapper21:25:040
14469910654753385,53098cyclictest9-21ksoftirqd/021:10:100
14469910651853476,52944cyclictest32529-21munin-node21:30:260
14469910651553475,53040cyclictest0-21swapper21:41:290
14469910651253479,53033cyclictest0-21swapper22:53:500
14469910651253477,53035cyclictest0-21swapper00:35:590
14469910650553478,53027cyclictest0-21swapper21:46:200
14469910649753470,53027cyclictest0-21swapper23:02:530
14469910649253468,53024cyclictest0-21swapper23:12:550
14469910648653461,53025cyclictest0-21swapper00:34:390
14469910646753452,53015cyclictest0-21swapper23:50:060
14469910645453446,53008cyclictest0-21swapper00:05:310
14469910643953443,52996cyclictest0-21swapper21:18:430
14469910642853433,52995cyclictest0-21swapper23:26:290
14469910642253422,53000cyclictest0-21swapper19:47:060
14469910629353061,53222cyclictest0-21swapper00:15:030
14469910623253434,52798cyclictest0-21swapper21:04:380
14469910623053478,52752cyclictest0-21swapper20:35:400
14469910620453463,52741cyclictest0-21swapper20:23:170
14469910620353468,52735cyclictest0-21swapper20:17:050
14469910619353419,52774cyclictest0-21swapper20:28:580
14469910616453448,52716cyclictest0-21swapper19:53:580
14469910616453446,52718cyclictest0-21swapper19:30:410
14469910616153402,52759cyclictest0-21swapper19:57:190
14469910615853401,52757cyclictest0-21swapper23:43:040
14469910615453439,52715cyclictest0-21swapper22:45:480
14469910614653437,52709cyclictest0-21swapper19:24:090
14469910614353469,52674cyclictest0-21swapper20:34:300
14469910613953430,52709cyclictest0-21swapper20:47:540
14469910612353425,52698cyclictest0-21swapper19:40:340
14469910605652991,53063cyclictest0-21swapper23:09:440
14469910557153059,52509cyclictest11603-21rm00:10:320
14469910531852937,52379cyclictest3819-21ssh22:22:210
1446995390053431,469cyclictest0-21swapper20:52:250
1446995369418,53556cyclictest0-21swapper21:20:530
1446995358153430,151cyclictest0-21swapper21:05:390
1446995339825,53373cyclictest0-21swapper22:13:280
1446995339618,53378cyclictest0-21swapper00:22:460
1446995336727,53340cyclictest0-21swapper19:29:410
1446995329524,53177cyclictest0-21swapper23:22:380
1446995325718,53145cyclictest0-21swapper22:18:200
1446995319126,0cyclictest0-21swapper20:56:460
1446995308126,0cyclictest18917-21diskmemload23:55:180
1446995307925,53054cyclictest0-21swapper21:51:520
1446995307818,0cyclictest18917-21diskmemload21:56:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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