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2026-02-19 - 02:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Thu Feb 19, 2026 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
165769910740453483,53800cyclictest5200-21munin-node19:50:130
165769910700653466,53540cyclictest0-21swapper21:34:530
165769910686753410,53367cyclictest12475-21kworker/u2:123:42:000
165769910668453426,53167cyclictest11-21rcu_preempt00:34:150
165769910667053388,53190cyclictest0-21swapper20:28:440
165769910656553385,53060cyclictest0-21swapper21:37:540
165769910656453395,53078cyclictest0-21swapper20:15:300
165769910654653386,53097cyclictest9-21ksoftirqd/020:50:300
165769910652853376,53089cyclictest9-21ksoftirqd/000:21:510
165769910652253482,53040cyclictest0-21swapper00:04:160
165769910652053417,53037cyclictest0-21swapper20:42:080
165769910648453471,53013cyclictest0-21swapper23:00:380
165769910645553444,53011cyclictest0-21swapper21:01:340
165769910644853443,53005cyclictest0-21swapper21:51:280
165769910644653451,52995cyclictest0-21swapper20:33:250
165769910643453394,53040cyclictest0-21swapper21:16:280
165769910642953432,52997cyclictest0-21swapper00:16:300
165769910642853437,52991cyclictest0-21swapper23:06:200
165769910639753445,52952cyclictest0-21swapper19:39:000
165769910635653464,52829cyclictest3950irq/9-acpi00:35:350
165769910631453400,52822cyclictest0-21swapper20:11:090
165769910627653381,52802cyclictest0-21swapper19:33:580
165769910624053468,52772cyclictest0-21swapper22:35:510
165769910618653465,52721cyclictest0-21swapper19:27:060
165769910616753447,52720cyclictest0-21swapper20:37:470
165769910616353402,52761cyclictest0-21swapper00:13:590
165769910616053447,52713cyclictest0-21swapper20:49:200
165769910615753447,52710cyclictest0-21swapper21:07:150
165769910612253422,52700cyclictest0-21swapper22:06:420
165769910575152979,52770cyclictest1907-21snmpd23:11:210
165769910566253001,52658cyclictest6089-21ssh23:32:470
165769910536053062,52298cyclictest0-21swapper22:00:000
165769910509552993,52100cyclictest0-21swapper21:57:200
165769910504352937,52104cyclictest0-21swapper00:09:280
16576995372716,53618cyclictest0-21swapper00:25:020
16576995371527,53595cyclictest9-21ksoftirqd/022:12:540
16576995363925,53493cyclictest0-21swapper22:34:500
16576995362018,0cyclictest0-21swapper22:21:370
16576995358824,53472cyclictest0-21swapper20:20:020
16576995358553434,151cyclictest0-21swapper22:46:140
16576995357153421,150cyclictest0-21swapper21:12:570
16576995342325,53398cyclictest0-21swapper23:24:450
16576995333926,53313cyclictest0-21swapper22:44:230
16576995324517,53202cyclictest0-21swapper22:29:390
16576995318753131,56cyclictest0-21swapper22:54:460
1657699530979,53083cyclictest0-21swapper23:29:260
16576995308025,52963cyclictest0-21swapper23:56:240
16576995277727,52750cyclictest0-21swapper23:48:120
165769922591079,1156cyclictest2099-21runrttasks21:47:270
165769920261015,884cyclictest5869-21diskmemload23:53:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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