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2026-02-05 - 11:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 50 highest latencies:
System rack6slot6 (updated Thu Feb 05, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2769299210831105361,105468cyclictest0-21swapper23:13:150
276929910665953382,53186cyclictest0-21swapper22:20:200
276929910654753386,53096cyclictest0-21swapper23:28:390
276929910651053473,53037cyclictest0-21swapper22:46:470
276929910645053403,53047cyclictest0-21swapper21:24:240
276929910639853472,52835cyclictest0-21swapper22:03:450
276929910639553451,52944cyclictest0-21swapper23:20:470
276929910639053449,52941cyclictest0-21swapper19:46:350
276929910634953428,52921cyclictest0-21swapper20:56:250
276929910634653461,52820cyclictest9-21ksoftirqd/020:07:410
276929910624953385,52799cyclictest0-21swapper21:06:590
276929910623753442,52795cyclictest0-21swapper21:03:170
276929910621553412,52766cyclictest0-21swapper21:41:180
276929910620553466,52739cyclictest0-21swapper00:16:230
276929910557353017,52550cyclictest19345-21ssh22:14:280
276929910500352918,52083cyclictest0-21swapper19:57:490
2769299531258,9cyclictest0-21swapper21:59:540
27692995278127,52754cyclictest0-21swapper19:27:000
276929924991077,1300cyclictest17987-21rm00:32:180
276929924781081,1273cyclictest14546-21ssh22:54:190
276929924761096,1282cyclictest8564-21ssh23:31:300
276929924701060,1257cyclictest18877-21ssh23:46:240
276929924571093,1238cyclictest9-21ksoftirqd/021:48:000
276929923371040,1205cyclictest9-21ksoftirqd/021:25:040
276929923051073,1109cyclictest0-21swapper20:29:480
276929923031079,1101cyclictest0-21swapper19:39:430
276929923021094,1084cyclictest21295-21ssh00:36:590
276929922911091,1075cyclictest1741-21hald21:34:570
276929922531100,1061cyclictest11-21rcu_preempt19:32:510
276929921841033,1053cyclictest11847-21ssh00:23:550
276929921401038,1064cyclictest14429-21ssh22:06:160
276929921021041,1026cyclictest0-21swapper22:30:020
276929920661038,939cyclictest3950irq/9-acpi22:58:510
276929920591003,1022cyclictest0-21swapper21:19:420
276929920531013,1005cyclictest0-21swapper00:14:530
27692992018999,952cyclictest134850irq/9-eth023:15:360
276929920151096,825cyclictest3950irq/9-acpi21:10:290
276929920081093,824cyclictest3950irq/9-acpi22:16:280
27692991964953,977cyclictest0-21swapper23:58:580
27692991936941,958cyclictest23785-21ssh23:06:530
276929919141087,733cyclictest0-21swapper00:00:590
276929918741016,823cyclictest7197-21ssh22:43:260
27692991838992,809cyclictest17050-21ssh23:44:540
27692991805930,840cyclictest0-21swapper20:53:040
276929918031010,793cyclictest0-21swapper21:37:170
276929917731063,710cyclictest0-21swapper20:31:080
276929917571095,538cyclictest182092sleep020:17:340
276929917261026,700cyclictest0-21swapper23:36:520
276929916871098,589cyclictest0-21swapper20:22:560
276929916831016,629cyclictest15130-21ssh00:28:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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