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2026-01-13 - 21:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the 792 highest latencies:
System rack6slot6 (updated Tue Jan 13, 2026 12:43:35)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304019910678453422,53362cyclictest3950irq/9-acpi11:55:550
304019910677653423,53353cyclictest0-21swapper08:08:190
304019910664453466,53178cyclictest0-21swapper11:24:560
304019910660953448,53161cyclictest0-21swapper10:28:190
304019910658153460,53121cyclictest0-21swapper08:17:010
304019910650953465,53044cyclictest0-21swapper09:05:250
304019910644753400,53047cyclictest0-21swapper07:24:060
304019910644453400,53044cyclictest0-21swapper10:06:430
304019910643953396,53043cyclictest0-21swapper08:53:120
304019910642653429,52997cyclictest0-21swapper10:36:220
304019910641153428,52983cyclictest0-21swapper09:35:440
304019910636353469,52894cyclictest0-21swapper08:48:100
304019910626853408,52767cyclictest9-21ksoftirqd/012:15:100
304019910626253449,52813cyclictest0-21swapper09:01:540
304019910623853471,52730cyclictest0-21swapper08:44:490
304019910619753465,52732cyclictest0-21swapper07:19:050
304019910619353464,52729cyclictest0-21swapper09:42:560
304019910580853364,52444cyclictest0-21swapper10:31:400
304019910560152951,52647cyclictest14345-21diskmemload12:21:220
304019910540053046,52351cyclictest4867-21ssh12:07:480
304019910502452928,52094cyclictest0-21swapper11:42:210
30401995375753423,334cyclictest0-21swapper11:05:400
30401995370232,569cyclictest0-21swapper08:56:330
30401995359553419,176cyclictest0-21swapper08:10:300
30401995353953387,152cyclictest0-21swapper08:03:480
30401995350353481,0cyclictest9-21ksoftirqd/007:47:330
30401995331626,53197cyclictest0-21swapper07:42:210
30401995326026,53234cyclictest0-21swapper07:32:290
30401995317426,53148cyclictest0-21swapper12:10:490
30401995317225,53147cyclictest0-21swapper08:38:080
30401995311626,53090cyclictest0-21swapper08:30:350
30401995307527,53048cyclictest0-21swapper09:24:210
30401995292952910,18cyclictest0-21swapper11:16:230
304019924561085,1245cyclictest13411-21ssh11:32:480
304019924401067,1248cyclictest17573-21ssh09:14:380
304019923941040,1230cyclictest14345-21diskmemload11:35:390
304019923691041,1202cyclictest27731-21rm10:18:360
304019923401078,1171cyclictest3950irq/9-acpi09:19:290
304019922531039,1190cyclictest14345-21diskmemload10:00:510
304019921911072,1021cyclictest14345-21diskmemload10:24:080
304019921471049,974cyclictest2272-21munin-node07:14:130
304019921151046,948cyclictest0-21swapper09:26:010
304019921101044,1013cyclictest13325-21ssh09:56:400
304019921091080,907cyclictest0-21swapper11:54:340
304019921091030,1079cyclictest0-21swapper12:35:460
304019921001039,1027cyclictest0-21swapper07:56:250
304019920981039,1025cyclictest0-21swapper09:51:590
304019920831070,921cyclictest0-21swapper12:33:350
304019920641029,1014cyclictest0-21swapper08:22:130
304019920321033,999cyclictest0-21swapper10:42:330
304019919941057,838cyclictest23145-21ssh10:10:540
30401991971993,945cyclictest3950irq/9-acpi10:57:080
304019919701002,934cyclictest0-21swapper07:52:040
304019918921045,786cyclictest0-21swapper12:28:040
304019918771021,762cyclictest0-21swapper07:38:000
304019918741031,843cyclictest0-21swapper09:32:030
304019918631047,696cyclictest0-21swapper12:01:060
304019918251078,622cyclictest23612-21ssh11:47:520
304019918101074,736cyclictest0-21swapper11:27:560
304019917631092,671cyclictest0-21swapper11:14:430
304019917611054,707cyclictest0-21swapper10:54:170
304019917491068,616cyclictest9-21ksoftirqd/008:27:040
304019917211025,574cyclictest14658-21ssh10:46:240
304019915911084,507cyclictest0-21swapper07:28:370
30401991539997,480cyclictest9-21ksoftirqd/009:48:280
304019915271046,389cyclictest0-21swapper11:02:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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