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2026-02-11 - 09:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6 (updated Wed Feb 11, 2026 00:43:28)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
178409910659253473,53119cyclictest0-21swapper22:10:560
178409910644653401,53045cyclictest0-21swapper20:45:510
178409910638453400,52984cyclictest0-21swapper19:47:550
178409910621753476,52741cyclictest0-21swapper20:28:060
178409910614453060,53082cyclictest0-21swapper22:45:260
178409910614153057,53082cyclictest0-21swapper19:57:070
178409910611553053,53060cyclictest0-21swapper22:36:130
178409910611353034,53077cyclictest0-21swapper00:28:150
178409910609753003,53092cyclictest0-21swapper21:19:510
178409910604352945,53096cyclictest0-21swapper21:38:060
178409910603852959,53077cyclictest0-21swapper23:54:460
178409910601653000,53014cyclictest16577-21ssh21:32:550
178409910600952929,53078cyclictest21851-21kworker/0:219:26:390
178409910547553189,52276cyclictest0-21swapper21:28:040
178409910516453059,52103cyclictest0-21swapper23:07:020
178409910515553050,52100cyclictest0-21swapper21:57:120
178409910515153044,52105cyclictest0-21swapper22:55:490
178409910513352976,52154cyclictest25449-21ssh22:30:110
178409910512953029,52098cyclictest0-21swapper19:36:310
178409910511953022,52095cyclictest0-21swapper00:01:480
178409910511053021,52087cyclictest0-21swapper00:10:300
178409910511053007,52101cyclictest0-21swapper21:05:470
178409910508852991,52095cyclictest0-21swapper23:02:210
178409910508752991,52094cyclictest0-21swapper23:42:220
178409910508352979,52102cyclictest0-21swapper23:19:160
178409910508152980,52099cyclictest0-21swapper21:43:380
178409910507252979,52091cyclictest0-21swapper00:05:390
178409910503852946,52087cyclictest0-21swapper22:01:030
178409910502452900,52122cyclictest0-21swapper20:19:240
178409910494852897,52049cyclictest0-21swapper23:58:070
17840995401726,53891cyclictest2099-21runrttasks19:41:230
1784099530988,53088cyclictest0-21swapper19:34:010
1784099530968,53086cyclictest0-21swapper00:32:570
17840995307626,53050cyclictest0-21swapper20:39:190
17840995307425,52957cyclictest0-21swapper21:02:560
17840995278925,52764cyclictest0-21swapper20:07:500
17840995228716,52267cyclictest0-21swapper20:50:330
17840995219511,52182cyclictest134850irq/9-eth023:20:460
178409924441046,1274cyclictest2099-21runrttasks23:33:500
178409919841052,866cyclictest134850irq/9-eth019:51:060
178409919301066,770cyclictest0-21swapper20:59:150
178409919301064,772cyclictest0-21swapper20:32:370
178409917321006,690cyclictest17319-21ssh22:18:380
17840991589757,829cyclictest0-21swapper21:51:000
17840991559756,800cyclictest0-21swapper23:13:540
17840991519753,762cyclictest0-21swapper00:21:430
17840991509734,771cyclictest0-21swapper21:13:390
17840991502684,815cyclictest0-21swapper22:50:370
178409914681097,371cyclictest0-21swapper20:01:080
17840991457719,726cyclictest27413-21ssh21:47:490
178409914551094,361cyclictest0-21swapper20:42:400
178409914491092,357cyclictest0-21swapper21:23:020
178409914361041,395cyclictest0-21swapper22:20:590
178409914151072,343cyclictest0-21swapper22:40:040
17840991337625,705cyclictest0-21swapper23:49:340
17840991329619,708cyclictest0-21swapper22:09:560
17840991296605,688cyclictest0-21swapper23:38:210
17840991223595,626cyclictest0-21swapper00:35:580
17840991216618,595cyclictest13081-21hwlatdetect-tra19:16:460
17840991203707,486cyclictest2099-21runrttasks23:29:280
17840991202610,589cyclictest8419-21hwlatdetect-tra19:11:440
17840991182599,581cyclictest134850irq/9-eth022:28:510
17840991173592,577cyclictest6014-21hwlatdetect-tra19:20:570
17840991163501,660cyclictest0-21swapper00:16:120
1784099111024,961cyclictest1907-21snmpd20:10:110
17840991087462,623cyclictest0-21swapper20:22:040
1233122020,2sleep019239-21hwlatdetect-tra19:05:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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