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2026-03-09 - 09:33
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6 (updated Mon Mar 09, 2026 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
245319910712853459,53547cyclictest27949-21diskmemload23:56:000
245319910672553483,53242cyclictest0-21swapper23:02:050
245319910670153449,53186cyclictest0-21swapper20:20:590
245319910668553464,53098cyclictest27949-21diskmemload23:14:390
245319910657153455,53116cyclictest0-21swapper00:18:570
245319910654453389,53092cyclictest0-21swapper22:13:210
245319910653353443,53090cyclictest0-21swapper19:50:500
245319910651253470,53042cyclictest0-21swapper20:11:060
245319910649053468,53022cyclictest0-21swapper20:45:560
245319910649053463,53027cyclictest0-21swapper00:36:520
245319910648853462,53026cyclictest0-21swapper20:58:090
245319910648753433,53054cyclictest0-21swapper22:18:320
245319910648053458,53022cyclictest0-21swapper22:40:390
245319910647953471,53008cyclictest0-21swapper21:36:400
245319910645953466,52993cyclictest0-21swapper21:06:520
245319910645453466,52988cyclictest0-21swapper22:38:080
245319910645453449,53005cyclictest0-21swapper23:39:560
245319910644953401,53048cyclictest0-21swapper23:48:080
245319910644853445,53003cyclictest0-21swapper00:34:420
245319910644853399,53049cyclictest0-21swapper21:13:040
245319910644453455,52989cyclictest0-21swapper23:18:500
245319910643653396,53040cyclictest0-21swapper23:43:570
245319910640953428,52981cyclictest0-21swapper19:37:260
245319910622553475,52750cyclictest0-21swapper20:29:210
245319910618053424,52756cyclictest0-21swapper19:29:040
245319910615453440,52714cyclictest0-21swapper23:23:010
245319910614853397,52751cyclictest0-21swapper22:24:140
245319910613053431,52699cyclictest0-21swapper00:29:500
245319910611953419,52700cyclictest0-21swapper20:17:580
245319910588853041,52845cyclictest25121-21ssh21:53:050
245319910578453324,52460cyclictest0-21swapper21:47:030
245319910541953165,52254cyclictest0-21swapper21:40:010
24531995393753401,472cyclictest9-21ksoftirqd/020:42:450
24531995389953460,439cyclictest0-21swapper22:52:420
24531995383353432,401cyclictest0-21swapper20:34:320
24531995362253446,176cyclictest0-21swapper21:20:560
24531995360553427,178cyclictest0-21swapper21:28:380
24531995354025,53515cyclictest0-21swapper19:57:020
245319928982861,33cyclictest1741-21hald22:33:070
245319923221082,1114cyclictest2099-21runrttasks20:39:140
245319923031089,1115cyclictest1907-21snmpd22:00:070
245319922311088,1052cyclictest9-21ksoftirqd/023:07:570
245319922131062,1056cyclictest0-21swapper19:24:120
245319921511099,927cyclictest13571-21ssh00:00:120
245319921411088,954cyclictest27949-21diskmemload22:27:550
245319921041086,923cyclictest0-21swapper00:23:380
245319920881039,1028cyclictest0-21swapper23:50:590
245319920711019,931cyclictest0-21swapper19:48:290
245319919861031,860cyclictest0-21swapper00:12:250
245319919481017,895cyclictest19189-21ssh00:07:540
245319919301089,718cyclictest2099-21runrttasks23:34:140
245319919151010,872cyclictest134850irq/9-eth022:48:210
245319918651090,708cyclictest3950irq/9-acpi21:58:270
24531991767927,803cyclictest27949-21diskmemload22:05:390
245319917241007,626cyclictest24524-21cyclictest23:27:520
245319916311045,586cyclictest0-21swapper21:33:090
245319916261080,481cyclictest134850irq/9-eth020:06:340
245319915801050,435cyclictest0-21swapper19:41:570
245319915521037,423cyclictest9-21ksoftirqd/020:51:070
245319915301091,439cyclictest0-21swapper22:59:440
245319914791000,415cyclictest0-21swapper20:02:330
245319914571097,360cyclictest0-21swapper19:32:040
245319914491087,362cyclictest0-21swapper21:01:500
245319914391082,357cyclictest0-21swapper21:16:040
24531991061623,434cyclictest22846-21hwlatdetect-tra19:16:500
24531991003598,400cyclictest15664-21hwlatdetect-tra19:13:590
2927622060,1sleep029277-21hwlatdetect-tra19:08:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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