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2026-03-03 - 03:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack6slot6 (updated Tue Mar 03, 2026 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
315769910706853469,53476cyclictest17536-21ssh23:03:060
315769910702253421,53507cyclictest0-21swapper23:59:020
315769910680953474,53335cyclictest0-21swapper22:05:300
315769910671353422,53291cyclictest0-21swapper00:12:260
315769910669753470,53163cyclictest9-21ksoftirqd/023:15:400
315769910669253463,53229cyclictest0-21swapper21:12:440
315769910664653476,53107cyclictest9-21ksoftirqd/021:34:410
315769910664453473,53105cyclictest0-21swapper21:23:180
315769910664453420,53224cyclictest3950irq/9-acpi23:43:380
315769910660653479,53127cyclictest0-21swapper21:52:060
315769910658553467,53118cyclictest0-21swapper22:20:540
315769910657353469,53041cyclictest31567-21cyclictest23:20:310
315769910655153403,53148cyclictest0-21swapper20:14:380
315769910650053475,53025cyclictest0-21swapper21:49:150
315769910648553452,53033cyclictest0-21swapper20:52:490
315769910645653402,53054cyclictest0-21swapper22:29:370
315769910645253448,53004cyclictest0-21swapper20:07:260
315769910643153396,52971cyclictest1856-21kworker/0:021:19:060
315769910642853432,52996cyclictest0-21swapper23:12:390
315769910642653403,53023cyclictest0-21swapper19:49:510
315769910642453391,53033cyclictest0-21swapper00:07:250
315769910637853387,52926cyclictest0-21swapper19:31:250
315769910637653385,52926cyclictest0-21swapper00:01:430
315769910636653444,52922cyclictest0-21swapper21:04:520
315769910635853376,52916cyclictest0-21swapper20:29:220
315769910629953410,52889cyclictest0-21swapper19:44:190
315769910518053060,52118cyclictest0-21swapper23:46:390
315769910510253000,52100cyclictest0-21swapper21:59:280
31576995331225,53219cyclictest0-21swapper20:44:260
31576995328227,53255cyclictest0-21swapper23:06:170
31576995326026,0cyclictest0-21swapper00:38:040
31576995317025,53080cyclictest9-21ksoftirqd/020:39:550
31576995305027,53023cyclictest0-21swapper20:20:290
31576995299126,52965cyclictest0-21swapper22:13:220
31576995276624,52742cyclictest0-21swapper20:32:430
315769924751082,1268cyclictest14360-21ssh00:32:420
315769924361081,1257cyclictest29818-21munin-node19:35:160
315769924241095,1232cyclictest4361-21diskmemload21:35:410
315769923301096,1109cyclictest11927-21ssh00:29:510
315769922501030,1172cyclictest27403-21ssh21:43:030
315769922471027,1198cyclictest8459-21ssh22:02:190
315769922241013,1211cyclictest5470-21ssh23:32:250
315769921321029,1005cyclictest4361-21diskmemload22:56:140
315769920801023,1020cyclictest4783-21ssh00:19:080
315769920621014,1010cyclictest17524-21ssh21:28:490
315769919481041,813cyclictest0-21swapper00:22:290
315769919411040,811cyclictest0-21swapper19:53:010
315769919071037,777cyclictest0-21swapper22:51:130
31576991898925,963cyclictest1297-21kworker/0:222:45:210
315769918971090,716cyclictest9-21ksoftirqd/022:40:300
315769918781085,702cyclictest9-21ksoftirqd/020:01:340
315769918531044,809cyclictest0-21swapper21:07:430
315769918261079,649cyclictest8590-21ssh23:36:460
315769917481093,655cyclictest0-21swapper22:33:580
315769916811101,580cyclictest0-21swapper19:29:250
315769916721016,618cyclictest18583-21ssh22:17:030
315769916671095,572cyclictest0-21swapper23:52:200
315769916631093,570cyclictest0-21swapper22:36:290
315769916591092,567cyclictest0-21swapper20:57:000
315769916301078,552cyclictest0-21swapper20:17:180
315769916241097,435cyclictest9-21ksoftirqd/019:59:230
315769915391014,431cyclictest0-21swapper20:46:270
315769915141013,434cyclictest0-21swapper23:28:440
31576991159620,537cyclictest23546-21hwlatdetect-tra19:14:100
31576991081577,500cyclictest4535-21hwlatdetect-tra19:19:520
31576991002541,458cyclictest10497-21grep19:22:430
179422290,2sleep01795-21hwlatdetect-tra19:08:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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