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2024-04-24 - 18:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot7.osadl.org (updated Thu Jan 11, 2024 00:44:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,4564
"cycles":100000000,4563
"load":"idle",4562
"condition":{4561
"clock":"2300"4559
"family":"x86",4558
"vendor":"Intel",4557
"processor":{4555
"dataset":"2024-01-08T15:37:35+0100"4553
"origin":"2024-01-08T12:43:22+0100",4552
"timestamps":{4551
"granularity":"microseconds"4549
7310:34:304547
80,10:34:374546
"maxima":[4545
010:33:174542
0,10:33:174541
0,10:33:174540
0,10:33:174539
0,10:33:174538
0,10:33:174537
0,10:33:174536
0,10:33:174535
0,10:33:174534
0,10:33:174533
0,10:33:174532
0,10:33:174531
0,10:33:174530
0,10:33:174529
0,10:33:174528
0,10:33:174527
0,10:33:174526
0,10:33:174525
0,10:33:174524
0,10:33:174523
0,10:33:174522
0,10:33:174521
0,10:33:174520
0,10:33:174519
0,10:33:174518
0,10:33:174517
0,10:33:174516
0,10:33:174515
0,10:33:174514
0,10:33:174513
0,10:33:174512
0,10:33:174511
0,10:33:174510
0,10:33:174509
0,10:33:174508
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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