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2026-06-18 - 15:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot7.osadl.org (updated Thu Jun 18, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,4564
"cycles":100000000,4563
"load":"idle",4562
"condition":{4561
"clock":"2300"4559
"family":"x86",4558
"vendor":"Intel",4557
"processor":{4555
"dataset":"2024-01-08T15:37:35+0100"4553
"origin":"2024-01-08T12:43:22+0100",4552
"timestamps":{4551
"granularity":"microseconds"4549
7315:30:544547
80,15:31:014546
"maxima":[4545
015:29:414542
0,15:29:414541
0,15:29:414540
0,15:29:414539
0,15:29:414538
0,15:29:414537
0,15:29:414536
0,15:29:414535
0,15:29:414534
0,15:29:414533
0,15:29:414532
0,15:29:414531
0,15:29:414530
0,15:29:414529
0,15:29:414528
0,15:29:414527
0,15:29:414526
0,15:29:414525
0,15:29:414524
0,15:29:414523
0,15:29:414522
0,15:29:414521
0,15:29:414520
0,15:29:414519
0,15:29:414518
0,15:29:414517
0,15:29:414516
0,15:29:414515
0,15:29:414514
0,15:29:414513
0,15:29:414512
0,15:29:414511
0,15:29:414510
0,15:29:414509
0,15:29:414508
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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