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2026-08-17 - 14:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot7.osadl.org (updated Mon Aug 17, 2026 12:44:21)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,4564
"cycles":100000000,4563
"load":"idle",4562
"condition":{4561
"clock":"2300"4559
"family":"x86",4558
"vendor":"Intel",4557
"processor":{4555
"dataset":"2024-01-08T15:37:35+0100"4553
"origin":"2024-01-08T12:43:22+0100",4552
"timestamps":{4551
"granularity":"microseconds"4549
7312:23:194547
80,12:23:264546
"maxima":[4545
012:22:064542
0,12:22:064541
0,12:22:064540
0,12:22:064539
0,12:22:064538
0,12:22:064537
0,12:22:064536
0,12:22:064535
0,12:22:064534
0,12:22:064533
0,12:22:064532
0,12:22:064531
0,12:22:064530
0,12:22:064529
0,12:22:064528
0,12:22:064527
0,12:22:064526
0,12:22:064525
0,12:22:064524
0,12:22:064523
0,12:22:064522
0,12:22:064521
0,12:22:064520
0,12:22:064519
0,12:22:064518
0,12:22:064517
0,12:22:064516
0,12:22:064515
0,12:22:064514
0,12:22:064513
0,12:22:064512
0,12:22:064511
0,12:22:064510
0,12:22:064509
0,12:22:064508
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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