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2026-09-11 - 10:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Sep 11, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811580,1136rtkit-daemon4793-21kerneloops19:08:543
845399670662,6cyclictest4793-21kerneloops21:44:282
845399667657,8cyclictest4793-21kerneloops22:32:482
844199666653,11cyclictest4793-21kerneloops21:11:260
846299664655,7cyclictest4793-21kerneloops00:17:183
845399664660,2cyclictest4793-21kerneloops21:20:132
845399663653,8cyclictest4793-21kerneloops21:19:522
844899662655,1cyclictest4793-21kerneloops20:55:201
846299661654,5cyclictest4793-21kerneloops22:01:213
845399661653,6cyclictest4793-21kerneloops20:55:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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