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2026-05-13 - 10:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Wed May 13, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2304899638631,5cyclictest4793-21kerneloops21:22:182
2305499634627,5cyclictest4793-21kerneloops22:07:043
2303599634623,9cyclictest4793-21kerneloops22:51:020
2305499633625,6cyclictest4793-21kerneloops23:39:493
2305499633624,7cyclictest4793-21kerneloops22:32:053
2303599633625,6cyclictest4793-21kerneloops20:05:300
2303599632625,6cyclictest4793-21kerneloops21:11:290
2305499631626,4cyclictest4793-21kerneloops21:59:513
2304899631625,5cyclictest4793-21kerneloops22:07:452
2304099631623,6cyclictest4793-21kerneloops00:16:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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