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2026-05-11 - 00:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun May 10, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
585499636629,5cyclictest4793-21kerneloops10:58:493
585499636627,7cyclictest4793-21kerneloops11:04:213
584899634625,7cyclictest4793-21kerneloops09:45:152
584499634628,4cyclictest4793-21kerneloops12:39:171
584499634628,4cyclictest4793-21kerneloops10:32:091
585499633627,5cyclictest4793-21kerneloops09:19:193
584499633627,4cyclictest4793-21kerneloops09:35:091
584499633626,5cyclictest4793-21kerneloops11:38:541
583699633625,7cyclictest4793-21kerneloops07:50:340
583699633625,6cyclictest4793-21kerneloops07:36:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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