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2026-06-17 - 01:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Jun 16, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1339299637633,2cyclictest4793-21kerneloops11:26:523
1338499635631,2cyclictest4793-21kerneloops12:10:092
1337699634628,5cyclictest4793-21kerneloops12:02:421
1337699634628,4cyclictest4793-21kerneloops08:40:321
1339299633627,5cyclictest4793-21kerneloops07:47:463
1337099633625,6cyclictest4793-21kerneloops09:17:270
1338499631623,6cyclictest4793-21kerneloops11:54:232
1338499631623,6cyclictest4793-21kerneloops10:30:202
1337699631628,2cyclictest4793-21kerneloops08:11:151
1337699631624,6cyclictest4793-21kerneloops10:37:051
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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