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2026-04-03 - 09:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Apr 03, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2947999635627,6cyclictest4793-21kerneloops20:48:361
2947999634628,4cyclictest4793-21kerneloops20:21:101
2947999634627,6cyclictest4793-21kerneloops00:22:271
2949499633627,5cyclictest4793-21kerneloops20:05:063
2947999633626,5cyclictest4793-21kerneloops21:41:391
2949499632625,5cyclictest4793-21kerneloops20:58:433
2947999632626,5cyclictest4793-21kerneloops20:08:161
2947999632626,5cyclictest4793-21kerneloops20:02:461
2947999632626,5cyclictest4793-21kerneloops20:02:461
2947999632625,5cyclictest4793-21kerneloops19:41:481
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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