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2026-02-08 - 07:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Feb 08, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
855399590582,6cyclictest4793-21kerneloops20:37:031
856999589581,6cyclictest4793-21kerneloops23:32:273
856999589581,6cyclictest4793-21kerneloops20:04:183
856999588581,6cyclictest4793-21kerneloops20:34:363
856999588581,5cyclictest4793-21kerneloops21:39:393
856999588581,5cyclictest4793-21kerneloops21:22:423
856999588581,5cyclictest4793-21kerneloops00:25:553
856999588581,5cyclictest4793-21kerneloops00:06:153
855399588582,5cyclictest4793-21kerneloops20:01:571
856999587582,4cyclictest4793-21kerneloops22:31:093
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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