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2026-07-20 - 15:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Jul 20, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
101899664658,4cyclictest4793-21kerneloops11:35:003
101899664657,6cyclictest4793-21kerneloops10:18:363
101899664655,7cyclictest4793-21kerneloops08:52:003
100599664657,5cyclictest4793-21kerneloops10:36:511
101899663656,5cyclictest4793-21kerneloops09:25:293
99699662654,6cyclictest4793-21kerneloops09:45:100
99699662653,8cyclictest4793-21kerneloops12:09:490
101899662655,5cyclictest4793-21kerneloops08:35:043
99699661651,8cyclictest4793-21kerneloops10:08:500
99699661651,8cyclictest4793-21kerneloops10:08:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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