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2026-03-13 - 23:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Mar 13, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2063499650640,8cyclictest4793-21kerneloops11:25:513
2063499635628,6cyclictest4793-21kerneloops09:35:303
2061899634627,6cyclictest4793-21kerneloops08:44:521
2061399634623,9cyclictest4793-21kerneloops09:17:560
2063499633626,5cyclictest4793-21kerneloops08:04:523
2063499633624,7cyclictest4793-21kerneloops12:01:103
2062899633625,6cyclictest4793-21kerneloops10:11:582
2061899633628,4cyclictest4793-21kerneloops07:10:311
2061899633626,5cyclictest4793-21kerneloops11:57:291
2061899633626,5cyclictest4793-21kerneloops11:43:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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