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2026-04-16 - 23:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Apr 16, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1941999639628,9cyclictest4793-21kerneloops10:31:030
1944099635628,6cyclictest4793-21kerneloops10:30:323
1942599635627,6cyclictest4793-21kerneloops09:43:521
1944099634628,5cyclictest4793-21kerneloops10:01:173
1944099634627,5cyclictest4793-21kerneloops09:21:593
1944099634627,5cyclictest4793-21kerneloops07:14:093
1944099633626,6cyclictest4793-21kerneloops11:26:013
1942999633624,7cyclictest4793-21kerneloops10:59:152
1944099632626,5cyclictest4793-21kerneloops11:03:263
1942999632625,6cyclictest4793-21kerneloops07:51:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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