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2025-11-02 - 12:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Nov 02, 2025 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64479814130,1392rtkit-daemon4927-21kerneloops19:08:472
80099763751,10cyclictest4927-21kerneloops22:28:470
82099753745,7cyclictest4927-21kerneloops00:20:423
82099752746,5cyclictest4927-21kerneloops23:05:433
82099752744,7cyclictest4927-21kerneloops23:51:383
80699752744,6cyclictest4927-21kerneloops00:04:271
80099752744,7cyclictest4927-21kerneloops00:29:260
82099751745,5cyclictest4927-21kerneloops00:12:593
80699751745,4cyclictest4927-21kerneloops19:41:461
80099751740,9cyclictest4927-21kerneloops21:39:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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