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2026-09-01 - 06:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Sep 01, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812640,1252rtkit-daemon4793-21kerneloops19:07:512
1394099680676,2cyclictest4793-21kerneloops21:45:480
1395399666659,5cyclictest4793-21kerneloops00:02:142
1394699665656,7cyclictest4793-21kerneloops21:59:141
1395399664654,8cyclictest4793-21kerneloops22:37:452
1396299663656,5cyclictest4793-21kerneloops23:04:133
1396299663655,6cyclictest4793-21kerneloops21:32:513
1394699663654,7cyclictest4793-21kerneloops21:12:521
1396299662655,6cyclictest4793-21kerneloops22:18:173
1396299662655,5cyclictest4793-21kerneloops22:51:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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