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2026-07-14 - 15:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Jul 14, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1567699664654,8cyclictest4793-21kerneloops09:56:171
1567699663657,4cyclictest4793-21kerneloops08:02:211
1567099663653,8cyclictest4793-21kerneloops10:58:240
1568199662654,6cyclictest4793-21kerneloops09:21:572
1567699662655,5cyclictest4793-21kerneloops08:05:141
1569199661653,6cyclictest4793-21kerneloops11:43:323
1568199661654,5cyclictest4793-21kerneloops08:25:102
1568199661653,6cyclictest4793-21kerneloops07:55:432
1567699661653,6cyclictest4793-21kerneloops10:30:001
1569199660657,2cyclictest4793-21kerneloops09:17:233
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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