You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-01 - 07:51
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Wed Apr 01, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3031699635628,5cyclictest4793-21kerneloops00:20:541
3033299634626,6cyclictest4793-21kerneloops22:06:013
3033299633627,4cyclictest4793-21kerneloops20:40:413
3033299632625,5cyclictest4793-21kerneloops23:26:053
3032399632628,2cyclictest4793-21kerneloops22:15:562
3031699632628,2cyclictest4793-21kerneloops21:14:181
3031699632624,6cyclictest4793-21kerneloops22:52:331
3033299631625,5cyclictest4793-21kerneloops19:49:043
3033299631624,5cyclictest4793-21kerneloops19:20:073
3031099631624,5cyclictest4793-21kerneloops21:08:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional