You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-25 - 07:39
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Dec 25, 2025 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311699586574,10cyclictest4793-21kerneloops23:49:090
311699586574,10cyclictest4793-21kerneloops23:34:250
311699586573,11cyclictest4793-21kerneloops23:55:140
311699586571,13cyclictest4793-21kerneloops19:10:130
313799584576,6cyclictest4793-21kerneloops21:44:283
312199584577,5cyclictest4793-21kerneloops22:44:591
311699584573,9cyclictest4793-21kerneloops23:03:480
313799582574,6cyclictest4793-21kerneloops23:05:353
312199582575,5cyclictest4793-21kerneloops23:40:471
311699582574,6cyclictest4793-21kerneloops22:49:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional