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2026-03-06 - 12:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Mar 06, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12412775751,19sleep04793-21kerneloops19:09:360
12412775751,19sleep04793-21kerneloops19:09:350
142199634627,5cyclictest4793-21kerneloops20:39:283
142199633627,4cyclictest4793-21kerneloops21:52:093
141299633626,5cyclictest4793-21kerneloops20:24:362
140799633625,6cyclictest4793-21kerneloops21:07:401
142199632623,7cyclictest4793-21kerneloops21:05:433
140799632626,5cyclictest4793-21kerneloops22:49:231
140799632624,6cyclictest4793-21kerneloops21:26:331
140099632624,6cyclictest4793-21kerneloops21:58:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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