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2026-05-26 - 14:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue May 26, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1323499640633,6cyclictest4793-21kerneloops22:25:180
1325599636627,7cyclictest4793-21kerneloops22:20:093
1323499636625,9cyclictest4793-21kerneloops22:43:390
1324199635628,5cyclictest4793-21kerneloops22:07:561
1325599634626,7cyclictest4793-21kerneloops21:00:273
1325599633624,7cyclictest4793-21kerneloops00:05:233
1324999633624,7cyclictest4793-21kerneloops22:06:202
1324199633624,7cyclictest4793-21kerneloops19:35:121
1323499633625,7cyclictest4793-21kerneloops00:28:530
1323499633625,6cyclictest4793-21kerneloops19:45:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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