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2026-05-08 - 00:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu May 07, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2771199648639,7cyclictest4793-21kerneloops09:45:232
2771799636627,7cyclictest4793-21kerneloops11:15:413
2771799635627,6cyclictest4793-21kerneloops12:27:453
2770399635628,5cyclictest4793-21kerneloops08:22:151
2771799634627,5cyclictest4793-21kerneloops09:04:573
2770399634627,5cyclictest4793-21kerneloops09:17:521
2769699634624,8cyclictest4793-21kerneloops09:15:420
2771199633625,6cyclictest4793-21kerneloops08:16:072
2771799632626,4cyclictest4793-21kerneloops07:39:543
2771799632625,6cyclictest4793-21kerneloops09:42:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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