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2026-07-23 - 17:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Jul 23, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1858899679667,10cyclictest4793-21kerneloops12:18:490
1859699666652,12cyclictest4793-21kerneloops12:30:281
1859699664658,5cyclictest4793-21kerneloops08:24:331
1859699663657,5cyclictest4793-21kerneloops07:47:351
1861099662658,2cyclictest4793-21kerneloops09:59:573
1861099662658,2cyclictest4793-21kerneloops09:59:573
1859699662656,5cyclictest4793-21kerneloops07:59:551
1860199661652,7cyclictest4793-21kerneloops10:14:172
1859699661655,4cyclictest4793-21kerneloops07:22:191
1858899661648,11cyclictest4793-21kerneloops12:31:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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