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2026-07-26 - 19:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Jul 26, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812540,1242rtkit-daemon4793-21kerneloops07:06:181
2935899663654,7cyclictest4793-21kerneloops09:28:132
2936699662655,5cyclictest4793-21kerneloops07:19:043
2934999662657,4cyclictest4793-21kerneloops12:38:031
2934999662653,7cyclictest4793-21kerneloops11:35:521
2936699661654,5cyclictest4793-21kerneloops08:00:463
2936699660653,5cyclictest4793-21kerneloops08:05:573
2934999660655,4cyclictest4793-21kerneloops10:20:051
2934999660654,5cyclictest4793-21kerneloops09:28:341
2934999660653,6cyclictest4793-21kerneloops10:18:091
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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