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2026-03-28 - 15:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Mar 28, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1496499646637,7cyclictest4793-21kerneloops11:45:242
1497199634625,7cyclictest4793-21kerneloops09:38:543
1495899634627,5cyclictest4793-21kerneloops09:06:271
1495899634626,6cyclictest4793-21kerneloops07:22:571
1494799634624,8cyclictest4793-21kerneloops07:53:280
1495899633626,5cyclictest4793-21kerneloops12:23:221
1495899633625,6cyclictest4793-21kerneloops07:49:421
1494799633624,7cyclictest4793-21kerneloops12:34:430
1497199632626,5cyclictest4793-21kerneloops10:41:543
1497199632626,5cyclictest4793-21kerneloops10:02:043
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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