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2025-12-22 - 06:27
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Dec 22, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
580799600590,8cyclictest4793-21kerneloops23:00:080
582899584577,5cyclictest4793-21kerneloops00:34:433
582899582576,4cyclictest4793-21kerneloops00:27:453
580799582571,9cyclictest4793-21kerneloops23:21:070
582099581573,6cyclictest4793-21kerneloops19:17:502
582899580573,5cyclictest4793-21kerneloops21:26:363
582899580573,5cyclictest4793-21kerneloops20:19:533
581299580571,7cyclictest4793-21kerneloops22:59:471
580799580573,6cyclictest4793-21kerneloops20:41:400
582899579570,7cyclictest4793-21kerneloops20:45:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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