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2026-01-09 - 05:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Jan 09, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3114199584577,5cyclictest4793-21kerneloops19:56:553
3114199583576,5cyclictest4793-21kerneloops20:51:163
3113699583574,7cyclictest4793-21kerneloops00:02:082
3112899583577,5cyclictest4793-21kerneloops20:13:541
3112899582573,7cyclictest4793-21kerneloops21:35:441
3114199581574,5cyclictest4793-21kerneloops20:09:123
3114199580574,5cyclictest4793-21kerneloops20:49:413
3114199580574,5cyclictest4793-21kerneloops20:49:413
3114199580574,5cyclictest4793-21kerneloops20:21:363
3114199580574,2cyclictest4793-21kerneloops22:09:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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