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2026-04-24 - 23:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Apr 24, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811980,1185rtkit-daemon4793-21kerneloops07:07:062
486299639629,8cyclictest4793-21kerneloops10:57:500
488399635628,6cyclictest4793-21kerneloops10:04:543
488399633627,4cyclictest4793-21kerneloops12:35:553
488399633626,5cyclictest4793-21kerneloops07:31:543
488399633625,6cyclictest4793-21kerneloops07:44:103
488399633625,6cyclictest4793-21kerneloops07:11:073
486899633628,4cyclictest4793-21kerneloops09:39:101
486899633625,6cyclictest4793-21kerneloops11:29:251
486299633626,6cyclictest4793-21kerneloops10:34:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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