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2026-04-20 - 00:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Apr 19, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2322599634626,6cyclictest4793-21kerneloops09:49:213
2321199634628,5cyclictest4793-21kerneloops10:24:141
2322599633623,8cyclictest4793-21kerneloops10:43:213
2322599632625,6cyclictest4793-21kerneloops12:25:283
2322599631623,6cyclictest4793-21kerneloops12:23:233
2322599631622,8cyclictest4793-21kerneloops10:32:233
2322099631624,6cyclictest4793-21kerneloops11:10:292
2321199631628,2cyclictest4793-21kerneloops07:53:311
2321199631624,5cyclictest4793-21kerneloops07:41:361
2320799631624,5cyclictest4793-21kerneloops09:26:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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