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2026-05-20 - 12:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Wed May 20, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2163099645638,5cyclictest4793-21kerneloops22:55:162
2162599637628,7cyclictest4793-21kerneloops19:38:171
2163999636627,7cyclictest4793-21kerneloops21:03:053
2162599636628,6cyclictest4793-21kerneloops23:27:331
2162599635628,5cyclictest4793-21kerneloops19:25:291
2162599635627,6cyclictest4793-21kerneloops19:52:231
2163999634625,7cyclictest4793-21kerneloops20:40:133
2162599634628,4cyclictest4793-21kerneloops21:21:421
2162599634628,4cyclictest4793-21kerneloops20:24:121
2162599634627,5cyclictest4793-21kerneloops22:28:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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