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2026-04-10 - 22:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Apr 10, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1630799635625,8cyclictest4793-21kerneloops12:20:580
1632999634627,5cyclictest4793-21kerneloops08:46:073
1632999634626,6cyclictest4793-21kerneloops08:19:563
1632999633627,5cyclictest4793-21kerneloops10:32:383
1631299633627,5cyclictest4793-21kerneloops07:11:461
1632999632627,4cyclictest4793-21kerneloops08:30:263
1632999632625,5cyclictest4793-21kerneloops10:29:263
1632399632625,6cyclictest4793-21kerneloops08:18:112
1630799632624,7cyclictest4793-21kerneloops12:05:230
1632999631625,5cyclictest4793-21kerneloops10:35:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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