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2026-03-12 - 17:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Mar 12, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1026599637627,8cyclictest4793-21kerneloops12:25:263
1026599636627,7cyclictest4793-21kerneloops11:07:383
1026599636627,7cyclictest4793-21kerneloops11:07:373
1026599635627,6cyclictest4793-21kerneloops10:15:453
1026599635627,6cyclictest4793-21kerneloops09:40:453
1026599634626,6cyclictest4793-21kerneloops08:45:093
1026599634626,6cyclictest4793-21kerneloops08:35:303
1025399634627,5cyclictest4793-21kerneloops12:12:301
1026599633626,6cyclictest4793-21kerneloops10:38:423
1026599633626,5cyclictest4793-21kerneloops11:15:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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