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2026-09-07 - 08:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Sep 07, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3252999689680,7cyclictest4793-21kerneloops21:30:202
3252399663657,4cyclictest4793-21kerneloops22:52:341
3252399663657,4cyclictest4793-21kerneloops22:52:341
3252399662656,4cyclictest4793-21kerneloops00:06:281
3252399662654,6cyclictest4793-21kerneloops00:35:321
3252399662654,6cyclictest4793-21kerneloops00:35:321
3251799662651,9cyclictest4793-21kerneloops20:50:140
3252399661655,4cyclictest4793-21kerneloops21:52:071
3252399661654,5cyclictest4793-21kerneloops00:33:261
3252399661654,5cyclictest4793-21kerneloops00:04:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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