You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-01 - 06:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Feb 01, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3212899588582,5cyclictest4793-21kerneloops20:29:513
3212899588579,7cyclictest4793-21kerneloops22:27:363
3211399588579,7cyclictest4793-21kerneloops23:17:491
3210799588579,7cyclictest4793-21kerneloops23:59:400
3210799588578,8cyclictest4793-21kerneloops23:23:350
3212899587579,7cyclictest4793-21kerneloops19:42:193
3212899587578,8cyclictest4793-21kerneloops23:27:373
3212899587578,8cyclictest4793-21kerneloops23:27:363
3212899586580,5cyclictest4793-21kerneloops23:01:513
3212899586580,5cyclictest4793-21kerneloops22:36:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional