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2026-09-16 - 09:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Wed Sep 16, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812750,1264rtkit-daemon4793-21kerneloops19:08:202
2249099666657,7cyclictest4793-21kerneloops21:39:203
2247699666658,7cyclictest4793-21kerneloops20:09:501
2249099664655,7cyclictest4793-21kerneloops00:10:513
2247699663655,6cyclictest4793-21kerneloops19:44:231
2247099662653,7cyclictest4793-21kerneloops21:42:530
2249099660654,5cyclictest4793-21kerneloops19:22:213
2247699660655,4cyclictest4793-21kerneloops20:42:471
2247699660653,6cyclictest4793-21kerneloops22:16:561
2249099659655,2cyclictest4793-21kerneloops21:10:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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