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2026-07-17 - 15:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Jul 17, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1792299667658,7cyclictest4793-21kerneloops10:32:071
1792299666657,7cyclictest4793-21kerneloops10:57:301
1792299665657,6cyclictest4793-21kerneloops12:29:471
1792299664657,5cyclictest4793-21kerneloops11:49:391
1792299664657,5cyclictest4793-21kerneloops11:49:391
1792299664657,5cyclictest4793-21kerneloops10:11:131
1792299664656,6cyclictest4793-21kerneloops11:09:031
1792299664656,6cyclictest4793-21kerneloops07:17:461
1791699664655,7cyclictest4793-21kerneloops09:39:140
1791699664653,9cyclictest4793-21kerneloops10:18:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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