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2026-04-25 - 11:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Apr 25, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2377499637627,6cyclictest4793-21kerneloops20:47:081
2378799636629,5cyclictest4793-21kerneloops23:33:273
2376799635626,8cyclictest4793-21kerneloops23:12:550
2378799633626,5cyclictest4793-21kerneloops21:39:433
2378799633624,7cyclictest4793-21kerneloops19:33:463
2377499633628,4cyclictest4793-21kerneloops22:42:261
2376799633625,6cyclictest4793-21kerneloops21:36:080
2376799633625,6cyclictest4793-21kerneloops00:02:010
2378799632626,5cyclictest4793-21kerneloops19:25:263
2378799632626,5cyclictest4793-21kerneloops19:13:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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