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2026-05-12 - 09:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue May 12, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1730199650643,6cyclictest4793-21kerneloops20:55:181
1730199645642,2cyclictest4793-21kerneloops21:10:201
1730199636629,5cyclictest4793-21kerneloops23:55:531
1730199635627,6cyclictest4793-21kerneloops21:06:461
1729499635623,10cyclictest4793-21kerneloops23:11:170
1731599634628,5cyclictest4793-21kerneloops22:02:163
1731599634628,5cyclictest4793-21kerneloops00:02:373
1731599634624,8cyclictest4793-21kerneloops22:29:583
1730999633625,6cyclictest4793-21kerneloops19:26:452
1729499633625,6cyclictest4793-21kerneloops21:14:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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