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2026-03-10 - 19:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Mar 10, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1292199639630,7cyclictest4793-21kerneloops11:20:222
1292699637627,8cyclictest4793-21kerneloops12:33:503
1292699635626,7cyclictest4793-21kerneloops10:09:313
1292699635626,7cyclictest4793-21kerneloops10:09:313
1292699635625,8cyclictest4793-21kerneloops11:41:313
1292699635625,8cyclictest4793-21kerneloops11:41:303
1291299635627,6cyclictest4793-21kerneloops09:58:361
1292699634626,6cyclictest4793-21kerneloops11:00:113
1292199632624,6cyclictest4793-21kerneloops09:25:042
1291299632626,5cyclictest4793-21kerneloops11:46:061
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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