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2026-07-02 - 12:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Jul 02, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1190399678674,2cyclictest4793-21kerneloops22:40:543
1188799664655,7cyclictest4793-21kerneloops20:37:331
1188799664655,7cyclictest4793-21kerneloops19:48:031
1190399663655,6cyclictest4793-21kerneloops20:43:273
1188799663654,7cyclictest4793-21kerneloops22:03:331
1188099663653,8cyclictest4793-21kerneloops23:23:420
1190399662655,6cyclictest4793-21kerneloops21:00:473
1188799662653,7cyclictest4793-21kerneloops20:00:331
1190399661655,5cyclictest4793-21kerneloops22:38:043
1188799661655,4cyclictest4793-21kerneloops21:31:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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