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2025-12-17 - 00:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Dec 16, 2025 12:44:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2683199587583,2cyclictest4793-21kerneloops09:00:163
2681899584575,7cyclictest4793-21kerneloops11:06:551
2683199583575,6cyclictest4793-21kerneloops11:54:053
2683199583575,6cyclictest4793-21kerneloops09:43:503
2683199583574,7cyclictest4793-21kerneloops11:04:163
2682699583574,7cyclictest4793-21kerneloops09:42:442
2683199582575,6cyclictest4793-21kerneloops11:35:293
2683199582575,5cyclictest4793-21kerneloops10:08:563
2683199581573,6cyclictest4793-21kerneloops12:08:143
2683199581573,6cyclictest4793-21kerneloops07:25:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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