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2026-04-09 - 23:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Apr 09, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1715999637626,9cyclictest4793-21kerneloops10:23:070
1716999636627,7cyclictest4793-21kerneloops12:07:312
1716499635627,7cyclictest4793-21kerneloops12:27:171
1716499635627,7cyclictest4793-21kerneloops10:49:051
1718099632623,7cyclictest4793-21kerneloops09:56:083
1716499632624,7cyclictest4793-21kerneloops10:44:511
1716499632624,7cyclictest4793-21kerneloops10:44:501
1716499631625,5cyclictest4793-21kerneloops09:09:161
1716499631625,4cyclictest4793-21kerneloops09:17:361
1715999631619,10cyclictest4793-21kerneloops10:30:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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