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2025-05-09 - 06:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri May 09, 2025 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
80199717710,5cyclictest4927-21kerneloops22:33:212
79799710702,6cyclictest4927-21kerneloops19:40:241
79599710698,10cyclictest4927-21kerneloops22:30:240
80999709701,6cyclictest4927-21kerneloops19:25:513
80199709705,2cyclictest4927-21kerneloops23:55:262
79799709701,6cyclictest4927-21kerneloops23:01:101
80999708702,5cyclictest4927-21kerneloops23:05:373
80999708701,5cyclictest4927-21kerneloops21:39:453
80999708701,5cyclictest4927-21kerneloops00:16:543
80999708700,6cyclictest4927-21kerneloops23:47:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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