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2026-05-29 - 20:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri May 29, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3069599636628,6cyclictest4793-21kerneloops07:41:421
3068999635624,9cyclictest4793-21kerneloops12:33:110
3068999635624,9cyclictest4793-21kerneloops10:45:220
3070799634627,6cyclictest4793-21kerneloops11:43:073
3070799634627,5cyclictest4793-21kerneloops08:31:213
3070199633626,5cyclictest4793-21kerneloops07:25:512
3068999633626,5cyclictest4793-21kerneloops07:11:540
3068999633625,6cyclictest4793-21kerneloops08:23:270
3069599632629,1cyclictest4793-21kerneloops11:27:431
3068999632624,7cyclictest4793-21kerneloops11:25:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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