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2026-06-01 - 21:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Jun 01, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
700599658653,4cyclictest4793-21kerneloops09:40:173
700199637629,6cyclictest4793-21kerneloops12:09:232
700599634627,6cyclictest4793-21kerneloops07:50:563
699199632629,2cyclictest4793-21kerneloops11:42:141
699199632625,6cyclictest4793-21kerneloops12:33:101
700199631621,8cyclictest4793-21kerneloops12:24:382
698799631622,8cyclictest4793-21kerneloops10:05:150
700599630628,1cyclictest4793-21kerneloops09:19:573
700599630624,5cyclictest4793-21kerneloops10:21:473
700599630623,6cyclictest4793-21kerneloops12:16:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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