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2025-11-25 - 12:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Nov 25, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2239699799791,6cyclictest4927-21kerneloops21:36:203
2238599799790,7cyclictest4927-21kerneloops21:19:251
2238599798791,5cyclictest4927-21kerneloops21:51:351
2237999798788,8cyclictest4927-21kerneloops00:28:050
2238599796788,6cyclictest4927-21kerneloops21:58:401
2238599795789,4cyclictest4927-21kerneloops20:32:031
2238599795788,5cyclictest4927-21kerneloops23:01:331
2238599795788,5cyclictest4927-21kerneloops20:26:271
2238599795787,6cyclictest4927-21kerneloops22:21:081
2239699794788,5cyclictest4927-21kerneloops20:53:463
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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