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2026-06-23 - 06:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Jun 23, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
699699669665,2cyclictest4793-21kerneloops23:30:181
701099665656,7cyclictest4793-21kerneloops00:16:193
699699664655,7cyclictest4793-21kerneloops23:55:381
700599663654,7cyclictest4793-21kerneloops23:06:562
699699663656,5cyclictest4793-21kerneloops23:47:301
701099662655,5cyclictest4793-21kerneloops20:36:143
699199662651,9cyclictest4793-21kerneloops23:46:260
699699661655,4cyclictest4793-21kerneloops19:13:531
699199661652,7cyclictest4793-21kerneloops20:00:090
700599660654,4cyclictest4793-21kerneloops19:38:242
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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