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2026-07-05 - 12:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Jul 05, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1832599665656,7cyclictest4793-21kerneloops00:12:521
1833999664656,6cyclictest4793-21kerneloops22:12:553
1832599664658,4cyclictest4793-21kerneloops00:17:381
1832599664657,5cyclictest4793-21kerneloops00:04:301
1832599664655,7cyclictest4793-21kerneloops00:07:091
1833999663657,5cyclictest4793-21kerneloops22:57:053
1833999663657,5cyclictest4793-21kerneloops19:19:093
1833999663655,6cyclictest4793-21kerneloops22:37:023
1833999662655,5cyclictest4793-21kerneloops22:46:213
1832599662654,6cyclictest4793-21kerneloops00:39:431
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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