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2026-03-09 - 06:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Mar 09, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
143999634627,6cyclictest4793-21kerneloops23:41:033
143999634625,7cyclictest4793-21kerneloops23:16:313
143999633626,6cyclictest4793-21kerneloops21:33:573
142699633625,6cyclictest4793-21kerneloops20:17:341
143999632627,4cyclictest4793-21kerneloops20:09:573
142699632626,4cyclictest4793-21kerneloops19:49:321
142699632624,6cyclictest4793-21kerneloops21:38:561
142699631624,6cyclictest4793-21kerneloops19:52:531
141699631623,7cyclictest4793-21kerneloops21:46:080
143999630624,5cyclictest4793-21kerneloops22:54:073
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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