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2025-08-30 - 01:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Aug 29, 2025 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2493699728719,7cyclictest4927-21kerneloops09:33:202
2493699724714,8cyclictest4927-21kerneloops12:17:442
2493699715704,9cyclictest4927-21kerneloops11:21:572
2493699715704,9cyclictest4927-21kerneloops11:21:572
2494399711703,6cyclictest4927-21kerneloops08:35:593
2493699709700,7cyclictest4927-21kerneloops10:20:192
2493099707703,2cyclictest4927-21kerneloops12:13:391
2493099707703,2cyclictest4927-21kerneloops09:02:031
2492299707698,7cyclictest4927-21kerneloops12:12:440
2492299707697,8cyclictest4927-21kerneloops11:56:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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