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2026-05-02 - 01:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri May 01, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3241799636627,7cyclictest4793-21kerneloops07:14:503
3241799635627,6cyclictest4793-21kerneloops12:10:563
3241799634627,6cyclictest4793-21kerneloops07:55:223
3241799634625,7cyclictest4793-21kerneloops10:35:323
3239699634623,9cyclictest4793-21kerneloops10:00:270
3241799633627,4cyclictest4793-21kerneloops07:21:043
3241799632626,5cyclictest4793-21kerneloops08:38:453
3241799632625,5cyclictest4793-21kerneloops10:51:193
3241799632624,7cyclictest4793-21kerneloops09:26:443
3241799632623,7cyclictest4793-21kerneloops12:16:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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