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2026-03-25 - 05:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Wed Mar 25, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889810850,1074rtkit-daemon4793-21kerneloops19:08:471
2809899636627,7cyclictest4793-21kerneloops22:06:361
2811199634628,4cyclictest4793-21kerneloops19:44:093
2809399633624,7cyclictest4793-21kerneloops21:47:030
2811199632626,4cyclictest4793-21kerneloops20:52:493
2811199632626,4cyclictest4793-21kerneloops20:39:353
2809899632625,6cyclictest4793-21kerneloops23:35:341
2809899632625,5cyclictest4793-21kerneloops00:11:461
2809399632623,7cyclictest4793-21kerneloops23:22:140
2810399631624,6cyclictest4793-21kerneloops23:10:462
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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