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2026-06-29 - 09:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Jun 29, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
881899665657,6cyclictest4793-21kerneloops22:35:423
881899665656,7cyclictest4793-21kerneloops22:20:353
880299664655,7cyclictest4793-21kerneloops23:50:161
879799664655,7cyclictest4793-21kerneloops23:20:320
880299663654,7cyclictest4793-21kerneloops23:38:501
880299662656,4cyclictest4793-21kerneloops20:05:031
880299662653,7cyclictest4793-21kerneloops23:10:121
881899661656,4cyclictest4793-21kerneloops20:19:103
881199661653,6cyclictest4793-21kerneloops19:42:112
881199661652,7cyclictest4793-21kerneloops20:15:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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