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2026-08-10 - 22:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Aug 10, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
734399664655,7cyclictest4793-21kerneloops08:15:173
734399663656,6cyclictest4793-21kerneloops09:23:333
732199663655,6cyclictest4793-21kerneloops07:43:490
734399662659,2cyclictest4793-21kerneloops10:48:373
734399662655,6cyclictest4793-21kerneloops09:32:273
734399661655,5cyclictest4793-21kerneloops12:12:313
734399661655,5cyclictest4793-21kerneloops12:04:203
733099661654,5cyclictest4793-21kerneloops09:00:391
734399660654,5cyclictest4793-21kerneloops11:32:143
734399660653,6cyclictest4793-21kerneloops11:29:573
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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