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2025-12-20 - 08:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Dec 20, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889810950,1084rtkit-daemon4793-21kerneloops19:08:083
2957199584576,6cyclictest4793-21kerneloops23:12:403
2955099584574,8cyclictest4793-21kerneloops23:45:210
2955799583576,5cyclictest4793-21kerneloops21:06:521
2955799583575,6cyclictest4793-21kerneloops19:44:411
2956299582573,7cyclictest4793-21kerneloops19:49:152
2957199581575,4cyclictest4793-21kerneloops21:49:303
2957199581572,7cyclictest4793-21kerneloops20:00:153
2955099581573,6cyclictest4793-21kerneloops23:22:350
2956299580574,4cyclictest4793-21kerneloops23:39:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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