You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-04 - 20:06
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Aug 04, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1461899671662,7cyclictest4793-21kerneloops12:25:333
1461899665656,2cyclictest4793-21kerneloops10:03:423
1460199663656,6cyclictest4793-21kerneloops10:08:241
1461899662656,5cyclictest4793-21kerneloops07:28:323
1461899662656,4cyclictest4793-21kerneloops07:37:523
1461199661653,6cyclictest4793-21kerneloops10:57:042
1460199661655,5cyclictest4793-21kerneloops11:34:481
1460199661655,5cyclictest4793-21kerneloops10:46:561
1459599661653,6cyclictest4793-21kerneloops11:10:500
1459599661651,8cyclictest4793-21kerneloops10:18:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional