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2026-03-31 - 08:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Mar 31, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
463499636628,7cyclictest4793-21kerneloops19:32:401
465099632624,6cyclictest4793-21kerneloops21:43:523
463499632626,5cyclictest4793-21kerneloops23:43:271
463499632626,5cyclictest4793-21kerneloops22:30:441
465099631628,2cyclictest4793-21kerneloops00:35:263
465099631623,6cyclictest4793-21kerneloops20:48:393
465099631622,8cyclictest4793-21kerneloops21:00:263
462999631622,7cyclictest4793-21kerneloops22:40:260
463499630628,1cyclictest4793-21kerneloops22:37:581
462999630622,6cyclictest4793-21kerneloops22:23:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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