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2026-07-29 - 17:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Wed Jul 29, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1162799672659,11cyclictest4793-21kerneloops11:20:090
1164199664660,2cyclictest4793-21kerneloops11:00:092
1163399663655,6cyclictest4793-21kerneloops10:39:381
1162799663654,7cyclictest4793-21kerneloops12:09:070
1164199662653,7cyclictest4793-21kerneloops12:22:022
1164899660653,6cyclictest4793-21kerneloops09:22:423
1164199660653,5cyclictest4793-21kerneloops12:31:192
1163399660656,2cyclictest4793-21kerneloops07:14:311
1163399660655,4cyclictest4793-21kerneloops07:57:241
1163399660653,5cyclictest4793-21kerneloops09:35:331
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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