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2026-05-11 - 13:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon May 11, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1944099653643,8cyclictest4793-21kerneloops22:54:132
1944099637628,7cyclictest4793-21kerneloops21:27:432
1944799636627,7cyclictest4793-21kerneloops21:28:343
1943199636627,7cyclictest4793-21kerneloops20:45:501
1944799635628,6cyclictest4793-21kerneloops21:38:383
1943199635626,7cyclictest4793-21kerneloops22:17:111
1943199633626,5cyclictest4793-21kerneloops21:49:481
1943199633626,5cyclictest4793-21kerneloops20:56:141
1944799632626,5cyclictest4793-21kerneloops00:18:323
1944099632626,5cyclictest4793-21kerneloops23:06:452
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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