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2026-06-20 - 05:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Jun 20, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
826499667658,7cyclictest4793-21kerneloops23:07:183
826499664656,6cyclictest4793-21kerneloops22:42:153
826499664656,6cyclictest4793-21kerneloops00:22:333
826499664655,7cyclictest4793-21kerneloops00:25:023
824999664658,5cyclictest4793-21kerneloops19:48:081
826499663655,6cyclictest4793-21kerneloops22:47:543
826499662656,5cyclictest4793-21kerneloops23:54:283
826499662656,5cyclictest4793-21kerneloops21:18:153
826499662655,5cyclictest4793-21kerneloops22:22:293
826499662654,6cyclictest4793-21kerneloops23:23:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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