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2026-05-01 - 00:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Apr 30, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1006299636627,7cyclictest4793-21kerneloops07:58:331
1005599636627,7cyclictest4793-21kerneloops10:46:510
1007699633626,6cyclictest4793-21kerneloops12:05:263
1006299633627,5cyclictest4793-21kerneloops07:25:251
1006299633627,4cyclictest4793-21kerneloops10:30:491
1006299633626,5cyclictest4793-21kerneloops11:47:561
1007699632625,6cyclictest4793-21kerneloops10:17:493
1005599632625,6cyclictest4793-21kerneloops10:06:490
1006899631625,4cyclictest4793-21kerneloops09:26:552
1005599631623,6cyclictest4793-21kerneloops11:24:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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