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2026-05-23 - 13:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat May 23, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2880399642629,11cyclictest4793-21kerneloops23:25:160
2882599635627,7cyclictest4793-21kerneloops21:54:533
2881299635628,5cyclictest4793-21kerneloops23:07:011
2882599634626,6cyclictest4793-21kerneloops22:34:083
2882599633626,5cyclictest4793-21kerneloops21:47:493
2882599633624,7cyclictest4793-21kerneloops22:20:563
2881999633626,6cyclictest4793-21kerneloops00:09:052
2880399633622,9cyclictest4793-21kerneloops00:12:430
2882599632626,5cyclictest4793-21kerneloops23:47:543
2881999632626,5cyclictest4793-21kerneloops21:43:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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