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2026-06-14 - 01:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Jun 13, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
946199636629,5cyclictest4793-21kerneloops08:48:023
945299635629,5cyclictest4793-21kerneloops10:37:432
944799635628,6cyclictest4793-21kerneloops11:47:011
946199634626,6cyclictest4793-21kerneloops08:29:173
946199633628,4cyclictest4793-21kerneloops10:12:143
946199633625,6cyclictest4793-21kerneloops10:15:233
944799633626,5cyclictest4793-21kerneloops09:31:241
944799633625,7cyclictest4793-21kerneloops08:43:331
944099633623,8cyclictest4793-21kerneloops12:39:320
946199632625,5cyclictest4793-21kerneloops11:33:543
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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