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2026-04-06 - 09:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Apr 06, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3244199635629,5cyclictest4793-21kerneloops23:54:563
3244199635627,7cyclictest4793-21kerneloops21:28:393
3244199634625,7cyclictest4793-21kerneloops23:08:433
3244199634625,7cyclictest4793-21kerneloops22:29:513
3242799633626,6cyclictest4793-21kerneloops21:24:041
3242099633623,8cyclictest4793-21kerneloops21:12:290
3244199632626,5cyclictest4793-21kerneloops19:51:383
3244199632625,6cyclictest4793-21kerneloops19:46:273
3242799632626,5cyclictest4793-21kerneloops23:17:291
3244199631624,5cyclictest4793-21kerneloops19:16:163
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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