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2025-09-18 - 10:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Sep 18, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
345799712703,7cyclictest4927-21kerneloops20:39:073
345799709702,5cyclictest4927-21kerneloops20:55:493
345099709700,7cyclictest4927-21kerneloops21:16:172
344599709703,5cyclictest4927-21kerneloops22:51:361
344599709703,5cyclictest4927-21kerneloops22:38:241
343699709699,8cyclictest4927-21kerneloops21:39:150
345799708701,5cyclictest4927-21kerneloops20:27:263
344599708701,6cyclictest4927-21kerneloops22:11:301
344599707699,6cyclictest4927-21kerneloops23:10:541
344599707699,6cyclictest4927-21kerneloops23:10:541
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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