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2026-06-08 - 20:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Jun 08, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1596499636628,6cyclictest4793-21kerneloops09:39:533
1596499635627,6cyclictest4793-21kerneloops08:26:013
1594299635625,8cyclictest4793-21kerneloops07:56:400
1596499634628,5cyclictest4793-21kerneloops08:36:533
1596499634625,7cyclictest4793-21kerneloops12:19:263
1596499633626,6cyclictest4793-21kerneloops10:59:103
1596499633626,5cyclictest4793-21kerneloops09:50:083
1594699633626,5cyclictest4793-21kerneloops12:08:221
1594299633629,2cyclictest4793-21kerneloops12:33:240
1595799632624,6cyclictest4793-21kerneloops11:55:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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