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2026-08-23 - 02:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Aug 23, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812590,1248rtkit-daemon4793-21kerneloops19:07:042
860499663652,9cyclictest4793-21kerneloops23:29:310
862699662655,6cyclictest4793-21kerneloops20:22:033
861099662656,4cyclictest4793-21kerneloops19:39:251
861099662655,6cyclictest4793-21kerneloops19:44:491
861099662654,6cyclictest4793-21kerneloops23:08:251
860499662658,2cyclictest4793-21kerneloops23:51:400
860499662655,6cyclictest4793-21kerneloops00:02:390
860499662654,6cyclictest4793-21kerneloops23:23:270
860499662653,8cyclictest4793-21kerneloops00:30:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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