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2026-01-29 - 04:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Jan 29, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889810920,1080rtkit-daemon4793-21kerneloops19:06:260
1915199589583,5cyclictest4793-21kerneloops23:16:163
1915199589581,7cyclictest4793-21kerneloops21:09:303
1913099589580,8cyclictest4793-21kerneloops22:19:470
1913999588582,5cyclictest4793-21kerneloops22:10:451
1913999587582,4cyclictest4793-21kerneloops19:15:111
1913099587577,8cyclictest4793-21kerneloops22:36:310
1914799586579,5cyclictest4793-21kerneloops20:27:292
1913999586579,5cyclictest4793-21kerneloops00:29:311
1913999586579,5cyclictest4793-21kerneloops00:03:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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