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2026-05-05 - 01:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon May 04, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1525599637626,9cyclictest4793-21kerneloops12:03:480
1527699636628,6cyclictest4793-21kerneloops09:13:133
1526199634627,5cyclictest4793-21kerneloops08:27:021
1526199632625,5cyclictest4793-21kerneloops11:57:421
1526199632625,5cyclictest4793-21kerneloops07:23:161
1526199632624,6cyclictest4793-21kerneloops12:30:201
1525599632625,5cyclictest4793-21kerneloops11:58:570
1525599632625,5cyclictest4793-21kerneloops07:29:430
1525599632624,6cyclictest4793-21kerneloops08:53:420
1526699631623,6cyclictest4793-21kerneloops10:06:012
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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