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2026-07-11 - 13:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Jul 11, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1372699694686,6cyclictest4793-21kerneloops19:35:182
1373499663656,5cyclictest4793-21kerneloops21:21:313
1371799662653,7cyclictest4793-21kerneloops00:10:021
1373499661654,5cyclictest4793-21kerneloops23:52:293
1371799661658,2cyclictest4793-21kerneloops22:04:581
1373499660653,5cyclictest4793-21kerneloops21:39:343
1373499659656,2cyclictest4793-21kerneloops23:47:243
1371399659649,8cyclictest4793-21kerneloops23:36:130
1373499658651,6cyclictest4793-21kerneloops23:38:233
1373499658651,5cyclictest4793-21kerneloops20:53:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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