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2026-08-20 - 01:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Wed Aug 19, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812960,1281rtkit-daemon4793-21kerneloops07:08:323
811399666657,7cyclictest4793-21kerneloops08:01:443
810299664656,6cyclictest4793-21kerneloops10:19:511
809699663651,10cyclictest4793-21kerneloops11:17:570
810299662653,7cyclictest4793-21kerneloops08:38:361
811399661657,2cyclictest4793-21kerneloops12:26:243
811399661655,5cyclictest4793-21kerneloops10:38:353
811399661654,5cyclictest4793-21kerneloops11:42:423
810299661655,5cyclictest4793-21kerneloops08:51:471
811399660655,4cyclictest4793-21kerneloops12:33:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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