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2026-03-07 - 14:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Mar 06, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2663299648645,2cyclictest4793-21kerneloops11:28:133
2663299637628,7cyclictest4793-21kerneloops12:37:003
2662799635631,2cyclictest4793-21kerneloops09:36:492
2661999632623,7cyclictest4793-21kerneloops07:31:111
2661099632624,6cyclictest4793-21kerneloops07:16:150
2661099632622,8cyclictest4793-21kerneloops11:00:530
2663299630627,2cyclictest4793-21kerneloops08:09:013
2663299630627,1cyclictest4793-21kerneloops07:17:523
2662799630624,5cyclictest4793-21kerneloops10:12:022
2662799630623,5cyclictest4793-21kerneloops07:53:382
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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