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2026-09-13 - 08:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Sep 13, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
537299666657,8cyclictest4793-21kerneloops23:35:443
535499665657,6cyclictest4793-21kerneloops00:07:021
535499664658,5cyclictest4793-21kerneloops00:28:451
535499663657,5cyclictest4793-21kerneloops22:27:081
535499663654,7cyclictest4793-21kerneloops20:03:241
537299662655,6cyclictest4793-21kerneloops23:46:073
537299662654,6cyclictest4793-21kerneloops19:42:573
537299662654,6cyclictest4793-21kerneloops19:42:563
536699661653,6cyclictest4793-21kerneloops22:53:012
535499661655,5cyclictest4793-21kerneloops19:52:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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