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2026-04-13 - 22:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Apr 13, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
806499633625,6cyclictest4793-21kerneloops09:10:193
805699633625,6cyclictest4793-21kerneloops08:58:362
804799633624,7cyclictest4793-21kerneloops11:15:411
806499632626,5cyclictest4793-21kerneloops10:08:303
806499632625,5cyclictest4793-21kerneloops08:55:223
806499632624,6cyclictest4793-21kerneloops11:46:563
805699632625,6cyclictest4793-21kerneloops12:07:042
804799632624,6cyclictest4793-21kerneloops07:35:011
806499631627,2cyclictest4793-21kerneloops10:51:323
806499631627,2cyclictest4793-21kerneloops08:15:003
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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