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2026-06-04 - 22:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Jun 04, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2630299636627,7cyclictest4793-21kerneloops12:11:300
2632199635628,5cyclictest4793-21kerneloops11:26:583
2632199634626,7cyclictest4793-21kerneloops10:33:543
2632199633628,4cyclictest4793-21kerneloops12:35:493
2632199633628,4cyclictest4793-21kerneloops12:35:493
2632199633626,6cyclictest4793-21kerneloops11:11:563
2630799633626,5cyclictest4793-21kerneloops08:52:381
2630299633626,5cyclictest4793-21kerneloops08:11:030
2630299633625,6cyclictest4793-21kerneloops12:19:350
2630299633625,6cyclictest4793-21kerneloops10:28:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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