You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-14 - 11:25
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu May 14, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2749199638629,7cyclictest4793-21kerneloops22:12:360
2749699634627,6cyclictest4793-21kerneloops21:28:381
2749699634626,7cyclictest4793-21kerneloops21:57:251
2749199633623,8cyclictest4793-21kerneloops22:03:240
2750699632625,5cyclictest4793-21kerneloops23:06:133
2749699632626,5cyclictest4793-21kerneloops00:12:121
2749199632626,5cyclictest4793-21kerneloops22:57:120
2750699631625,5cyclictest4793-21kerneloops20:16:593
2749699631625,5cyclictest4793-21kerneloops23:45:071
2749699631625,5cyclictest4793-21kerneloops22:04:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional