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2026-09-19 - 09:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Sep 19, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
341299668664,2cyclictest4793-21kerneloops21:22:540
341299668657,9cyclictest4793-21kerneloops23:59:250
343499665657,6cyclictest4793-21kerneloops22:08:183
341299664654,8cyclictest4793-21kerneloops19:16:530
341299664652,10cyclictest4793-21kerneloops00:20:090
343499663657,5cyclictest4793-21kerneloops19:11:093
342699663653,8cyclictest4793-21kerneloops22:10:482
343499662656,5cyclictest4793-21kerneloops22:41:233
343499661656,4cyclictest4793-21kerneloops22:48:473
343499661654,5cyclictest4793-21kerneloops23:51:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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