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2026-07-08 - 13:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Wed Jul 08, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1914799669661,6cyclictest4793-21kerneloops21:55:402
1915499664656,6cyclictest4793-21kerneloops22:55:093
1914299663656,6cyclictest4793-21kerneloops21:38:111
1915499662654,6cyclictest4793-21kerneloops23:22:293
1915499662654,6cyclictest4793-21kerneloops23:08:103
1914299662654,6cyclictest4793-21kerneloops21:28:471
1915499661658,2cyclictest4793-21kerneloops23:14:563
1915499661655,5cyclictest4793-21kerneloops20:13:003
1914299661655,4cyclictest4793-21kerneloops00:25:421
1915499660653,5cyclictest4793-21kerneloops22:15:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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