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2026-03-21 - 15:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Mar 21, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2539299645641,2cyclictest4793-21kerneloops09:16:552
2538699635627,6cyclictest4793-21kerneloops10:52:571
2538699635626,7cyclictest4793-21kerneloops09:59:141
2539999633626,5cyclictest4793-21kerneloops11:54:513
2539999633625,6cyclictest4793-21kerneloops12:21:333
2538699633625,6cyclictest4793-21kerneloops08:29:391
2538699633624,7cyclictest4793-21kerneloops08:07:111
2539299632625,5cyclictest4793-21kerneloops12:37:192
2539299632623,7cyclictest4793-21kerneloops12:21:432
2538699632624,6cyclictest4793-21kerneloops12:28:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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