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2026-03-15 - 00:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Mar 14, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1899599635627,6cyclictest4793-21kerneloops07:10:443
1899599633625,6cyclictest4793-21kerneloops08:18:493
1897999632626,5cyclictest4793-21kerneloops10:06:551
1897999632625,5cyclictest4793-21kerneloops09:18:061
1897999632624,6cyclictest4793-21kerneloops09:33:341
1897999632624,6cyclictest4793-21kerneloops09:33:331
1897499632625,6cyclictest4793-21kerneloops07:29:590
1898799631627,2cyclictest4793-21kerneloops10:39:322
1897499631623,6cyclictest4793-21kerneloops09:09:130
1899599630622,6cyclictest4793-21kerneloops09:57:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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