You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-13 - 23:01
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Aug 13, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2909899667658,7cyclictest4793-21kerneloops11:10:112
2908999666662,2cyclictest4793-21kerneloops10:10:261
2908999665657,6cyclictest4793-21kerneloops08:06:051
2910499664655,7cyclictest4793-21kerneloops11:05:323
2908999664656,6cyclictest4793-21kerneloops10:52:051
2910499663658,4cyclictest4793-21kerneloops10:35:133
2910499663657,5cyclictest4793-21kerneloops11:16:373
2910499663657,5cyclictest4793-21kerneloops11:16:373
2909899663654,7cyclictest4793-21kerneloops09:02:262
2908999662657,4cyclictest4793-21kerneloops11:15:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional