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2026-03-01 - 08:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Mar 01, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2997399636627,7cyclictest4793-21kerneloops21:30:153
2997399635627,6cyclictest4793-21kerneloops19:37:423
2997399634627,6cyclictest4793-21kerneloops19:19:103
2997399634627,5cyclictest4793-21kerneloops23:05:473
2997399634627,5cyclictest4793-21kerneloops19:43:533
2997399634627,5cyclictest4793-21kerneloops19:31:343
2997399634626,6cyclictest4793-21kerneloops21:56:163
2997399634625,7cyclictest4793-21kerneloops22:22:473
2997399633627,5cyclictest4793-21kerneloops21:28:433
2997399633627,5cyclictest4793-21kerneloops21:06:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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