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2026-05-17 - 12:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun May 17, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811810,1169rtkit-daemon4793-21kerneloops19:08:452
1795599640636,2cyclictest4793-21kerneloops22:28:313
1794699636627,7cyclictest4793-21kerneloops00:22:522
1793999634628,5cyclictest4793-21kerneloops20:44:491
1793499634622,10cyclictest4793-21kerneloops00:28:290
1795599632629,2cyclictest4793-21kerneloops22:24:583
1795599632623,7cyclictest4793-21kerneloops23:33:433
1793499632624,6cyclictest4793-21kerneloops22:35:560
1795599631625,5cyclictest4793-21kerneloops00:18:113
1795599631624,5cyclictest4793-21kerneloops21:33:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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