You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-07 - 23:25
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Jun 07, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811930,1181rtkit-daemon4793-21kerneloops07:05:312
3050199634628,5cyclictest4793-21kerneloops08:34:311
3050199634628,4cyclictest4793-21kerneloops11:40:371
3051499633628,4cyclictest4793-21kerneloops11:01:453
3050599633627,5cyclictest4793-21kerneloops10:41:552
3050599633624,7cyclictest4793-21kerneloops09:30:292
3049499632625,6cyclictest4793-21kerneloops09:41:590
3049499632625,5cyclictest4793-21kerneloops08:44:550
3049499632624,6cyclictest4793-21kerneloops08:55:550
3050599631625,5cyclictest4793-21kerneloops08:41:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional