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2026-01-18 - 02:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat Jan 17, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889810830,1072rtkit-daemon4793-21kerneloops07:06:142
3153299599588,9cyclictest4793-21kerneloops09:36:390
3153699587577,8cyclictest4793-21kerneloops08:12:491
3155299584577,6cyclictest4793-21kerneloops11:44:383
3155299584575,7cyclictest4793-21kerneloops10:40:423
3155299583577,5cyclictest4793-21kerneloops07:53:593
3155299583576,5cyclictest4793-21kerneloops11:45:433
3155299583574,7cyclictest4793-21kerneloops12:20:473
3155299581576,4cyclictest4793-21kerneloops07:26:463
3153299581572,7cyclictest4793-21kerneloops11:40:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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