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2026-03-29 - 06:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Mar 29, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3182799658645,11cyclictest4793-21kerneloops23:27:430
3183799636632,2cyclictest4793-21kerneloops00:00:172
3183299634627,5cyclictest4793-21kerneloops19:31:111
3184899633627,5cyclictest4793-21kerneloops00:38:263
3184899633623,8cyclictest4793-21kerneloops22:54:193
3183299633626,5cyclictest4793-21kerneloops22:34:331
3182799633624,7cyclictest4793-21kerneloops00:19:040
3183799632623,7cyclictest4793-21kerneloops23:25:532
3183299632625,5cyclictest4793-21kerneloops19:16:041
3184899631626,4cyclictest4793-21kerneloops21:48:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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