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2026-03-20 - 08:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Mar 20, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811780,1166rtkit-daemon4793-21kerneloops19:07:222
558699635627,6cyclictest4793-21kerneloops20:32:183
556999634625,7cyclictest4793-21kerneloops23:22:141
556499634625,8cyclictest4793-21kerneloops22:41:320
556499633623,8cyclictest4793-21kerneloops21:31:190
558699631625,5cyclictest4793-21kerneloops20:14:083
558099631624,5cyclictest4793-21kerneloops23:39:252
556999631623,6cyclictest4793-21kerneloops22:42:151
558699630622,6cyclictest4793-21kerneloops21:27:333
558099630622,6cyclictest4793-21kerneloops23:50:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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