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2026-04-06 - 22:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Apr 06, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1000599634627,6cyclictest4793-21kerneloops09:12:483
1000599634627,5cyclictest4793-21kerneloops10:59:433
999299633626,5cyclictest4793-21kerneloops10:10:141
1000599633628,4cyclictest4793-21kerneloops09:27:333
1000599633626,5cyclictest4793-21kerneloops07:17:153
1000599632627,4cyclictest4793-21kerneloops11:45:223
1000599632624,6cyclictest4793-21kerneloops09:55:083
1000599632624,6cyclictest4793-21kerneloops07:30:093
1000599631624,6cyclictest4793-21kerneloops12:13:583
1000599631624,6cyclictest4793-21kerneloops08:25:333
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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