You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-24 - 03:44
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Apr 24, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812020,1190rtkit-daemon4793-21kerneloops19:08:190
2151599637628,7cyclictest4793-21kerneloops00:38:241
2152999635628,6cyclictest4793-21kerneloops19:57:063
2152999635628,6cyclictest4793-21kerneloops19:57:053
2152999634627,5cyclictest4793-21kerneloops19:28:243
2152999634625,7cyclictest4793-21kerneloops22:19:013
2152999631625,5cyclictest4793-21kerneloops21:00:313
2152999631625,5cyclictest4793-21kerneloops20:58:213
2152999631625,5cyclictest4793-21kerneloops20:21:133
2152999631625,5cyclictest4793-21kerneloops00:38:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional