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2025-11-18 - 10:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Tue Nov 18, 2025 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2031799812802,8cyclictest4927-21kerneloops23:53:100
2032499799790,7cyclictest4927-21kerneloops22:53:421
2032499798792,4cyclictest4927-21kerneloops23:35:431
2032499798790,6cyclictest4927-21kerneloops23:19:041
2033499797790,5cyclictest4927-21kerneloops19:21:483
2033499796789,5cyclictest4927-21kerneloops21:03:233
2032499796790,5cyclictest4927-21kerneloops20:47:181
2033499795787,7cyclictest4927-21kerneloops00:26:043
2032999795787,6cyclictest4927-21kerneloops23:19:592
2032499795788,5cyclictest4927-21kerneloops22:57:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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