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2026-05-09 - 02:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sat May 09, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3061299647637,8cyclictest4793-21kerneloops00:19:042
3061299642633,7cyclictest4793-21kerneloops22:40:182
3059999638628,8cyclictest4793-21kerneloops23:50:040
3062099635628,6cyclictest4793-21kerneloops22:36:383
3062099635626,7cyclictest4793-21kerneloops22:26:453
3062099635626,7cyclictest4793-21kerneloops22:26:443
3062099634625,7cyclictest4793-21kerneloops19:26:193
3062099633627,5cyclictest4793-21kerneloops21:34:133
3062099633624,7cyclictest4793-21kerneloops23:45:183
3062099632626,4cyclictest4793-21kerneloops19:33:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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