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2026-04-05 - 20:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Sun Apr 05, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2368499633626,5cyclictest4793-21kerneloops09:40:053
2368499633625,6cyclictest4793-21kerneloops07:49:573
2367899633625,7cyclictest4793-21kerneloops09:21:282
2368499632627,4cyclictest4793-21kerneloops12:08:113
2368499632626,5cyclictest4793-21kerneloops11:00:413
2367299632626,5cyclictest4793-21kerneloops11:29:241
2368499631626,4cyclictest4793-21kerneloops11:38:163
2368499631625,5cyclictest4793-21kerneloops08:07:073
2368499631622,7cyclictest4793-21kerneloops09:35:063
2367899631621,8cyclictest4793-21kerneloops11:17:382
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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