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2026-01-19 - 02:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Mon Jan 19, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2905299585576,7cyclictest4793-21kerneloops23:31:081
2904799585576,8cyclictest4793-21kerneloops00:15:240
2904799584573,9cyclictest4793-21kerneloops00:28:180
2905299583577,5cyclictest4793-21kerneloops21:43:021
2905299583577,5cyclictest4793-21kerneloops19:14:301
2904799583574,7cyclictest4793-21kerneloops21:18:010
2906899582577,4cyclictest4793-21kerneloops20:38:543
2906899582576,5cyclictest4793-21kerneloops20:14:493
2904799582573,7cyclictest4793-21kerneloops20:25:040
2904799582573,5cyclictest4793-21kerneloops19:51:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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