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2026-03-19 - 05:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Thu Mar 19, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
327699636632,2cyclictest4793-21kerneloops22:35:361
328399634624,8cyclictest4793-21kerneloops21:22:482
327099634622,10cyclictest4793-21kerneloops21:12:200
328999633625,6cyclictest4793-21kerneloops22:11:523
327099633624,7cyclictest4793-21kerneloops21:59:230
328999632624,6cyclictest4793-21kerneloops20:36:153
328399632624,6cyclictest4793-21kerneloops21:09:272
328399632624,6cyclictest4793-21kerneloops20:34:322
327699632625,6cyclictest4793-21kerneloops23:59:461
327699631624,6cyclictest4793-21kerneloops23:19:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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