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2026-06-26 - 07:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Jun 26, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812570,1246rtkit-daemon4793-21kerneloops19:08:523
1794899674661,11cyclictest4793-21kerneloops22:50:320
1794899674661,11cyclictest4793-21kerneloops22:50:320
1795399664656,6cyclictest4793-21kerneloops00:35:251
1795399664656,6cyclictest4793-21kerneloops00:35:251
1797099663656,5cyclictest4793-21kerneloops23:15:073
1795399662652,8cyclictest4793-21kerneloops19:31:061
1796499661654,5cyclictest4793-21kerneloops23:55:242
1796499661652,5cyclictest4793-21kerneloops20:14:482
1794899661651,8cyclictest4793-21kerneloops00:25:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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