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2026-08-07 - 22:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Fri Aug 07, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
530399675664,9cyclictest4793-21kerneloops09:31:170
531599674670,2cyclictest4793-21kerneloops12:01:462
530399674661,11cyclictest4793-21kerneloops09:19:380
532499665656,7cyclictest4793-21kerneloops10:21:393
531599665661,2cyclictest4793-21kerneloops11:05:262
532499664655,7cyclictest4793-21kerneloops09:45:413
531099664655,7cyclictest4793-21kerneloops08:36:051
532499661654,5cyclictest4793-21kerneloops11:16:183
532499660657,2cyclictest4793-21kerneloops10:53:263
532499660654,5cyclictest4793-21kerneloops09:07:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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