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2026-06-11 - 00:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack6slot8.osadl.org (updated Wed Jun 10, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1809899637627,8cyclictest4793-21kerneloops10:11:003
1809899636627,7cyclictest4793-21kerneloops11:18:473
1808399636629,5cyclictest4793-21kerneloops09:59:141
1809899635626,7cyclictest4793-21kerneloops09:24:083
1809899634628,5cyclictest4793-21kerneloops09:36:433
1809899634627,6cyclictest4793-21kerneloops10:29:053
1809899634627,5cyclictest4793-21kerneloops11:49:163
1809899634627,5cyclictest4793-21kerneloops11:42:473
1809899634627,5cyclictest4793-21kerneloops08:59:493
1809899634626,6cyclictest4793-21kerneloops09:18:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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