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2026-06-27 - 22:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Jun 27, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
97899665659,4cyclictest4793-21kerneloops12:09:271
98999664656,6cyclictest4793-21kerneloops11:03:103
97899664658,5cyclictest4793-21kerneloops10:00:531
98999663656,5cyclictest4793-21kerneloops07:58:463
98999661655,4cyclictest4793-21kerneloops12:39:393
98999661655,4cyclictest4793-21kerneloops08:23:153
98999661654,5cyclictest4793-21kerneloops07:31:303
96799661652,7cyclictest4793-21kerneloops09:43:110
98999660657,2cyclictest4793-21kerneloops11:28:503
98999660654,5cyclictest4793-21kerneloops08:56:353
97899660653,5cyclictest4793-21kerneloops11:12:421
96799660651,7cyclictest4793-21kerneloops09:26:020
98999659652,5cyclictest4793-21kerneloops08:17:163
98499659653,5cyclictest4793-21kerneloops12:36:572
98499659653,4cyclictest4793-21kerneloops11:41:002
98499659651,7cyclictest4793-21kerneloops11:31:102
96799659652,5cyclictest4793-21kerneloops07:53:070
96799659648,9cyclictest4793-21kerneloops11:56:140
98499658653,4cyclictest4793-21kerneloops11:22:402
97899658654,2cyclictest4793-21kerneloops07:23:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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