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2025-11-26 - 03:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Nov 26, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2103699813802,9cyclictest4927-21kerneloops22:16:380
2105299801791,8cyclictest4927-21kerneloops00:22:152
2104699798790,6cyclictest4927-21kerneloops19:58:221
2104699797790,5cyclictest4927-21kerneloops20:09:191
2104699797790,5cyclictest4927-21kerneloops20:09:181
2104699797790,5cyclictest4927-21kerneloops19:15:411
2105999796788,6cyclictest4927-21kerneloops19:23:363
2105299796788,6cyclictest4927-21kerneloops20:59:482
2104699796789,5cyclictest4927-21kerneloops21:29:391
2104699796789,5cyclictest4927-21kerneloops19:32:211
2103699796788,6cyclictest4927-21kerneloops22:10:410
2105999795788,6cyclictest4927-21kerneloops20:04:463
2105999795787,6cyclictest4927-21kerneloops21:07:013
2104699795788,5cyclictest4927-21kerneloops23:36:311
2104699795788,5cyclictest4927-21kerneloops00:09:381
2105999794787,5cyclictest4927-21kerneloops21:30:003
2105299794787,5cyclictest4927-21kerneloops19:52:382
2104699794788,4cyclictest4927-21kerneloops20:14:521
2105999792788,2cyclictest4927-21kerneloops19:28:033
2105999792785,5cyclictest4927-21kerneloops21:28:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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