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2026-04-29 - 05:03
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Apr 29, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2733499636627,7cyclictest4793-21kerneloops19:43:481
2732799636627,7cyclictest4793-21kerneloops00:01:460
2734799635628,5cyclictest4793-21kerneloops20:15:013
2734799635627,6cyclictest4793-21kerneloops22:57:493
2734799634627,5cyclictest4793-21kerneloops19:15:263
2734799633628,3cyclictest4793-21kerneloops22:04:503
2734799633626,5cyclictest4793-21kerneloops21:38:433
2732799633625,7cyclictest4793-21kerneloops00:29:290
2732799633625,7cyclictest4793-21kerneloops00:29:280
2732799633623,9cyclictest4793-21kerneloops21:58:500
2734799632626,5cyclictest4793-21kerneloops22:52:543
2734799632625,5cyclictest4793-21kerneloops20:27:343
2734799631625,4cyclictest4793-21kerneloops23:34:013
2733999631625,4cyclictest4793-21kerneloops19:45:562
2733999631624,5cyclictest4793-21kerneloops19:21:382
2733999631623,6cyclictest4793-21kerneloops00:23:402
2733999631622,7cyclictest4793-21kerneloops20:12:532
2733499631622,7cyclictest4793-21kerneloops23:18:141
2732799631622,7cyclictest4793-21kerneloops00:38:480
2734799630627,2cyclictest4793-21kerneloops23:12:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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