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2026-05-12 - 21:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue May 12, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2911299641629,10cyclictest4793-21kerneloops11:55:040
2913299636627,7cyclictest4793-21kerneloops11:34:343
2913299635628,5cyclictest4793-21kerneloops11:18:223
2913299635628,5cyclictest4793-21kerneloops08:24:003
2913299635628,5cyclictest4793-21kerneloops07:20:553
2911899635627,6cyclictest4793-21kerneloops09:48:521
2913299634629,4cyclictest4793-21kerneloops11:03:323
2913299634629,4cyclictest4793-21kerneloops11:03:313
2913299634628,5cyclictest4793-21kerneloops09:47:043
2913299634628,4cyclictest4793-21kerneloops10:29:133
2913299634627,5cyclictest4793-21kerneloops11:07:313
2913299634627,5cyclictest4793-21kerneloops07:47:553
2913299634626,6cyclictest4793-21kerneloops08:52:123
2913299634626,6cyclictest4793-21kerneloops08:04:343
2913299634626,6cyclictest4793-21kerneloops07:58:403
2911899634626,6cyclictest4793-21kerneloops08:13:301
2911899634625,7cyclictest4793-21kerneloops11:58:351
2913299633628,4cyclictest4793-21kerneloops12:11:213
2913299633628,4cyclictest4793-21kerneloops09:01:193
2913299633627,5cyclictest4793-21kerneloops12:33:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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