You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-10 - 20:53
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Jan 10, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3152899584577,5cyclictest4793-21kerneloops11:36:341
3152899583577,5cyclictest4793-21kerneloops12:34:291
3152899583576,6cyclictest4793-21kerneloops09:16:571
3152199583574,7cyclictest4793-21kerneloops12:13:210
3154399582574,7cyclictest4793-21kerneloops12:12:583
3154399582574,6cyclictest4793-21kerneloops10:39:003
3152199582574,6cyclictest4793-21kerneloops09:18:320
3154399581572,7cyclictest4793-21kerneloops10:05:403
3153699581574,6cyclictest4793-21kerneloops12:06:592
3153699581573,6cyclictest4793-21kerneloops07:58:392
3152199581573,7cyclictest4793-21kerneloops07:27:300
3154399580573,6cyclictest4793-21kerneloops09:55:343
3152899580575,4cyclictest4793-21kerneloops10:36:181
3152199580573,5cyclictest4793-21kerneloops08:22:050
3152199580572,6cyclictest4793-21kerneloops08:13:060
3154399579577,1cyclictest4793-21kerneloops09:06:343
3154399579572,5cyclictest4793-21kerneloops08:08:163
3154399579570,7cyclictest4793-21kerneloops10:12:403
3152199579572,6cyclictest4793-21kerneloops09:39:540
3152199579570,7cyclictest4793-21kerneloops09:40:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional