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2026-03-18 - 06:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Mar 18, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2293399639631,6cyclictest4793-21kerneloops23:00:171
2294099635631,2cyclictest4793-21kerneloops00:25:072
2293399635626,7cyclictest4793-21kerneloops19:10:121
2294699634626,6cyclictest4793-21kerneloops21:16:493
2293399633626,5cyclictest4793-21kerneloops19:39:171
2292499632625,5cyclictest4793-21kerneloops22:43:300
2294699631623,6cyclictest4793-21kerneloops21:32:313
2293399630624,4cyclictest4793-21kerneloops22:18:041
2293399630623,6cyclictest4793-21kerneloops19:51:571
2294699629626,2cyclictest4793-21kerneloops19:33:453
2294699629625,2cyclictest4793-21kerneloops00:33:083
2294699629624,4cyclictest4793-21kerneloops00:36:403
2294099629626,2cyclictest4793-21kerneloops21:39:392
2294099629623,5cyclictest4793-21kerneloops21:53:322
2293399629627,1cyclictest4793-21kerneloops20:40:461
2293399629626,2cyclictest4793-21kerneloops22:35:451
2293399629625,2cyclictest4793-21kerneloops21:32:201
2292499629622,5cyclictest4793-21kerneloops23:45:290
2294699628620,6cyclictest4793-21kerneloops19:13:263
2292499628621,6cyclictest4793-21kerneloops23:35:580
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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