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2026-05-08 - 18:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri May 08, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
871799640630,8cyclictest4793-21kerneloops10:04:303
870199635628,6cyclictest4793-21kerneloops10:56:081
871799634626,6cyclictest4793-21kerneloops09:28:263
871799634626,6cyclictest4793-21kerneloops07:43:023
870199634626,6cyclictest4793-21kerneloops07:47:161
870199633626,5cyclictest4793-21kerneloops11:55:241
869699633623,9cyclictest4793-21kerneloops11:57:520
871799632623,7cyclictest4793-21kerneloops11:42:083
871199632623,7cyclictest4793-21kerneloops09:05:552
870199632625,6cyclictest4793-21kerneloops12:08:531
869699632624,6cyclictest4793-21kerneloops12:28:420
871199631624,5cyclictest4793-21kerneloops11:47:582
871199631623,6cyclictest4793-21kerneloops10:26:552
871199631622,7cyclictest4793-21kerneloops07:21:052
869699631623,6cyclictest4793-21kerneloops09:19:160
871799630624,5cyclictest4793-21kerneloops09:23:273
871799630623,5cyclictest4793-21kerneloops10:55:143
871199630624,4cyclictest4793-21kerneloops10:06:492
871199630620,6cyclictest4793-21kerneloops07:27:372
870199630623,5cyclictest4793-21kerneloops09:33:221
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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