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2026-01-22 - 21:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Jan 22, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2014299584571,11cyclictest4793-21kerneloops07:27:161
2015599583576,6cyclictest4793-21kerneloops11:56:163
2014999583574,7cyclictest4793-21kerneloops10:36:302
2014999582574,6cyclictest4793-21kerneloops07:27:062
2014299582573,7cyclictest4793-21kerneloops11:20:101
2015599581575,5cyclictest4793-21kerneloops09:45:213
2014299581574,5cyclictest4793-21kerneloops08:26:491
2015599580573,5cyclictest4793-21kerneloops10:21:593
2014999580574,5cyclictest4793-21kerneloops10:40:432
2014999580574,5cyclictest4793-21kerneloops08:11:562
2014999580573,5cyclictest4793-21kerneloops09:58:142
2014999580573,5cyclictest4793-21kerneloops07:40:352
2013499580576,2cyclictest4793-21kerneloops11:38:530
2015599579572,5cyclictest4793-21kerneloops08:29:523
2014299579576,2cyclictest4793-21kerneloops11:18:131
2014299579576,2cyclictest4793-21kerneloops09:00:531
2014299579572,6cyclictest4793-21kerneloops09:50:241
2014299579572,5cyclictest4793-21kerneloops08:21:441
2013499579573,5cyclictest4793-21kerneloops08:02:470
2013499579572,5cyclictest4793-21kerneloops09:00:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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