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2025-08-21 - 22:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Aug 21, 2025 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2558499723714,7cyclictest4927-21kerneloops10:50:143
2558499711703,6cyclictest4927-21kerneloops09:13:193
2556699711700,9cyclictest4927-21kerneloops09:25:120
2556699711700,9cyclictest4927-21kerneloops09:25:110
2558499710702,6cyclictest4927-21kerneloops07:59:213
2558499709703,4cyclictest4927-21kerneloops08:31:003
2558499709703,4cyclictest4927-21kerneloops07:27:333
2558499709702,5cyclictest4927-21kerneloops07:14:083
2558499708701,5cyclictest4927-21kerneloops09:45:393
2558499708700,6cyclictest4927-21kerneloops10:34:063
2558499707702,4cyclictest4927-21kerneloops10:36:343
2558499707700,5cyclictest4927-21kerneloops10:20:373
2558499707700,5cyclictest4927-21kerneloops09:19:043
2557799707699,6cyclictest4927-21kerneloops11:32:542
2557799707699,6cyclictest4927-21kerneloops10:29:402
2557799707698,7cyclictest4927-21kerneloops09:28:112
2557799707698,7cyclictest4927-21kerneloops09:28:102
2558499706700,5cyclictest4927-21kerneloops08:40:173
2558499706700,4cyclictest4927-21kerneloops07:22:363
2557799706700,5cyclictest4927-21kerneloops12:29:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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