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2026-02-24 - 02:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Feb 24, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
623199635627,6cyclictest4793-21kerneloops19:54:411
623199634626,6cyclictest4793-21kerneloops20:50:051
624899633625,6cyclictest4793-21kerneloops21:55:583
623199633628,4cyclictest4793-21kerneloops23:39:421
623199633626,5cyclictest4793-21kerneloops23:49:481
623199633626,5cyclictest4793-21kerneloops19:48:061
624099632625,5cyclictest4793-21kerneloops19:58:432
624099632624,7cyclictest4793-21kerneloops23:53:422
623199632626,4cyclictest4793-21kerneloops00:21:351
624899631625,5cyclictest4793-21kerneloops20:37:543
623199631625,4cyclictest4793-21kerneloops22:37:081
623199631625,4cyclictest4793-21kerneloops20:12:431
623199631624,5cyclictest4793-21kerneloops23:08:001
624899630621,7cyclictest4793-21kerneloops00:33:533
624099630623,5cyclictest4793-21kerneloops22:56:472
624099630622,6cyclictest4793-21kerneloops20:39:432
624099629621,6cyclictest4793-21kerneloops20:02:492
623199629626,2cyclictest4793-21kerneloops19:18:371
623199629622,5cyclictest4793-21kerneloops00:06:551
622799629621,6cyclictest4793-21kerneloops23:33:220
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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