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2026-06-03 - 12:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Jun 03, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3147399644640,2cyclictest4793-21kerneloops21:47:343
3146099636628,6cyclictest4793-21kerneloops20:37:401
3147399634628,5cyclictest4793-21kerneloops20:59:323
3146099634625,7cyclictest4793-21kerneloops19:52:511
3145499634622,10cyclictest4793-21kerneloops22:55:540
3147399633625,7cyclictest4793-21kerneloops22:02:483
3146899633625,6cyclictest4793-21kerneloops21:57:482
3146899633624,7cyclictest4793-21kerneloops00:02:432
3146099633625,6cyclictest4793-21kerneloops23:26:331
3146099633625,6cyclictest4793-21kerneloops23:26:321
3147399632626,4cyclictest4793-21kerneloops20:47:483
3147399632624,6cyclictest4793-21kerneloops22:50:073
3146099632624,6cyclictest4793-21kerneloops23:51:341
3146099632620,10cyclictest4793-21kerneloops22:12:491
3147399631628,2cyclictest4793-21kerneloops20:51:463
3146099631628,2cyclictest4793-21kerneloops20:02:371
3146099631623,6cyclictest4793-21kerneloops21:56:271
3147399630628,1cyclictest4793-21kerneloops20:38:363
3147399630624,4cyclictest4793-21kerneloops00:18:143
3146899630625,4cyclictest4793-21kerneloops23:45:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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