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2026-02-19 - 21:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Feb 19, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2409099664661,2cyclictest4793-21kerneloops08:35:180
2409599635625,8cyclictest4793-21kerneloops09:54:321
2409099635631,2cyclictest4793-21kerneloops11:10:490
2409599632625,5cyclictest4793-21kerneloops11:37:461
2409599632624,7cyclictest4793-21kerneloops10:21:531
2410999631625,5cyclictest4793-21kerneloops07:55:463
2410999631624,5cyclictest4793-21kerneloops09:52:253
2410399631624,6cyclictest4793-21kerneloops08:22:322
2410399631623,6cyclictest4793-21kerneloops10:06:222
2410399631623,6cyclictest4793-21kerneloops08:25:072
2409599631621,8cyclictest4793-21kerneloops09:36:421
2410999630627,2cyclictest4793-21kerneloops10:23:343
2409599630623,6cyclictest4793-21kerneloops12:29:191
2410399629623,4cyclictest4793-21kerneloops09:02:192
2409599629623,5cyclictest4793-21kerneloops09:32:151
2409099629622,6cyclictest4793-21kerneloops10:37:460
2409099629620,8cyclictest4793-21kerneloops11:24:020
2410999628621,6cyclictest4793-21kerneloops09:16:403
2410999628620,6cyclictest4793-21kerneloops11:31:373
2410999628620,6cyclictest4793-21kerneloops09:37:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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