You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-05-03 - 02:02
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri May 02, 2025 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2433199711701,8cyclictest4927-21kerneloops11:09:270
2435599708702,5cyclictest4927-21kerneloops12:37:123
2434299708702,5cyclictest4927-21kerneloops12:29:351
2434299708701,5cyclictest4927-21kerneloops12:32:281
2434299708701,5cyclictest4927-21kerneloops10:39:211
2434899706699,6cyclictest4927-21kerneloops07:25:562
2434899706699,5cyclictest4927-21kerneloops12:04:402
2433199706699,5cyclictest4927-21kerneloops08:06:470
2434299705702,2cyclictest4927-21kerneloops09:38:051
2434299705702,2cyclictest4927-21kerneloops07:51:461
2434299705702,1cyclictest4927-21kerneloops07:22:331
2433199705697,6cyclictest4927-21kerneloops07:51:130
2433199705696,7cyclictest4927-21kerneloops10:13:280
2435599704701,2cyclictest4927-21kerneloops11:00:313
2435599704697,5cyclictest4927-21kerneloops09:16:483
2434899704698,5cyclictest4927-21kerneloops09:01:132
2433199704697,5cyclictest4927-21kerneloops08:18:380
2433199704696,6cyclictest4927-21kerneloops07:19:360
2435599703700,2cyclictest4927-21kerneloops12:20:113
2435599703700,2cyclictest4927-21kerneloops10:35:573
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional