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2026-09-05 - 21:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Sep 05, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2258199670666,2cyclictest4793-21kerneloops10:00:010
2260399664656,6cyclictest4793-21kerneloops12:25:433
2258699664655,7cyclictest4793-21kerneloops09:46:181
2260399663654,7cyclictest4793-21kerneloops11:51:193
2259799662653,7cyclictest4793-21kerneloops08:19:552
2260399661653,6cyclictest4793-21kerneloops08:26:273
2258699661655,5cyclictest4793-21kerneloops11:22:201
2258199661654,6cyclictest4793-21kerneloops10:11:300
2260399660654,5cyclictest4793-21kerneloops11:32:043
2260399660654,5cyclictest4793-21kerneloops09:14:223
2260399660654,5cyclictest4793-21kerneloops08:34:103
2260399660652,6cyclictest4793-21kerneloops08:00:263
2258699660651,7cyclictest4793-21kerneloops10:33:311
2258199660647,11cyclictest4793-21kerneloops11:14:540
2258699659656,1cyclictest4793-21kerneloops09:51:241
2258699659656,1cyclictest4793-21kerneloops09:51:231
2258699659655,2cyclictest4793-21kerneloops11:48:191
2258699659653,5cyclictest4793-21kerneloops09:26:161
2258699659653,4cyclictest4793-21kerneloops08:09:081
2258699659652,5cyclictest4793-21kerneloops07:59:031
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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