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2026-01-13 - 23:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Jan 13, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
151899585576,7cyclictest4793-21kerneloops07:30:211
153099584576,6cyclictest4793-21kerneloops11:46:033
150999584575,8cyclictest4793-21kerneloops09:30:290
153099583576,5cyclictest4793-21kerneloops07:17:063
153099583575,7cyclictest4793-21kerneloops09:42:453
153099583575,6cyclictest4793-21kerneloops11:40:023
152499583574,7cyclictest4793-21kerneloops12:37:502
151899583575,6cyclictest4793-21kerneloops11:16:341
151899583575,6cyclictest4793-21kerneloops08:14:021
150999582573,8cyclictest4793-21kerneloops09:39:420
150999582573,7cyclictest4793-21kerneloops11:20:510
153099581574,5cyclictest4793-21kerneloops08:59:023
153099581573,6cyclictest4793-21kerneloops09:33:503
151899580572,6cyclictest4793-21kerneloops11:22:151
151899580572,6cyclictest4793-21kerneloops07:39:241
150999580571,7cyclictest4793-21kerneloops12:11:570
150999580571,7cyclictest4793-21kerneloops10:44:190
150999580571,7cyclictest4793-21kerneloops08:32:400
153099579573,5cyclictest4793-21kerneloops11:09:403
152499579571,7cyclictest4793-21kerneloops08:05:432
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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