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2026-05-19 - 00:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon May 18, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
526999647637,8cyclictest4793-21kerneloops09:27:520
527599641637,2cyclictest4793-21kerneloops10:44:231
527599636628,6cyclictest4793-21kerneloops07:33:061
527599636627,7cyclictest4793-21kerneloops09:53:501
529099634626,6cyclictest4793-21kerneloops11:19:203
526999634626,6cyclictest4793-21kerneloops09:40:390
529099633625,6cyclictest4793-21kerneloops09:45:523
527599633628,4cyclictest4793-21kerneloops09:44:141
527599633628,4cyclictest4793-21kerneloops08:19:341
526999633624,8cyclictest4793-21kerneloops12:06:070
526999633623,8cyclictest4793-21kerneloops10:40:310
528499632624,7cyclictest4793-21kerneloops07:31:202
528499631627,2cyclictest4793-21kerneloops11:47:522
529099630624,5cyclictest4793-21kerneloops10:16:183
528499630623,6cyclictest4793-21kerneloops09:47:172
528499630622,7cyclictest4793-21kerneloops09:59:062
527599630627,1cyclictest4793-21kerneloops11:05:101
527599630627,1cyclictest4793-21kerneloops08:45:061
529099629626,2cyclictest4793-21kerneloops09:11:073
529099629620,7cyclictest4793-21kerneloops08:19:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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