You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-30 - 18:30
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Aug 30, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1245399667663,2cyclictest4793-21kerneloops12:15:093
1245399667663,2cyclictest4793-21kerneloops12:15:093
1245399667663,2cyclictest4793-21kerneloops10:32:123
1245399664659,3cyclictest4793-21kerneloops12:28:333
1245399664657,5cyclictest4793-21kerneloops12:32:113
1245399664657,5cyclictest4793-21kerneloops10:39:523
1244699662652,8cyclictest4793-21kerneloops11:45:592
1243799662654,6cyclictest4793-21kerneloops12:02:091
1243799662653,7cyclictest4793-21kerneloops10:21:311
1245399661654,5cyclictest4793-21kerneloops11:26:463
1244699661652,7cyclictest4793-21kerneloops11:30:182
1244699661652,7cyclictest4793-21kerneloops11:25:192
1243799661657,2cyclictest4793-21kerneloops12:09:571
1243799661653,7cyclictest4793-21kerneloops11:25:301
1245399660654,4cyclictest4793-21kerneloops11:50:043
1243799660657,2cyclictest4793-21kerneloops09:38:441
1243799660651,7cyclictest4793-21kerneloops10:50:431
1243399660653,5cyclictest4793-21kerneloops08:31:570
1243399660652,7cyclictest4793-21kerneloops08:53:350
1245399659652,6cyclictest4793-21kerneloops12:01:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional