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2026-05-25 - 06:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon May 25, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2538399666659,5cyclictest4793-21kerneloops20:55:171
2539999633626,5cyclictest4793-21kerneloops21:16:353
2539999633626,5cyclictest4793-21kerneloops19:21:243
2539999632627,4cyclictest4793-21kerneloops00:29:003
2537899632623,7cyclictest4793-21kerneloops22:50:050
2539999631627,2cyclictest4793-21kerneloops20:01:233
2539999631626,4cyclictest4793-21kerneloops22:18:403
2539999631625,5cyclictest4793-21kerneloops23:47:283
2537899631624,6cyclictest4793-21kerneloops22:02:100
2539999630626,2cyclictest4793-21kerneloops21:42:393
2539999629621,6cyclictest4793-21kerneloops21:05:023
2539299629626,1cyclictest4793-21kerneloops22:30:562
2537899629623,5cyclictest4793-21kerneloops23:19:060
2539999628625,2cyclictest4793-21kerneloops20:12:453
2539299628624,2cyclictest4793-21kerneloops19:15:572
2539299628622,5cyclictest4793-21kerneloops20:50:362
2539299628622,4cyclictest4793-21kerneloops22:21:212
2539299628621,5cyclictest4793-21kerneloops20:30:112
2537899628618,8cyclictest4793-21kerneloops00:16:430
2539299627624,2cyclictest4793-21kerneloops23:50:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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