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2026-02-20 - 22:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Feb 20, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2026899636627,7cyclictest4793-21kerneloops08:58:323
2026899635628,5cyclictest4793-21kerneloops08:45:533
2026899635627,6cyclictest4793-21kerneloops11:42:463
2026899634627,5cyclictest4793-21kerneloops10:29:533
2026899634626,6cyclictest4793-21kerneloops12:19:543
2026899634626,6cyclictest4793-21kerneloops08:53:173
2026899633627,5cyclictest4793-21kerneloops10:45:283
2026899633627,4cyclictest4793-21kerneloops08:00:293
2026899633626,5cyclictest4793-21kerneloops11:21:033
2026899633626,5cyclictest4793-21kerneloops10:15:053
2026899633626,5cyclictest4793-21kerneloops08:32:273
2026899633626,5cyclictest4793-21kerneloops08:11:223
2026899633625,6cyclictest4793-21kerneloops07:53:443
2026899632626,5cyclictest4793-21kerneloops10:56:293
2026899632625,5cyclictest4793-21kerneloops12:04:513
2026899632625,5cyclictest4793-21kerneloops07:48:553
2026899632624,6cyclictest4793-21kerneloops07:21:173
2025299632625,5cyclictest4793-21kerneloops08:39:371
2024599632624,6cyclictest4793-21kerneloops08:54:080
2026899631624,5cyclictest4793-21kerneloops07:40:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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