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2026-08-21 - 17:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Aug 21, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3216199664655,7cyclictest4793-21kerneloops07:50:301
3215699662653,7cyclictest4793-21kerneloops11:10:350
3217299661657,2cyclictest4793-21kerneloops12:39:452
3216199661654,5cyclictest4793-21kerneloops11:03:101
3217899660653,5cyclictest4793-21kerneloops10:20:203
3216199660657,2cyclictest4793-21kerneloops10:14:261
3215699660652,6cyclictest4793-21kerneloops12:21:470
3215699660648,10cyclictest4793-21kerneloops11:51:030
3217899659654,4cyclictest4793-21kerneloops11:44:213
3217899659653,5cyclictest4793-21kerneloops12:07:083
3217899659652,5cyclictest4793-21kerneloops09:21:253
3217899659650,7cyclictest4793-21kerneloops09:39:553
3216199659654,4cyclictest4793-21kerneloops12:38:191
3216199659654,4cyclictest4793-21kerneloops10:54:121
3217299658655,2cyclictest4793-21kerneloops08:18:372
3216199658655,2cyclictest4793-21kerneloops11:44:111
3216199658651,5cyclictest4793-21kerneloops10:07:251
3217899657654,2cyclictest4793-21kerneloops11:00:323
3217899657654,2cyclictest4793-21kerneloops08:18:473
3217299657652,4cyclictest4793-21kerneloops08:02:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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