You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2025-12-06 - 04:59
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Dec 06, 2025 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2963599808798,8cyclictest4927-21kerneloops23:56:033
2963599807803,2cyclictest4927-21kerneloops21:25:423
2963599799791,6cyclictest4927-21kerneloops19:38:293
2961899798789,7cyclictest4927-21kerneloops19:36:511
2963599797790,6cyclictest4927-21kerneloops23:23:323
2961899797790,5cyclictest4927-21kerneloops22:06:481
2961899797789,6cyclictest4927-21kerneloops00:22:061
2961899796790,5cyclictest4927-21kerneloops00:04:401
2961499796786,8cyclictest4927-21kerneloops22:26:520
2961499796786,8cyclictest4927-21kerneloops22:10:540
2961899794786,6cyclictest4927-21kerneloops22:10:331
2963599793787,5cyclictest4927-21kerneloops21:32:173
2963599793784,7cyclictest4927-21kerneloops00:08:113
2962799793785,6cyclictest4927-21kerneloops19:39:222
2961899793787,4cyclictest4927-21kerneloops23:32:121
2961899793786,5cyclictest4927-21kerneloops23:53:171
2961899793786,5cyclictest4927-21kerneloops20:21:251
2961499793783,8cyclictest4927-21kerneloops23:46:550
2963599792786,4cyclictest4927-21kerneloops20:02:213
2963599792784,7cyclictest4927-21kerneloops22:17:373
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional