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2026-09-18 - 01:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Sep 17, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2921299685675,8cyclictest4793-21kerneloops11:56:060
2923399666657,7cyclictest4793-21kerneloops10:27:443
2923399666656,8cyclictest4793-21kerneloops11:04:163
2923399665658,5cyclictest4793-21kerneloops12:14:203
2923399665658,5cyclictest4793-21kerneloops10:16:023
2923399665655,8cyclictest4793-21kerneloops12:20:453
2923399665655,8cyclictest4793-21kerneloops11:05:483
2922199665657,6cyclictest4793-21kerneloops11:44:261
2922199665657,6cyclictest4793-21kerneloops08:50:171
2923399664657,5cyclictest4793-21kerneloops11:33:103
2923399664656,6cyclictest4793-21kerneloops11:45:373
2923399664654,8cyclictest4793-21kerneloops09:35:103
2921299664655,7cyclictest4793-21kerneloops11:04:380
2923399663657,5cyclictest4793-21kerneloops09:06:103
2923399663656,5cyclictest4793-21kerneloops07:45:283
2923399663655,6cyclictest4793-21kerneloops10:30:333
2923399663655,6cyclictest4793-21kerneloops09:16:293
2921299663659,2cyclictest4793-21kerneloops10:58:140
2923399662656,5cyclictest4793-21kerneloops12:28:423
2923399662656,5cyclictest4793-21kerneloops11:52:433
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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