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2026-02-07 - 14:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Feb 07, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1713999588581,6cyclictest4793-21kerneloops11:28:123
1713199588580,6cyclictest4793-21kerneloops07:14:242
1713999587580,5cyclictest4793-21kerneloops10:57:443
1713999587580,5cyclictest4793-21kerneloops10:08:413
1713999587579,6cyclictest4793-21kerneloops12:09:413
1713999587577,8cyclictest4793-21kerneloops11:09:083
1713999586581,4cyclictest4793-21kerneloops10:54:073
1713999586579,6cyclictest4793-21kerneloops11:45:353
1713999586578,7cyclictest4793-21kerneloops07:18:423
1713199586578,6cyclictest4793-21kerneloops08:51:072
1712699586581,4cyclictest4793-21kerneloops08:59:251
1713999585580,4cyclictest4793-21kerneloops09:42:043
1713999585579,5cyclictest4793-21kerneloops12:01:173
1713999585579,4cyclictest4793-21kerneloops08:01:403
1713999585578,5cyclictest4793-21kerneloops12:24:363
1713999585577,6cyclictest4793-21kerneloops09:35:263
1713999585577,6cyclictest4793-21kerneloops09:03:213
1713999585577,6cyclictest4793-21kerneloops08:17:353
1713199585578,6cyclictest4793-21kerneloops09:41:222
1712699585580,4cyclictest4793-21kerneloops07:23:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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