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2026-02-28 - 04:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Feb 28, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1835099639635,2cyclictest4793-21kerneloops22:22:330
1837199638629,7cyclictest4793-21kerneloops22:27:113
1835699633626,5cyclictest4793-21kerneloops22:03:351
1835699632625,5cyclictest4793-21kerneloops00:29:431
1835099632624,6cyclictest4793-21kerneloops22:31:050
1836099631623,7cyclictest4793-21kerneloops23:57:092
1837199630622,7cyclictest4793-21kerneloops23:23:103
1836099630623,6cyclictest4793-21kerneloops22:18:062
1836099630622,6cyclictest4793-21kerneloops21:59:422
1835699630624,5cyclictest4793-21kerneloops00:04:541
1837199629622,5cyclictest4793-21kerneloops19:52:583
1835699629621,6cyclictest4793-21kerneloops19:20:211
1836099628622,5cyclictest4793-21kerneloops22:36:582
1835699628622,5cyclictest4793-21kerneloops21:57:461
1835099628619,7cyclictest4793-21kerneloops00:17:360
1837199627619,6cyclictest4793-21kerneloops21:48:073
1837199627619,6cyclictest4793-21kerneloops21:30:103
1837199627618,7cyclictest4793-21kerneloops00:01:483
1836099627621,5cyclictest4793-21kerneloops23:44:382
1835699627619,6cyclictest4793-21kerneloops20:07:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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