You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-24 - 22:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Feb 24, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
504799641631,8cyclictest4793-21kerneloops10:36:290
504799634623,9cyclictest4793-21kerneloops09:49:130
506999633625,6cyclictest4793-21kerneloops09:29:283
504799633625,6cyclictest4793-21kerneloops07:39:380
504799633620,11cyclictest4793-21kerneloops09:37:150
505699632626,5cyclictest4793-21kerneloops08:31:181
505699632625,6cyclictest4793-21kerneloops08:55:301
505699632624,7cyclictest4793-21kerneloops10:39:011
505699632622,8cyclictest4793-21kerneloops10:49:131
506999631625,5cyclictest4793-21kerneloops11:35:363
506299631624,6cyclictest4793-21kerneloops12:31:512
506299631622,7cyclictest4793-21kerneloops10:54:012
504799631625,5cyclictest4793-21kerneloops08:16:350
504799631623,7cyclictest4793-21kerneloops07:50:340
506999630625,4cyclictest4793-21kerneloops07:36:013
506299630624,5cyclictest4793-21kerneloops12:24:582
506299630624,5cyclictest4793-21kerneloops09:51:222
506299630624,4cyclictest4793-21kerneloops12:26:032
506299630624,4cyclictest4793-21kerneloops10:49:232
506299630622,7cyclictest4793-21kerneloops10:04:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional