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2026-02-23 - 02:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Feb 22, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811630,1152rtkit-daemon4793-21kerneloops07:06:380
1269399635628,5cyclictest4793-21kerneloops12:02:183
1267599635624,9cyclictest4793-21kerneloops11:35:370
1269399634627,5cyclictest4793-21kerneloops10:11:413
1268099633623,8cyclictest4793-21kerneloops12:34:101
1269399632625,5cyclictest4793-21kerneloops09:45:213
1268099632626,5cyclictest4793-21kerneloops08:35:521
1268099632624,2cyclictest4793-21kerneloops11:18:001
1268099632624,2cyclictest4793-21kerneloops08:22:451
1268099632624,2cyclictest4793-21kerneloops08:16:311
1268099632624,2cyclictest4793-21kerneloops08:16:301
1267599632624,6cyclictest4793-21kerneloops12:38:020
1267599632623,7cyclictest4793-21kerneloops08:32:530
1268599631623,6cyclictest4793-21kerneloops11:45:412
1269399630625,4cyclictest4793-21kerneloops10:56:343
1269399630623,5cyclictest4793-21kerneloops10:28:263
1268099630623,5cyclictest4793-21kerneloops11:20:071
1267599630620,8cyclictest4793-21kerneloops09:39:520
1269399629626,2cyclictest4793-21kerneloops09:30:083
1268599629621,7cyclictest4793-21kerneloops12:02:072
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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