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2026-05-13 - 22:42
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed May 13, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811880,1176rtkit-daemon4793-21kerneloops07:05:462
1096499656647,7cyclictest4793-21kerneloops12:30:152
1094799647633,12cyclictest4793-21kerneloops10:53:070
1096899637628,7cyclictest4793-21kerneloops08:14:423
1095699636628,7cyclictest4793-21kerneloops08:15:341
1095699635629,5cyclictest4793-21kerneloops10:43:181
1095699634625,7cyclictest4793-21kerneloops08:52:041
1096899633627,5cyclictest4793-21kerneloops08:32:093
1096899633626,5cyclictest4793-21kerneloops08:44:063
1095699633626,5cyclictest4793-21kerneloops07:35:321
1095699633623,8cyclictest4793-21kerneloops10:34:401
1096899632626,5cyclictest4793-21kerneloops11:25:463
1096499632624,6cyclictest4793-21kerneloops10:06:152
1095699632626,4cyclictest4793-21kerneloops07:55:571
1095699632623,7cyclictest4793-21kerneloops08:41:381
1096899631623,6cyclictest4793-21kerneloops09:35:493
1096499631625,5cyclictest4793-21kerneloops10:37:272
1095699631627,2cyclictest4793-21kerneloops12:20:231
1095699631625,5cyclictest4793-21kerneloops10:13:251
1095699631624,6cyclictest4793-21kerneloops08:24:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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