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2026-07-13 - 03:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Jul 13, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
58799670660,8cyclictest4793-21kerneloops23:01:532
59399665658,5cyclictest4793-21kerneloops21:59:493
57799665657,6cyclictest4793-21kerneloops20:35:151
57799664657,6cyclictest4793-21kerneloops00:32:301
58799663654,7cyclictest4793-21kerneloops22:22:052
57799663656,5cyclictest4793-21kerneloops22:51:361
57799663656,5cyclictest4793-21kerneloops22:11:571
57299663654,7cyclictest4793-21kerneloops00:27:430
59399661658,2cyclictest4793-21kerneloops23:48:483
59399661656,4cyclictest4793-21kerneloops21:41:423
59399661655,5cyclictest4793-21kerneloops20:49:493
58799661654,5cyclictest4793-21kerneloops21:16:452
58799661652,7cyclictest4793-21kerneloops22:40:212
57799661655,5cyclictest4793-21kerneloops20:54:551
57799661655,5cyclictest4793-21kerneloops20:54:551
57299661652,7cyclictest4793-21kerneloops00:21:590
57299661651,8cyclictest4793-21kerneloops22:50:130
59399660652,6cyclictest4793-21kerneloops23:42:263
57799660657,2cyclictest4793-21kerneloops22:02:161
57799660654,5cyclictest4793-21kerneloops19:24:071
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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