You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-18 - 16:33
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Jun 18, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3034599634628,5cyclictest4793-21kerneloops10:30:233
3033299633630,1cyclictest4793-21kerneloops07:20:251
3033299633625,6cyclictest4793-21kerneloops10:13:581
3033299633625,6cyclictest4793-21kerneloops08:32:351
3032799633623,8cyclictest4793-21kerneloops12:20:400
3034599632629,1cyclictest4793-21kerneloops11:54:433
3032799632623,7cyclictest4793-21kerneloops11:08:590
3034599631628,2cyclictest4793-21kerneloops08:33:063
3033299631628,2cyclictest4793-21kerneloops08:11:341
3033299631626,4cyclictest4793-21kerneloops11:52:151
3033299631625,5cyclictest4793-21kerneloops09:18:221
3033299631624,5cyclictest4793-21kerneloops09:32:441
3033299631623,6cyclictest4793-21kerneloops12:23:501
3033299631623,6cyclictest4793-21kerneloops10:40:391
3032799630622,6cyclictest4793-21kerneloops12:02:090
3033799629624,4cyclictest4793-21kerneloops09:47:522
3034599628625,1cyclictest4793-21kerneloops08:25:183
3033799628620,7cyclictest4793-21kerneloops10:09:042
3033799628619,7cyclictest4793-21kerneloops08:40:142
3033299628624,2cyclictest4793-21kerneloops11:00:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional