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2025-06-28 - 23:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Jun 28, 2025 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
425799711703,6cyclictest4927-21kerneloops09:25:241
425799708701,5cyclictest4927-21kerneloops10:51:581
425799708700,6cyclictest4927-21kerneloops08:09:021
427199707699,6cyclictest4927-21kerneloops07:28:133
425799707698,7cyclictest4927-21kerneloops12:20:041
425099707698,8cyclictest4927-21kerneloops07:33:300
427199706700,5cyclictest4927-21kerneloops08:09:223
425799706702,2cyclictest4927-21kerneloops08:29:241
425799706698,6cyclictest4927-21kerneloops11:30:531
427199705696,7cyclictest4927-21kerneloops09:44:013
426599705698,5cyclictest4927-21kerneloops10:17:232
425799705702,2cyclictest4927-21kerneloops12:04:081
427199704702,1cyclictest4927-21kerneloops08:03:023
426599704698,5cyclictest4927-21kerneloops10:56:472
425099704700,2cyclictest4927-21kerneloops07:28:020
425099704698,5cyclictest4927-21kerneloops11:47:150
425099704695,7cyclictest4927-21kerneloops09:47:360
427199703700,2cyclictest4927-21kerneloops10:48:383
427199703696,5cyclictest4927-21kerneloops07:51:013
426599703700,2cyclictest4927-21kerneloops11:20:022
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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