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2026-01-07 - 11:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Jan 07, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889810770,1065rtkit-daemon4793-21kerneloops19:09:312
2308999599589,8cyclictest4793-21kerneloops21:45:490
2309599585578,6cyclictest4793-21kerneloops19:23:051
2309599585576,7cyclictest4793-21kerneloops21:25:181
2311299583576,6cyclictest4793-21kerneloops21:38:113
2309599583577,4cyclictest4793-21kerneloops20:58:441
2311299582574,7cyclictest4793-21kerneloops23:25:203
2308999582572,8cyclictest4793-21kerneloops21:18:420
2311299581573,6cyclictest4793-21kerneloops23:17:113
2310699581572,7cyclictest4793-21kerneloops21:53:372
2309599581574,6cyclictest4793-21kerneloops23:57:331
2311299580574,5cyclictest4793-21kerneloops19:51:463
2311299580574,5cyclictest4793-21kerneloops19:19:443
2311299580573,5cyclictest4793-21kerneloops20:07:393
2310699580571,7cyclictest4793-21kerneloops23:36:362
2309599580573,5cyclictest4793-21kerneloops22:54:351
2308999580572,7cyclictest4793-21kerneloops19:42:570
2311299579576,2cyclictest4793-21kerneloops19:21:313
2311299579573,5cyclictest4793-21kerneloops00:27:463
2311299579572,5cyclictest4793-21kerneloops22:28:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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