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2026-09-11 - 23:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Sep 11, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2645099683679,2cyclictest4793-21kerneloops09:29:440
2646699662653,7cyclictest4793-21kerneloops11:49:532
2645099662653,7cyclictest4793-21kerneloops10:30:450
2647499661654,5cyclictest4793-21kerneloops10:01:283
2647499661654,5cyclictest4793-21kerneloops07:47:283
2645799661653,6cyclictest4793-21kerneloops11:47:331
2645799661652,7cyclictest4793-21kerneloops10:13:491
2645099661652,7cyclictest4793-21kerneloops09:44:230
2647499660653,6cyclictest4793-21kerneloops09:02:153
2646699660651,7cyclictest4793-21kerneloops11:30:062
2646699660651,7cyclictest4793-21kerneloops09:22:062
2645099660649,9cyclictest4793-21kerneloops11:40:300
2647499659652,5cyclictest4793-21kerneloops12:31:173
2647499659652,5cyclictest4793-21kerneloops09:19:583
2646699659652,5cyclictest4793-21kerneloops11:07:382
2646699659650,7cyclictest4793-21kerneloops10:36:482
2645799659654,4cyclictest4793-21kerneloops09:49:581
2645799659654,4cyclictest4793-21kerneloops09:49:581
2645799659651,7cyclictest4793-21kerneloops11:15:151
2646699658652,4cyclictest4793-21kerneloops10:42:582
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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