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2026-02-11 - 17:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Feb 11, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811920,1181rtkit-daemon4793-21kerneloops07:09:563
2204999645631,12cyclictest4793-21kerneloops11:28:080
2206999635627,7cyclictest4793-21kerneloops08:02:093
2205699635628,6cyclictest4793-21kerneloops11:26:221
2205699635627,6cyclictest4793-21kerneloops07:53:551
2205699635625,8cyclictest4793-21kerneloops09:00:561
2205699634627,6cyclictest4793-21kerneloops10:37:011
2205699634627,6cyclictest4793-21kerneloops07:36:061
2205699634627,5cyclictest4793-21kerneloops08:19:351
2205699634627,5cyclictest4793-21kerneloops07:28:001
2205699634626,7cyclictest4793-21kerneloops12:22:361
2205699634626,6cyclictest4793-21kerneloops08:27:021
2205699634626,6cyclictest4793-21kerneloops07:11:011
2205699633627,5cyclictest4793-21kerneloops11:53:461
2205699633627,5cyclictest4793-21kerneloops11:38:371
2205699633627,5cyclictest4793-21kerneloops10:44:421
2205699633627,5cyclictest4793-21kerneloops08:43:091
2205699633627,5cyclictest4793-21kerneloops08:12:411
2205699633627,5cyclictest4793-21kerneloops07:33:541
2206999632627,4cyclictest4793-21kerneloops10:18:153
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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