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2026-02-16 - 04:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Feb 16, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812620,1251rtkit-daemon4793-21kerneloops19:07:221
251599635629,5cyclictest4793-21kerneloops23:43:253
251599634627,6cyclictest4793-21kerneloops21:20:373
251599633625,7cyclictest4793-21kerneloops00:15:273
250599633626,5cyclictest4793-21kerneloops21:58:171
249999633631,1cyclictest4793-21kerneloops23:29:460
249999632624,7cyclictest4793-21kerneloops19:23:170
251599631624,6cyclictest4793-21kerneloops23:53:003
250599631626,4cyclictest4793-21kerneloops22:14:131
250599631624,5cyclictest4793-21kerneloops21:48:061
251599630627,2cyclictest4793-21kerneloops22:05:203
251199630624,5cyclictest4793-21kerneloops20:21:422
249999630622,7cyclictest4793-21kerneloops20:13:010
251199629621,6cyclictest4793-21kerneloops23:14:092
250599629626,2cyclictest4793-21kerneloops23:10:141
250599629619,8cyclictest4793-21kerneloops00:39:171
251599628621,6cyclictest4793-21kerneloops22:37:123
251599628621,6cyclictest4793-21kerneloops22:14:033
249999628621,6cyclictest4793-21kerneloops00:18:390
251199627620,6cyclictest4793-21kerneloops20:18:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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