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2026-04-30 - 05:14
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Apr 29, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
249899656644,10cyclictest4793-21kerneloops07:35:120
251999635628,5cyclictest4793-21kerneloops11:32:103
251999635627,6cyclictest4793-21kerneloops07:50:583
249899635627,6cyclictest4793-21kerneloops10:21:450
251999634627,5cyclictest4793-21kerneloops08:32:293
249899633623,8cyclictest4793-21kerneloops07:18:190
251999632627,4cyclictest4793-21kerneloops08:28:313
251199632625,5cyclictest4793-21kerneloops10:18:122
250299632625,5cyclictest4793-21kerneloops10:23:521
251999631622,7cyclictest4793-21kerneloops10:14:043
251199631624,6cyclictest4793-21kerneloops08:07:222
251199631623,2cyclictest4793-21kerneloops12:15:062
251199631622,7cyclictest4793-21kerneloops09:38:122
249899631624,5cyclictest4793-21kerneloops07:52:250
251199630624,4cyclictest4793-21kerneloops08:29:352
251199630623,5cyclictest4793-21kerneloops11:58:142
251199630623,5cyclictest4793-21kerneloops10:12:162
251199630623,1cyclictest4793-21kerneloops09:45:332
251199630622,6cyclictest4793-21kerneloops10:27:462
251199630622,2cyclictest4793-21kerneloops08:55:272
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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