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2026-06-06 - 13:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Jun 06, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3040899673664,7cyclictest4793-21kerneloops23:20:181
3039999637625,10cyclictest4793-21kerneloops21:11:110
3042299634626,6cyclictest4793-21kerneloops23:38:553
3042299634626,6cyclictest4793-21kerneloops19:38:113
3042299634625,7cyclictest4793-21kerneloops23:03:253
3042299634625,7cyclictest4793-21kerneloops22:29:463
3040899634627,5cyclictest4793-21kerneloops19:25:001
3042299633626,6cyclictest4793-21kerneloops22:48:473
3040899633626,6cyclictest4793-21kerneloops21:30:561
3042299632626,5cyclictest4793-21kerneloops22:09:243
3040899632624,6cyclictest4793-21kerneloops21:27:521
3040899631626,4cyclictest4793-21kerneloops21:11:531
3040899631624,5cyclictest4793-21kerneloops21:06:571
3040899631623,6cyclictest4793-21kerneloops20:18:291
3042299630624,5cyclictest4793-21kerneloops19:28:583
3040899630627,1cyclictest4793-21kerneloops22:51:181
3040899630623,5cyclictest4793-21kerneloops19:59:381
3040899630623,5cyclictest4793-21kerneloops00:05:561
3039999630623,5cyclictest4793-21kerneloops20:06:550
3042299629623,4cyclictest4793-21kerneloops22:04:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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