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2026-01-22 - 07:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Jan 22, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
471699585575,8cyclictest4793-21kerneloops22:47:272
472599584577,5cyclictest4793-21kerneloops23:47:533
472599583577,5cyclictest4793-21kerneloops22:24:423
472599583576,5cyclictest4793-21kerneloops19:45:443
472599583574,7cyclictest4793-21kerneloops00:33:533
472599582575,5cyclictest4793-21kerneloops23:06:333
471099582577,4cyclictest4793-21kerneloops22:31:491
472599581576,4cyclictest4793-21kerneloops22:13:083
471099581575,4cyclictest4793-21kerneloops22:25:471
471099580576,2cyclictest4793-21kerneloops19:21:331
471099580574,5cyclictest4793-21kerneloops21:59:271
471099580574,5cyclictest4793-21kerneloops20:17:061
470499580573,5cyclictest4793-21kerneloops23:15:520
470499580570,8cyclictest4793-21kerneloops00:26:210
472599579574,3cyclictest4793-21kerneloops00:22:473
471699579574,3cyclictest4793-21kerneloops00:25:162
470499579571,7cyclictest4793-21kerneloops23:56:420
471699578574,2cyclictest4793-21kerneloops22:03:102
471699578572,4cyclictest4793-21kerneloops00:30:282
471099578570,6cyclictest4793-21kerneloops20:34:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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