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2026-03-11 - 08:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Mar 11, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1718399633624,7cyclictest4793-21kerneloops20:40:180
1720499631623,6cyclictest4793-21kerneloops22:08:463
1720499630623,6cyclictest4793-21kerneloops19:19:543
1719099630627,2cyclictest4793-21kerneloops00:29:571
1719099630622,6cyclictest4793-21kerneloops00:08:161
1719099630620,8cyclictest4793-21kerneloops21:39:461
1718399630620,8cyclictest4793-21kerneloops21:14:570
1720499629621,6cyclictest4793-21kerneloops23:31:543
1719799629622,5cyclictest4793-21kerneloops21:48:582
1719099629623,5cyclictest4793-21kerneloops23:57:251
1719099629622,6cyclictest4793-21kerneloops21:10:151
1719099629622,5cyclictest4793-21kerneloops21:26:541
1719099629621,6cyclictest4793-21kerneloops19:57:491
1718399629622,6cyclictest4793-21kerneloops22:58:430
1720499628621,5cyclictest4793-21kerneloops00:18:163
1719799628621,6cyclictest4793-21kerneloops23:52:412
1719099628625,2cyclictest4793-21kerneloops20:00:061
1719099628622,4cyclictest4793-21kerneloops23:34:261
1719099628621,5cyclictest4793-21kerneloops23:47:311
1719099628620,6cyclictest4793-21kerneloops22:49:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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