You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-08-12 - 14:49
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Aug 12, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2767699686671,13cyclictest4793-21kerneloops12:39:180
2769399663655,6cyclictest4793-21kerneloops09:10:173
2768299663657,5cyclictest4793-21kerneloops07:42:381
2769399662656,5cyclictest4793-21kerneloops09:18:253
2768299662657,4cyclictest4793-21kerneloops09:23:511
2768299662655,6cyclictest4793-21kerneloops10:01:151
2768299662654,7cyclictest4793-21kerneloops11:08:511
2769399661655,4cyclictest4793-21kerneloops09:52:423
2769399661652,7cyclictest4793-21kerneloops12:30:193
2768899661652,7cyclictest4793-21kerneloops10:08:242
2768299661653,6cyclictest4793-21kerneloops07:26:071
2767699661653,7cyclictest4793-21kerneloops08:01:270
2767699661651,8cyclictest4793-21kerneloops11:44:210
2769399660657,2cyclictest4793-21kerneloops11:09:443
2768299660652,6cyclictest4793-21kerneloops12:04:131
2768299660652,6cyclictest4793-21kerneloops08:12:411
2769399659657,1cyclictest4793-21kerneloops09:47:103
2769399659656,2cyclictest4793-21kerneloops11:38:253
2769399659653,5cyclictest4793-21kerneloops07:14:123
2769399659652,5cyclictest4793-21kerneloops10:40:423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional