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2026-04-10 - 06:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Apr 10, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1020099642639,2cyclictest4793-21kerneloops22:10:522
1019199635627,6cyclictest4793-21kerneloops21:12:351
1019199634625,7cyclictest4793-21kerneloops21:59:081
1019199634625,7cyclictest4793-21kerneloops21:59:071
1020899633627,5cyclictest4793-21kerneloops19:51:363
1019199633627,4cyclictest4793-21kerneloops20:16:141
1019199633626,5cyclictest4793-21kerneloops20:36:331
1020899632628,2cyclictest4793-21kerneloops19:56:473
1020899632625,5cyclictest4793-21kerneloops21:04:283
1020899632623,7cyclictest4793-21kerneloops21:15:363
1020099632625,5cyclictest4793-21kerneloops20:41:322
1020099631625,5cyclictest4793-21kerneloops20:33:312
1020099631624,6cyclictest4793-21kerneloops21:05:432
1020099631624,5cyclictest4793-21kerneloops23:37:532
1020099631624,5cyclictest4793-21kerneloops23:37:532
1019199631625,5cyclictest4793-21kerneloops21:03:571
1018799631619,10cyclictest4793-21kerneloops00:36:060
1020899630626,2cyclictest4793-21kerneloops21:52:233
1020099630624,5cyclictest4793-21kerneloops19:31:282
1018799630624,5cyclictest4793-21kerneloops20:08:520
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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