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2026-06-15 - 15:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Jun 15, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1254499637628,7cyclictest4793-21kerneloops00:39:031
1254499636627,7cyclictest4793-21kerneloops22:01:471
1255899635627,6cyclictest4793-21kerneloops22:25:283
1255899634628,4cyclictest4793-21kerneloops23:25:433
1255899634627,5cyclictest4793-21kerneloops21:16:173
1255899634627,5cyclictest4793-21kerneloops19:23:113
1254499634627,5cyclictest4793-21kerneloops20:36:441
1255899633626,6cyclictest4793-21kerneloops20:16:233
1254499633625,6cyclictest4793-21kerneloops20:00:461
1254499632623,7cyclictest4793-21kerneloops23:02:251
1253799632624,7cyclictest4793-21kerneloops20:22:580
1253799632622,8cyclictest4793-21kerneloops21:48:410
1255899631628,2cyclictest4793-21kerneloops23:43:563
1255899631627,2cyclictest4793-21kerneloops00:37:073
1255899631625,5cyclictest4793-21kerneloops20:59:143
1255299631623,6cyclictest4793-21kerneloops23:30:402
1254499631627,2cyclictest4793-21kerneloops22:18:261
1254499631625,5cyclictest4793-21kerneloops20:49:261
1254499631624,5cyclictest4793-21kerneloops19:29:401
1254499631623,6cyclictest4793-21kerneloops19:33:231
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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