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2026-06-30 - 22:43
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Jun 30, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1571499671667,2cyclictest4793-21kerneloops09:21:092
1572099663656,6cyclictest4793-21kerneloops07:51:443
1572099663656,6cyclictest4793-21kerneloops07:16:543
1572099663656,5cyclictest4793-21kerneloops08:51:223
1572099663654,7cyclictest4793-21kerneloops10:23:253
1570199663654,7cyclictest4793-21kerneloops12:17:350
1570699662656,4cyclictest4793-21kerneloops09:35:181
1572099661658,1cyclictest4793-21kerneloops08:04:113
1571499661654,5cyclictest4793-21kerneloops09:06:372
1570199661651,8cyclictest4793-21kerneloops09:49:220
1570199661650,9cyclictest4793-21kerneloops09:12:070
1572099660657,1cyclictest4793-21kerneloops08:13:033
1571499660654,5cyclictest4793-21kerneloops07:57:122
1570199660651,7cyclictest4793-21kerneloops08:36:070
1572099659656,2cyclictest4793-21kerneloops08:48:493
1572099659650,7cyclictest4793-21kerneloops10:25:213
1570699659652,6cyclictest4793-21kerneloops07:55:381
1570199659650,7cyclictest4793-21kerneloops12:25:110
1572099658655,1cyclictest4793-21kerneloops07:58:143
1572099658650,6cyclictest4793-21kerneloops09:55:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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