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2025-12-09 - 06:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Dec 09, 2025 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1160599817807,8cyclictest4927-21kerneloops23:33:442
1161399799789,8cyclictest4927-21kerneloops20:36:013
1159299798787,9cyclictest4927-21kerneloops21:50:190
1161399797790,5cyclictest4927-21kerneloops23:12:083
1161399797790,5cyclictest4927-21kerneloops19:56:543
1161399797790,5cyclictest4927-21kerneloops19:33:573
1161399797790,5cyclictest4927-21kerneloops19:11:063
1161399796790,5cyclictest4927-21kerneloops19:21:483
1161399796790,4cyclictest4927-21kerneloops20:53:003
1161399796789,5cyclictest4927-21kerneloops21:23:053
1161399796788,6cyclictest4927-21kerneloops20:20:593
1159999796792,2cyclictest4927-21kerneloops21:11:501
1159999796788,6cyclictest4927-21kerneloops23:07:521
1161399795789,5cyclictest4927-21kerneloops21:34:233
1161399795789,4cyclictest4927-21kerneloops00:39:093
1159999795788,5cyclictest4927-21kerneloops23:26:491
1161399794787,5cyclictest4927-21kerneloops22:13:253
1159999794787,6cyclictest4927-21kerneloops23:11:571
1159999794787,5cyclictest4927-21kerneloops19:47:211
1159299794788,5cyclictest4927-21kerneloops19:57:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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