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2026-04-05 - 11:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Apr 05, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
551399635627,7cyclictest4793-21kerneloops23:23:263
551399635626,7cyclictest4793-21kerneloops21:08:593
551399635626,7cyclictest4793-21kerneloops19:34:393
550899635625,8cyclictest4793-21kerneloops20:35:142
551399634626,6cyclictest4793-21kerneloops22:07:333
550899634625,7cyclictest4793-21kerneloops23:41:312
551399632627,4cyclictest4793-21kerneloops23:48:483
551399632625,6cyclictest4793-21kerneloops21:14:383
550299632624,6cyclictest4793-21kerneloops00:09:401
550299631624,5cyclictest4793-21kerneloops20:05:481
550899630622,7cyclictest4793-21kerneloops23:50:572
550299630626,2cyclictest4793-21kerneloops20:57:471
550299630624,5cyclictest4793-21kerneloops19:16:011
549699630623,6cyclictest4793-21kerneloops21:41:250
549699630621,7cyclictest4793-21kerneloops23:31:450
549699630621,7cyclictest4793-21kerneloops20:49:280
550899629624,4cyclictest4793-21kerneloops22:24:382
550899629624,4cyclictest4793-21kerneloops20:42:042
551399628626,1cyclictest4793-21kerneloops19:55:023
551399628625,2cyclictest4793-21kerneloops22:24:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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