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2026-04-03 - 01:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Apr 02, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1970299632623,7cyclictest4793-21kerneloops12:07:143
1969299632623,6cyclictest4793-21kerneloops11:04:482
1968899632624,7cyclictest4793-21kerneloops10:00:291
1968899632624,6cyclictest4793-21kerneloops09:27:161
1970299631624,5cyclictest4793-21kerneloops12:12:033
1970299631624,5cyclictest4793-21kerneloops09:48:453
1970299631622,7cyclictest4793-21kerneloops09:57:043
1969299631622,7cyclictest4793-21kerneloops11:45:352
1968899631622,7cyclictest4793-21kerneloops08:28:371
1968299631624,5cyclictest4793-21kerneloops12:16:080
1968299631622,8cyclictest4793-21kerneloops10:11:450
1970299630623,5cyclictest4793-21kerneloops11:33:053
1970299630622,6cyclictest4793-21kerneloops08:26:133
1970299630621,7cyclictest4793-21kerneloops12:26:433
1969299630623,5cyclictest4793-21kerneloops08:19:022
1968899630621,7cyclictest4793-21kerneloops07:24:431
1968299630623,6cyclictest4793-21kerneloops07:27:030
1970299629623,5cyclictest4793-21kerneloops09:42:413
1969299629621,6cyclictest4793-21kerneloops09:47:192
1968299629622,6cyclictest4793-21kerneloops07:12:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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