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2026-08-27 - 18:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Aug 27, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
94799669660,7cyclictest4793-21kerneloops10:06:320
95299664657,5cyclictest4793-21kerneloops09:01:251
95299663657,4cyclictest4793-21kerneloops08:08:071
95299663656,5cyclictest4793-21kerneloops07:37:291
95299663656,5cyclictest4793-21kerneloops07:17:421
94799663649,12cyclictest4793-21kerneloops11:42:330
96999662655,5cyclictest4793-21kerneloops11:09:313
96999662655,5cyclictest4793-21kerneloops10:00:113
96999662653,7cyclictest4793-21kerneloops09:10:183
96399662654,6cyclictest4793-21kerneloops12:04:512
95299662656,5cyclictest4793-21kerneloops07:22:591
95299662655,5cyclictest4793-21kerneloops08:20:421
95299662653,7cyclictest4793-21kerneloops07:12:021
94799662654,6cyclictest4793-21kerneloops08:50:050
96999661655,4cyclictest4793-21kerneloops11:39:233
96999661653,6cyclictest4793-21kerneloops10:25:593
95299661655,4cyclictest4793-21kerneloops07:44:591
94799661653,6cyclictest4793-21kerneloops10:02:490
96999660655,4cyclictest4793-21kerneloops08:57:543
96999660655,4cyclictest4793-21kerneloops07:31:183
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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