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2026-01-18 - 02:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Jan 18, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2938299584577,5cyclictest4793-21kerneloops20:38:141
2937799583570,11cyclictest4793-21kerneloops21:33:040
2939999582576,5cyclictest4793-21kerneloops19:57:113
2938299581574,5cyclictest4793-21kerneloops21:22:251
2938299581573,6cyclictest4793-21kerneloops22:31:311
2937799581573,7cyclictest4793-21kerneloops19:39:420
2939999580575,4cyclictest4793-21kerneloops00:29:003
2939999580569,9cyclictest4793-21kerneloops19:21:323
2938299580573,6cyclictest4793-21kerneloops19:42:081
2939999579576,2cyclictest4793-21kerneloops00:01:203
2939999579573,4cyclictest4793-21kerneloops20:49:263
2937799579568,10cyclictest4793-21kerneloops23:51:150
2939399578571,5cyclictest4793-21kerneloops00:38:302
2938299578570,6cyclictest4793-21kerneloops21:19:231
2939999577567,8cyclictest4793-21kerneloops00:35:513
2939399577571,4cyclictest4793-21kerneloops21:18:422
2938299577574,2cyclictest4793-21kerneloops22:23:401
2938299577572,4cyclictest4793-21kerneloops22:40:251
2937799577570,6cyclictest4793-21kerneloops00:27:320
2939999576570,5cyclictest4793-21kerneloops22:02:553
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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