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2026-04-27 - 03:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Apr 27, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811910,1179rtkit-daemon4793-21kerneloops19:08:473
1873499638631,5cyclictest4793-21kerneloops00:03:283
1871799638634,2cyclictest4793-21kerneloops22:51:331
1871799636628,6cyclictest4793-21kerneloops23:34:151
1873499634626,6cyclictest4793-21kerneloops20:40:503
1873499634625,7cyclictest4793-21kerneloops00:35:433
1873499633626,5cyclictest4793-21kerneloops21:20:043
1873499633626,5cyclictest4793-21kerneloops19:29:133
1871399633623,2cyclictest4793-21kerneloops22:08:220
1871799632628,2cyclictest4793-21kerneloops22:49:561
1871799632625,5cyclictest4793-21kerneloops21:31:041
1871799632624,6cyclictest4793-21kerneloops21:43:331
1873499631623,7cyclictest4793-21kerneloops22:35:223
1872899631625,4cyclictest4793-21kerneloops20:38:342
1872899631624,5cyclictest4793-21kerneloops23:14:482
1873499630624,5cyclictest4793-21kerneloops21:28:553
1872899630622,7cyclictest4793-21kerneloops21:32:082
1872899630622,6cyclictest4793-21kerneloops21:02:392
1871799630627,1cyclictest4793-21kerneloops22:57:061
1871799630622,6cyclictest4793-21kerneloops21:56:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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