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2026-02-21 - 11:56
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Feb 21, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1015899652641,9cyclictest4793-21kerneloops22:10:300
1016599636629,5cyclictest4793-21kerneloops22:11:541
1015899636623,11cyclictest4793-21kerneloops21:52:560
1016599634625,7cyclictest4793-21kerneloops21:59:181
1016599633627,5cyclictest4793-21kerneloops20:48:321
1016599633624,7cyclictest4793-21kerneloops22:35:151
1017999632627,4cyclictest4793-21kerneloops20:57:203
1017999632625,6cyclictest4793-21kerneloops20:39:543
1016599632627,4cyclictest4793-21kerneloops19:30:381
1016599631623,7cyclictest4793-21kerneloops22:56:461
1015899631623,6cyclictest4793-21kerneloops22:34:010
1015899631622,7cyclictest4793-21kerneloops19:24:140
1015899631621,8cyclictest4793-21kerneloops19:14:360
1017999630627,2cyclictest4793-21kerneloops19:21:533
1017999630623,6cyclictest4793-21kerneloops22:47:433
1017999630623,6cyclictest4793-21kerneloops22:47:433
1017999630623,5cyclictest4793-21kerneloops20:44:233
1017999630622,6cyclictest4793-21kerneloops22:51:033
1017199630624,5cyclictest4793-21kerneloops20:14:032
1016599630627,1cyclictest4793-21kerneloops21:30:371
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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