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2025-12-13 - 20:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Dec 12, 2025 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64479814970,1485rtkit-daemon4927-21kerneloops19:05:403
2576999797789,6cyclictest4927-21kerneloops21:08:293
2575599796789,6cyclictest4927-21kerneloops21:14:441
2576299795787,6cyclictest4927-21kerneloops21:33:582
2575599795788,5cyclictest4927-21kerneloops00:36:101
2574899795788,6cyclictest4927-21kerneloops23:53:180
2576999794787,6cyclictest4927-21kerneloops21:24:323
2576999794785,7cyclictest4927-21kerneloops20:37:543
2575599794791,2cyclictest4927-21kerneloops20:36:251
2575599794788,5cyclictest4927-21kerneloops00:26:581
2575599794785,7cyclictest4927-21kerneloops23:10:291
2574899794785,7cyclictest4927-21kerneloops20:45:230
2574899794784,8cyclictest4927-21kerneloops21:32:360
2576999793786,5cyclictest4927-21kerneloops20:09:163
2576299793787,5cyclictest4927-21kerneloops23:41:542
2576299793787,5cyclictest4927-21kerneloops22:23:532
2576299793784,7cyclictest4927-21kerneloops23:35:232
2575599793790,2cyclictest4927-21kerneloops20:45:131
2575599793790,2cyclictest4927-21kerneloops00:24:421
2575599793786,5cyclictest4927-21kerneloops21:26:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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