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2026-02-19 - 09:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Feb 19, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2539899650646,2cyclictest4793-21kerneloops23:06:552
2539899650646,2cyclictest4793-21kerneloops23:06:552
2540399633627,5cyclictest4793-21kerneloops21:46:543
2540399631625,4cyclictest4793-21kerneloops21:11:383
2540399630624,5cyclictest4793-21kerneloops20:04:493
2539199630623,5cyclictest4793-21kerneloops23:30:341
2540399629622,5cyclictest4793-21kerneloops00:14:193
2540399629621,6cyclictest4793-21kerneloops00:08:293
2539899629620,7cyclictest4793-21kerneloops22:49:402
2538299629623,5cyclictest4793-21kerneloops20:04:590
2538299629623,5cyclictest4793-21kerneloops19:56:350
2538299629623,5cyclictest4793-21kerneloops19:56:340
2538299629620,8cyclictest4793-21kerneloops00:15:310
2540399628625,2cyclictest4793-21kerneloops21:33:053
2540399628623,4cyclictest4793-21kerneloops20:08:413
2540399628622,5cyclictest4793-21kerneloops21:51:543
2540399628620,6cyclictest4793-21kerneloops21:57:363
2539899628623,4cyclictest4793-21kerneloops21:48:212
2539899628622,5cyclictest4793-21kerneloops23:13:492
2539899628620,7cyclictest4793-21kerneloops22:16:222
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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