You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-25 - 13:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Feb 25, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1943799640636,2cyclictest4793-21kerneloops23:09:093
1943799638629,7cyclictest4793-21kerneloops23:22:513
1943799634625,7cyclictest4793-21kerneloops21:28:303
1942599634625,7cyclictest4793-21kerneloops22:40:161
1942599634625,7cyclictest4793-21kerneloops20:50:101
1943799633627,5cyclictest4793-21kerneloops19:42:213
1943799633626,5cyclictest4793-21kerneloops19:17:173
1943799633626,5cyclictest4793-21kerneloops19:11:233
1943799633626,5cyclictest4793-21kerneloops00:39:223
1943799632626,5cyclictest4793-21kerneloops23:31:493
1943799632626,5cyclictest4793-21kerneloops22:05:403
1943799632625,5cyclictest4793-21kerneloops20:34:533
1942599632626,5cyclictest4793-21kerneloops22:04:361
1942599632626,5cyclictest4793-21kerneloops19:38:171
1942599632626,5cyclictest4793-21kerneloops19:38:171
1942599632625,6cyclictest4793-21kerneloops23:21:261
1943399631625,5cyclictest4793-21kerneloops19:11:562
1943399631623,6cyclictest4793-21kerneloops23:09:302
1942599631626,4cyclictest4793-21kerneloops22:34:281
1942599631625,5cyclictest4793-21kerneloops19:33:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional