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2026-01-28 - 13:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Jan 28, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2065199591582,7cyclictest4793-21kerneloops00:21:113
2063899588582,4cyclictest4793-21kerneloops00:00:311
2062799587579,6cyclictest4793-21kerneloops23:49:130
2065199586580,5cyclictest4793-21kerneloops20:35:463
2063899586580,5cyclictest4793-21kerneloops00:35:271
2062799586577,7cyclictest4793-21kerneloops23:11:000
2065199585578,5cyclictest4793-21kerneloops22:46:273
2064499585578,5cyclictest4793-21kerneloops20:35:032
2064499585578,5cyclictest4793-21kerneloops19:36:552
2063899585580,4cyclictest4793-21kerneloops19:50:571
2063899585579,4cyclictest4793-21kerneloops00:26:191
2062799585578,6cyclictest4793-21kerneloops20:57:070
2062799585577,6cyclictest4793-21kerneloops21:11:330
2062799585576,7cyclictest4793-21kerneloops00:38:480
2065199584581,2cyclictest4793-21kerneloops21:24:143
2065199584581,1cyclictest4793-21kerneloops00:37:233
2065199584577,6cyclictest4793-21kerneloops22:12:583
2065199584575,7cyclictest4793-21kerneloops22:09:283
2064499584578,5cyclictest4793-21kerneloops22:52:052
2064499584578,4cyclictest4793-21kerneloops21:00:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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