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2026-04-23 - 23:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Apr 23, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2434099636628,6cyclictest4793-21kerneloops09:30:293
2434099634624,8cyclictest4793-21kerneloops10:57:033
2432499634627,6cyclictest4793-21kerneloops07:30:301
2434099633627,5cyclictest4793-21kerneloops11:38:133
2434099633626,5cyclictest4793-21kerneloops07:59:193
2431999633625,6cyclictest4793-21kerneloops09:30:090
2433199632627,4cyclictest4793-21kerneloops07:47:052
2432499632626,4cyclictest4793-21kerneloops07:25:411
2434099630623,5cyclictest4793-21kerneloops11:32:543
2433199630623,6cyclictest4793-21kerneloops10:08:092
2433199630623,5cyclictest4793-21kerneloops10:36:352
2432499630627,2cyclictest4793-21kerneloops10:11:521
2432499630627,2cyclictest4793-21kerneloops10:02:221
2431999630623,6cyclictest4793-21kerneloops07:20:530
2431999630623,6cyclictest4793-21kerneloops07:20:530
2431999630620,8cyclictest4793-21kerneloops10:48:440
2434099629624,4cyclictest4793-21kerneloops10:11:413
2432499629626,1cyclictest4793-21kerneloops12:34:481
2432499629625,2cyclictest4793-21kerneloops08:41:121
2434099628626,1cyclictest4793-21kerneloops07:35:293
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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