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2026-06-12 - 14:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Jun 12, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1137399643633,8cyclictest4793-21kerneloops10:32:343
1135799634626,6cyclictest4793-21kerneloops09:56:261
1137399633627,5cyclictest4793-21kerneloops10:53:553
1137399633627,4cyclictest4793-21kerneloops07:33:283
1135799633626,5cyclictest4793-21kerneloops08:53:441
1135299633625,6cyclictest4793-21kerneloops11:40:530
1137399632624,6cyclictest4793-21kerneloops11:24:583
1136599632623,7cyclictest4793-21kerneloops10:07:052
1137399631629,1cyclictest4793-21kerneloops08:25:163
1137399631628,1cyclictest4793-21kerneloops08:09:523
1137399631623,7cyclictest4793-21kerneloops09:09:523
1137399631623,6cyclictest4793-21kerneloops12:15:273
1135799631627,2cyclictest4793-21kerneloops08:38:291
1135799631624,5cyclictest4793-21kerneloops12:27:391
1137399630627,2cyclictest4793-21kerneloops10:12:193
1137399630627,2cyclictest4793-21kerneloops08:42:143
1137399630624,4cyclictest4793-21kerneloops08:13:113
1137399630622,6cyclictest4793-21kerneloops07:43:533
1136599630624,5cyclictest4793-21kerneloops09:33:312
1136599630624,4cyclictest4793-21kerneloops07:15:482
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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