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2026-03-19 - 14:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Mar 19, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1729999635626,7cyclictest4793-21kerneloops12:19:471
1731299634626,6cyclictest4793-21kerneloops11:19:383
1731299634625,7cyclictest4793-21kerneloops08:08:533
1730599634627,5cyclictest4793-21kerneloops11:56:352
1729999634626,6cyclictest4793-21kerneloops11:32:561
1731299633624,7cyclictest4793-21kerneloops12:22:393
1728899633625,7cyclictest4793-21kerneloops11:25:250
1731299632623,7cyclictest4793-21kerneloops11:30:013
1729999632629,2cyclictest4793-21kerneloops08:15:501
1729999632625,6cyclictest4793-21kerneloops10:36:181
1731299631624,5cyclictest4793-21kerneloops08:56:073
1731299631623,6cyclictest4793-21kerneloops10:31:433
1728899631623,7cyclictest4793-21kerneloops07:46:260
1731299630621,7cyclictest4793-21kerneloops09:59:233
1730599630623,5cyclictest4793-21kerneloops12:08:192
1731299629622,5cyclictest4793-21kerneloops12:33:423
1731299629622,5cyclictest4793-21kerneloops09:31:283
1730599629623,5cyclictest4793-21kerneloops11:17:222
1729999629626,2cyclictest4793-21kerneloops09:47:081
1729999629623,4cyclictest4793-21kerneloops11:04:101
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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