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2026-07-19 - 05:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Jul 19, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
183199683672,9cyclictest4793-21kerneloops00:04:560
185299670666,2cyclictest4793-21kerneloops21:22:443
183199666654,10cyclictest4793-21kerneloops00:09:010
183199664652,10cyclictest4793-21kerneloops23:50:040
183899662655,5cyclictest4793-21kerneloops23:09:131
183199662651,9cyclictest4793-21kerneloops21:06:590
183199662650,10cyclictest4793-21kerneloops23:16:240
185299661655,5cyclictest4793-21kerneloops22:53:263
185299661652,7cyclictest4793-21kerneloops22:07:463
183899661657,2cyclictest4793-21kerneloops22:19:551
183899661653,7cyclictest4793-21kerneloops23:19:371
183199661652,8cyclictest4793-21kerneloops22:10:230
185299660654,5cyclictest4793-21kerneloops23:27:303
183899660657,2cyclictest4793-21kerneloops19:31:191
183199660648,10cyclictest4793-21kerneloops21:39:470
185299659656,2cyclictest4793-21kerneloops23:08:193
183899659656,2cyclictest4793-21kerneloops21:34:161
183899659656,2cyclictest4793-21kerneloops21:34:151
183199659650,7cyclictest4793-21kerneloops20:16:260
185299658655,2cyclictest4793-21kerneloops23:10:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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