You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-25 - 12:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Jan 25, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811160,1105rtkit-daemon4793-21kerneloops19:09:001
3266299585577,7cyclictest4793-21kerneloops22:14:532
3265499585577,7cyclictest4793-21kerneloops00:06:221
3264599585578,5cyclictest4793-21kerneloops21:08:020
3266699584576,6cyclictest4793-21kerneloops19:35:183
3264599584577,6cyclictest4793-21kerneloops23:18:100
3266699583581,1cyclictest4793-21kerneloops20:36:303
3266699583579,2cyclictest4793-21kerneloops21:01:343
3266699583577,5cyclictest4793-21kerneloops19:43:423
3266299583577,5cyclictest4793-21kerneloops22:31:142
3264599583577,5cyclictest4793-21kerneloops00:29:550
3264599583576,5cyclictest4793-21kerneloops23:24:150
3264599583574,8cyclictest4793-21kerneloops21:56:360
3266699582579,2cyclictest4793-21kerneloops19:10:483
3266699582576,5cyclictest4793-21kerneloops00:04:563
3266299582575,5cyclictest4793-21kerneloops23:22:512
3266699581579,1cyclictest4793-21kerneloops22:51:083
3266299581576,4cyclictest4793-21kerneloops00:28:192
3266299581575,5cyclictest4793-21kerneloops23:56:232
3265499581579,1cyclictest4793-21kerneloops00:18:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional