You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-15 - 00:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Jan 14, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1548299584576,6cyclictest4793-21kerneloops10:53:151
1549599583574,7cyclictest4793-21kerneloops11:45:113
1549599581575,4cyclictest4793-21kerneloops07:14:593
1549599581574,5cyclictest4793-21kerneloops08:18:243
1548299581575,5cyclictest4793-21kerneloops07:46:371
1547899581570,9cyclictest4793-21kerneloops11:32:340
1549599580573,5cyclictest4793-21kerneloops12:16:043
1549599580573,5cyclictest4793-21kerneloops12:16:043
1549099580574,5cyclictest4793-21kerneloops10:41:142
1548299580571,7cyclictest4793-21kerneloops11:33:151
1547899580570,8cyclictest4793-21kerneloops10:06:510
1549599579576,2cyclictest4793-21kerneloops09:53:213
1549099579570,7cyclictest4793-21kerneloops07:42:312
1548299579572,5cyclictest4793-21kerneloops10:20:591
1548299579572,5cyclictest4793-21kerneloops09:12:361
1547899579573,5cyclictest4793-21kerneloops08:09:290
1547899579570,7cyclictest4793-21kerneloops10:40:090
1549599578575,2cyclictest4793-21kerneloops10:12:503
1549599578575,2cyclictest4793-21kerneloops07:20:593
1547899578571,6cyclictest4793-21kerneloops10:36:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional