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2025-11-29 - 04:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Nov 28, 2025 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1072899802798,2cyclictest4927-21kerneloops11:47:010
1075099797790,5cyclictest4927-21kerneloops09:09:123
1074199797788,7cyclictest4927-21kerneloops09:19:452
1074199797787,8cyclictest4927-21kerneloops09:30:192
1073399797790,5cyclictest4927-21kerneloops07:46:441
1072899797788,7cyclictest4927-21kerneloops10:33:320
1072899796787,7cyclictest4927-21kerneloops11:20:040
1072899796786,8cyclictest4927-21kerneloops12:05:300
1075099795791,2cyclictest4927-21kerneloops11:00:053
1075099795791,2cyclictest4927-21kerneloops11:00:043
1075099795787,6cyclictest4927-21kerneloops10:27:293
1073399795789,5cyclictest4927-21kerneloops10:13:391
1075099794788,5cyclictest4927-21kerneloops10:08:383
1074199794785,7cyclictest4927-21kerneloops12:34:062
1073399794787,5cyclictest4927-21kerneloops09:34:121
1075099793789,2cyclictest4927-21kerneloops11:34:423
1075099793788,4cyclictest4927-21kerneloops10:49:493
1075099793786,5cyclictest4927-21kerneloops10:52:263
1074199793786,6cyclictest4927-21kerneloops11:54:062
1074199793784,7cyclictest4927-21kerneloops12:11:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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