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2026-08-24 - 17:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Aug 24, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1305899680671,7cyclictest4793-21kerneloops11:35:183
1304199664656,6cyclictest4793-21kerneloops08:20:521
1304199664654,8cyclictest4793-21kerneloops10:42:111
1305099663654,7cyclictest4793-21kerneloops08:33:092
1304199663656,5cyclictest4793-21kerneloops10:25:521
1303699663654,7cyclictest4793-21kerneloops09:13:070
1304199662656,5cyclictest4793-21kerneloops09:44:531
1304199662656,5cyclictest4793-21kerneloops07:52:571
1304199662654,6cyclictest4793-21kerneloops09:12:021
1305899661655,5cyclictest4793-21kerneloops08:10:323
1304199661655,5cyclictest4793-21kerneloops09:24:451
1303699661652,8cyclictest4793-21kerneloops11:51:000
1305899660653,5cyclictest4793-21kerneloops10:35:083
1305099660653,5cyclictest4793-21kerneloops10:02:392
1305099660652,7cyclictest4793-21kerneloops10:39:092
1304199660653,5cyclictest4793-21kerneloops12:01:171
1305899659656,2cyclictest4793-21kerneloops11:19:493
1305899659654,4cyclictest4793-21kerneloops09:07:133
1304199659656,2cyclictest4793-21kerneloops07:39:271
1304199659652,6cyclictest4793-21kerneloops12:30:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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