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2026-02-16 - 19:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Feb 16, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2723399635627,6cyclictest4793-21kerneloops07:54:583
2723399633626,6cyclictest4793-21kerneloops07:12:343
2723399633625,6cyclictest4793-21kerneloops11:19:473
2722199633626,5cyclictest4793-21kerneloops10:13:161
2721299633624,8cyclictest4793-21kerneloops11:44:410
2723399632626,5cyclictest4793-21kerneloops12:09:413
2722199632624,6cyclictest4793-21kerneloops10:30:481
2722199631625,5cyclictest4793-21kerneloops08:14:571
2723399630625,4cyclictest4793-21kerneloops08:46:123
2723399630624,4cyclictest4793-21kerneloops11:13:473
2721299630624,5cyclictest4793-21kerneloops10:07:100
2722899629620,7cyclictest4793-21kerneloops09:18:402
2722199629626,2cyclictest4793-21kerneloops11:45:451
2722199629626,2cyclictest4793-21kerneloops09:21:531
2722199629623,5cyclictest4793-21kerneloops10:47:061
2721299629625,2cyclictest4793-21kerneloops10:40:550
2721299629620,8cyclictest4793-21kerneloops10:14:300
2723399628622,5cyclictest4793-21kerneloops12:16:483
2723399628622,5cyclictest4793-21kerneloops10:49:183
2722199628623,4cyclictest4793-21kerneloops09:40:541
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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