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2026-03-05 - 07:28
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Mar 05, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
124799638631,5cyclictest4793-21kerneloops00:26:292
124299636628,6cyclictest4793-21kerneloops22:06:441
124799634625,7cyclictest4793-21kerneloops23:48:272
124299634627,6cyclictest4793-21kerneloops20:41:021
125499633626,5cyclictest4793-21kerneloops19:59:183
124299633626,5cyclictest4793-21kerneloops21:37:231
124299633624,7cyclictest4793-21kerneloops00:30:401
124299633624,7cyclictest4793-21kerneloops00:30:391
125499632626,4cyclictest4793-21kerneloops20:37:593
125499632626,4cyclictest4793-21kerneloops20:10:503
125499632626,4cyclictest4793-21kerneloops19:46:173
124299632626,5cyclictest4793-21kerneloops23:14:321
123399632625,6cyclictest4793-21kerneloops21:58:040
124299631627,2cyclictest4793-21kerneloops00:37:501
124299630627,2cyclictest4793-21kerneloops20:17:181
124799629622,6cyclictest4793-21kerneloops20:14:042
123399629625,2cyclictest4793-21kerneloops23:40:010
124299628626,1cyclictest4793-21kerneloops21:51:301
123399628619,7cyclictest4793-21kerneloops00:03:310
125499627621,5cyclictest4793-21kerneloops21:03:083
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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