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2026-05-26 - 22:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue May 26, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
613899649640,7cyclictest4793-21kerneloops10:08:273
612599635628,5cyclictest4793-21kerneloops08:15:071
613899634626,6cyclictest4793-21kerneloops08:27:553
613899634626,6cyclictest4793-21kerneloops07:37:373
613899634625,7cyclictest4793-21kerneloops09:51:053
612599634626,6cyclictest4793-21kerneloops09:36:261
613899633626,5cyclictest4793-21kerneloops09:07:523
613899633625,6cyclictest4793-21kerneloops11:36:073
613899633625,6cyclictest4793-21kerneloops11:33:303
613899633624,7cyclictest4793-21kerneloops10:39:343
612599633627,5cyclictest4793-21kerneloops11:13:191
612599633626,6cyclictest4793-21kerneloops07:42:451
613899632623,7cyclictest4793-21kerneloops08:03:023
613099632626,5cyclictest4793-21kerneloops10:40:292
613099632626,5cyclictest4793-21kerneloops10:40:282
613099632626,4cyclictest4793-21kerneloops10:47:442
613099632625,5cyclictest4793-21kerneloops11:26:582
612599632623,7cyclictest4793-21kerneloops10:37:371
612099632623,7cyclictest4793-21kerneloops10:25:510
613899631623,7cyclictest4793-21kerneloops08:52:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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