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2026-05-15 - 21:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri May 15, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
478399637628,7cyclictest4793-21kerneloops11:54:101
479999635627,7cyclictest4793-21kerneloops12:13:223
478399635625,8cyclictest4793-21kerneloops08:00:111
478399634628,5cyclictest4793-21kerneloops09:46:581
478399634627,5cyclictest4793-21kerneloops11:30:221
479999633627,4cyclictest4793-21kerneloops11:00:283
479999633627,4cyclictest4793-21kerneloops07:12:303
479299633625,6cyclictest4793-21kerneloops10:37:272
478399633628,4cyclictest4793-21kerneloops10:06:011
478399633627,5cyclictest4793-21kerneloops08:41:281
477899633620,11cyclictest4793-21kerneloops12:05:380
478399632628,2cyclictest4793-21kerneloops08:11:561
478399632626,4cyclictest4793-21kerneloops07:51:411
477899632623,7cyclictest4793-21kerneloops10:05:480
477899632622,8cyclictest4793-21kerneloops07:45:380
479999631623,6cyclictest4793-21kerneloops09:44:213
479999631623,6cyclictest4793-21kerneloops08:54:333
479999631622,7cyclictest4793-21kerneloops09:51:153
478399631625,5cyclictest4793-21kerneloops09:19:131
479999630625,4cyclictest4793-21kerneloops07:37:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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