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2026-03-29 - 19:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Mar 29, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2902699635626,7cyclictest4793-21kerneloops11:42:043
2902699633626,6cyclictest4793-21kerneloops10:42:543
2900399633624,7cyclictest4793-21kerneloops12:01:420
2902699631624,5cyclictest4793-21kerneloops08:03:233
2901999631625,5cyclictest4793-21kerneloops09:46:502
2901999631625,5cyclictest4793-21kerneloops09:46:502
2901999631623,7cyclictest4793-21kerneloops09:38:182
2901999630622,7cyclictest4793-21kerneloops10:55:412
2900399630622,6cyclictest4793-21kerneloops12:14:330
2902699629624,4cyclictest4793-21kerneloops09:20:253
2902699629621,6cyclictest4793-21kerneloops08:14:083
2901099629622,5cyclictest4793-21kerneloops11:15:021
2900399629620,7cyclictest4793-21kerneloops09:32:260
2901999628626,1cyclictest4793-21kerneloops11:29:192
2901999628622,5cyclictest4793-21kerneloops09:44:122
2901999628620,6cyclictest4793-21kerneloops08:30:262
2901999628619,7cyclictest4793-21kerneloops11:41:322
2901999628617,9cyclictest4793-21kerneloops09:19:412
2901099628621,5cyclictest4793-21kerneloops09:15:321
2901099628620,6cyclictest4793-21kerneloops10:59:021
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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