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2026-08-09 - 14:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Aug 09, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2432099664655,7cyclictest4793-21kerneloops09:13:511
2433299663657,4cyclictest4793-21kerneloops11:12:403
2433299663655,6cyclictest4793-21kerneloops10:32:433
2432099663657,4cyclictest4793-21kerneloops08:22:161
2433299662656,5cyclictest4793-21kerneloops11:32:293
2432099662656,5cyclictest4793-21kerneloops12:35:311
2431499662653,7cyclictest4793-21kerneloops09:24:260
2433299661653,6cyclictest4793-21kerneloops11:00:513
2432099661654,5cyclictest4793-21kerneloops10:43:361
2432099661654,5cyclictest4793-21kerneloops10:43:351
2432099661653,6cyclictest4793-21kerneloops07:49:051
2431499661653,7cyclictest4793-21kerneloops07:48:540
2433299660653,6cyclictest4793-21kerneloops11:23:493
2432099660653,5cyclictest4793-21kerneloops10:46:501
2431499660650,8cyclictest4793-21kerneloops10:50:190
2433299659654,4cyclictest4793-21kerneloops09:08:473
2433299659652,5cyclictest4793-21kerneloops08:40:433
2432099659652,5cyclictest4793-21kerneloops09:36:251
2432099659651,6cyclictest4793-21kerneloops09:52:351
2431499659652,5cyclictest4793-21kerneloops08:06:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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