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2026-05-11 - 21:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon May 11, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
112599646637,7cyclictest4793-21kerneloops09:11:342
113199638629,7cyclictest4793-21kerneloops12:20:013
113199634627,6cyclictest4793-21kerneloops08:53:103
113199634625,7cyclictest4793-21kerneloops10:23:233
111999633626,5cyclictest4793-21kerneloops07:10:011
111299633624,7cyclictest4793-21kerneloops08:47:140
113199632625,5cyclictest4793-21kerneloops09:52:503
113199632623,7cyclictest4793-21kerneloops07:41:213
111999632629,2cyclictest4793-21kerneloops07:22:181
111299632625,5cyclictest4793-21kerneloops09:11:430
111299632620,10cyclictest4793-21kerneloops10:35:060
113199631627,2cyclictest4793-21kerneloops12:36:093
113199631624,6cyclictest4793-21kerneloops10:47:453
113199631623,6cyclictest4793-21kerneloops09:22:463
113199631623,6cyclictest4793-21kerneloops09:15:203
111299631623,6cyclictest4793-21kerneloops11:10:090
113199630624,5cyclictest4793-21kerneloops10:40:293
113199630624,4cyclictest4793-21kerneloops11:36:113
113199630624,4cyclictest4793-21kerneloops11:08:123
113199630623,5cyclictest4793-21kerneloops10:28:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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