You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-01 - 20:45
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Apr 01, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1987399635625,8cyclictest4793-21kerneloops09:36:021
1987399635625,8cyclictest4793-21kerneloops09:36:011
1987399633626,5cyclictest4793-21kerneloops07:58:311
1988499632626,5cyclictest4793-21kerneloops08:20:313
1988499632625,5cyclictest4793-21kerneloops10:30:513
1987899632626,5cyclictest4793-21kerneloops12:28:572
1987399632626,5cyclictest4793-21kerneloops12:11:161
1987399632626,5cyclictest4793-21kerneloops10:20:101
1987399632625,5cyclictest4793-21kerneloops11:02:051
1987399632624,6cyclictest4793-21kerneloops08:30:501
1988499631624,6cyclictest4793-21kerneloops08:27:153
1987899631623,6cyclictest4793-21kerneloops08:50:102
1987399631623,7cyclictest4793-21kerneloops11:58:201
1987899630623,6cyclictest4793-21kerneloops07:39:302
1987399630624,5cyclictest4793-21kerneloops07:40:331
1987399630624,4cyclictest4793-21kerneloops12:26:171
1986699630623,6cyclictest4793-21kerneloops09:19:320
1986699630622,7cyclictest4793-21kerneloops09:56:400
1988499629625,2cyclictest4793-21kerneloops08:00:503
1988499629622,5cyclictest4793-21kerneloops08:55:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional