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2026-05-14 - 18:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu May 14, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2387599666654,10cyclictest4793-21kerneloops11:05:160
2389699644634,8cyclictest4793-21kerneloops10:48:183
2388899635626,7cyclictest4793-21kerneloops07:17:492
2389699634627,5cyclictest4793-21kerneloops11:00:553
2388299634626,6cyclictest4793-21kerneloops08:23:121
2389699632629,2cyclictest4793-21kerneloops08:45:353
2389699632626,5cyclictest4793-21kerneloops08:09:243
2388299632626,5cyclictest4793-21kerneloops08:01:381
2388299632625,5cyclictest4793-21kerneloops10:49:231
2388299632625,5cyclictest4793-21kerneloops10:36:091
2388299632625,5cyclictest4793-21kerneloops09:15:251
2388899631624,5cyclictest4793-21kerneloops12:26:002
2388299631623,6cyclictest4793-21kerneloops07:52:571
2389699630623,5cyclictest4793-21kerneloops07:21:553
2388899630622,6cyclictest4793-21kerneloops07:57:022
2389699629620,7cyclictest4793-21kerneloops09:14:533
2388899629623,5cyclictest4793-21kerneloops10:29:142
2387599629623,5cyclictest4793-21kerneloops08:07:410
2387599629620,7cyclictest4793-21kerneloops11:53:050
2388899628626,1cyclictest4793-21kerneloops09:35:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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