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2026-01-01 - 02:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Jan 01, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2380399585576,7cyclictest4793-21kerneloops20:02:241
2381599581574,6cyclictest4793-21kerneloops20:55:563
2381599581572,7cyclictest4793-21kerneloops22:57:223
2380399581574,5cyclictest4793-21kerneloops22:03:441
2381599580575,4cyclictest4793-21kerneloops21:04:543
2381599580574,5cyclictest4793-21kerneloops20:38:403
2381599580574,5cyclictest4793-21kerneloops00:19:163
2380399580574,5cyclictest4793-21kerneloops23:51:011
2380399580573,6cyclictest4793-21kerneloops22:19:381
2380399580573,5cyclictest4793-21kerneloops20:39:451
2379499580572,7cyclictest4793-21kerneloops21:36:460
2380399579576,2cyclictest4793-21kerneloops21:44:331
2380399579576,2cyclictest4793-21kerneloops21:44:331
2380399579573,5cyclictest4793-21kerneloops20:34:481
2380399579572,5cyclictest4793-21kerneloops00:29:131
2379499579574,4cyclictest4793-21kerneloops22:21:450
2381099578572,4cyclictest4793-21kerneloops19:59:532
2381099578572,4cyclictest4793-21kerneloops19:33:432
2381099578570,6cyclictest4793-21kerneloops00:33:132
2380399578576,1cyclictest4793-21kerneloops21:06:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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