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2025-12-26 - 22:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Dec 26, 2025 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1794099585576,7cyclictest4793-21kerneloops11:57:403
1793199583570,8cyclictest4793-21kerneloops12:34:012
1792499583576,5cyclictest4793-21kerneloops11:51:491
1792499583574,7cyclictest4793-21kerneloops08:10:381
1794099582575,5cyclictest4793-21kerneloops08:37:103
1794099581574,6cyclictest4793-21kerneloops12:25:333
1791999581570,9cyclictest4793-21kerneloops10:24:020
1794099580574,5cyclictest4793-21kerneloops08:02:433
1791999580572,7cyclictest4793-21kerneloops07:55:550
1791999579572,6cyclictest4793-21kerneloops09:52:290
1791999579572,6cyclictest4793-21kerneloops09:06:000
1791999579570,8cyclictest4793-21kerneloops09:39:280
1794099578570,6cyclictest4793-21kerneloops10:42:203
1793199578572,5cyclictest4793-21kerneloops10:42:112
1793199578571,5cyclictest4793-21kerneloops11:13:182
1792499578576,1cyclictest4793-21kerneloops08:30:511
1794099577574,1cyclictest4793-21kerneloops11:21:363
1793199577574,2cyclictest4793-21kerneloops09:09:052
1793199577570,6cyclictest4793-21kerneloops08:22:152
1793199577569,6cyclictest4793-21kerneloops10:24:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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