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2026-09-24 - 06:16
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Sep 24, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2228099670662,6cyclictest4793-21kerneloops22:30:352
2227199666657,7cyclictest4793-21kerneloops22:23:111
2228699663656,5cyclictest4793-21kerneloops20:10:283
2228699663655,6cyclictest4793-21kerneloops19:33:323
2228699663654,7cyclictest4793-21kerneloops21:37:083
2227199663656,5cyclictest4793-21kerneloops23:37:021
2227199663655,6cyclictest4793-21kerneloops19:39:151
2227199663655,6cyclictest4793-21kerneloops19:16:571
2227199663655,6cyclictest4793-21kerneloops19:10:391
2228099662654,6cyclictest4793-21kerneloops21:29:452
2227199662655,5cyclictest4793-21kerneloops20:38:241
2227199662654,6cyclictest4793-21kerneloops23:04:121
2227199662654,6cyclictest4793-21kerneloops20:12:571
2226599662652,8cyclictest4793-21kerneloops21:43:470
2226599662651,9cyclictest4793-21kerneloops22:48:530
2228099661655,5cyclictest4793-21kerneloops00:12:182
2227199661655,5cyclictest4793-21kerneloops20:34:461
2226599661653,7cyclictest4793-21kerneloops20:45:330
2226599661653,6cyclictest4793-21kerneloops23:45:090
2228699660653,6cyclictest4793-21kerneloops23:56:523
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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