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2026-02-13 - 19:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Feb 13, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2136499650646,2cyclictest4793-21kerneloops10:05:400
2137599643641,1cyclictest4793-21kerneloops10:57:292
2138399636627,7cyclictest4793-21kerneloops09:53:483
2137599635625,8cyclictest4793-21kerneloops10:00:312
2137099634626,7cyclictest4793-21kerneloops12:29:581
2137099634626,7cyclictest4793-21kerneloops12:29:581
2138399633624,7cyclictest4793-21kerneloops08:00:183
2138399631625,5cyclictest4793-21kerneloops11:23:573
2137599631624,6cyclictest4793-21kerneloops09:31:172
2136499631624,6cyclictest4793-21kerneloops11:54:450
2136499631624,5cyclictest4793-21kerneloops09:45:270
2138399630621,7cyclictest4793-21kerneloops11:47:293
2137599630624,5cyclictest4793-21kerneloops12:33:192
2137599630622,6cyclictest4793-21kerneloops12:22:232
2137099630627,2cyclictest4793-21kerneloops07:35:571
2137099630624,5cyclictest4793-21kerneloops09:13:091
2136499630625,3cyclictest4793-21kerneloops10:51:340
2136499630625,3cyclictest4793-21kerneloops10:51:340
2138399629622,5cyclictest4793-21kerneloops09:11:423
2137599629625,2cyclictest4793-21kerneloops10:50:292
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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