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2026-01-20 - 17:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Jan 20, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889810780,1066rtkit-daemon4793-21kerneloops07:09:002
2590399585577,6cyclictest4793-21kerneloops11:44:591
2590399583575,6cyclictest4793-21kerneloops09:15:041
2592099582575,5cyclictest4793-21kerneloops11:07:263
2592099582575,5cyclictest4793-21kerneloops10:59:433
2590399581575,5cyclictest4793-21kerneloops07:22:391
2590399581575,5cyclictest4793-21kerneloops07:22:391
2590399581574,6cyclictest4793-21kerneloops11:18:341
2589699581573,6cyclictest4793-21kerneloops10:58:200
2589699581573,6cyclictest4793-21kerneloops09:33:200
2590399580571,7cyclictest4793-21kerneloops10:35:311
2592099579571,1cyclictest4793-21kerneloops11:51:483
2592099579569,2cyclictest4793-21kerneloops09:05:013
2591299579573,5cyclictest4793-21kerneloops10:41:012
2591299579572,6cyclictest4793-21kerneloops11:37:482
2592099578571,1cyclictest4793-21kerneloops08:23:473
2592099578570,7cyclictest4793-21kerneloops10:21:113
2591299578572,4cyclictest4793-21kerneloops11:06:122
2590399578574,2cyclictest4793-21kerneloops11:26:211
2590399578573,4cyclictest4793-21kerneloops10:08:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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