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2026-05-08 - 06:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri May 08, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1922499650639,9cyclictest4793-21kerneloops00:33:230
1924799636628,6cyclictest4793-21kerneloops23:33:343
1923199636627,7cyclictest4793-21kerneloops22:45:121
1923199634626,6cyclictest4793-21kerneloops20:33:571
1922499633629,2cyclictest4793-21kerneloops00:36:020
1922499633625,6cyclictest4793-21kerneloops22:37:380
1924799632627,4cyclictest4793-21kerneloops00:15:073
1924799632626,5cyclictest4793-21kerneloops22:36:033
1923199632626,5cyclictest4793-21kerneloops20:39:011
1924099631624,5cyclictest4793-21kerneloops20:39:552
1923199631624,6cyclictest4793-21kerneloops21:06:341
1922499631624,5cyclictest4793-21kerneloops23:51:270
1924099630622,6cyclictest4793-21kerneloops22:40:172
1924799629624,4cyclictest4793-21kerneloops19:34:283
1924799629622,5cyclictest4793-21kerneloops23:46:523
1923199629621,7cyclictest4793-21kerneloops21:50:211
1922499629623,5cyclictest4793-21kerneloops20:52:240
1923199628619,7cyclictest4793-21kerneloops00:01:001
1922499628621,5cyclictest4793-21kerneloops19:39:290
1922499628620,6cyclictest4793-21kerneloops22:44:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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