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2026-03-03 - 05:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Mar 03, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2919999636627,7cyclictest4793-21kerneloops22:33:283
2917899636626,8cyclictest4793-21kerneloops00:34:470
2919999634626,6cyclictest4793-21kerneloops19:17:023
2918799634625,7cyclictest4793-21kerneloops22:30:081
2919999633627,4cyclictest4793-21kerneloops22:38:463
2919999632626,5cyclictest4793-21kerneloops21:16:583
2919999632625,5cyclictest4793-21kerneloops20:57:043
2918799632626,5cyclictest4793-21kerneloops21:58:471
2918799632626,4cyclictest4793-21kerneloops19:52:161
2917899632625,5cyclictest4793-21kerneloops22:29:040
2917899632625,5cyclictest4793-21kerneloops22:29:030
2919999631625,5cyclictest4793-21kerneloops00:02:253
2917899631624,5cyclictest4793-21kerneloops20:06:550
2917899631622,7cyclictest4793-21kerneloops22:40:020
2919999630625,4cyclictest4793-21kerneloops20:22:103
2918799630624,5cyclictest4793-21kerneloops22:26:001
2918799630624,5cyclictest4793-21kerneloops22:26:001
2918799630622,6cyclictest4793-21kerneloops21:06:141
2917899630624,5cyclictest4793-21kerneloops22:46:010
2917899630622,6cyclictest4793-21kerneloops23:29:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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