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2026-03-08 - 07:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Mar 08, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1201799654645,7cyclictest4793-21kerneloops23:43:051
1203099635627,6cyclictest4793-21kerneloops22:17:143
1201799635626,7cyclictest4793-21kerneloops20:10:141
1203099634626,7cyclictest4793-21kerneloops00:31:553
1201799634627,5cyclictest4793-21kerneloops23:47:501
1203099633625,6cyclictest4793-21kerneloops20:59:593
1201799633627,5cyclictest4793-21kerneloops20:18:481
1201799633627,4cyclictest4793-21kerneloops20:34:231
1203099632626,5cyclictest4793-21kerneloops21:19:363
1203099632625,6cyclictest4793-21kerneloops22:44:453
1203099632624,6cyclictest4793-21kerneloops19:41:333
1201799632625,5cyclictest4793-21kerneloops19:13:221
1201799632624,6cyclictest4793-21kerneloops21:44:221
1201799632624,6cyclictest4793-21kerneloops21:44:211
1203099631625,4cyclictest4793-21kerneloops19:48:083
1201799631625,5cyclictest4793-21kerneloops19:57:231
1201799631625,4cyclictest4793-21kerneloops22:01:131
1201799631625,4cyclictest4793-21kerneloops21:00:311
1201799631625,4cyclictest4793-21kerneloops00:24:491
1201799631624,5cyclictest4793-21kerneloops23:59:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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