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2026-02-27 - 02:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Feb 27, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1280599647638,7cyclictest4793-21kerneloops22:30:483
1278499635626,7cyclictest4793-21kerneloops20:29:260
1280599634626,7cyclictest4793-21kerneloops23:53:463
1280599634626,7cyclictest4793-21kerneloops21:21:033
1280599633626,5cyclictest4793-21kerneloops19:17:083
1280599633625,6cyclictest4793-21kerneloops00:15:063
1280599632626,4cyclictest4793-21kerneloops19:34:223
1280599632623,7cyclictest4793-21kerneloops20:09:563
1280599632623,7cyclictest4793-21kerneloops00:05:193
1279199632624,6cyclictest4793-21kerneloops21:42:491
1279199632624,6cyclictest4793-21kerneloops21:32:021
1280599631625,5cyclictest4793-21kerneloops19:50:563
1280599631625,4cyclictest4793-21kerneloops21:01:493
1280599631624,6cyclictest4793-21kerneloops22:49:043
1280599631624,6cyclictest4793-21kerneloops19:42:093
1279199631624,5cyclictest4793-21kerneloops19:11:161
1280599630626,2cyclictest4793-21kerneloops19:45:103
1279199630624,5cyclictest4793-21kerneloops23:30:181
1278499630623,6cyclictest4793-21kerneloops21:39:370
1280599629622,6cyclictest4793-21kerneloops19:26:193
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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