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2026-04-28 - 03:21
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Apr 27, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2666399640636,2cyclictest4793-21kerneloops11:29:510
2667499636627,7cyclictest4793-21kerneloops09:45:451
2668799634626,6cyclictest4793-21kerneloops09:09:393
2668799633627,5cyclictest4793-21kerneloops08:18:303
2667499633627,4cyclictest4793-21kerneloops07:20:481
2667499633626,6cyclictest4793-21kerneloops07:17:131
2666399633625,6cyclictest4793-21kerneloops11:55:030
2666399633625,6cyclictest4793-21kerneloops09:51:200
2668799632626,5cyclictest4793-21kerneloops07:25:353
2668799632626,4cyclictest4793-21kerneloops11:39:133
2668799632624,6cyclictest4793-21kerneloops08:01:213
2667499632626,4cyclictest4793-21kerneloops11:05:061
2666399632626,5cyclictest4793-21kerneloops07:11:310
2666399632624,7cyclictest4793-21kerneloops10:00:320
2668799631626,4cyclictest4793-21kerneloops07:49:473
2667499631628,2cyclictest4793-21kerneloops07:46:231
2666399631627,3cyclictest4793-21kerneloops09:37:560
2668799630627,2cyclictest4793-21kerneloops11:26:213
2668799630621,7cyclictest4793-21kerneloops09:14:283
2667499630628,1cyclictest4793-21kerneloops10:10:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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