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2026-09-21 - 02:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Sep 21, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812160,1205rtkit-daemon4793-21kerneloops19:08:543
1914899664655,7cyclictest4793-21kerneloops19:59:203
1913599664657,6cyclictest4793-21kerneloops19:32:571
1913599664656,6cyclictest4793-21kerneloops20:15:391
1913599663657,4cyclictest4793-21kerneloops20:51:171
1913599663654,7cyclictest4793-21kerneloops22:00:301
1913099663653,9cyclictest4793-21kerneloops23:53:240
1914899662656,5cyclictest4793-21kerneloops22:48:553
1913599662655,5cyclictest4793-21kerneloops19:17:581
1914899661656,4cyclictest4793-21kerneloops21:15:263
1914899661655,5cyclictest4793-21kerneloops22:38:413
1914899661655,5cyclictest4793-21kerneloops22:38:413
1914899661653,6cyclictest4793-21kerneloops22:15:533
1914299661654,6cyclictest4793-21kerneloops23:56:032
1914299661654,5cyclictest4793-21kerneloops20:16:422
1914299661653,6cyclictest4793-21kerneloops22:51:452
1913599661654,5cyclictest4793-21kerneloops22:35:091
1913599661654,5cyclictest4793-21kerneloops22:35:081
1913099661654,6cyclictest4793-21kerneloops22:59:370
1914899660654,4cyclictest4793-21kerneloops23:00:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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