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2026-01-02 - 22:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Jan 02, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2031199583576,5cyclictest4793-21kerneloops08:09:003
2031199583575,6cyclictest4793-21kerneloops09:06:223
2031199582575,6cyclictest4793-21kerneloops07:18:483
2029899582576,5cyclictest4793-21kerneloops10:54:531
2031199581576,4cyclictest4793-21kerneloops10:26:513
2030399581574,6cyclictest4793-21kerneloops09:21:452
2030399580573,5cyclictest4793-21kerneloops09:34:242
2030399580573,2cyclictest4793-21kerneloops07:52:172
2029899580573,5cyclictest4793-21kerneloops10:20:491
2031199579576,1cyclictest4793-21kerneloops09:00:183
2030399579572,5cyclictest4793-21kerneloops11:06:412
2031199578575,2cyclictest4793-21kerneloops09:29:533
2031199578571,6cyclictest4793-21kerneloops10:30:203
2031199578571,5cyclictest4793-21kerneloops11:13:253
2030399578571,6cyclictest4793-21kerneloops09:42:032
2029899578570,7cyclictest4793-21kerneloops08:48:181
2029199578572,5cyclictest4793-21kerneloops12:31:560
2031199577574,2cyclictest4793-21kerneloops07:33:343
2031199577569,7cyclictest4793-21kerneloops08:21:513
2030399577569,6cyclictest4793-21kerneloops09:45:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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