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2026-04-26 - 02:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Apr 26, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
581899635626,8cyclictest4793-21kerneloops20:34:300
582399634628,5cyclictest4793-21kerneloops00:12:271
583599633627,5cyclictest4793-21kerneloops19:18:563
583599633625,6cyclictest4793-21kerneloops20:42:173
583199633626,6cyclictest4793-21kerneloops00:06:532
583199632625,5cyclictest4793-21kerneloops22:03:062
583199632625,5cyclictest4793-21kerneloops20:04:582
583199632620,10cyclictest4793-21kerneloops21:50:222
583599631628,1cyclictest4793-21kerneloops20:03:333
583599631624,5cyclictest4793-21kerneloops19:31:563
583599631623,6cyclictest4793-21kerneloops23:20:133
583199631625,5cyclictest4793-21kerneloops00:21:592
582399631624,6cyclictest4793-21kerneloops22:41:051
582399631624,5cyclictest4793-21kerneloops23:41:521
582399631623,6cyclictest4793-21kerneloops22:55:491
582399631623,6cyclictest4793-21kerneloops22:55:491
581899631622,8cyclictest4793-21kerneloops21:24:150
581899631621,9cyclictest4793-21kerneloops22:15:440
583599630627,2cyclictest4793-21kerneloops22:47:283
583599630627,1cyclictest4793-21kerneloops21:25:393
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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