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2025-12-31 - 09:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Dec 31, 2025 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2896299583577,5cyclictest4793-21kerneloops21:29:193
2894999583575,6cyclictest4793-21kerneloops23:25:171
2896299582574,6cyclictest4793-21kerneloops19:35:113
2896299582573,7cyclictest4793-21kerneloops23:07:403
2895899582573,7cyclictest4793-21kerneloops22:12:552
2894999581573,6cyclictest4793-21kerneloops22:09:021
2894599581572,7cyclictest4793-21kerneloops00:33:110
2894599581571,8cyclictest4793-21kerneloops23:56:520
2896299580573,5cyclictest4793-21kerneloops22:16:173
2896299580573,5cyclictest4793-21kerneloops21:38:093
2896299580571,7cyclictest4793-21kerneloops20:43:543
2894999580576,2cyclictest4793-21kerneloops21:01:041
2894999580575,4cyclictest4793-21kerneloops21:16:031
2894999580572,6cyclictest4793-21kerneloops21:33:371
2894599580572,7cyclictest4793-21kerneloops22:08:520
2896299579576,2cyclictest4793-21kerneloops20:13:213
2896299579569,8cyclictest4793-21kerneloops21:21:353
2895899579573,5cyclictest4793-21kerneloops23:01:472
2894999579571,6cyclictest4793-21kerneloops21:40:271
2894999579571,6cyclictest4793-21kerneloops21:40:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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