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2026-02-15 - 03:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Feb 15, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1493199646637,7cyclictest4793-21kerneloops00:36:573
1492399638634,2cyclictest4793-21kerneloops20:40:122
1492399638629,7cyclictest4793-21kerneloops23:44:222
1493199635627,6cyclictest4793-21kerneloops23:53:463
1493199635626,7cyclictest4793-21kerneloops19:29:293
1493199635626,7cyclictest4793-21kerneloops00:17:173
1493199634628,5cyclictest4793-21kerneloops19:20:363
1493199634627,6cyclictest4793-21kerneloops20:45:373
1493199634627,5cyclictest4793-21kerneloops00:29:073
1493199634626,6cyclictest4793-21kerneloops22:39:233
1493199634625,7cyclictest4793-21kerneloops21:26:193
1491499634626,7cyclictest4793-21kerneloops21:58:051
1493199633627,5cyclictest4793-21kerneloops22:31:393
1493199633627,5cyclictest4793-21kerneloops00:13:053
1493199633627,4cyclictest4793-21kerneloops19:15:293
1493199633626,6cyclictest4793-21kerneloops20:33:053
1493199633626,6cyclictest4793-21kerneloops19:36:263
1493199633626,6cyclictest4793-21kerneloops19:31:063
1493199633626,5cyclictest4793-21kerneloops20:16:443
1493199633625,6cyclictest4793-21kerneloops19:45:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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