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2026-08-18 - 15:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Aug 18, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1480899667658,7cyclictest4793-21kerneloops12:09:563
1480499666662,2cyclictest4793-21kerneloops10:24:112
1480899664657,6cyclictest4793-21kerneloops10:21:443
1480899664656,6cyclictest4793-21kerneloops09:42:073
1480899664656,6cyclictest4793-21kerneloops09:21:073
1480899664655,7cyclictest4793-21kerneloops11:25:353
1480899664654,8cyclictest4793-21kerneloops11:17:553
1480899663657,5cyclictest4793-21kerneloops12:39:133
1480899663657,5cyclictest4793-21kerneloops09:55:243
1480899663655,7cyclictest4793-21kerneloops10:35:463
1480899663654,7cyclictest4793-21kerneloops11:06:543
1480899662655,6cyclictest4793-21kerneloops12:18:363
1479699662655,5cyclictest4793-21kerneloops07:50:021
1480899661655,5cyclictest4793-21kerneloops12:27:063
1480899661655,5cyclictest4793-21kerneloops12:21:063
1480899661655,5cyclictest4793-21kerneloops09:25:433
1480899661655,4cyclictest4793-21kerneloops12:33:293
1480899661654,6cyclictest4793-21kerneloops10:50:383
1480899661654,5cyclictest4793-21kerneloops10:15:303
1480899661654,5cyclictest4793-21kerneloops08:37:443
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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