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2026-01-02 - 04:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Jan 02, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1458399587583,2cyclictest4793-21kerneloops21:34:290
1458399587572,13cyclictest4793-21kerneloops22:01:010
1460099583576,6cyclictest4793-21kerneloops20:00:303
1460099583575,7cyclictest4793-21kerneloops00:03:263
1460099583575,6cyclictest4793-21kerneloops19:50:323
1460099582575,5cyclictest4793-21kerneloops20:55:223
1458899582577,4cyclictest4793-21kerneloops19:27:341
1458399582574,6cyclictest4793-21kerneloops19:25:500
1458899581577,2cyclictest4793-21kerneloops00:21:301
1458899581575,4cyclictest4793-21kerneloops20:06:321
1458899581573,6cyclictest4793-21kerneloops21:56:471
1458399581571,8cyclictest4793-21kerneloops21:01:400
1458899580577,1cyclictest4793-21kerneloops19:38:431
1458899580575,4cyclictest4793-21kerneloops21:24:271
1460099579573,5cyclictest4793-21kerneloops23:46:513
1460099579572,5cyclictest4793-21kerneloops23:29:553
1460099579572,5cyclictest4793-21kerneloops23:05:313
1458899579573,5cyclictest4793-21kerneloops20:43:331
1460099578575,2cyclictest4793-21kerneloops23:18:143
1460099578573,4cyclictest4793-21kerneloops19:16:453
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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