You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-08 - 15:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Feb 08, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
880399636628,6cyclictest4793-21kerneloops11:40:131
880899634630,2cyclictest4793-21kerneloops10:09:132
881899633627,5cyclictest4793-21kerneloops09:48:513
880399633626,5cyclictest4793-21kerneloops11:50:311
880399633626,5cyclictest4793-21kerneloops11:50:311
880399633625,7cyclictest4793-21kerneloops10:53:501
880399633625,6cyclictest4793-21kerneloops07:49:501
881899632627,4cyclictest4793-21kerneloops11:50:523
881899632627,4cyclictest4793-21kerneloops11:50:523
881899632625,5cyclictest4793-21kerneloops07:45:053
880399632624,6cyclictest4793-21kerneloops10:47:151
880399631626,4cyclictest4793-21kerneloops11:49:391
880399631625,4cyclictest4793-21kerneloops09:58:251
881899630626,2cyclictest4793-21kerneloops10:39:193
880399630627,2cyclictest4793-21kerneloops09:53:291
880399630625,4cyclictest4793-21kerneloops12:17:391
880399630624,5cyclictest4793-21kerneloops09:28:041
879799630623,5cyclictest4793-21kerneloops09:52:040
881899629626,2cyclictest4793-21kerneloops09:41:143
880399629622,5cyclictest4793-21kerneloops11:35:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional