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2026-08-03 - 12:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Aug 03, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3081699665657,4cyclictest4793-21kerneloops22:53:053
3081699664656,6cyclictest4793-21kerneloops23:18:593
3080399664656,6cyclictest4793-21kerneloops20:59:131
3081699663656,6cyclictest4793-21kerneloops22:28:523
3081699663655,6cyclictest4793-21kerneloops19:14:063
3080399663655,6cyclictest4793-21kerneloops22:36:181
3081699662656,4cyclictest4793-21kerneloops23:31:513
3080399662657,4cyclictest4793-21kerneloops00:29:151
3080399662655,6cyclictest4793-21kerneloops21:24:101
3080399662654,6cyclictest4793-21kerneloops23:44:441
3079899662654,6cyclictest4793-21kerneloops22:12:040
3079899662652,8cyclictest4793-21kerneloops21:23:590
3080399661654,5cyclictest4793-21kerneloops23:09:021
3079899661651,4cyclictest4793-21kerneloops19:57:010
3080899660654,4cyclictest4793-21kerneloops19:10:512
3081699659653,5cyclictest4793-21kerneloops20:52:263
3081699659651,6cyclictest4793-21kerneloops21:20:153
3080899659652,5cyclictest4793-21kerneloops19:44:102
3080399659656,2cyclictest4793-21kerneloops21:13:411
3079899659650,3cyclictest4793-21kerneloops19:29:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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