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2026-05-10 - 07:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun May 10, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1534099645635,8cyclictest4793-21kerneloops22:18:453
1532699636628,6cyclictest4793-21kerneloops23:47:491
1532699636628,6cyclictest4793-21kerneloops21:27:161
1534099635627,6cyclictest4793-21kerneloops20:54:243
1532699635629,5cyclictest4793-21kerneloops23:07:411
1532699635627,6cyclictest4793-21kerneloops19:23:231
1532699635626,7cyclictest4793-21kerneloops23:18:291
1534099634628,5cyclictest4793-21kerneloops19:43:383
1532699634627,5cyclictest4793-21kerneloops23:35:031
1532699634626,6cyclictest4793-21kerneloops19:14:061
1532699634625,7cyclictest4793-21kerneloops00:12:061
1534099633626,5cyclictest4793-21kerneloops00:23:423
1534099633624,7cyclictest4793-21kerneloops22:23:023
1532699633627,5cyclictest4793-21kerneloops22:39:241
1532699633626,6cyclictest4793-21kerneloops00:16:541
1532699633626,5cyclictest4793-21kerneloops22:56:401
1532699633626,5cyclictest4793-21kerneloops22:28:121
1532699633626,5cyclictest4793-21kerneloops22:28:121
1532699633626,5cyclictest4793-21kerneloops22:10:521
1532699633626,5cyclictest4793-21kerneloops21:06:451
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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