You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-09 - 14:46
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Jun 09, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2644999636628,6cyclictest4793-21kerneloops09:15:573
2643099635626,8cyclictest4793-21kerneloops10:59:010
2644999633628,4cyclictest4793-21kerneloops07:30:553
2644999633627,5cyclictest4793-21kerneloops08:36:083
2644999633627,4cyclictest4793-21kerneloops07:56:013
2644999633627,4cyclictest4793-21kerneloops07:46:023
2643699633626,5cyclictest4793-21kerneloops07:33:591
2644999632626,5cyclictest4793-21kerneloops08:07:373
2644999632624,6cyclictest4793-21kerneloops11:16:123
2643699632627,4cyclictest4793-21kerneloops08:47:071
2643699632626,5cyclictest4793-21kerneloops11:28:491
2643699632625,5cyclictest4793-21kerneloops08:20:481
2644999631627,2cyclictest4793-21kerneloops09:04:033
2644299631623,6cyclictest4793-21kerneloops08:27:002
2643699631628,2cyclictest4793-21kerneloops08:08:521
2643699631623,6cyclictest4793-21kerneloops07:57:481
2643099631624,6cyclictest4793-21kerneloops10:17:490
2643099631622,8cyclictest4793-21kerneloops07:54:440
2644999630628,1cyclictest4793-21kerneloops09:38:583
2644999630627,2cyclictest4793-21kerneloops12:34:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional