You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-24 - 17:53
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun May 24, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2841999636630,5cyclictest4793-21kerneloops11:17:553
2841999635628,6cyclictest4793-21kerneloops10:29:363
2841999633624,7cyclictest4793-21kerneloops08:56:393
2839899633625,6cyclictest4793-21kerneloops08:48:250
2840399632626,5cyclictest4793-21kerneloops11:06:251
2841999631628,2cyclictest4793-21kerneloops09:26:373
2841999631624,6cyclictest4793-21kerneloops12:36:253
2841199631624,5cyclictest4793-21kerneloops11:52:032
2840399631628,2cyclictest4793-21kerneloops12:11:081
2840399631625,5cyclictest4793-21kerneloops08:21:321
2840399631621,8cyclictest4793-21kerneloops09:34:431
2841999630624,5cyclictest4793-21kerneloops10:39:233
2840399630621,7cyclictest4793-21kerneloops10:43:441
2841999629623,5cyclictest4793-21kerneloops10:11:323
2841999629623,4cyclictest4793-21kerneloops09:55:233
2841999629622,6cyclictest4793-21kerneloops09:52:023
2841199629623,5cyclictest4793-21kerneloops12:01:522
2841199629621,7cyclictest4793-21kerneloops12:31:142
2840399629626,2cyclictest4793-21kerneloops08:03:041
2840399629626,2cyclictest4793-21kerneloops07:43:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional