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2026-03-16 - 05:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Mar 16, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
227499637628,7cyclictest4793-21kerneloops23:25:273
227499634625,7cyclictest4793-21kerneloops21:28:033
227499633625,6cyclictest4793-21kerneloops22:20:303
226199633625,6cyclictest4793-21kerneloops23:40:121
227499632624,6cyclictest4793-21kerneloops19:25:243
225399632625,5cyclictest4793-21kerneloops22:05:200
225399632625,5cyclictest4793-21kerneloops22:05:200
225399632624,6cyclictest4793-21kerneloops23:58:070
227499631625,5cyclictest4793-21kerneloops22:19:303
227499631623,7cyclictest4793-21kerneloops22:52:113
226799631624,5cyclictest4793-21kerneloops20:28:042
226199631623,6cyclictest4793-21kerneloops00:22:381
225399631625,5cyclictest4793-21kerneloops22:44:140
227499630622,6cyclictest4793-21kerneloops19:59:433
226199630623,5cyclictest4793-21kerneloops23:03:471
227499629623,5cyclictest4793-21kerneloops19:39:253
227499629622,5cyclictest4793-21kerneloops23:51:483
226199629623,4cyclictest4793-21kerneloops19:35:301
225399629621,6cyclictest4793-21kerneloops00:36:160
227499628625,2cyclictest4793-21kerneloops23:02:323
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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