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2026-05-16 - 21:48
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat May 16, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2792799634625,7cyclictest4793-21kerneloops11:41:252
2791999634629,4cyclictest4793-21kerneloops08:15:341
2792799633625,6cyclictest4793-21kerneloops09:21:162
2791999633627,5cyclictest4793-21kerneloops08:06:381
2791499633622,9cyclictest4793-21kerneloops10:27:470
2791999632624,7cyclictest4793-21kerneloops12:36:181
2793599631626,4cyclictest4793-21kerneloops08:52:203
2793599631625,5cyclictest4793-21kerneloops11:07:443
2792799631625,4cyclictest4793-21kerneloops08:01:402
2793599630626,2cyclictest4793-21kerneloops12:26:543
2791499630624,5cyclictest4793-21kerneloops09:17:570
2791499630623,6cyclictest4793-21kerneloops09:06:060
2791499630623,6cyclictest4793-21kerneloops09:06:060
2793599629625,2cyclictest4793-21kerneloops11:48:533
2793599629623,5cyclictest4793-21kerneloops10:41:233
2791499629623,5cyclictest4793-21kerneloops08:55:450
2791499629622,6cyclictest4793-21kerneloops11:43:530
2793599628626,1cyclictest4793-21kerneloops08:31:173
2793599628625,2cyclictest4793-21kerneloops07:15:063
2793599628625,1cyclictest4793-21kerneloops08:04:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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