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2026-03-15 - 16:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Mar 15, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2400299634627,6cyclictest4793-21kerneloops11:38:211
2401599632625,5cyclictest4793-21kerneloops09:50:163
2400299632626,5cyclictest4793-21kerneloops12:16:311
2401599631625,5cyclictest4793-21kerneloops08:04:313
2400699631623,6cyclictest4793-21kerneloops07:36:342
2400699631620,9cyclictest4793-21kerneloops10:04:242
2400299631625,5cyclictest4793-21kerneloops09:48:101
2400299631624,6cyclictest4793-21kerneloops10:01:581
2400299631624,5cyclictest4793-21kerneloops09:13:521
2400699630624,5cyclictest4793-21kerneloops12:26:262
2400299630619,9cyclictest4793-21kerneloops08:25:231
2399599630620,8cyclictest4793-21kerneloops10:29:090
2399599630617,11cyclictest4793-21kerneloops10:10:260
2401599629626,2cyclictest4793-21kerneloops11:20:203
2401599629620,7cyclictest4793-21kerneloops07:40:133
2400699629623,5cyclictest4793-21kerneloops10:42:112
2400299629627,1cyclictest4793-21kerneloops07:34:471
2401599628625,2cyclictest4793-21kerneloops09:28:393
2401599628618,8cyclictest4793-21kerneloops12:11:363
2400699628620,6cyclictest4793-21kerneloops09:35:232
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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