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2026-04-28 - 16:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Apr 28, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1085099634627,5cyclictest4793-21kerneloops20:30:251
1085099634626,6cyclictest4793-21kerneloops22:36:281
1085099634626,6cyclictest4793-21kerneloops19:14:211
1086699632626,4cyclictest4793-21kerneloops20:49:323
1085099632625,6cyclictest4793-21kerneloops22:29:371
1086699631626,4cyclictest4793-21kerneloops20:35:203
1085599631624,5cyclictest4793-21kerneloops23:57:572
1085599631623,7cyclictest4793-21kerneloops21:25:292
1085099631628,2cyclictest4793-21kerneloops22:08:301
1085099631626,4cyclictest4793-21kerneloops20:08:111
1084399631627,2cyclictest4793-21kerneloops23:40:220
1084399631624,6cyclictest4793-21kerneloops20:09:360
1084399631623,7cyclictest4793-21kerneloops22:55:500
1084399631622,8cyclictest4793-21kerneloops19:23:270
1086699630628,1cyclictest4793-21kerneloops22:20:433
1086699630624,4cyclictest4793-21kerneloops21:41:143
1086699630623,5cyclictest4793-21kerneloops00:32:033
1085599630623,5cyclictest4793-21kerneloops22:34:352
1085099630627,2cyclictest4793-21kerneloops19:40:371
1084399630620,8cyclictest4793-21kerneloops23:10:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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