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2026-05-09 - 19:18
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat May 09, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2841399660657,1cyclictest4793-21kerneloops07:20:162
2840599636629,5cyclictest4793-21kerneloops10:09:071
2840599636627,7cyclictest4793-21kerneloops08:15:181
2842199635628,5cyclictest4793-21kerneloops08:21:433
2842199635627,6cyclictest4793-21kerneloops09:47:173
2842199635627,6cyclictest4793-21kerneloops09:47:173
2842199634625,7cyclictest4793-21kerneloops10:29:103
2840599634625,7cyclictest4793-21kerneloops12:31:061
2842199633628,4cyclictest4793-21kerneloops11:44:473
2842199633626,6cyclictest4793-21kerneloops10:35:133
2842199633625,6cyclictest4793-21kerneloops10:16:553
2840099633625,7cyclictest4793-21kerneloops07:47:030
2842199632625,5cyclictest4793-21kerneloops10:14:463
2840099632624,6cyclictest4793-21kerneloops08:25:370
2842199631628,2cyclictest4793-21kerneloops09:08:193
2842199631621,8cyclictest4793-21kerneloops08:04:013
2841399631624,6cyclictest4793-21kerneloops07:15:052
2842199630624,5cyclictest4793-21kerneloops08:45:203
2841399630623,6cyclictest4793-21kerneloops10:50:532
2840599630628,1cyclictest4793-21kerneloops10:00:571
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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