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2026-04-12 - 20:47
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Apr 12, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2169699632624,6cyclictest4793-21kerneloops09:32:053
2167599632623,7cyclictest4793-21kerneloops08:55:430
2169699631623,6cyclictest4793-21kerneloops07:41:143
2169199631624,5cyclictest4793-21kerneloops11:28:172
2169199631623,6cyclictest4793-21kerneloops12:00:032
2168099631624,5cyclictest4793-21kerneloops12:31:531
2167599631622,7cyclictest4793-21kerneloops10:41:360
2167599631621,8cyclictest4793-21kerneloops08:20:410
2168099630627,2cyclictest4793-21kerneloops09:44:371
2168099630627,2cyclictest4793-21kerneloops09:44:371
2168099630624,5cyclictest4793-21kerneloops10:03:501
2167599630624,4cyclictest4793-21kerneloops09:30:190
2167599630623,5cyclictest4793-21kerneloops12:08:480
2169699629627,1cyclictest4793-21kerneloops10:38:323
2169199629623,5cyclictest4793-21kerneloops09:27:462
2167599629621,6cyclictest4793-21kerneloops11:49:550
2167599629620,7cyclictest4793-21kerneloops10:19:130
2167599629620,7cyclictest4793-21kerneloops07:50:060
2169699628625,2cyclictest4793-21kerneloops08:08:093
2169699628625,2cyclictest4793-21kerneloops08:08:083
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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