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2026-05-31 - 11:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun May 31, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2653299652643,7cyclictest4793-21kerneloops21:58:553
2651599639629,8cyclictest4793-21kerneloops23:52:511
2653299637630,5cyclictest4793-21kerneloops23:21:263
2653299637629,6cyclictest4793-21kerneloops19:34:043
2651599635628,6cyclictest4793-21kerneloops21:18:391
2651199635626,7cyclictest4793-21kerneloops00:02:240
2651599634627,5cyclictest4793-21kerneloops23:14:481
2651599634627,5cyclictest4793-21kerneloops21:50:401
2651199634626,7cyclictest4793-21kerneloops19:31:460
2651199634624,8cyclictest4793-21kerneloops21:29:480
2653299633627,5cyclictest4793-21kerneloops23:29:353
2652699633625,6cyclictest4793-21kerneloops22:02:142
2651599633627,4cyclictest4793-21kerneloops20:59:041
2651599633627,4cyclictest4793-21kerneloops20:12:051
2651599633626,5cyclictest4793-21kerneloops19:21:171
2651599633626,5cyclictest4793-21kerneloops19:21:161
2651199633621,10cyclictest4793-21kerneloops23:09:590
2653299632626,5cyclictest4793-21kerneloops23:32:043
2653299632626,4cyclictest4793-21kerneloops19:29:293
2652699632626,5cyclictest4793-21kerneloops21:07:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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