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2026-05-07 - 06:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu May 07, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1463899659657,1cyclictest4793-21kerneloops23:50:183
1461699636626,8cyclictest4793-21kerneloops23:05:220
1462399635628,5cyclictest4793-21kerneloops00:29:581
1462399634626,6cyclictest4793-21kerneloops20:55:041
1462399634626,6cyclictest4793-21kerneloops19:26:081
1461699634627,5cyclictest4793-21kerneloops22:39:040
1461699634625,7cyclictest4793-21kerneloops21:48:170
1462399633625,6cyclictest4793-21kerneloops22:22:131
1462399633625,6cyclictest4793-21kerneloops21:05:321
1463899632624,6cyclictest4793-21kerneloops20:20:333
1462399632626,4cyclictest4793-21kerneloops20:19:201
1462399632626,4cyclictest4793-21kerneloops20:19:201
1462399632624,6cyclictest4793-21kerneloops00:38:481
1461699632622,8cyclictest4793-21kerneloops00:18:110
1463899631628,1cyclictest4793-21kerneloops21:24:473
1463199631623,6cyclictest4793-21kerneloops19:40:132
1463199630624,5cyclictest4793-21kerneloops19:21:262
1461699630623,5cyclictest4793-21kerneloops00:11:270
1461699630621,7cyclictest4793-21kerneloops21:42:480
1461699630621,7cyclictest4793-21kerneloops20:48:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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