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2026-03-17 - 07:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Mar 17, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
201799638632,4cyclictest4793-21kerneloops22:16:140
203899634627,5cyclictest4793-21kerneloops20:57:333
203899633625,6cyclictest4793-21kerneloops19:56:303
202799633626,5cyclictest4793-21kerneloops22:41:401
202799633626,5cyclictest4793-21kerneloops21:16:151
202799633626,5cyclictest4793-21kerneloops00:05:261
203899632629,1cyclictest4793-21kerneloops22:51:003
203899632626,5cyclictest4793-21kerneloops21:12:563
203899631626,4cyclictest4793-21kerneloops21:16:043
203899631624,6cyclictest4793-21kerneloops21:07:353
203199631623,6cyclictest4793-21kerneloops20:03:262
202799631623,6cyclictest4793-21kerneloops22:17:501
203899630624,4cyclictest4793-21kerneloops23:43:333
203899630622,6cyclictest4793-21kerneloops23:45:513
203199630623,5cyclictest4793-21kerneloops22:27:242
203199630622,6cyclictest4793-21kerneloops20:27:482
201799630623,6cyclictest4793-21kerneloops22:22:280
201799630621,7cyclictest4793-21kerneloops19:47:120
203899629627,1cyclictest4793-21kerneloops20:01:483
203899629622,5cyclictest4793-21kerneloops23:51:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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