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2026-01-23 - 21:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Jan 23, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1452199588580,6cyclictest4793-21kerneloops12:38:083
1451499587577,8cyclictest4793-21kerneloops12:01:172
1452199586577,7cyclictest4793-21kerneloops11:11:133
1450899585576,7cyclictest4793-21kerneloops10:43:341
1450899583577,5cyclictest4793-21kerneloops08:39:541
1450899583575,6cyclictest4793-21kerneloops11:10:081
1452199582576,5cyclictest4793-21kerneloops09:38:463
1452199582576,4cyclictest4793-21kerneloops08:44:093
1450899582574,6cyclictest4793-21kerneloops09:24:231
1452199581577,2cyclictest4793-21kerneloops08:45:543
1451499581575,5cyclictest4793-21kerneloops12:34:032
1451499581573,7cyclictest4793-21kerneloops11:21:012
1450899581572,7cyclictest4793-21kerneloops07:55:191
1450899581572,7cyclictest4793-21kerneloops07:55:191
1452199580571,7cyclictest4793-21kerneloops11:09:243
1451499580574,5cyclictest4793-21kerneloops09:38:132
1450899580577,2cyclictest4793-21kerneloops09:35:541
1450899580571,7cyclictest4793-21kerneloops12:30:101
1452199579573,5cyclictest4793-21kerneloops12:20:263
1452199579573,4cyclictest4793-21kerneloops07:20:423
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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