You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-17 - 20:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Feb 17, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1112599634627,6cyclictest4793-21kerneloops10:36:151
1111899633623,8cyclictest4793-21kerneloops09:18:090
1112599632624,6cyclictest4793-21kerneloops07:22:181
1111899632624,6cyclictest4793-21kerneloops12:17:120
1112599631624,5cyclictest4793-21kerneloops08:03:321
1113099630627,2cyclictest4793-21kerneloops10:38:002
1112599630625,4cyclictest4793-21kerneloops07:30:001
1112599630625,4cyclictest4793-21kerneloops07:29:591
1112599630624,5cyclictest4793-21kerneloops07:39:511
1112599630622,6cyclictest4793-21kerneloops09:43:511
1112599630621,7cyclictest4793-21kerneloops10:27:031
1111899630624,5cyclictest4793-21kerneloops11:16:560
1111899630623,5cyclictest4793-21kerneloops10:16:230
1111899630622,7cyclictest4793-21kerneloops07:26:370
1111899630622,7cyclictest4793-21kerneloops07:26:360
1113599629623,5cyclictest4793-21kerneloops07:44:183
1113099629622,6cyclictest4793-21kerneloops08:29:202
1113099629622,5cyclictest4793-21kerneloops07:47:422
1112599629626,2cyclictest4793-21kerneloops11:06:551
1112599629626,2cyclictest4793-21kerneloops09:46:261
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional