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2026-06-24 - 21:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Jun 24, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1506799676665,9cyclictest4793-21kerneloops12:15:160
1508999673663,8cyclictest4793-21kerneloops09:40:563
1506799664653,9cyclictest4793-21kerneloops10:21:460
1508999663655,6cyclictest4793-21kerneloops09:27:323
1507399663656,6cyclictest4793-21kerneloops12:25:541
1507399663656,6cyclictest4793-21kerneloops12:02:281
1506799663654,7cyclictest4793-21kerneloops10:55:530
1508999662654,6cyclictest4793-21kerneloops09:02:273
1508999662653,7cyclictest4793-21kerneloops09:46:393
1507399662655,5cyclictest4793-21kerneloops09:13:531
1506799662653,7cyclictest4793-21kerneloops10:45:180
1508999661655,5cyclictest4793-21kerneloops10:26:533
1508999661655,5cyclictest4793-21kerneloops08:10:523
1508999661655,5cyclictest4793-21kerneloops07:48:153
1508999661655,4cyclictest4793-21kerneloops07:53:403
1508999661654,5cyclictest4793-21kerneloops07:14:213
1508999661653,6cyclictest4793-21kerneloops08:40:353
1507399661656,4cyclictest4793-21kerneloops07:50:351
1508999660655,4cyclictest4793-21kerneloops09:08:543
1508999660654,5cyclictest4793-21kerneloops10:48:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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