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2026-01-19 - 16:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Jan 19, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889810930,1082rtkit-daemon4793-21kerneloops07:07:351
1401199592582,8cyclictest4793-21kerneloops10:01:443
1401199584576,6cyclictest4793-21kerneloops12:16:423
1401199584576,6cyclictest4793-21kerneloops09:35:593
1399999584577,5cyclictest4793-21kerneloops09:47:251
1399999584577,5cyclictest4793-21kerneloops09:19:431
1399099584573,9cyclictest4793-21kerneloops12:10:180
1399999583576,5cyclictest4793-21kerneloops12:38:581
1399999583576,5cyclictest4793-21kerneloops11:49:291
1399999583576,5cyclictest4793-21kerneloops09:13:091
1401199582575,5cyclictest4793-21kerneloops08:33:303
1399999582573,7cyclictest4793-21kerneloops07:19:511
1399099582578,2cyclictest4793-21kerneloops09:42:220
1399999581574,5cyclictest4793-21kerneloops11:30:421
1399999581572,7cyclictest4793-21kerneloops08:50:231
1401199580577,2cyclictest4793-21kerneloops09:52:483
1401199580572,7cyclictest4793-21kerneloops12:03:053
1401199580569,2cyclictest4793-21kerneloops09:12:263
1399099580573,6cyclictest4793-21kerneloops11:29:080
1401199579577,1cyclictest4793-21kerneloops11:05:043
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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