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2026-07-31 - 12:06
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri Jul 31, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1155999673663,8cyclictest4793-21kerneloops23:10:423
1154799664657,5cyclictest4793-21kerneloops21:26:091
1155999663655,6cyclictest4793-21kerneloops22:32:013
1155999663655,6cyclictest4793-21kerneloops20:08:533
1154799661654,6cyclictest4793-21kerneloops22:16:381
1154799661654,5cyclictest4793-21kerneloops21:39:551
1154199661651,8cyclictest4793-21kerneloops21:30:230
1155999660652,6cyclictest4793-21kerneloops21:47:423
1155999660650,8cyclictest4793-21kerneloops00:29:003
1155999659651,6cyclictest4793-21kerneloops23:22:273
1155999659647,10cyclictest4793-21kerneloops21:27:423
1154799659653,5cyclictest4793-21kerneloops21:04:361
1154799659652,5cyclictest4793-21kerneloops22:08:401
1155999658651,5cyclictest4793-21kerneloops23:45:493
1155999658651,5cyclictest4793-21kerneloops22:51:353
1155999658650,7cyclictest4793-21kerneloops20:11:143
1155499658652,2cyclictest4793-21kerneloops19:59:042
1155499658651,5cyclictest4793-21kerneloops23:14:142
1154799658652,5cyclictest4793-21kerneloops19:53:001
1154199658648,8cyclictest4793-21kerneloops23:28:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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