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2026-09-02 - 19:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Sep 02, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2246299665661,2cyclictest4793-21kerneloops12:06:202
2245799665655,8cyclictest4793-21kerneloops10:43:321
2247199663656,5cyclictest4793-21kerneloops08:21:303
2245099663655,7cyclictest4793-21kerneloops12:26:030
2247199662656,5cyclictest4793-21kerneloops07:15:403
2247199662653,7cyclictest4793-21kerneloops09:33:083
2245099662651,9cyclictest4793-21kerneloops11:05:230
2247199661653,6cyclictest4793-21kerneloops08:40:383
2247199661653,6cyclictest4793-21kerneloops08:40:383
2245799661653,6cyclictest4793-21kerneloops08:07:101
2245099661652,7cyclictest4793-21kerneloops12:13:440
2245099661651,8cyclictest4793-21kerneloops09:08:010
2247199660654,5cyclictest4793-21kerneloops12:05:263
2247199660653,5cyclictest4793-21kerneloops10:49:143
2247199660651,7cyclictest4793-21kerneloops10:02:123
2245799660657,2cyclictest4793-21kerneloops07:34:561
2245799660654,5cyclictest4793-21kerneloops08:25:561
2245799660653,5cyclictest4793-21kerneloops08:39:331
2245799660650,8cyclictest4793-21kerneloops10:21:501
2245099660653,6cyclictest4793-21kerneloops09:48:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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