You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-04-19 - 20:55
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Apr 19, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2322599634626,6cyclictest4793-21kerneloops09:49:213
2321199634628,5cyclictest4793-21kerneloops10:24:141
2322599633623,8cyclictest4793-21kerneloops10:43:213
2322599632625,6cyclictest4793-21kerneloops12:25:283
2322599631623,6cyclictest4793-21kerneloops12:23:233
2322599631622,8cyclictest4793-21kerneloops10:32:233
2322099631624,6cyclictest4793-21kerneloops11:10:292
2321199631628,2cyclictest4793-21kerneloops07:53:311
2321199631624,5cyclictest4793-21kerneloops07:41:361
2320799631624,5cyclictest4793-21kerneloops09:26:530
2320799631621,8cyclictest4793-21kerneloops11:11:230
2321199630627,2cyclictest4793-21kerneloops08:18:131
2320799630622,6cyclictest4793-21kerneloops11:20:440
2322599629624,4cyclictest4793-21kerneloops08:38:023
2322099629626,2cyclictest4793-21kerneloops11:15:582
2322099629624,4cyclictest4793-21kerneloops12:17:262
2321199629623,4cyclictest4793-21kerneloops09:14:261
2322599628625,2cyclictest4793-21kerneloops07:12:433
2322599628625,1cyclictest4793-21kerneloops08:33:033
2322099628625,2cyclictest4793-21kerneloops12:39:352
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional