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2026-05-27 - 09:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed May 27, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
309199651641,8cyclictest4793-21kerneloops21:28:080
311399646642,2cyclictest4793-21kerneloops23:45:193
311399637629,6cyclictest4793-21kerneloops21:57:053
310199635626,7cyclictest4793-21kerneloops23:06:421
310899634626,7cyclictest4793-21kerneloops21:38:432
310199634627,5cyclictest4793-21kerneloops22:29:341
311399633626,5cyclictest4793-21kerneloops20:41:423
310199633626,6cyclictest4793-21kerneloops22:22:181
310199633624,7cyclictest4793-21kerneloops19:59:281
310899632626,5cyclictest4793-21kerneloops21:09:582
310899632623,7cyclictest4793-21kerneloops00:39:012
310199632626,4cyclictest4793-21kerneloops23:26:001
310199632625,5cyclictest4793-21kerneloops23:40:091
310199632624,6cyclictest4793-21kerneloops21:47:121
311399631628,2cyclictest4793-21kerneloops23:17:093
310899631626,4cyclictest4793-21kerneloops22:18:572
310899631625,5cyclictest4793-21kerneloops22:41:592
310899631625,5cyclictest4793-21kerneloops21:52:542
310899631625,5cyclictest4793-21kerneloops00:13:572
310899631624,5cyclictest4793-21kerneloops21:57:482
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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