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2026-04-23 - 11:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Apr 23, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
930199648638,8cyclictest4793-21kerneloops22:06:311
929499644634,8cyclictest4793-21kerneloops00:28:120
930199639630,7cyclictest4793-21kerneloops23:05:021
930199639630,7cyclictest4793-21kerneloops23:05:021
930199636629,5cyclictest4793-21kerneloops22:17:331
930199634629,4cyclictest4793-21kerneloops00:13:021
930199634627,5cyclictest4793-21kerneloops22:11:521
931699633626,5cyclictest4793-21kerneloops00:37:343
930999633624,7cyclictest4793-21kerneloops00:00:172
930999632624,7cyclictest4793-21kerneloops23:29:372
930999632623,7cyclictest4793-21kerneloops19:55:192
930199632626,5cyclictest4793-21kerneloops20:57:331
931699631627,2cyclictest4793-21kerneloops23:40:093
930199631628,1cyclictest4793-21kerneloops21:14:241
930199631624,5cyclictest4793-21kerneloops21:31:051
930199631623,6cyclictest4793-21kerneloops23:40:511
929499631624,6cyclictest4793-21kerneloops22:35:580
931699630623,6cyclictest4793-21kerneloops22:35:473
931699630623,5cyclictest4793-21kerneloops23:45:303
930999630623,5cyclictest4793-21kerneloops19:54:052
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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