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2026-05-01 - 06:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri May 01, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1781699640629,9cyclictest4793-21kerneloops19:17:330
1783799635627,6cyclictest4793-21kerneloops21:50:583
1782399635627,6cyclictest4793-21kerneloops23:11:441
1781699635626,7cyclictest4793-21kerneloops21:33:560
1782899633625,7cyclictest4793-21kerneloops20:25:382
1781699633621,10cyclictest4793-21kerneloops21:15:270
1783799632625,5cyclictest4793-21kerneloops20:20:033
1783799631628,2cyclictest4793-21kerneloops21:23:163
1783799631624,5cyclictest4793-21kerneloops19:36:083
1782899631625,5cyclictest4793-21kerneloops20:39:482
1782899631622,7cyclictest4793-21kerneloops20:49:352
1782399631627,2cyclictest4793-21kerneloops21:44:371
1782399631626,4cyclictest4793-21kerneloops23:22:541
1782399631624,5cyclictest4793-21kerneloops22:55:591
1782399631623,6cyclictest4793-21kerneloops21:28:361
1781699631624,5cyclictest4793-21kerneloops22:58:270
1783799630627,2cyclictest4793-21kerneloops22:14:433
1783799630627,1cyclictest4793-21kerneloops00:32:113
1782899630624,5cyclictest4793-21kerneloops23:49:122
1782899630624,5cyclictest4793-21kerneloops22:34:402
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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