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2026-06-21 - 21:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Jun 21, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1951299663655,6cyclictest4793-21kerneloops09:30:183
1949799663656,5cyclictest4793-21kerneloops12:06:021
1951299662655,6cyclictest4793-21kerneloops08:08:033
1951299662654,6cyclictest4793-21kerneloops10:51:373
1949799662656,5cyclictest4793-21kerneloops08:04:571
1949799662653,7cyclictest4793-21kerneloops10:23:181
1951299661653,6cyclictest4793-21kerneloops08:30:493
1951299661653,6cyclictest4793-21kerneloops07:45:423
1949199661653,6cyclictest4793-21kerneloops07:23:330
1951299660653,5cyclictest4793-21kerneloops11:18:043
1951299660652,6cyclictest4793-21kerneloops12:11:543
1949799660653,5cyclictest4793-21kerneloops07:18:291
1949199660651,8cyclictest4793-21kerneloops12:00:570
1951299659657,1cyclictest4793-21kerneloops11:55:473
1951299659656,1cyclictest4793-21kerneloops12:36:073
1949799659651,6cyclictest4793-21kerneloops11:21:341
1949799659651,6cyclictest4793-21kerneloops08:14:191
1949199659652,5cyclictest4793-21kerneloops11:55:270
1949199659650,7cyclictest4793-21kerneloops10:58:530
1951299658655,1cyclictest4793-21kerneloops11:24:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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