You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-28 - 10:07
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Jul 28, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
261799665657,6cyclictest4793-21kerneloops20:24:181
261799664657,5cyclictest4793-21kerneloops22:40:051
261799664657,5cyclictest4793-21kerneloops19:19:331
261799663657,5cyclictest4793-21kerneloops21:09:361
261799663656,6cyclictest4793-21kerneloops20:06:451
261799662655,5cyclictest4793-21kerneloops22:35:021
261799662655,5cyclictest4793-21kerneloops21:22:231
263099661655,5cyclictest4793-21kerneloops19:11:083
261799661655,5cyclictest4793-21kerneloops22:48:361
261799661653,6cyclictest4793-21kerneloops23:19:381
261199661653,6cyclictest4793-21kerneloops23:26:340
261199661653,6cyclictest4793-21kerneloops22:32:150
261199661652,7cyclictest4793-21kerneloops21:00:020
263099660657,2cyclictest4793-21kerneloops22:04:183
263099660653,6cyclictest4793-21kerneloops21:02:563
263099660653,5cyclictest4793-21kerneloops22:35:243
262199660653,5cyclictest4793-21kerneloops20:21:182
262199660653,5cyclictest4793-21kerneloops19:27:262
261799660653,5cyclictest4793-21kerneloops22:00:321
261199660652,6cyclictest4793-21kerneloops22:29:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional