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2026-05-21 - 01:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed May 20, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
214699649639,8cyclictest4793-21kerneloops12:21:092
214699648644,2cyclictest4793-21kerneloops10:34:462
213399642638,2cyclictest4793-21kerneloops11:33:320
213999636628,6cyclictest4793-21kerneloops11:15:281
215499635627,6cyclictest4793-21kerneloops08:56:423
215499634626,6cyclictest4793-21kerneloops11:57:123
215499634626,6cyclictest4793-21kerneloops10:02:353
213999634625,7cyclictest4793-21kerneloops07:10:241
215499633624,7cyclictest4793-21kerneloops09:21:573
213399633623,8cyclictest4793-21kerneloops12:29:460
213999632626,5cyclictest4793-21kerneloops12:35:451
213399632624,7cyclictest4793-21kerneloops09:59:090
213399632623,8cyclictest4793-21kerneloops07:18:350
215499631628,2cyclictest4793-21kerneloops11:45:473
215499631625,4cyclictest4793-21kerneloops11:31:233
215499631624,5cyclictest4793-21kerneloops08:22:043
215499631621,8cyclictest4793-21kerneloops09:58:273
214699631625,5cyclictest4793-21kerneloops09:51:132
213999631622,7cyclictest4793-21kerneloops11:04:561
215499630624,4cyclictest4793-21kerneloops07:23:473
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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