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2025-12-10 - 09:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Dec 10, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2066499798790,6cyclictest4927-21kerneloops20:35:111
2067699797789,6cyclictest4927-21kerneloops20:26:173
2067099797789,6cyclictest4927-21kerneloops00:11:512
2066499797790,6cyclictest4927-21kerneloops23:51:221
2065899797785,10cyclictest4927-21kerneloops22:11:530
2065899797785,10cyclictest4927-21kerneloops22:11:530
2067699796788,6cyclictest4927-21kerneloops00:39:143
2067099796787,7cyclictest4927-21kerneloops20:32:192
2067699795791,2cyclictest4927-21kerneloops00:13:243
2067699795788,6cyclictest4927-21kerneloops21:04:063
2067699794787,5cyclictest4927-21kerneloops21:06:173
2066499794791,2cyclictest4927-21kerneloops22:04:361
2066499794787,5cyclictest4927-21kerneloops23:47:161
2066499794787,5cyclictest4927-21kerneloops20:16:201
2067699793790,2cyclictest4927-21kerneloops21:40:333
2067699793786,6cyclictest4927-21kerneloops21:55:293
2067699793785,6cyclictest4927-21kerneloops20:12:153
2067699793784,7cyclictest4927-21kerneloops21:23:413
2067699792786,4cyclictest4927-21kerneloops23:08:543
2067699792785,5cyclictest4927-21kerneloops19:17:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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