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2026-05-25 - 20:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon May 25, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1837099647634,11cyclictest4793-21kerneloops09:26:100
1838799639630,7cyclictest4793-21kerneloops11:35:293
1838799635627,6cyclictest4793-21kerneloops07:23:063
1837599634628,5cyclictest4793-21kerneloops11:11:271
1837599634627,6cyclictest4793-21kerneloops07:36:431
1837599634627,6cyclictest4793-21kerneloops07:36:431
1838799633623,8cyclictest4793-21kerneloops12:29:503
1838799633623,8cyclictest4793-21kerneloops12:29:503
1838199633624,7cyclictest4793-21kerneloops09:49:552
1837099633623,8cyclictest4793-21kerneloops10:37:040
1838799632628,2cyclictest4793-21kerneloops08:46:353
1838799631625,5cyclictest4793-21kerneloops11:32:363
1838199631625,4cyclictest4793-21kerneloops08:39:042
1837599631626,4cyclictest4793-21kerneloops10:13:041
1838799630627,2cyclictest4793-21kerneloops07:33:513
1837599630622,6cyclictest4793-21kerneloops12:08:291
1837599630621,7cyclictest4793-21kerneloops09:13:571
1837599630621,7cyclictest4793-21kerneloops09:13:561
1838799629627,1cyclictest4793-21kerneloops09:46:543
1838799629622,5cyclictest4793-21kerneloops11:05:043
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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