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2026-01-21 - 07:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Jan 21, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1982699582576,5cyclictest4793-21kerneloops22:30:393
1982699582573,7cyclictest4793-21kerneloops00:28:183
1980999582576,5cyclictest4793-21kerneloops23:27:021
1981899581572,7cyclictest4793-21kerneloops00:09:562
1980999581575,5cyclictest4793-21kerneloops19:24:421
1980599581572,7cyclictest4793-21kerneloops23:59:420
1981899580571,7cyclictest4793-21kerneloops23:07:292
1982699579571,6cyclictest4793-21kerneloops22:41:523
1981899579573,5cyclictest4793-21kerneloops20:32:382
1981899579573,4cyclictest4793-21kerneloops19:45:072
1981899579572,5cyclictest4793-21kerneloops23:28:582
1980999579571,6cyclictest4793-21kerneloops23:45:091
1980999579571,5cyclictest4793-21kerneloops23:23:011
1980599579571,7cyclictest4793-21kerneloops19:31:180
1982699578575,2cyclictest4793-21kerneloops20:17:073
1982699578570,6cyclictest4793-21kerneloops22:13:433
1980999578574,3cyclictest4793-21kerneloops21:35:531
1980999578572,5cyclictest4793-21kerneloops19:26:161
1980599578571,5cyclictest4793-21kerneloops22:16:330
1982699577572,4cyclictest4793-21kerneloops21:47:243
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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