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2026-05-17 - 22:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun May 17, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3088099635629,5cyclictest4793-21kerneloops10:55:271
3088099635626,7cyclictest4793-21kerneloops07:10:471
3087599635626,7cyclictest4793-21kerneloops08:10:350
3088099634628,5cyclictest4793-21kerneloops09:27:391
3088099634627,6cyclictest4793-21kerneloops09:06:591
3088099633627,5cyclictest4793-21kerneloops12:27:561
3088099633627,5cyclictest4793-21kerneloops08:53:511
3088099632625,6cyclictest4793-21kerneloops10:08:551
3089699631625,5cyclictest4793-21kerneloops10:29:493
3089699631625,4cyclictest4793-21kerneloops11:31:173
3088099631627,2cyclictest4793-21kerneloops10:40:161
3088099631625,5cyclictest4793-21kerneloops09:01:181
3088099631625,4cyclictest4793-21kerneloops07:34:521
3089699630624,5cyclictest4793-21kerneloops11:04:153
3089699630623,5cyclictest4793-21kerneloops08:34:073
3089699630623,5cyclictest4793-21kerneloops07:25:463
3089699630623,5cyclictest4793-21kerneloops07:25:453
3088799630624,4cyclictest4793-21kerneloops10:15:192
3088099630627,2cyclictest4793-21kerneloops08:47:041
3088099630627,2cyclictest4793-21kerneloops08:18:131
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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