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2025-11-20 - 04:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Nov 20, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1616399799791,6cyclictest4927-21kerneloops22:59:223
1614899799792,5cyclictest4927-21kerneloops20:58:061
1616399798792,4cyclictest4927-21kerneloops21:30:513
1614899798791,5cyclictest4927-21kerneloops20:48:201
1616399797789,6cyclictest4927-21kerneloops20:33:463
1614899797790,5cyclictest4927-21kerneloops20:42:281
1616399796790,4cyclictest4927-21kerneloops21:25:453
1616399796788,6cyclictest4927-21kerneloops19:35:053
1615599796788,7cyclictest4927-21kerneloops00:19:442
1614899796790,4cyclictest4927-21kerneloops21:25:571
1614899796790,4cyclictest4927-21kerneloops20:22:131
1616399795789,5cyclictest4927-21kerneloops23:09:423
1616399795789,5cyclictest4927-21kerneloops21:23:463
1614299795782,11cyclictest4927-21kerneloops00:34:400
1616399794787,5cyclictest4927-21kerneloops00:22:113
1614299794786,7cyclictest4927-21kerneloops22:04:570
1614299794786,6cyclictest4927-21kerneloops21:57:500
1614299794786,6cyclictest4927-21kerneloops21:23:260
1616399793791,1cyclictest4927-21kerneloops21:12:153
1616399793789,2cyclictest4927-21kerneloops22:34:593
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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