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2026-05-04 - 06:17
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon May 04, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2399999636629,5cyclictest4793-21kerneloops20:48:381
2401699635626,7cyclictest4793-21kerneloops19:45:453
2400899635626,7cyclictest4793-21kerneloops23:54:272
2401699634627,6cyclictest4793-21kerneloops22:56:063
2400899634624,8cyclictest4793-21kerneloops22:32:562
2399999634628,5cyclictest4793-21kerneloops20:17:291
2401699633627,5cyclictest4793-21kerneloops20:26:483
2401699633627,4cyclictest4793-21kerneloops23:54:383
2401699633624,7cyclictest4793-21kerneloops23:41:533
2400899633625,6cyclictest4793-21kerneloops22:44:392
2399999633628,4cyclictest4793-21kerneloops19:20:461
2399999632626,5cyclictest4793-21kerneloops23:39:331
2399599632625,5cyclictest4793-21kerneloops22:27:550
2401699631625,4cyclictest4793-21kerneloops23:27:443
2401699631624,5cyclictest4793-21kerneloops20:20:113
2401699631623,6cyclictest4793-21kerneloops19:54:243
2399599631622,7cyclictest4793-21kerneloops21:21:350
2401699630627,2cyclictest4793-21kerneloops00:02:563
2399999630627,2cyclictest4793-21kerneloops19:12:531
2399999630624,5cyclictest4793-21kerneloops21:53:501
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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