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2026-05-20 - 00:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue May 19, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2266499636626,8cyclictest4793-21kerneloops11:27:130
2268199634627,6cyclictest4793-21kerneloops11:17:233
2268199633626,6cyclictest4793-21kerneloops10:07:563
2268199633625,6cyclictest4793-21kerneloops08:21:533
2268199632626,5cyclictest4793-21kerneloops10:52:453
2268199632625,6cyclictest4793-21kerneloops09:04:283
2266899632625,6cyclictest4793-21kerneloops09:17:011
2266899631628,2cyclictest4793-21kerneloops12:39:381
2266499631624,6cyclictest4793-21kerneloops11:12:440
2267599630622,6cyclictest4793-21kerneloops10:33:562
2266899630627,2cyclictest4793-21kerneloops12:16:291
2266899630622,6cyclictest4793-21kerneloops10:56:181
2266499630623,5cyclictest4793-21kerneloops08:19:250
2266499630622,7cyclictest4793-21kerneloops08:09:510
2268199629622,6cyclictest4793-21kerneloops08:51:373
2266899629626,1cyclictest4793-21kerneloops07:43:181
2266899629621,6cyclictest4793-21kerneloops11:19:321
2266499629621,6cyclictest4793-21kerneloops09:03:220
2268199628622,4cyclictest4793-21kerneloops11:20:483
2267599628622,4cyclictest4793-21kerneloops11:15:472
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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