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2026-02-14 - 13:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Feb 14, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3046999634627,5cyclictest4793-21kerneloops23:57:501
3046999634625,7cyclictest4793-21kerneloops00:18:111
3048599632625,5cyclictest4793-21kerneloops21:19:443
3046999632625,5cyclictest4793-21kerneloops23:54:071
3048599631627,2cyclictest4793-21kerneloops21:51:033
3046999631624,5cyclictest4793-21kerneloops20:34:561
3048599630625,4cyclictest4793-21kerneloops23:55:523
3048599630625,4cyclictest4793-21kerneloops19:51:153
3046999630624,5cyclictest4793-21kerneloops00:03:361
3048599629624,4cyclictest4793-21kerneloops21:04:163
3048599629622,5cyclictest4793-21kerneloops22:53:593
3046999629623,5cyclictest4793-21kerneloops20:10:371
3046999629623,4cyclictest4793-21kerneloops20:26:021
3046999629622,5cyclictest4793-21kerneloops22:32:421
3046999629620,7cyclictest4793-21kerneloops00:11:361
3046499629619,8cyclictest4793-21kerneloops21:00:100
3048599627620,5cyclictest4793-21kerneloops23:15:273
3047899627622,4cyclictest4793-21kerneloops19:10:102
3046999627621,5cyclictest4793-21kerneloops21:44:571
3046999627621,4cyclictest4793-21kerneloops23:26:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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