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2026-07-22 - 08:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Jul 22, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2557499692684,6cyclictest4793-21kerneloops21:41:143
2556299665657,7cyclictest4793-21kerneloops23:34:161
2557499663655,7cyclictest4793-21kerneloops22:06:183
2557499663655,6cyclictest4793-21kerneloops20:40:183
2555399662655,6cyclictest4793-21kerneloops00:27:410
2556999660653,5cyclictest4793-21kerneloops19:45:032
2556299660653,5cyclictest4793-21kerneloops00:24:111
2556299660652,6cyclictest4793-21kerneloops20:12:351
2557499659653,4cyclictest4793-21kerneloops20:59:443
2556999659652,5cyclictest4793-21kerneloops19:11:122
2556299659653,5cyclictest4793-21kerneloops21:12:001
2556299659653,4cyclictest4793-21kerneloops22:23:411
2555399659652,6cyclictest4793-21kerneloops22:37:010
2557499658655,2cyclictest4793-21kerneloops23:29:493
2556999658655,2cyclictest4793-21kerneloops20:03:192
2556999658652,5cyclictest4793-21kerneloops22:24:532
2557499657650,5cyclictest4793-21kerneloops19:11:443
2556999657651,5cyclictest4793-21kerneloops20:13:072
2556999657651,5cyclictest4793-21kerneloops00:09:382
2556999657651,4cyclictest4793-21kerneloops22:15:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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