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2026-03-26 - 17:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Mar 26, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3100699634625,7cyclictest4793-21kerneloops11:45:541
3099899634622,10cyclictest4793-21kerneloops10:19:280
3101899633626,5cyclictest4793-21kerneloops09:24:073
3101899632626,5cyclictest4793-21kerneloops12:23:553
3101899632626,5cyclictest4793-21kerneloops12:14:183
3101899632625,5cyclictest4793-21kerneloops10:45:263
3100699632626,5cyclictest4793-21kerneloops11:07:271
3100699632625,5cyclictest4793-21kerneloops10:12:491
3100699632624,6cyclictest4793-21kerneloops11:42:071
3100699632624,6cyclictest4793-21kerneloops09:14:201
3099899632624,6cyclictest4793-21kerneloops08:41:590
3101399631624,5cyclictest4793-21kerneloops08:03:332
3099899631622,7cyclictest4793-21kerneloops09:31:470
3101899630621,7cyclictest4793-21kerneloops11:21:153
3101899629623,4cyclictest4793-21kerneloops12:05:363
3101899628626,1cyclictest4793-21kerneloops09:41:413
3101899628626,1cyclictest4793-21kerneloops09:31:353
3101899628624,2cyclictest4793-21kerneloops10:05:453
3101899628618,8cyclictest4793-21kerneloops09:38:403
3100699628623,4cyclictest4793-21kerneloops11:57:351
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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