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2026-02-18 - 09:45
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Feb 18, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1240199637634,1cyclictest4793-21kerneloops21:43:350
1240199636624,11cyclictest4793-21kerneloops23:02:090
1240799635628,6cyclictest4793-21kerneloops23:06:321
1240799634625,7cyclictest4793-21kerneloops21:50:181
1240799634625,7cyclictest4793-21kerneloops21:50:181
1242199633624,7cyclictest4793-21kerneloops00:04:063
1242199632625,6cyclictest4793-21kerneloops19:28:173
1242199632625,5cyclictest4793-21kerneloops21:48:413
1240199632623,7cyclictest4793-21kerneloops21:55:470
1242199631626,4cyclictest4793-21kerneloops20:29:083
1242199631626,4cyclictest4793-21kerneloops19:44:173
1242199631625,5cyclictest4793-21kerneloops20:01:483
1242199631625,5cyclictest4793-21kerneloops00:16:483
1242199631624,5cyclictest4793-21kerneloops20:56:363
1242199631623,6cyclictest4793-21kerneloops19:13:303
1240799631626,4cyclictest4793-21kerneloops23:51:471
1242199630627,2cyclictest4793-21kerneloops21:54:433
1242199630627,2cyclictest4793-21kerneloops21:54:433
1242199630623,5cyclictest4793-21kerneloops23:34:463
1242199630623,5cyclictest4793-21kerneloops23:34:463
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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