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2026-02-22 - 12:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Feb 22, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3239999635625,8cyclictest4793-21kerneloops22:07:393
3239999634627,5cyclictest4793-21kerneloops20:55:353
3239999634627,5cyclictest4793-21kerneloops19:41:313
3239999633627,4cyclictest4793-21kerneloops19:17:163
3238499633626,5cyclictest4793-21kerneloops23:40:191
3238499633624,7cyclictest4793-21kerneloops23:51:411
3238499632626,4cyclictest4793-21kerneloops21:00:341
3238499632624,7cyclictest4793-21kerneloops20:29:251
3237899632623,7cyclictest4793-21kerneloops20:58:060
3237899632622,8cyclictest4793-21kerneloops00:36:310
3239999631625,4cyclictest4793-21kerneloops19:24:153
3239999631623,6cyclictest4793-21kerneloops23:57:593
3238499631624,5cyclictest4793-21kerneloops22:19:261
3238499631624,5cyclictest4793-21kerneloops19:42:481
3238499631623,6cyclictest4793-21kerneloops23:16:471
3238499631622,7cyclictest4793-21kerneloops20:45:501
3239999630624,5cyclictest4793-21kerneloops00:17:013
3239999629623,4cyclictest4793-21kerneloops20:48:193
3239999629621,6cyclictest4793-21kerneloops23:02:213
3238499629626,2cyclictest4793-21kerneloops21:54:401
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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