You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-05-24 - 05:56
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun May 24, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811660,1155rtkit-daemon4793-21kerneloops19:09:021
1044599647637,8cyclictest4793-21kerneloops22:51:302
1043699635627,6cyclictest4793-21kerneloops23:28:011
1043699635626,7cyclictest4793-21kerneloops22:03:091
1043199635623,10cyclictest4793-21kerneloops22:55:330
1045299634628,5cyclictest4793-21kerneloops22:46:343
1045299634626,7cyclictest4793-21kerneloops21:20:493
1045299634626,6cyclictest4793-21kerneloops21:00:373
1045299633627,5cyclictest4793-21kerneloops19:22:573
1045299633626,6cyclictest4793-21kerneloops23:53:593
1045299633626,5cyclictest4793-21kerneloops20:34:163
1043699633627,4cyclictest4793-21kerneloops20:45:451
1043699633625,6cyclictest4793-21kerneloops22:07:491
1043699633625,6cyclictest4793-21kerneloops22:07:491
1043699633620,11cyclictest4793-21kerneloops19:31:141
1043199633621,10cyclictest4793-21kerneloops23:18:270
1045299632623,2cyclictest4793-21kerneloops22:33:523
1043199632622,8cyclictest4793-21kerneloops23:05:100
1045299631626,4cyclictest4793-21kerneloops23:34:423
1045299631624,6cyclictest4793-21kerneloops23:17:253
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional