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2026-09-08 - 22:01
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Sep 08, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2932899669665,2cyclictest4793-21kerneloops09:43:123
2931499667663,2cyclictest4793-21kerneloops12:12:201
2932899666662,2cyclictest4793-21kerneloops10:55:053
2931499665657,6cyclictest4793-21kerneloops07:40:021
2931499663657,5cyclictest4793-21kerneloops09:39:091
2931499663656,5cyclictest4793-21kerneloops08:41:211
2930799663653,8cyclictest4793-21kerneloops11:52:130
2932899662656,4cyclictest4793-21kerneloops08:23:323
2932899662655,5cyclictest4793-21kerneloops08:38:333
2931499662656,4cyclictest4793-21kerneloops12:03:331
2931499662656,4cyclictest4793-21kerneloops12:03:321
2931499662656,4cyclictest4793-21kerneloops08:50:401
2932899661652,7cyclictest4793-21kerneloops12:17:223
2931499661658,2cyclictest4793-21kerneloops08:31:051
2930799661653,6cyclictest4793-21kerneloops08:25:320
2932899660657,2cyclictest4793-21kerneloops11:06:203
2932899660656,2cyclictest4793-21kerneloops07:39:523
2932899660654,5cyclictest4793-21kerneloops12:38:373
2932099660654,4cyclictest4793-21kerneloops09:12:302
2931499660656,2cyclictest4793-21kerneloops11:51:391
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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