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2026-08-06 - 12:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Aug 06, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1307999683680,1cyclictest4793-21kerneloops00:03:482
1307399667654,11cyclictest4793-21kerneloops20:03:511
1308699666661,3cyclictest4793-21kerneloops00:10:543
1308699665658,6cyclictest4793-21kerneloops23:46:063
1307399664657,6cyclictest4793-21kerneloops19:30:581
1308699663654,7cyclictest4793-21kerneloops22:16:393
1307999663655,6cyclictest4793-21kerneloops00:28:182
1308699662655,5cyclictest4793-21kerneloops23:36:223
1308699662655,5cyclictest4793-21kerneloops00:00:023
1307399662657,4cyclictest4793-21kerneloops19:22:151
1307399662656,4cyclictest4793-21kerneloops20:44:411
1306599662654,7cyclictest4793-21kerneloops22:40:450
1306599662652,8cyclictest4793-21kerneloops22:11:210
1308699661655,5cyclictest4793-21kerneloops19:11:343
1307399661654,5cyclictest4793-21kerneloops20:16:331
1306599661654,6cyclictest4793-21kerneloops19:31:490
1306599661653,6cyclictest4793-21kerneloops20:07:370
1308699660655,4cyclictest4793-21kerneloops21:12:363
1308699660654,5cyclictest4793-21kerneloops22:56:033
1308699660653,6cyclictest4793-21kerneloops00:26:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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