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2026-09-15 - 00:34
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Sep 14, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889813090,1295rtkit-daemon4793-21kerneloops07:07:043
2531199664657,6cyclictest4793-21kerneloops08:23:551
2531199664656,6cyclictest4793-21kerneloops09:04:401
2532699663655,6cyclictest4793-21kerneloops08:40:583
2531199663655,6cyclictest4793-21kerneloops08:35:211
2530499663650,11cyclictest4793-21kerneloops10:29:490
2532699662654,6cyclictest4793-21kerneloops12:26:183
2532699661654,6cyclictest4793-21kerneloops12:03:333
2532699661654,6cyclictest4793-21kerneloops11:33:123
2531199661655,5cyclictest4793-21kerneloops12:28:131
2531199661654,5cyclictest4793-21kerneloops11:33:021
2531199661653,7cyclictest4793-21kerneloops11:11:101
2532699660653,5cyclictest4793-21kerneloops10:43:063
2531799660654,4cyclictest4793-21kerneloops09:31:002
2531199660657,1cyclictest4793-21kerneloops08:45:081
2531799659651,6cyclictest4793-21kerneloops11:42:552
2531199659652,5cyclictest4793-21kerneloops11:42:261
2531199659651,6cyclictest4793-21kerneloops10:03:581
2532699658654,2cyclictest4793-21kerneloops09:34:093
2532699658652,4cyclictest4793-21kerneloops09:58:363
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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