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2026-05-28 - 11:00
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu May 28, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2545699641637,2cyclictest4793-21kerneloops22:33:142
2544199638627,9cyclictest4793-21kerneloops21:49:000
2544199637626,9cyclictest4793-21kerneloops00:03:490
2544899636627,7cyclictest4793-21kerneloops00:27:101
2546199634628,5cyclictest4793-21kerneloops23:55:533
2546199634627,6cyclictest4793-21kerneloops21:21:103
2546199634627,5cyclictest4793-21kerneloops22:51:303
2544899634628,5cyclictest4793-21kerneloops20:16:481
2544899634627,5cyclictest4793-21kerneloops22:58:441
2544199634630,2cyclictest4793-21kerneloops22:29:130
2546199633625,6cyclictest4793-21kerneloops21:58:303
2546199633624,7cyclictest4793-21kerneloops22:06:373
2546199632626,5cyclictest4793-21kerneloops20:37:533
2546199632625,5cyclictest4793-21kerneloops21:19:463
2544899632628,2cyclictest4793-21kerneloops20:32:421
2544899632626,5cyclictest4793-21kerneloops00:00:281
2544899632626,4cyclictest4793-21kerneloops23:33:211
2546199631627,2cyclictest4793-21kerneloops19:31:513
2545699631624,5cyclictest4793-21kerneloops20:33:462
2544899631627,2cyclictest4793-21kerneloops20:35:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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