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2026-02-04 - 14:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Feb 04, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
359299599585,12cyclictest4793-21kerneloops12:30:100
359299591579,10cyclictest4793-21kerneloops12:36:220
360599590580,8cyclictest4793-21kerneloops12:24:062
361299589580,7cyclictest4793-21kerneloops12:38:173
361299588582,4cyclictest4793-21kerneloops09:41:233
359999588581,5cyclictest4793-21kerneloops07:46:521
359999588581,5cyclictest4793-21kerneloops07:19:161
361299587580,5cyclictest4793-21kerneloops12:01:183
361299587580,5cyclictest4793-21kerneloops09:28:463
361299587578,7cyclictest4793-21kerneloops08:01:243
361299586581,4cyclictest4793-21kerneloops09:54:563
359999586580,4cyclictest4793-21kerneloops10:44:231
359999586579,6cyclictest4793-21kerneloops09:42:071
361299585577,6cyclictest4793-21kerneloops10:47:093
361299585576,7cyclictest4793-21kerneloops11:02:463
359299585577,6cyclictest4793-21kerneloops11:39:010
361299584576,6cyclictest4793-21kerneloops10:35:033
361299583580,2cyclictest4793-21kerneloops08:49:303
361299583577,5cyclictest4793-21kerneloops09:30:573
361299583577,4cyclictest4793-21kerneloops11:26:263
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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