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2026-05-22 - 02:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Fri May 22, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1093899649646,2cyclictest4793-21kerneloops00:35:182
1093299646637,7cyclictest4793-21kerneloops00:12:291
1093299638631,5cyclictest4793-21kerneloops23:08:561
1094599636627,7cyclictest4793-21kerneloops22:59:473
1093299635628,5cyclictest4793-21kerneloops21:40:101
1093299634627,5cyclictest4793-21kerneloops22:13:011
1092499633621,10cyclictest4793-21kerneloops23:38:030
1093899632625,5cyclictest4793-21kerneloops19:21:032
1093899632624,7cyclictest4793-21kerneloops22:46:152
1093299632626,5cyclictest4793-21kerneloops00:07:441
1092499632625,5cyclictest4793-21kerneloops22:09:440
1092499632622,8cyclictest4793-21kerneloops23:19:560
1094599631626,4cyclictest4793-21kerneloops21:15:343
1094599631625,5cyclictest4793-21kerneloops20:25:233
1094599631625,4cyclictest4793-21kerneloops23:30:353
1094599631624,5cyclictest4793-21kerneloops00:15:413
1093899631622,7cyclictest4793-21kerneloops23:55:552
1093299631625,4cyclictest4793-21kerneloops20:52:531
1092499631625,4cyclictest4793-21kerneloops00:01:560
1094599630627,2cyclictest4793-21kerneloops21:07:533
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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