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2026-04-22 - 21:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Apr 22, 2026 12:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
542299638630,6cyclictest4793-21kerneloops10:58:142
542899633627,5cyclictest4793-21kerneloops09:19:153
541699633627,5cyclictest4793-21kerneloops07:22:081
541699633624,7cyclictest4793-21kerneloops12:18:361
541699633624,7cyclictest4793-21kerneloops12:18:361
540799633625,6cyclictest4793-21kerneloops11:12:080
541699632624,6cyclictest4793-21kerneloops10:14:571
540799632625,5cyclictest4793-21kerneloops07:53:110
540799632623,7cyclictest4793-21kerneloops08:54:510
542899631623,7cyclictest4793-21kerneloops11:42:303
542899631623,6cyclictest4793-21kerneloops08:47:173
542299631625,5cyclictest4793-21kerneloops10:38:092
542299631625,5cyclictest4793-21kerneloops10:38:092
542299631623,7cyclictest4793-21kerneloops11:35:332
542299631623,6cyclictest4793-21kerneloops11:50:062
541699631628,2cyclictest4793-21kerneloops07:52:381
540799631622,8cyclictest4793-21kerneloops09:44:460
542899630624,4cyclictest4793-21kerneloops07:49:473
542299630624,5cyclictest4793-21kerneloops09:09:042
540799630622,7cyclictest4793-21kerneloops08:17:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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