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2026-07-10 - 02:20
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Jul 09, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889813960,1383rtkit-daemon4793-21kerneloops07:08:302
1295599667657,8cyclictest4793-21kerneloops11:42:340
1296099664656,6cyclictest4793-21kerneloops08:01:041
1296099664656,6cyclictest4793-21kerneloops08:01:041
1297799663655,7cyclictest4793-21kerneloops09:41:223
1295599663652,9cyclictest4793-21kerneloops08:25:180
1297799662655,5cyclictest4793-21kerneloops11:51:133
1297799662653,7cyclictest4793-21kerneloops10:50:493
1296099662654,6cyclictest4793-21kerneloops07:49:021
1297799661654,5cyclictest4793-21kerneloops09:04:283
1296899661653,6cyclictest4793-21kerneloops10:56:522
1296099661654,6cyclictest4793-21kerneloops07:15:591
1296099660654,5cyclictest4793-21kerneloops11:32:391
1297799659656,1cyclictest4793-21kerneloops10:07:483
1297799659651,6cyclictest4793-21kerneloops10:33:303
1296899659652,6cyclictest4793-21kerneloops08:43:372
1295599659653,5cyclictest4793-21kerneloops07:26:140
1297799658655,2cyclictest4793-21kerneloops12:19:213
1297799658652,5cyclictest4793-21kerneloops10:35:403
1296899658653,4cyclictest4793-21kerneloops12:08:562
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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