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2026-03-04 - 06:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Wed Mar 04, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1605799643633,8cyclictest4793-21kerneloops22:38:052
1606199639631,6cyclictest4793-21kerneloops23:16:303
1606199637633,2cyclictest4793-21kerneloops23:02:573
1604099634625,7cyclictest4793-21kerneloops00:23:370
1606199633624,7cyclictest4793-21kerneloops21:29:193
1604999633627,5cyclictest4793-21kerneloops19:41:261
1606199632626,5cyclictest4793-21kerneloops20:38:093
1604999632624,6cyclictest4793-21kerneloops00:30:451
1604099632623,7cyclictest4793-21kerneloops20:42:590
1605799631625,4cyclictest4793-21kerneloops21:58:202
1604999631624,6cyclictest4793-21kerneloops20:34:581
1604999631623,6cyclictest4793-21kerneloops21:53:161
1604999631623,6cyclictest4793-21kerneloops21:39:051
1606199630623,5cyclictest4793-21kerneloops20:56:333
1606199630621,7cyclictest4793-21kerneloops22:46:163
1606199630619,7cyclictest4793-21kerneloops00:20:373
1605799630625,4cyclictest4793-21kerneloops21:37:072
1605799630622,6cyclictest4793-21kerneloops19:12:442
1604099630621,7cyclictest4793-21kerneloops23:56:000
1605799629624,4cyclictest4793-21kerneloops19:30:262
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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