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2026-08-15 - 15:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Aug 15, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812570,1245rtkit-daemon4793-21kerneloops07:05:502
2597799696689,5cyclictest4793-21kerneloops08:10:183
2597199681671,8cyclictest4793-21kerneloops10:57:002
2597799665658,5cyclictest4793-21kerneloops10:26:293
2596199665658,5cyclictest4793-21kerneloops11:52:281
2597799664657,5cyclictest4793-21kerneloops11:48:483
2595699663652,9cyclictest4793-21kerneloops10:34:310
2597799662655,6cyclictest4793-21kerneloops11:41:553
2596199662655,5cyclictest4793-21kerneloops07:26:191
2596199662653,7cyclictest4793-21kerneloops09:15:021
2597799661656,4cyclictest4793-21kerneloops07:50:443
2597799661655,5cyclictest4793-21kerneloops09:58:493
2597799661654,5cyclictest4793-21kerneloops12:36:133
2597799661654,5cyclictest4793-21kerneloops08:24:393
2597799660654,5cyclictest4793-21kerneloops09:17:173
2597799660654,5cyclictest4793-21kerneloops08:01:453
2597799660654,4cyclictest4793-21kerneloops09:54:443
2597799660652,6cyclictest4793-21kerneloops08:39:403
2596199660653,5cyclictest4793-21kerneloops11:26:301
2595699660650,8cyclictest4793-21kerneloops11:46:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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