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2025-12-18 - 20:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Dec 18, 2025 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1844099595585,8cyclictest4793-21kerneloops12:21:143
1844099586576,8cyclictest4793-21kerneloops08:57:553
1844099585576,7cyclictest4793-21kerneloops12:17:493
1844099584575,5cyclictest4793-21kerneloops12:33:403
1844099583574,7cyclictest4793-21kerneloops10:13:133
1844099583574,7cyclictest4793-21kerneloops09:50:243
1843199583577,5cyclictest4793-21kerneloops10:03:111
1844099582573,7cyclictest4793-21kerneloops11:16:363
1844099582573,7cyclictest4793-21kerneloops11:16:363
1843199582573,7cyclictest4793-21kerneloops11:46:041
1842699582574,7cyclictest4793-21kerneloops12:19:260
1844099581575,4cyclictest4793-21kerneloops10:24:123
1844099581574,6cyclictest4793-21kerneloops10:03:003
1844099581574,5cyclictest4793-21kerneloops11:11:113
1844099581574,5cyclictest4793-21kerneloops10:45:273
1844099581574,5cyclictest4793-21kerneloops09:26:223
1844099581573,6cyclictest4793-21kerneloops09:18:023
1844099581573,6cyclictest4793-21kerneloops07:35:563
1844099581572,7cyclictest4793-21kerneloops08:00:293
1843199581575,5cyclictest4793-21kerneloops08:47:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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