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2026-04-25 - 14:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Apr 25, 2026 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1886699637626,9cyclictest4793-21kerneloops10:00:180
1886699636625,9cyclictest4793-21kerneloops09:13:510
1886699636624,10cyclictest4793-21kerneloops10:56:000
1888799635628,5cyclictest4793-21kerneloops09:44:123
1887299635628,5cyclictest4793-21kerneloops08:52:091
1888799634627,6cyclictest4793-21kerneloops09:57:513
1888799634627,5cyclictest4793-21kerneloops11:02:133
1888799634626,6cyclictest4793-21kerneloops08:41:103
1887299634627,6cyclictest4793-21kerneloops11:58:161
1886699634626,6cyclictest4793-21kerneloops07:41:440
1886699634625,7cyclictest4793-21kerneloops10:08:260
1886699634624,8cyclictest4793-21kerneloops11:12:410
1886699634624,8cyclictest4793-21kerneloops10:19:170
1886699634624,8cyclictest4793-21kerneloops10:19:160
1886699634624,8cyclictest4793-21kerneloops09:44:440
1886699634623,9cyclictest4793-21kerneloops12:36:340
1888799633626,5cyclictest4793-21kerneloops07:44:023
1888799633624,7cyclictest4793-21kerneloops07:25:203
1887799633626,6cyclictest4793-21kerneloops12:33:562
1887799633626,5cyclictest4793-21kerneloops08:45:182
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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