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2026-03-22 - 15:15
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sun Mar 22, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1191699634627,5cyclictest4793-21kerneloops12:27:151
1191699634627,5cyclictest4793-21kerneloops12:21:501
1191699634627,5cyclictest4793-21kerneloops09:09:571
1191699634627,5cyclictest4793-21kerneloops08:21:561
1191699633627,5cyclictest4793-21kerneloops07:25:551
1191699633627,4cyclictest4793-21kerneloops08:44:521
1191699633627,4cyclictest4793-21kerneloops08:29:461
1191699633626,5cyclictest4793-21kerneloops09:04:581
1191699633626,5cyclictest4793-21kerneloops08:59:461
1191699633626,5cyclictest4793-21kerneloops08:33:121
1191699633626,5cyclictest4793-21kerneloops07:54:561
1191699632626,5cyclictest4793-21kerneloops11:38:361
1191699632626,5cyclictest4793-21kerneloops10:55:421
1191699632626,5cyclictest4793-21kerneloops07:21:171
1191699632626,4cyclictest4793-21kerneloops08:16:031
1191699632626,4cyclictest4793-21kerneloops08:01:421
1191699632625,5cyclictest4793-21kerneloops11:28:461
1191699632625,5cyclictest4793-21kerneloops07:41:291
1191699632625,5cyclictest4793-21kerneloops07:35:481
1191699632623,7cyclictest4793-21kerneloops10:50:281
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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