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2026-04-04 - 02:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Apr 04, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2595299637627,8cyclictest4793-21kerneloops00:13:053
2595299636627,5cyclictest4793-21kerneloops23:06:473
2595299633626,5cyclictest4793-21kerneloops20:02:083
2595299632626,4cyclictest4793-21kerneloops20:41:573
2594099632625,5cyclictest4793-21kerneloops00:39:021
2593499632624,7cyclictest4793-21kerneloops21:55:390
2595299631628,2cyclictest4793-21kerneloops22:22:243
2595299631625,5cyclictest4793-21kerneloops21:57:403
2595299631624,6cyclictest4793-21kerneloops19:39:093
2594799631622,7cyclictest4793-21kerneloops22:41:142
2594099631625,4cyclictest4793-21kerneloops20:28:181
2594099631625,4cyclictest4793-21kerneloops20:28:181
2594099631623,6cyclictest4793-21kerneloops21:26:331
2594799630623,6cyclictest4793-21kerneloops20:34:212
2594099630624,4cyclictest4793-21kerneloops22:49:021
2593499630620,8cyclictest4793-21kerneloops23:49:170
2593499630620,8cyclictest4793-21kerneloops23:49:170
2594799629623,4cyclictest4793-21kerneloops19:20:122
2593499629621,6cyclictest4793-21kerneloops22:28:040
2594799628620,6cyclictest4793-21kerneloops21:02:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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