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2025-12-30 - 04:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Dec 30, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
996999584575,7cyclictest4793-21kerneloops20:58:091
998499582577,4cyclictest4793-21kerneloops21:17:223
996999582575,5cyclictest4793-21kerneloops21:43:181
996999582573,5cyclictest4793-21kerneloops23:37:021
996399582579,1cyclictest4793-21kerneloops21:55:580
998499581574,5cyclictest4793-21kerneloops21:37:563
996999581574,6cyclictest4793-21kerneloops19:33:211
996999581574,5cyclictest4793-21kerneloops22:41:441
996999581574,5cyclictest4793-21kerneloops21:34:451
996999581574,5cyclictest4793-21kerneloops21:03:191
997699580573,5cyclictest4793-21kerneloops20:34:202
997699580572,6cyclictest4793-21kerneloops20:14:372
996999580572,6cyclictest4793-21kerneloops19:26:261
996399580573,5cyclictest4793-21kerneloops20:14:150
997699579574,4cyclictest4793-21kerneloops23:03:032
996999579574,4cyclictest4793-21kerneloops00:15:031
996999579572,5cyclictest4793-21kerneloops21:53:101
996999579571,6cyclictest4793-21kerneloops23:34:031
996999579570,7cyclictest4793-21kerneloops23:08:341
996399579571,6cyclictest4793-21kerneloops00:24:120
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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