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2026-02-26 - 13:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Thu Feb 26, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1494699635626,7cyclictest4793-21kerneloops21:21:123
1493099635626,7cyclictest4793-21kerneloops22:47:551
1494699634626,6cyclictest4793-21kerneloops21:19:463
1494699633627,5cyclictest4793-21kerneloops22:21:563
1494699632626,4cyclictest4793-21kerneloops20:52:553
1494699632626,1cyclictest4793-21kerneloops19:31:333
1493799632623,7cyclictest4793-21kerneloops23:53:142
1492599632622,8cyclictest4793-21kerneloops22:23:120
1493099631622,7cyclictest4793-21kerneloops19:25:141
1494699630623,6cyclictest4793-21kerneloops20:08:253
1494699630622,6cyclictest4793-21kerneloops21:53:113
1493799630623,5cyclictest4793-21kerneloops23:56:272
1493099630627,2cyclictest4793-21kerneloops19:36:401
1493099630624,5cyclictest4793-21kerneloops23:50:241
1493099630623,5cyclictest4793-21kerneloops21:22:481
1492599630623,5cyclictest4793-21kerneloops22:44:090
1494699629622,5cyclictest4793-21kerneloops22:35:243
1494699629622,5cyclictest4793-21kerneloops20:59:143
1494699629621,6cyclictest4793-21kerneloops22:06:513
1493799629623,4cyclictest4793-21kerneloops19:27:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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