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2026-01-24 - 11:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Jan 24, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889810950,1084rtkit-daemon4793-21kerneloops19:08:582
2706899592580,8cyclictest4793-21kerneloops21:36:173
2706899591582,7cyclictest4793-21kerneloops00:37:273
2706899590582,6cyclictest4793-21kerneloops22:13:353
2706899590580,8cyclictest4793-21kerneloops23:23:203
2706899590580,8cyclictest4793-21kerneloops22:37:083
2706099588579,7cyclictest4793-21kerneloops23:37:312
2706099587578,7cyclictest4793-21kerneloops21:16:132
2705399587582,4cyclictest4793-21kerneloops23:35:351
2705399587578,7cyclictest4793-21kerneloops19:55:131
2704799587580,5cyclictest4793-21kerneloops21:50:410
2705399586577,7cyclictest4793-21kerneloops23:05:171
2706099585578,5cyclictest4793-21kerneloops20:15:022
2705399585578,5cyclictest4793-21kerneloops23:20:401
2705399585577,6cyclictest4793-21kerneloops20:16:591
2704799585578,5cyclictest4793-21kerneloops23:24:240
2705399584581,2cyclictest4793-21kerneloops21:28:351
2705399584577,5cyclictest4793-21kerneloops23:11:291
2706899583577,4cyclictest4793-21kerneloops20:26:483
2706899583576,6cyclictest4793-21kerneloops23:59:063
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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