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2026-07-25 - 06:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Jul 25, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
623599675671,2cyclictest4793-21kerneloops23:49:572
622099664654,2cyclictest4793-21kerneloops20:40:150
622799663657,5cyclictest4793-21kerneloops20:37:541
622799663657,5cyclictest4793-21kerneloops20:37:541
622099663653,8cyclictest4793-21kerneloops22:03:040
624399662655,5cyclictest4793-21kerneloops20:23:053
622799661655,5cyclictest4793-21kerneloops19:21:091
622099661652,7cyclictest4793-21kerneloops20:26:060
624399660654,4cyclictest4793-21kerneloops23:09:363
624399660653,5cyclictest4793-21kerneloops21:13:473
623599660654,5cyclictest4793-21kerneloops20:54:512
623599660654,4cyclictest4793-21kerneloops20:03:432
622799660657,2cyclictest4793-21kerneloops20:48:181
622799660657,2cyclictest4793-21kerneloops00:31:441
624399659656,2cyclictest4793-21kerneloops22:39:393
624399659651,6cyclictest4793-21kerneloops21:33:043
624399659650,7cyclictest4793-21kerneloops22:03:253
623599659653,5cyclictest4793-21kerneloops19:35:252
623599659652,5cyclictest4793-21kerneloops19:51:302
622799659656,2cyclictest4793-21kerneloops23:56:241
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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