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2026-05-23 - 15:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat May 23, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1249099636625,9cyclictest4793-21kerneloops09:30:003
1247499636627,7cyclictest4793-21kerneloops12:13:261
1247499634628,4cyclictest4793-21kerneloops12:18:541
1249099633627,5cyclictest4793-21kerneloops08:38:403
1247499633627,5cyclictest4793-21kerneloops08:19:111
1247499633625,6cyclictest4793-21kerneloops08:28:241
1249099632629,2cyclictest4793-21kerneloops07:32:093
1249099632626,5cyclictest4793-21kerneloops11:21:223
1249099632626,5cyclictest4793-21kerneloops09:35:193
1249099632626,5cyclictest4793-21kerneloops08:47:203
1249099632626,4cyclictest4793-21kerneloops07:14:483
1247499632628,2cyclictest4793-21kerneloops08:43:351
1247499632626,5cyclictest4793-21kerneloops10:18:291
1247499632625,5cyclictest4793-21kerneloops11:25:041
1247499632625,5cyclictest4793-21kerneloops11:25:041
1247499632623,7cyclictest4793-21kerneloops10:00:351
1246899632623,7cyclictest4793-21kerneloops11:05:070
1246899632623,7cyclictest4793-21kerneloops09:12:580
1249099631624,6cyclictest4793-21kerneloops12:09:303
1249099630625,4cyclictest4793-21kerneloops08:20:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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