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2026-03-14 - 08:39
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Sat Mar 14, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
797999633624,7cyclictest4793-21kerneloops21:32:501
797499633625,6cyclictest4793-21kerneloops20:24:590
797999632626,5cyclictest4793-21kerneloops20:43:501
797499632623,7cyclictest4793-21kerneloops21:10:090
799399631622,7cyclictest4793-21kerneloops23:00:403
798799631624,5cyclictest4793-21kerneloops00:08:012
797999631620,8cyclictest4793-21kerneloops23:56:091
797499631623,7cyclictest4793-21kerneloops22:32:160
797499631622,7cyclictest4793-21kerneloops20:03:570
797499631622,7cyclictest4793-21kerneloops19:58:210
799399630627,2cyclictest4793-21kerneloops21:14:453
799399630624,4cyclictest4793-21kerneloops23:57:353
797999630621,7cyclictest4793-21kerneloops00:11:031
797499630624,5cyclictest4793-21kerneloops22:40:200
797499630622,6cyclictest4793-21kerneloops21:43:590
797499630619,9cyclictest4793-21kerneloops22:06:150
798799629622,6cyclictest4793-21kerneloops21:01:572
798799629622,5cyclictest4793-21kerneloops20:47:322
797999629623,5cyclictest4793-21kerneloops20:45:031
797999629620,7cyclictest4793-21kerneloops19:50:191
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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