You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-05 - 01:20
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Tue Nov 04, 2025 12:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1085899769760,7cyclictest4927-21kerneloops09:47:482
1085099755748,5cyclictest4927-21kerneloops09:38:551
1085099755747,6cyclictest4927-21kerneloops10:35:041
1085099755747,6cyclictest4927-21kerneloops09:26:491
1085099754746,6cyclictest4927-21kerneloops07:43:191
1085899753745,6cyclictest4927-21kerneloops09:39:382
1085099753747,5cyclictest4927-21kerneloops08:14:371
1085099752747,4cyclictest4927-21kerneloops09:48:201
1085099752745,5cyclictest4927-21kerneloops12:30:571
1084599752744,6cyclictest4927-21kerneloops08:54:070
1084599752743,7cyclictest4927-21kerneloops11:03:170
1084599752743,7cyclictest4927-21kerneloops07:42:160
1084599751742,7cyclictest4927-21kerneloops09:12:140
1084599751741,8cyclictest4927-21kerneloops10:52:410
1085099750743,5cyclictest4927-21kerneloops12:28:361
1084599750743,6cyclictest4927-21kerneloops10:47:590
1086399749741,6cyclictest4927-21kerneloops09:24:413
1085899749743,4cyclictest4927-21kerneloops07:48:232
1085899749742,5cyclictest4927-21kerneloops11:33:542
1085099749747,1cyclictest4927-21kerneloops09:21:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional