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2026-07-07 - 01:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack6slot8.osadl.org (updated Mon Jul 06, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1597899666658,6cyclictest4793-21kerneloops00:30:122
1597399664658,4cyclictest4793-21kerneloops19:58:001
1596699664652,10cyclictest4793-21kerneloops23:03:210
1598399663656,5cyclictest4793-21kerneloops23:02:483
1598399662654,6cyclictest4793-21kerneloops23:51:123
1597399662656,5cyclictest4793-21kerneloops23:05:381
1597399662655,5cyclictest4793-21kerneloops20:47:181
1598399661654,5cyclictest4793-21kerneloops20:41:553
1597899661657,2cyclictest4793-21kerneloops21:23:522
1597899661654,6cyclictest4793-21kerneloops20:08:102
1597899661652,7cyclictest4793-21kerneloops23:34:142
1597399661654,5cyclictest4793-21kerneloops19:54:351
1598399660657,2cyclictest4793-21kerneloops19:16:443
1598399660654,4cyclictest4793-21kerneloops23:59:013
1598399659653,4cyclictest4793-21kerneloops22:24:143
1598399659652,6cyclictest4793-21kerneloops21:29:483
1597899659653,5cyclictest4793-21kerneloops20:58:342
1597899659652,6cyclictest4793-21kerneloops23:58:512
1597899659651,7cyclictest4793-21kerneloops00:29:202
1597899659651,7cyclictest4793-21kerneloops00:29:202
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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