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2026-10-22 - 08:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Thu Oct 22, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889822500,2237rtkit-daemon4793-21kerneloops19:05:362
245619912231214,7cyclictest4793-21kerneloops23:34:290
245679912211213,7cyclictest4793-21kerneloops21:56:151
245679912191211,6cyclictest4793-21kerneloops23:10:421
245679912191211,6cyclictest4793-21kerneloops20:31:571
245679912181212,5cyclictest4793-21kerneloops23:00:241
245679912181212,5cyclictest4793-21kerneloops22:23:161
245679912181212,5cyclictest4793-21kerneloops22:23:161
245679912181212,5cyclictest4793-21kerneloops20:58:501
245679912181211,5cyclictest4793-21kerneloops19:36:021
245679912181211,5cyclictest4793-21kerneloops19:11:231
245679912181210,6cyclictest4793-21kerneloops21:00:461
245829912171211,5cyclictest4793-21kerneloops20:37:123
245829912171208,7cyclictest4793-21kerneloops19:45:343
245679912171211,5cyclictest4793-21kerneloops21:47:261
245679912171210,6cyclictest4793-21kerneloops23:55:201
245679912151210,4cyclictest4793-21kerneloops20:46:561
245679912151208,5cyclictest4793-21kerneloops21:08:441
245829912141208,5cyclictest4793-21kerneloops20:23:393
245829912141207,6cyclictest4793-21kerneloops00:36:273
245619912141206,7cyclictest4793-21kerneloops19:15:270
245619912141202,10cyclictest4793-21kerneloops23:25:230
245829912131207,5cyclictest4793-21kerneloops23:46:173
245829912131206,5cyclictest4793-21kerneloops22:11:013
245729912131206,6cyclictest4793-21kerneloops21:16:572
245729912131206,5cyclictest4793-21kerneloops23:30:532
245729912131206,5cyclictest4793-21kerneloops20:59:522
245729912131205,7cyclictest4793-21kerneloops20:39:102
245729912131205,6cyclictest4793-21kerneloops22:50:372
245679912131206,5cyclictest4793-21kerneloops21:37:481
245679912131206,5cyclictest4793-21kerneloops20:00:441
245679912131205,6cyclictest4793-21kerneloops19:20:021
245679912131204,7cyclictest4793-21kerneloops21:52:011
245679912131203,8cyclictest4793-21kerneloops00:33:181
245619912131206,6cyclictest4793-21kerneloops21:58:360
245619912131203,9cyclictest4793-21kerneloops22:00:450
245679912121205,5cyclictest4793-21kerneloops22:19:531
245679912121205,5cyclictest4793-21kerneloops20:25:551
245679912121205,5cyclictest4793-21kerneloops20:10:531
245679912121204,6cyclictest4793-21kerneloops23:42:351
245619912121205,6cyclictest4793-21kerneloops19:30:420
245619912121204,6cyclictest4793-21kerneloops22:58:370
245829912111205,5cyclictest4793-21kerneloops20:12:393
245729912111202,7cyclictest4793-21kerneloops20:41:272
245679912111204,5cyclictest4793-21kerneloops00:19:561
245619912111204,6cyclictest4793-21kerneloops22:13:320
245619912111204,6cyclictest4793-21kerneloops20:06:280
245619912111203,7cyclictest4793-21kerneloops19:49:400
245619912111201,8cyclictest4793-21kerneloops21:21:300
245829912101202,6cyclictest4793-21kerneloops19:37:053
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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