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2025-12-07 - 00:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Sat Dec 06, 2025 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64479815650,1553rtkit-daemon4927-21kerneloops07:09:041
2689199799792,6cyclictest4927-21kerneloops09:32:163
2686799799789,8cyclictest4927-21kerneloops11:49:180
2688499798787,7cyclictest4927-21kerneloops10:56:482
2687899797789,6cyclictest4927-21kerneloops12:39:551
2686799796789,5cyclictest4927-21kerneloops12:10:130
2689199795788,6cyclictest4927-21kerneloops09:02:353
2687899795786,7cyclictest4927-21kerneloops10:54:531
2689199794791,2cyclictest4927-21kerneloops08:44:513
2687899794788,5cyclictest4927-21kerneloops10:37:541
2687899794787,6cyclictest4927-21kerneloops10:09:121
2687899794787,5cyclictest4927-21kerneloops12:02:051
2689199793786,5cyclictest4927-21kerneloops08:11:283
2689199793786,5cyclictest4927-21kerneloops08:11:283
2688499793785,7cyclictest4927-21kerneloops11:09:472
2688499793784,7cyclictest4927-21kerneloops11:59:472
2688499793784,7cyclictest4927-21kerneloops07:45:012
2687899793790,2cyclictest4927-21kerneloops08:04:551
2687899793787,4cyclictest4927-21kerneloops08:40:251
2687899793785,6cyclictest4927-21kerneloops11:52:521
2689199792788,2cyclictest4927-21kerneloops07:46:043
2689199792786,5cyclictest4927-21kerneloops12:28:503
2689199792784,6cyclictest4927-21kerneloops09:42:123
2688499792782,8cyclictest4927-21kerneloops09:13:552
2688499792779,9cyclictest4927-21kerneloops12:17:232
2687899792789,2cyclictest4927-21kerneloops09:23:181
2687899792785,5cyclictest4927-21kerneloops10:31:521
2686799792785,6cyclictest4927-21kerneloops08:37:150
2687899791788,2cyclictest4927-21kerneloops11:29:431
2686799791788,2cyclictest4927-21kerneloops10:59:250
2689199790784,4cyclictest4927-21kerneloops10:39:083
2689199790783,5cyclictest4927-21kerneloops07:40:263
2688499790784,5cyclictest4927-21kerneloops08:32:462
2688499790783,5cyclictest4927-21kerneloops11:00:092
2687899790784,5cyclictest4927-21kerneloops11:33:231
2687899790784,5cyclictest4927-21kerneloops07:32:351
2689199789786,2cyclictest4927-21kerneloops07:25:393
2689199789783,5cyclictest4927-21kerneloops08:19:193
2689199789781,6cyclictest4927-21kerneloops08:39:433
2687899789782,5cyclictest4927-21kerneloops10:47:151
2687899789781,6cyclictest4927-21kerneloops09:09:191
2689199788785,2cyclictest4927-21kerneloops07:22:373
2689199788782,5cyclictest4927-21kerneloops09:13:343
2689199788781,5cyclictest4927-21kerneloops07:31:203
2689199788780,6cyclictest4927-21kerneloops07:38:483
2688499788782,5cyclictest4927-21kerneloops10:02:012
2687899788784,2cyclictest4927-21kerneloops12:15:151
2687899788781,6cyclictest4927-21kerneloops11:13:271
2686799788785,2cyclictest4927-21kerneloops10:05:210
2686799788781,6cyclictest4927-21kerneloops07:16:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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