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2026-08-27 - 04:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Thu Aug 27, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1360699670666,2cyclictest4793-21kerneloops21:52:343
1360699667657,6cyclictest4793-21kerneloops21:27:023
1360699664657,5cyclictest4793-21kerneloops21:17:593
1359399663657,5cyclictest4793-21kerneloops20:51:231
1359399663656,5cyclictest4793-21kerneloops20:07:571
1360699662655,5cyclictest4793-21kerneloops23:58:583
1359799662654,6cyclictest4793-21kerneloops21:37:542
1359799662654,6cyclictest4793-21kerneloops20:34:312
1360699661655,5cyclictest4793-21kerneloops00:14:213
1359399660653,5cyclictest4793-21kerneloops21:11:131
1359399660652,6cyclictest4793-21kerneloops00:10:041
1358699660652,6cyclictest4793-21kerneloops19:21:070
1360699659650,7cyclictest4793-21kerneloops20:10:143
1359399659652,5cyclictest4793-21kerneloops23:16:231
1358699659651,7cyclictest4793-21kerneloops19:37:560
1360699658652,2cyclictest4793-21kerneloops20:49:583
1359799658652,5cyclictest4793-21kerneloops00:10:372
1359799658650,6cyclictest4793-21kerneloops23:29:222
1360699657654,2cyclictest4793-21kerneloops00:06:203
1360699657652,4cyclictest4793-21kerneloops19:53:153
1360699657651,5cyclictest4793-21kerneloops23:47:323
1359799657654,2cyclictest4793-21kerneloops22:34:472
1359799657654,2cyclictest4793-21kerneloops19:50:142
1359799657654,2cyclictest4793-21kerneloops19:19:492
1359799657651,5cyclictest4793-21kerneloops20:12:342
1359399657654,2cyclictest4793-21kerneloops20:14:101
1359399657650,5cyclictest4793-21kerneloops22:50:441
1359399657650,5cyclictest4793-21kerneloops22:01:071
1360699656650,5cyclictest4793-21kerneloops20:27:203
1360699656649,5cyclictest4793-21kerneloops20:18:503
1359799656654,1cyclictest4793-21kerneloops19:57:072
1359799656646,8cyclictest4793-21kerneloops20:25:222
1359399656653,2cyclictest4793-21kerneloops20:38:371
1359399656646,8cyclictest4793-21kerneloops22:25:191
1358699656648,6cyclictest4793-21kerneloops22:34:170
1358699656647,7cyclictest4793-21kerneloops23:24:040
1360699655652,2cyclictest4793-21kerneloops00:01:253
1360699655648,6cyclictest4793-21kerneloops23:27:053
1359399655648,6cyclictest4793-21kerneloops21:47:391
1358699655647,6cyclictest4793-21kerneloops23:39:160
1360699654647,6cyclictest4793-21kerneloops22:24:373
1359799654648,5cyclictest4793-21kerneloops22:15:302
1359799654648,4cyclictest4793-21kerneloops20:39:092
1359399654651,2cyclictest4793-21kerneloops00:30:311
1358699654648,5cyclictest4793-21kerneloops22:48:370
1360699653648,4cyclictest4793-21kerneloops22:32:333
1359799653651,1cyclictest4793-21kerneloops21:27:462
1359799653642,9cyclictest4793-21kerneloops21:45:092
1359399653650,2cyclictest4793-21kerneloops22:45:581
1359399653646,5cyclictest4793-21kerneloops20:27:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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