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2026-01-31 - 05:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Sat Jan 31, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2659399588579,7cyclictest4793-21kerneloops19:30:013
2659399587581,4cyclictest4793-21kerneloops22:15:263
2659399587580,5cyclictest4793-21kerneloops21:34:433
2657599587579,6cyclictest4793-21kerneloops23:58:480
2658099586580,5cyclictest4793-21kerneloops21:43:031
2658799584576,6cyclictest4793-21kerneloops23:28:382
2658099584578,5cyclictest4793-21kerneloops20:54:121
2657599584575,7cyclictest4793-21kerneloops20:36:500
2658799583578,4cyclictest4793-21kerneloops22:46:452
2658099583578,4cyclictest4793-21kerneloops23:25:341
2658099583576,5cyclictest4793-21kerneloops21:16:361
2659399582580,1cyclictest4793-21kerneloops23:01:253
2659399582580,1cyclictest4793-21kerneloops23:01:253
2659399582580,1cyclictest4793-21kerneloops00:06:103
2658799582574,6cyclictest4793-21kerneloops21:48:312
2658099582579,2cyclictest4793-21kerneloops21:08:431
2659399581579,1cyclictest4793-21kerneloops22:42:073
2659399581579,1cyclictest4793-21kerneloops20:37:573
2659399581575,5cyclictest4793-21kerneloops19:32:303
2658799581575,4cyclictest4793-21kerneloops23:20:042
2658099581578,2cyclictest4793-21kerneloops20:10:541
2658099581574,6cyclictest4793-21kerneloops22:21:421
2657599581573,6cyclictest4793-21kerneloops22:02:210
2659399580572,6cyclictest4793-21kerneloops22:48:333
2658099580578,1cyclictest4793-21kerneloops20:49:501
2658099580573,5cyclictest4793-21kerneloops20:06:181
2658099580572,6cyclictest4793-21kerneloops23:10:591
2657599580573,6cyclictest4793-21kerneloops19:53:340
2658799579576,2cyclictest4793-21kerneloops22:00:572
2658799579574,4cyclictest4793-21kerneloops19:41:082
2658799579573,5cyclictest4793-21kerneloops23:01:362
2658799579573,5cyclictest4793-21kerneloops23:01:362
2658799579572,5cyclictest4793-21kerneloops21:32:332
2658099579576,2cyclictest4793-21kerneloops23:04:251
2658099579576,2cyclictest4793-21kerneloops23:04:241
2657599579576,1cyclictest4793-21kerneloops20:24:110
2657599579572,5cyclictest4793-21kerneloops00:01:480
2657599579571,6cyclictest4793-21kerneloops20:57:230
2659399578575,2cyclictest4793-21kerneloops22:01:513
2658799578576,1cyclictest4793-21kerneloops20:01:522
2658799578575,2cyclictest4793-21kerneloops23:31:472
2658799578572,5cyclictest4793-21kerneloops22:33:212
2659399577573,2cyclictest4793-21kerneloops22:30:473
2659399577571,5cyclictest4793-21kerneloops23:56:093
2659399577570,5cyclictest4793-21kerneloops00:37:563
2658799577574,1cyclictest4793-21kerneloops22:43:112
2658799577571,5cyclictest4793-21kerneloops00:01:072
2658099577574,2cyclictest4793-21kerneloops22:55:281
2657599577569,6cyclictest4793-21kerneloops20:14:070
2657599577569,6cyclictest4793-21kerneloops19:58:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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