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2025-05-02 - 12:56
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Fri May 02, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
64479813300,1319rtkit-daemon4927-21kerneloops19:05:123
98299741737,2cyclictest4927-21kerneloops22:40:181
99899728719,7cyclictest4927-21kerneloops22:57:183
99199711702,7cyclictest4927-21kerneloops22:03:582
99899709702,5cyclictest4927-21kerneloops22:00:563
98299709702,5cyclictest4927-21kerneloops20:42:451
99199708704,2cyclictest4927-21kerneloops00:12:562
99899707700,6cyclictest4927-21kerneloops20:20:373
98299707700,6cyclictest4927-21kerneloops20:32:381
98299707699,6cyclictest4927-21kerneloops23:09:001
98299707699,6cyclictest4927-21kerneloops22:33:341
97799707698,7cyclictest4927-21kerneloops20:40:060
98299706700,5cyclictest4927-21kerneloops23:29:561
98299706699,5cyclictest4927-21kerneloops19:56:411
97799706697,7cyclictest4927-21kerneloops19:46:300
99899705699,5cyclictest4927-21kerneloops20:34:573
98299705702,2cyclictest4927-21kerneloops21:59:101
98299705702,2cyclictest4927-21kerneloops00:28:581
97799705697,6cyclictest4927-21kerneloops20:04:070
97799704696,6cyclictest4927-21kerneloops19:42:340
99899703699,2cyclictest4927-21kerneloops00:33:013
98299703701,1cyclictest4927-21kerneloops19:36:131
98299703696,5cyclictest4927-21kerneloops22:53:571
97799703697,5cyclictest4927-21kerneloops19:22:590
99899702699,2cyclictest4927-21kerneloops21:04:493
99899702698,2cyclictest4927-21kerneloops19:28:403
99899702696,5cyclictest4927-21kerneloops19:35:083
99199702695,6cyclictest4927-21kerneloops19:46:072
99199702695,5cyclictest4927-21kerneloops21:20:132
98299702696,5cyclictest4927-21kerneloops22:10:161
98299702696,4cyclictest4927-21kerneloops20:36:441
97799702692,8cyclictest4927-21kerneloops21:51:020
99899701695,4cyclictest4927-21kerneloops20:58:133
99199701697,2cyclictest4927-21kerneloops20:33:192
98299701694,5cyclictest4927-21kerneloops21:22:121
97799701695,5cyclictest4927-21kerneloops20:35:060
99899700697,2cyclictest4927-21kerneloops21:45:543
99199700697,2cyclictest4927-21kerneloops20:39:452
99199700694,5cyclictest4927-21kerneloops20:12:032
98299700692,6cyclictest4927-21kerneloops23:17:551
97799700694,5cyclictest4927-21kerneloops19:39:140
99899699693,5cyclictest4927-21kerneloops20:54:243
99199699694,4cyclictest4927-21kerneloops00:36:212
98299699696,1cyclictest4927-21kerneloops21:37:461
98299699692,5cyclictest4927-21kerneloops19:14:581
97799699686,11cyclictest4927-21kerneloops22:34:160
99899698694,2cyclictest4927-21kerneloops21:38:263
99199698691,6cyclictest4927-21kerneloops21:49:572
99199698690,6cyclictest4927-21kerneloops22:17:032
99899697694,2cyclictest4927-21kerneloops23:17:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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