You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-06-18 - 03:18
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Thu Jun 18, 2026 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
495799662655,5cyclictest4793-21kerneloops22:30:163
495799635628,5cyclictest4793-21kerneloops22:28:003
495799634626,6cyclictest4793-21kerneloops20:30:103
495799634626,6cyclictest4793-21kerneloops20:30:103
495799633626,5cyclictest4793-21kerneloops22:01:513
494599633628,4cyclictest4793-21kerneloops00:18:401
494599633627,4cyclictest4793-21kerneloops00:31:151
494599633625,6cyclictest4793-21kerneloops23:04:451
493699633621,10cyclictest4793-21kerneloops19:11:150
495799632626,4cyclictest4793-21kerneloops19:24:393
494599632625,5cyclictest4793-21kerneloops21:38:041
494599632625,5cyclictest4793-21kerneloops21:33:161
494599632622,8cyclictest4793-21kerneloops22:28:091
495299631624,6cyclictest4793-21kerneloops00:06:222
494599631628,2cyclictest4793-21kerneloops19:51:151
494599631625,5cyclictest4793-21kerneloops21:40:331
494599631624,5cyclictest4793-21kerneloops22:40:091
494599631624,5cyclictest4793-21kerneloops21:20:451
494599631624,5cyclictest4793-21kerneloops20:00:151
494599631623,6cyclictest4793-21kerneloops19:37:471
494599631623,6cyclictest4793-21kerneloops19:34:231
494599631619,9cyclictest4793-21kerneloops23:55:111
493699631624,6cyclictest4793-21kerneloops22:56:300
495799630624,5cyclictest4793-21kerneloops23:30:153
495299630624,5cyclictest4793-21kerneloops23:46:402
495299630624,5cyclictest4793-21kerneloops23:46:402
495299630622,6cyclictest4793-21kerneloops21:19:312
494599630628,1cyclictest4793-21kerneloops19:41:241
494599630627,1cyclictest4793-21kerneloops21:52:501
494599630625,4cyclictest4793-21kerneloops22:09:391
494599630623,6cyclictest4793-21kerneloops19:45:591
494599630623,5cyclictest4793-21kerneloops22:59:001
494599630623,5cyclictest4793-21kerneloops21:03:081
494599630623,5cyclictest4793-21kerneloops20:26:251
494599630622,6cyclictest4793-21kerneloops21:46:351
494599630622,6cyclictest4793-21kerneloops21:16:271
493699630623,5cyclictest4793-21kerneloops20:46:590
493699630620,8cyclictest4793-21kerneloops21:10:460
495799629625,2cyclictest4793-21kerneloops23:52:453
495799629623,5cyclictest4793-21kerneloops21:14:113
495799629623,5cyclictest4793-21kerneloops19:36:323
495799629620,7cyclictest4793-21kerneloops21:17:313
494599629623,5cyclictest4793-21kerneloops22:21:571
494599629623,5cyclictest4793-21kerneloops22:00:361
494599629623,5cyclictest4793-21kerneloops21:07:031
494599629623,5cyclictest4793-21kerneloops00:29:061
494599629622,5cyclictest4793-21kerneloops20:59:101
494599629622,5cyclictest4793-21kerneloops20:48:031
494599629622,5cyclictest4793-21kerneloops19:12:181
494599629621,7cyclictest4793-21kerneloops23:05:591
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional