You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-24 - 04:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Sat Jan 24, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889810950,1084rtkit-daemon4793-21kerneloops19:08:582
2706899592580,8cyclictest4793-21kerneloops21:36:173
2706899591582,7cyclictest4793-21kerneloops00:37:273
2706899590582,6cyclictest4793-21kerneloops22:13:353
2706899590580,8cyclictest4793-21kerneloops23:23:203
2706899590580,8cyclictest4793-21kerneloops22:37:083
2706099588579,7cyclictest4793-21kerneloops23:37:312
2706099587578,7cyclictest4793-21kerneloops21:16:132
2705399587582,4cyclictest4793-21kerneloops23:35:351
2705399587578,7cyclictest4793-21kerneloops19:55:131
2704799587580,5cyclictest4793-21kerneloops21:50:410
2705399586577,7cyclictest4793-21kerneloops23:05:171
2706099585578,5cyclictest4793-21kerneloops20:15:022
2705399585578,5cyclictest4793-21kerneloops23:20:401
2705399585577,6cyclictest4793-21kerneloops20:16:591
2704799585578,5cyclictest4793-21kerneloops23:24:240
2705399584581,2cyclictest4793-21kerneloops21:28:351
2705399584577,5cyclictest4793-21kerneloops23:11:291
2706899583577,4cyclictest4793-21kerneloops20:26:483
2706899583576,6cyclictest4793-21kerneloops23:59:063
2706899583576,6cyclictest4793-21kerneloops23:59:063
2706099583576,6cyclictest4793-21kerneloops21:11:462
2705399583578,4cyclictest4793-21kerneloops22:22:561
2705399583578,4cyclictest4793-21kerneloops22:22:551
2705399583576,5cyclictest4793-21kerneloops22:13:161
2705399583575,6cyclictest4793-21kerneloops19:18:471
2706899582580,1cyclictest4793-21kerneloops20:02:003
2706899582576,5cyclictest4793-21kerneloops20:46:033
2706899582575,6cyclictest4793-21kerneloops22:04:433
2706899582573,7cyclictest4793-21kerneloops23:37:003
2706099582580,1cyclictest4793-21kerneloops21:42:122
2705399582579,2cyclictest4793-21kerneloops20:30:271
2705399582578,2cyclictest4793-21kerneloops22:35:021
2704799582580,1cyclictest4793-21kerneloops19:21:020
2706899581579,1cyclictest4793-21kerneloops22:28:233
2706899581578,2cyclictest4793-21kerneloops00:03:283
2706899581574,5cyclictest4793-21kerneloops23:01:433
2706099581579,1cyclictest4793-21kerneloops22:45:322
2705399581576,4cyclictest4793-21kerneloops20:55:511
2705399581574,5cyclictest4793-21kerneloops22:44:151
2705399581573,6cyclictest4793-21kerneloops21:31:491
2706899580577,1cyclictest4793-21kerneloops22:23:393
2706899580577,1cyclictest4793-21kerneloops22:23:383
2705399580577,1cyclictest4793-21kerneloops00:38:421
2705399580573,5cyclictest4793-21kerneloops23:27:571
2705399580572,6cyclictest4793-21kerneloops21:21:421
2704799580578,1cyclictest4793-21kerneloops00:25:310
2704799580577,2cyclictest4793-21kerneloops19:18:150
2706899579571,6cyclictest4793-21kerneloops00:26:013
2706099579573,5cyclictest4793-21kerneloops19:49:362
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional