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2026-07-16 - 04:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Thu Jul 16, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
415799666663,1cyclictest4793-21kerneloops00:25:060
416799665657,7cyclictest4793-21kerneloops21:48:031
416799663656,5cyclictest4793-21kerneloops19:29:011
416799663655,6cyclictest4793-21kerneloops00:17:241
415799663654,7cyclictest4793-21kerneloops20:03:020
418099662654,4cyclictest4793-21kerneloops20:27:053
415799662655,5cyclictest4793-21kerneloops00:20:080
418099661653,6cyclictest4793-21kerneloops19:53:343
416799661654,5cyclictest4793-21kerneloops00:13:181
416799661652,7cyclictest4793-21kerneloops23:18:121
416799660655,4cyclictest4793-21kerneloops20:42:001
415799660653,5cyclictest4793-21kerneloops19:32:230
418099659655,2cyclictest4793-21kerneloops22:02:493
417399659653,5cyclictest4793-21kerneloops20:04:072
417399659652,6cyclictest4793-21kerneloops22:22:192
417399659651,7cyclictest4793-21kerneloops23:43:552
417399659650,7cyclictest4793-21kerneloops00:19:132
416799659655,2cyclictest4793-21kerneloops20:32:391
416799659653,5cyclictest4793-21kerneloops23:08:491
416799659652,6cyclictest4793-21kerneloops21:51:051
416799659651,6cyclictest4793-21kerneloops20:29:141
415799659651,7cyclictest4793-21kerneloops00:18:190
418099658652,5cyclictest4793-21kerneloops21:27:153
418099658652,5cyclictest4793-21kerneloops00:33:133
418099658651,5cyclictest4793-21kerneloops19:44:253
417399658651,6cyclictest4793-21kerneloops23:14:062
417399658649,7cyclictest4793-21kerneloops21:12:142
416799658656,1cyclictest4793-21kerneloops21:26:231
416799658654,2cyclictest4793-21kerneloops21:34:551
416799658654,2cyclictest4793-21kerneloops21:34:551
417399657655,1cyclictest4793-21kerneloops21:52:292
417399657649,6cyclictest4793-21kerneloops20:56:442
416799657648,7cyclictest4793-21kerneloops00:00:421
415799657650,6cyclictest4793-21kerneloops22:05:300
418099656651,4cyclictest4793-21kerneloops19:33:493
418099656650,5cyclictest4793-21kerneloops00:10:373
416799656653,2cyclictest4793-21kerneloops21:42:311
416799656649,6cyclictest4793-21kerneloops23:33:541
416799656648,6cyclictest4793-21kerneloops00:06:421
418099655652,2cyclictest4793-21kerneloops22:51:433
417399655649,5cyclictest4793-21kerneloops22:04:172
417399655649,5cyclictest4793-21kerneloops21:45:522
416799655648,5cyclictest4793-21kerneloops23:45:521
416799655646,7cyclictest4793-21kerneloops21:24:381
417399654650,2cyclictest4793-21kerneloops22:43:432
417399654649,4cyclictest4793-21kerneloops19:35:372
417399654648,5cyclictest4793-21kerneloops21:04:022
417399654647,6cyclictest4793-21kerneloops23:24:592
416799654647,6cyclictest4793-21kerneloops19:35:581
416799654647,5cyclictest4793-21kerneloops20:36:491
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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