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2026-07-30 - 04:35
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Thu Jul 30, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889812720,1259rtkit-daemon4793-21kerneloops19:07:002
2348999673663,8cyclictest4793-21kerneloops22:18:193
2348999665657,6cyclictest4793-21kerneloops19:24:393
2347399664656,6cyclictest4793-21kerneloops21:12:291
2348299663655,6cyclictest4793-21kerneloops20:25:582
2347399663658,4cyclictest4793-21kerneloops22:22:451
2347399663657,5cyclictest4793-21kerneloops22:35:031
2348999662656,5cyclictest4793-21kerneloops23:21:243
2348999662654,6cyclictest4793-21kerneloops22:55:013
2347399662656,5cyclictest4793-21kerneloops22:52:451
2347399661654,6cyclictest4793-21kerneloops19:12:131
2347399661654,5cyclictest4793-21kerneloops21:06:111
2347399661654,5cyclictest4793-21kerneloops20:31:111
2347399661652,7cyclictest4793-21kerneloops23:16:071
2348999660656,2cyclictest4793-21kerneloops00:36:243
2348999660654,5cyclictest4793-21kerneloops22:53:263
2348299660654,5cyclictest4793-21kerneloops23:57:212
2348299660654,5cyclictest4793-21kerneloops21:08:282
2347399660657,2cyclictest4793-21kerneloops20:09:091
2346899660654,5cyclictest4793-21kerneloops20:32:140
2346899660653,5cyclictest4793-21kerneloops20:56:380
2348999659653,5cyclictest4793-21kerneloops20:48:413
2348999659653,4cyclictest4793-21kerneloops22:31:593
2347399659656,2cyclictest4793-21kerneloops23:09:001
2348999658655,2cyclictest4793-21kerneloops23:19:493
2348999658652,5cyclictest4793-21kerneloops20:10:543
2348999658650,6cyclictest4793-21kerneloops21:23:173
2348299658652,5cyclictest4793-21kerneloops20:55:572
2347399658656,1cyclictest4793-21kerneloops19:25:011
2347399658655,2cyclictest4793-21kerneloops23:14:191
2346899658651,6cyclictest4793-21kerneloops23:42:090
2348999657654,2cyclictest4793-21kerneloops19:44:333
2348999657650,5cyclictest4793-21kerneloops23:38:353
2348299657652,4cyclictest4793-21kerneloops23:53:462
2348299657651,5cyclictest4793-21kerneloops19:36:442
2347399657655,1cyclictest4793-21kerneloops21:48:261
2347399657654,2cyclictest4793-21kerneloops22:09:251
2347399657651,5cyclictest4793-21kerneloops20:41:511
2346899657655,1cyclictest4793-21kerneloops20:36:100
2346899657653,2cyclictest4793-21kerneloops21:36:100
2346899657647,8cyclictest4793-21kerneloops00:16:500
2348999656649,6cyclictest4793-21kerneloops23:28:183
2348299656651,4cyclictest4793-21kerneloops00:13:232
2346899656650,5cyclictest4793-21kerneloops23:47:240
2346899656648,6cyclictest4793-21kerneloops20:07:430
2348999655650,4cyclictest4793-21kerneloops20:39:443
2348299655653,1cyclictest4793-21kerneloops19:51:222
2348299655652,2cyclictest4793-21kerneloops21:24:322
2348299655650,4cyclictest4793-21kerneloops19:13:182
2346899655647,7cyclictest4793-21kerneloops00:29:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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