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2026-01-17 - 02:22
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Sat Jan 17, 2026 00:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1258999586577,7cyclictest4793-21kerneloops23:54:213
1258099585575,8cyclictest4793-21kerneloops00:17:542
1257599585578,5cyclictest4793-21kerneloops22:52:591
1257599585576,7cyclictest4793-21kerneloops20:53:271
1257599584576,7cyclictest4793-21kerneloops19:53:291
1257599584576,6cyclictest4793-21kerneloops23:23:371
1257599584576,6cyclictest4793-21kerneloops22:21:431
1257599584576,6cyclictest4793-21kerneloops20:24:121
1257599583576,5cyclictest4793-21kerneloops23:33:121
1257599583576,5cyclictest4793-21kerneloops23:14:561
1257599583576,5cyclictest4793-21kerneloops22:04:101
1257599583576,5cyclictest4793-21kerneloops19:37:371
1257599583575,6cyclictest4793-21kerneloops23:16:421
1257599583575,6cyclictest4793-21kerneloops22:45:531
1258999582577,4cyclictest4793-21kerneloops19:39:583
1258999582574,7cyclictest4793-21kerneloops19:15:143
1258999582573,7cyclictest4793-21kerneloops22:23:203
1258999582573,7cyclictest4793-21kerneloops00:22:183
1257599582577,4cyclictest4793-21kerneloops22:26:001
1257599582576,4cyclictest4793-21kerneloops20:47:001
1257599582575,5cyclictest4793-21kerneloops21:25:451
1257599582575,5cyclictest4793-21kerneloops20:19:411
1257599582575,5cyclictest4793-21kerneloops00:25:181
1257599582574,6cyclictest4793-21kerneloops23:06:091
1257599582574,6cyclictest4793-21kerneloops19:19:511
1257599581575,5cyclictest4793-21kerneloops23:39:361
1257599581574,5cyclictest4793-21kerneloops00:15:001
1257599581574,5cyclictest4793-21kerneloops00:02:451
1257599581573,6cyclictest4793-21kerneloops21:40:131
1257599581573,6cyclictest4793-21kerneloops21:31:291
1257599581573,6cyclictest4793-21kerneloops20:25:381
1256899581572,8cyclictest4793-21kerneloops22:09:540
1258999580574,5cyclictest4793-21kerneloops00:16:373
1258999580569,9cyclictest4793-21kerneloops21:27:233
1258099580570,8cyclictest4793-21kerneloops22:56:112
1258099580569,9cyclictest4793-21kerneloops21:20:142
1257599580574,5cyclictest4793-21kerneloops21:22:151
1257599580574,5cyclictest4793-21kerneloops20:06:261
1257599580574,5cyclictest4793-21kerneloops19:24:441
1257599580574,4cyclictest4793-21kerneloops20:57:451
1257599580574,4cyclictest4793-21kerneloops20:10:431
1257599580573,6cyclictest4793-21kerneloops19:56:191
1257599580573,5cyclictest4793-21kerneloops19:30:461
1256899580574,5cyclictest4793-21kerneloops20:03:060
1256899580572,6cyclictest4793-21kerneloops20:36:440
1258099579574,4cyclictest4793-21kerneloops23:25:052
1257599579573,5cyclictest4793-21kerneloops21:47:341
1257599579572,5cyclictest4793-21kerneloops22:42:531
1257599579572,5cyclictest4793-21kerneloops19:45:081
1256899579573,5cyclictest4793-21kerneloops19:49:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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