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2026-07-02 - 03:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Thu Jul 02, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1190399678674,2cyclictest4793-21kerneloops22:40:543
1188799664655,7cyclictest4793-21kerneloops20:37:331
1188799664655,7cyclictest4793-21kerneloops19:48:031
1190399663655,6cyclictest4793-21kerneloops20:43:273
1188799663654,7cyclictest4793-21kerneloops22:03:331
1188099663653,8cyclictest4793-21kerneloops23:23:420
1190399662655,6cyclictest4793-21kerneloops21:00:473
1188799662653,7cyclictest4793-21kerneloops20:00:331
1190399661655,5cyclictest4793-21kerneloops22:38:043
1188799661655,4cyclictest4793-21kerneloops21:31:381
1188099661652,7cyclictest4793-21kerneloops20:38:380
1188099661651,8cyclictest4793-21kerneloops20:56:430
1190399660654,4cyclictest4793-21kerneloops19:17:043
1190399660653,5cyclictest4793-21kerneloops00:13:493
1189599660653,5cyclictest4793-21kerneloops21:02:322
1188799660654,5cyclictest4793-21kerneloops23:23:531
1188799660654,5cyclictest4793-21kerneloops22:51:231
1188799660652,6cyclictest4793-21kerneloops22:38:251
1188799660651,7cyclictest4793-21kerneloops19:37:301
1188099660656,2cyclictest4793-21kerneloops23:05:280
1188099660653,6cyclictest4793-21kerneloops00:07:510
1190399658655,1cyclictest4793-21kerneloops23:50:373
1190399658652,5cyclictest4793-21kerneloops20:33:043
1189599658652,5cyclictest4793-21kerneloops23:51:412
1189599658649,7cyclictest4793-21kerneloops20:50:212
1190399657654,2cyclictest4793-21kerneloops19:28:133
1190399657654,1cyclictest4793-21kerneloops19:24:163
1189599657652,4cyclictest4793-21kerneloops19:25:412
1189599657650,5cyclictest4793-21kerneloops00:06:072
1188799657654,2cyclictest4793-21kerneloops21:26:591
1188099657654,2cyclictest4793-21kerneloops20:19:000
1188099657651,5cyclictest4793-21kerneloops20:20:590
1188099657650,5cyclictest4793-21kerneloops00:17:210
1190399656649,6cyclictest4793-21kerneloops21:43:453
1188099656652,2cyclictest4793-21kerneloops19:29:580
1188099656649,5cyclictest4793-21kerneloops22:20:020
1188099656649,5cyclictest4793-21kerneloops22:20:020
1188099656646,8cyclictest4793-21kerneloops20:06:560
1189599655650,4cyclictest4793-21kerneloops00:00:592
1189599655650,4cyclictest4793-21kerneloops00:00:582
1189599655649,5cyclictest4793-21kerneloops22:00:532
1189599655648,5cyclictest4793-21kerneloops20:35:232
1188799655652,2cyclictest4793-21kerneloops22:14:091
1188099655652,1cyclictest4793-21kerneloops22:30:560
1188099655650,3cyclictest4793-21kerneloops21:28:490
1188099655649,5cyclictest4793-21kerneloops00:25:390
1188099655648,6cyclictest4793-21kerneloops21:39:090
1188099655648,5cyclictest4793-21kerneloops20:34:190
1188099655646,7cyclictest4793-21kerneloops21:31:070
1190399654647,6cyclictest4793-21kerneloops19:36:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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