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2025-12-08 - 03:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Mon Dec 08, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
328899813803,8cyclictest4927-21kerneloops23:27:002
329399808799,7cyclictest4927-21kerneloops21:34:513
328899804793,9cyclictest4927-21kerneloops23:15:192
329399798791,5cyclictest4927-21kerneloops21:50:083
329399798790,6cyclictest4927-21kerneloops20:57:223
328199798789,7cyclictest4927-21kerneloops23:51:171
329399797790,5cyclictest4927-21kerneloops21:06:253
327599797785,10cyclictest4927-21kerneloops23:19:570
328899796787,7cyclictest4927-21kerneloops20:52:102
328899795788,5cyclictest4927-21kerneloops22:35:372
327599795785,8cyclictest4927-21kerneloops20:53:470
329399794787,5cyclictest4927-21kerneloops22:11:033
328199794787,5cyclictest4927-21kerneloops21:14:191
328199794787,5cyclictest4927-21kerneloops21:14:191
328199794786,6cyclictest4927-21kerneloops21:19:241
327599794786,6cyclictest4927-21kerneloops22:49:040
329399793787,4cyclictest4927-21kerneloops23:14:193
329399793787,4cyclictest4927-21kerneloops21:00:563
328199793785,6cyclictest4927-21kerneloops21:42:261
327599793785,6cyclictest4927-21kerneloops23:24:170
329399792783,7cyclictest4927-21kerneloops23:05:213
329399792783,7cyclictest4927-21kerneloops21:25:293
328199792789,2cyclictest4927-21kerneloops22:12:501
327599792785,5cyclictest4927-21kerneloops19:13:200
327599792784,6cyclictest4927-21kerneloops20:46:490
327599792784,6cyclictest4927-21kerneloops19:22:460
329399791786,4cyclictest4927-21kerneloops23:39:333
328199791785,5cyclictest4927-21kerneloops00:02:201
328199791783,6cyclictest4927-21kerneloops22:23:461
327599791784,6cyclictest4927-21kerneloops20:17:420
327599791784,5cyclictest4927-21kerneloops00:09:010
329399790783,5cyclictest4927-21kerneloops19:20:273
328199790787,1cyclictest4927-21kerneloops23:44:431
328199790781,7cyclictest4927-21kerneloops23:22:271
327599790784,4cyclictest4927-21kerneloops21:00:240
327599790781,7cyclictest4927-21kerneloops20:28:480
328899789782,5cyclictest4927-21kerneloops00:25:092
328899789779,8cyclictest4927-21kerneloops21:51:002
328199789786,2cyclictest4927-21kerneloops21:54:331
328199789786,2cyclictest4927-21kerneloops20:29:101
328199789781,6cyclictest4927-21kerneloops20:17:001
328199789781,6cyclictest4927-21kerneloops20:09:061
327599789781,6cyclictest4927-21kerneloops20:08:010
329399788781,5cyclictest4927-21kerneloops20:39:233
329399788780,6cyclictest4927-21kerneloops22:59:233
327599788780,6cyclictest4927-21kerneloops21:13:170
327599788780,6cyclictest4927-21kerneloops21:13:170
327599788780,6cyclictest4927-21kerneloops19:38:040
327599788779,7cyclictest4927-21kerneloops23:56:100
329399787785,1cyclictest4927-21kerneloops22:32:563
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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