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2025-10-15 - 09:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Wed Oct 15, 2025 00:44:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1891199776767,7cyclictest4927-21kerneloops23:00:182
1890499756748,6cyclictest4927-21kerneloops20:48:241
1891899755747,6cyclictest4927-21kerneloops20:25:013
1890499755747,6cyclictest4927-21kerneloops22:51:301
1891899753747,4cyclictest4927-21kerneloops20:54:513
1891899753745,6cyclictest4927-21kerneloops00:39:313
1891899753743,8cyclictest4927-21kerneloops00:04:463
1890499753746,6cyclictest4927-21kerneloops20:57:091
1889999753742,9cyclictest4927-21kerneloops21:14:330
1891899752746,5cyclictest4927-21kerneloops20:09:123
1891899752746,5cyclictest4927-21kerneloops20:09:113
1891899751748,2cyclictest4927-21kerneloops21:51:443
1891899751744,6cyclictest4927-21kerneloops21:39:383
1891899751744,5cyclictest4927-21kerneloops21:11:343
1889999751743,6cyclictest4927-21kerneloops00:33:520
1891899750747,2cyclictest4927-21kerneloops23:09:523
1891899750747,2cyclictest4927-21kerneloops23:09:513
1891899750744,5cyclictest4927-21kerneloops00:05:393
1890499750741,7cyclictest4927-21kerneloops20:34:421
1889999750743,6cyclictest4927-21kerneloops19:32:190
1891199749742,6cyclictest4927-21kerneloops23:11:142
1891199749741,6cyclictest4927-21kerneloops23:43:212
1890499749746,2cyclictest4927-21kerneloops20:16:401
1890499749741,6cyclictest4927-21kerneloops23:57:121
1890499749740,7cyclictest4927-21kerneloops00:22:171
1889999749741,6cyclictest4927-21kerneloops23:39:580
1889999749741,6cyclictest4927-21kerneloops00:13:570
1889999749740,7cyclictest4927-21kerneloops22:00:140
1891199748742,5cyclictest4927-21kerneloops20:12:552
1891199748740,6cyclictest4927-21kerneloops23:55:342
1891199748740,6cyclictest4927-21kerneloops19:43:222
1891199748740,6cyclictest4927-21kerneloops00:00:112
1890499748740,6cyclictest4927-21kerneloops22:09:521
1889999748740,6cyclictest4927-21kerneloops23:42:400
1889999748740,6cyclictest4927-21kerneloops21:29:250
1890499747745,1cyclictest4927-21kerneloops19:20:571
1890499747739,7cyclictest4927-21kerneloops23:51:251
1891199746739,5cyclictest4927-21kerneloops21:11:132
1890499746743,2cyclictest4927-21kerneloops19:11:401
1890499746742,2cyclictest4927-21kerneloops19:39:191
1890499746739,6cyclictest4927-21kerneloops23:16:571
1891899745738,5cyclictest4927-21kerneloops23:29:073
1891199745739,5cyclictest4927-21kerneloops20:19:212
1890499745737,6cyclictest4927-21kerneloops19:33:121
1889999745737,6cyclictest4927-21kerneloops23:04:240
1891899744737,5cyclictest4927-21kerneloops23:20:203
1891899744735,7cyclictest4927-21kerneloops20:12:433
1891199744740,2cyclictest4927-21kerneloops21:18:092
1891199744738,4cyclictest4927-21kerneloops23:19:262
1891199744737,5cyclictest4927-21kerneloops23:29:392
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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