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2026-01-20 - 03:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Tue Jan 20, 2026 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
62889811210,1106rtkit-daemon4793-21kerneloops19:06:462
191999586576,8cyclictest4793-21kerneloops21:18:452
192799584577,5cyclictest4793-21kerneloops23:44:123
191399584577,5cyclictest4793-21kerneloops22:39:411
191399583576,5cyclictest4793-21kerneloops21:16:481
190699583575,6cyclictest4793-21kerneloops20:53:160
192799582574,6cyclictest4793-21kerneloops22:31:393
192799582574,6cyclictest4793-21kerneloops21:55:423
192799582573,7cyclictest4793-21kerneloops23:50:273
192799582573,7cyclictest4793-21kerneloops22:45:223
191999582574,6cyclictest4793-21kerneloops21:00:382
191399582575,5cyclictest4793-21kerneloops22:32:121
191399582573,7cyclictest4793-21kerneloops23:04:191
190699582573,7cyclictest4793-21kerneloops20:30:170
192799581574,5cyclictest4793-21kerneloops19:18:153
190699581574,5cyclictest4793-21kerneloops00:09:020
192799580574,5cyclictest4793-21kerneloops19:44:483
191999580573,5cyclictest4793-21kerneloops23:35:032
191399580575,4cyclictest4793-21kerneloops20:16:391
191399580573,5cyclictest4793-21kerneloops00:03:171
190699580572,6cyclictest4793-21kerneloops23:55:450
192799579572,5cyclictest4793-21kerneloops22:03:263
192799579572,5cyclictest4793-21kerneloops20:52:323
190699579573,5cyclictest4793-21kerneloops23:07:090
190699579572,6cyclictest4793-21kerneloops23:18:300
192799578572,5cyclictest4793-21kerneloops22:44:173
191999578571,5cyclictest4793-21kerneloops20:43:532
191399578576,1cyclictest4793-21kerneloops21:40:001
191399578575,2cyclictest4793-21kerneloops21:40:541
191399578575,2cyclictest4793-21kerneloops21:40:541
191399578575,2cyclictest4793-21kerneloops20:21:251
191399578571,5cyclictest4793-21kerneloops20:57:211
191399578571,5cyclictest4793-21kerneloops00:31:101
190699578574,2cyclictest4793-21kerneloops19:39:530
190699578571,6cyclictest4793-21kerneloops22:07:490
190699578571,5cyclictest4793-21kerneloops20:04:220
190699578571,5cyclictest4793-21kerneloops20:04:210
190699578569,7cyclictest4793-21kerneloops23:12:560
192799577571,5cyclictest4793-21kerneloops23:37:183
192799577569,6cyclictest4793-21kerneloops22:24:003
190699577574,2cyclictest4793-21kerneloops19:19:380
190699577572,4cyclictest4793-21kerneloops22:35:330
190699577570,5cyclictest4793-21kerneloops19:32:260
190699577570,5cyclictest4793-21kerneloops19:13:490
192799576574,1cyclictest4793-21kerneloops23:10:323
192799576573,2cyclictest4793-21kerneloops20:36:223
192799576569,5cyclictest4793-21kerneloops21:14:383
191399576572,2cyclictest4793-21kerneloops23:07:511
191399576572,2cyclictest4793-21kerneloops21:02:451
191399576569,6cyclictest4793-21kerneloops22:51:341
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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