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2025-12-26 - 09:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Fri Dec 26, 2025 00:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2901899586571,13cyclictest4793-21kerneloops22:20:200
2901899585581,2cyclictest4793-21kerneloops00:06:310
2903799584576,6cyclictest4793-21kerneloops20:48:063
2903799582575,5cyclictest4793-21kerneloops20:10:363
2901899582573,8cyclictest4793-21kerneloops19:11:130
2901899582573,7cyclictest4793-21kerneloops22:33:060
2903799581575,4cyclictest4793-21kerneloops20:41:483
2903799581573,7cyclictest4793-21kerneloops00:12:223
2902499581575,4cyclictest4793-21kerneloops21:41:091
2902499581574,5cyclictest4793-21kerneloops21:23:081
2901899581575,5cyclictest4793-21kerneloops23:59:120
2902899580573,5cyclictest4793-21kerneloops22:01:102
2902499580572,6cyclictest4793-21kerneloops19:23:481
2901899580573,5cyclictest4793-21kerneloops20:31:520
2903799579572,5cyclictest4793-21kerneloops23:30:503
2903799579572,5cyclictest4793-21kerneloops00:16:373
2902499579570,7cyclictest4793-21kerneloops00:32:361
2901899579572,6cyclictest4793-21kerneloops22:54:010
2901899579571,7cyclictest4793-21kerneloops21:39:440
2903799578569,7cyclictest4793-21kerneloops19:24:413
2902899578572,5cyclictest4793-21kerneloops20:54:312
2902499578574,2cyclictest4793-21kerneloops00:15:541
2901899578572,5cyclictest4793-21kerneloops20:59:470
2901899578570,6cyclictest4793-21kerneloops20:27:200
2903799577574,1cyclictest4793-21kerneloops19:55:343
2903799577572,4cyclictest4793-21kerneloops23:00:263
2903799577571,4cyclictest4793-21kerneloops23:13:023
2902899577571,5cyclictest4793-21kerneloops23:26:342
2902499577574,1cyclictest4793-21kerneloops20:32:241
2902499577571,4cyclictest4793-21kerneloops23:39:511
2902499577570,5cyclictest4793-21kerneloops20:48:281
2902499577569,6cyclictest4793-21kerneloops21:00:181
2901899577570,6cyclictest4793-21kerneloops23:52:040
2902899576574,1cyclictest4793-21kerneloops19:14:142
2902899576573,2cyclictest4793-21kerneloops21:06:252
2902499576573,2cyclictest4793-21kerneloops22:26:431
2902499576573,1cyclictest4793-21kerneloops22:41:591
2901899576570,5cyclictest4793-21kerneloops19:46:260
2902899575573,1cyclictest4793-21kerneloops23:10:122
2902899575572,2cyclictest4793-21kerneloops23:04:412
2902499575572,2cyclictest4793-21kerneloops20:51:171
2901899575570,4cyclictest4793-21kerneloops23:01:310
2902499574567,6cyclictest4793-21kerneloops23:51:331
2901899574567,6cyclictest4793-21kerneloops20:52:220
2903799573570,2cyclictest4793-21kerneloops21:03:223
2903799573566,6cyclictest4793-21kerneloops00:04:213
2902499573570,2cyclictest4793-21kerneloops20:03:371
2902499573565,6cyclictest4793-21kerneloops19:57:431
2902499573565,2cyclictest4793-21kerneloops22:50:301
2901899573571,1cyclictest4793-21kerneloops23:21:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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