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2026-03-30 - 22:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Mon Mar 30, 2026 12:44:03)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
889399639630,7cyclictest4793-21kerneloops11:58:533
889399634627,6cyclictest4793-21kerneloops10:06:273
889399633626,6cyclictest4793-21kerneloops09:34:453
887699633626,5cyclictest4793-21kerneloops10:16:251
889399632626,5cyclictest4793-21kerneloops10:36:413
888799632625,5cyclictest4793-21kerneloops07:17:072
888799632624,6cyclictest4793-21kerneloops10:33:582
888799632623,7cyclictest4793-21kerneloops10:04:512
888799632623,7cyclictest4793-21kerneloops09:06:092
887699632624,6cyclictest4793-21kerneloops08:25:021
889399631625,5cyclictest4793-21kerneloops10:55:173
889399631624,6cyclictest4793-21kerneloops07:46:163
889399631623,7cyclictest4793-21kerneloops10:02:023
887699631623,6cyclictest4793-21kerneloops07:59:551
887299631624,5cyclictest4793-21kerneloops09:03:180
887699630627,2cyclictest4793-21kerneloops07:51:001
887699630622,6cyclictest4793-21kerneloops09:48:391
889399629626,2cyclictest4793-21kerneloops11:41:503
889399629623,5cyclictest4793-21kerneloops07:43:573
889399629623,5cyclictest4793-21kerneloops07:32:143
888799629622,5cyclictest4793-21kerneloops07:43:172
887699629626,1cyclictest4793-21kerneloops07:17:381
887699629625,2cyclictest4793-21kerneloops09:43:081
889399628625,2cyclictest4793-21kerneloops08:13:083
889399628622,5cyclictest4793-21kerneloops11:31:523
888799628622,5cyclictest4793-21kerneloops11:07:402
888799628622,5cyclictest4793-21kerneloops07:50:372
888799628622,4cyclictest4793-21kerneloops08:30:302
888799628622,4cyclictest4793-21kerneloops07:38:112
887299628622,5cyclictest4793-21kerneloops08:47:470
887299628622,5cyclictest4793-21kerneloops08:03:150
887299628618,8cyclictest4793-21kerneloops10:30:120
889399627621,5cyclictest4793-21kerneloops09:40:583
887699627624,2cyclictest4793-21kerneloops10:05:131
887699627623,2cyclictest4793-21kerneloops09:33:411
887699627618,7cyclictest4793-21kerneloops10:49:171
887299627619,7cyclictest4793-21kerneloops10:38:150
889399626623,2cyclictest4793-21kerneloops11:46:073
887699626624,1cyclictest4793-21kerneloops09:03:501
887699626623,2cyclictest4793-21kerneloops12:01:091
888799625617,6cyclictest4793-21kerneloops07:45:212
887699625623,1cyclictest4793-21kerneloops10:31:181
887699625617,6cyclictest4793-21kerneloops10:26:151
889399624622,1cyclictest4793-21kerneloops08:25:333
889399624621,2cyclictest4793-21kerneloops10:44:513
889399624618,5cyclictest4793-21kerneloops11:18:193
887699624619,4cyclictest4793-21kerneloops09:10:371
887299624621,2cyclictest4793-21kerneloops12:06:150
887299624617,6cyclictest4793-21kerneloops08:42:460
888799623619,2cyclictest4793-21kerneloops11:10:002
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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