You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-21 - 04:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Wed Jan 21, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1982699582576,5cyclictest4793-21kerneloops22:30:393
1982699582573,7cyclictest4793-21kerneloops00:28:183
1980999582576,5cyclictest4793-21kerneloops23:27:021
1981899581572,7cyclictest4793-21kerneloops00:09:562
1980999581575,5cyclictest4793-21kerneloops19:24:421
1980599581572,7cyclictest4793-21kerneloops23:59:420
1981899580571,7cyclictest4793-21kerneloops23:07:292
1982699579571,6cyclictest4793-21kerneloops22:41:523
1981899579573,5cyclictest4793-21kerneloops20:32:382
1981899579573,4cyclictest4793-21kerneloops19:45:072
1981899579572,5cyclictest4793-21kerneloops23:28:582
1980999579571,6cyclictest4793-21kerneloops23:45:091
1980999579571,5cyclictest4793-21kerneloops23:23:011
1980599579571,7cyclictest4793-21kerneloops19:31:180
1982699578575,2cyclictest4793-21kerneloops20:17:073
1982699578570,6cyclictest4793-21kerneloops22:13:433
1980999578574,3cyclictest4793-21kerneloops21:35:531
1980999578572,5cyclictest4793-21kerneloops19:26:161
1980599578571,5cyclictest4793-21kerneloops22:16:330
1982699577572,4cyclictest4793-21kerneloops21:47:243
1981899577571,5cyclictest4793-21kerneloops21:53:432
1980999577575,1cyclictest4793-21kerneloops23:14:021
1980999577575,1cyclictest4793-21kerneloops00:07:161
1980999577574,2cyclictest4793-21kerneloops21:30:311
1980999577572,4cyclictest4793-21kerneloops22:57:151
1980999577570,5cyclictest4793-21kerneloops23:19:211
1980599577570,5cyclictest4793-21kerneloops20:45:290
1980599577568,7cyclictest4793-21kerneloops20:35:490
1980599577567,8cyclictest4793-21kerneloops00:18:420
1981899576573,1cyclictest4793-21kerneloops21:30:202
1981899576569,5cyclictest4793-21kerneloops22:46:072
1981899576569,5cyclictest4793-21kerneloops20:18:342
1980999576574,1cyclictest4793-21kerneloops21:21:431
1980999576573,2cyclictest4793-21kerneloops23:54:491
1980999576573,2cyclictest4793-21kerneloops22:48:141
1982699575567,6cyclictest4793-21kerneloops20:28:073
1982699575565,8cyclictest4793-21kerneloops20:32:283
1981899575570,3cyclictest4793-21kerneloops19:40:142
1981899575568,6cyclictest4793-21kerneloops22:07:392
1981899575568,5cyclictest4793-21kerneloops23:19:102
1981899575566,2cyclictest4793-21kerneloops20:11:512
1981899575566,2cyclictest4793-21kerneloops20:11:502
1980999575572,2cyclictest4793-21kerneloops19:35:341
1980599575567,6cyclictest4793-21kerneloops23:07:180
1982699574568,5cyclictest4793-21kerneloops00:34:443
1981899574571,2cyclictest4793-21kerneloops20:47:552
1981899574566,6cyclictest4793-21kerneloops21:11:222
1981899574566,2cyclictest4793-21kerneloops22:53:052
1982699573567,4cyclictest4793-21kerneloops23:16:303
1982699573567,4cyclictest4793-21kerneloops20:58:583
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional