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2026-02-14 - 04:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Sat Feb 14, 2026 00:44:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3046999634627,5cyclictest4793-21kerneloops23:57:501
3046999634625,7cyclictest4793-21kerneloops00:18:111
3048599632625,5cyclictest4793-21kerneloops21:19:443
3046999632625,5cyclictest4793-21kerneloops23:54:071
3048599631627,2cyclictest4793-21kerneloops21:51:033
3046999631624,5cyclictest4793-21kerneloops20:34:561
3048599630625,4cyclictest4793-21kerneloops23:55:523
3048599630625,4cyclictest4793-21kerneloops19:51:153
3046999630624,5cyclictest4793-21kerneloops00:03:361
3048599629624,4cyclictest4793-21kerneloops21:04:163
3048599629622,5cyclictest4793-21kerneloops22:53:593
3046999629623,5cyclictest4793-21kerneloops20:10:371
3046999629623,4cyclictest4793-21kerneloops20:26:021
3046999629622,5cyclictest4793-21kerneloops22:32:421
3046999629620,7cyclictest4793-21kerneloops00:11:361
3046499629619,8cyclictest4793-21kerneloops21:00:100
3048599627620,5cyclictest4793-21kerneloops23:15:273
3047899627622,4cyclictest4793-21kerneloops19:10:102
3046999627621,5cyclictest4793-21kerneloops21:44:571
3046999627621,4cyclictest4793-21kerneloops23:26:111
3046999627621,4cyclictest4793-21kerneloops23:26:101
3046999627617,8cyclictest4793-21kerneloops21:07:361
3048599626623,2cyclictest4793-21kerneloops23:35:183
3048599626623,2cyclictest4793-21kerneloops22:04:553
3048599626623,2cyclictest4793-21kerneloops20:39:053
3048599626620,5cyclictest4793-21kerneloops19:47:043
3048599626617,7cyclictest4793-21kerneloops22:20:533
3047899626624,1cyclictest4793-21kerneloops20:52:452
3047899626623,2cyclictest4793-21kerneloops20:22:362
3047899626620,4cyclictest4793-21kerneloops21:37:242
3046499626624,1cyclictest4793-21kerneloops20:45:130
3048599625622,2cyclictest4793-21kerneloops21:35:033
3048599625622,2cyclictest4793-21kerneloops21:07:473
3048599625619,5cyclictest4793-21kerneloops23:34:583
3047899625621,2cyclictest4793-21kerneloops19:40:082
3047899625620,4cyclictest4793-21kerneloops00:35:032
3046999625620,4cyclictest4793-21kerneloops23:15:381
3046999625620,4cyclictest4793-21kerneloops19:35:071
3046499625619,4cyclictest4793-21kerneloops22:02:270
3048599624621,2cyclictest4793-21kerneloops23:44:243
3048599624617,5cyclictest4793-21kerneloops20:45:043
3048599624616,7cyclictest4793-21kerneloops21:23:033
3047899624616,7cyclictest4793-21kerneloops23:11:132
3047899624616,6cyclictest4793-21kerneloops23:38:542
3046499624622,1cyclictest4793-21kerneloops22:21:040
3046499624616,7cyclictest4793-21kerneloops22:59:250
3046499624616,7cyclictest4793-21kerneloops00:15:200
3048599623621,1cyclictest4793-21kerneloops19:43:023
3048599623621,1cyclictest4793-21kerneloops19:36:433
3048599623619,2cyclictest4793-21kerneloops23:50:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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