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2026-05-03 - 22:32
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack6slot8.osadl.org (updated Sun May 03, 2026 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2336699635627,6cyclictest4793-21kerneloops10:26:321
2336699634626,7cyclictest4793-21kerneloops09:43:191
2336699634626,6cyclictest4793-21kerneloops11:14:151
2336699633626,5cyclictest4793-21kerneloops09:27:161
2335999633625,6cyclictest4793-21kerneloops10:41:100
2335999633622,9cyclictest4793-21kerneloops10:17:520
2337199632626,4cyclictest4793-21kerneloops10:03:132
2336699632623,7cyclictest4793-21kerneloops12:09:101
2335999632621,9cyclictest4793-21kerneloops11:36:490
2337999631624,5cyclictest4793-21kerneloops12:13:273
2337999631623,6cyclictest4793-21kerneloops11:59:213
2337999631623,6cyclictest4793-21kerneloops10:22:503
2337199631625,5cyclictest4793-21kerneloops10:58:432
2336699631628,2cyclictest4793-21kerneloops07:26:211
2337999630622,6cyclictest4793-21kerneloops09:45:483
2337199630624,4cyclictest4793-21kerneloops07:51:022
2337199630623,5cyclictest4793-21kerneloops08:30:412
2335999630620,8cyclictest4793-21kerneloops08:18:320
2337999629626,2cyclictest4793-21kerneloops09:50:553
2337999629626,2cyclictest4793-21kerneloops07:38:283
2337199629624,4cyclictest4793-21kerneloops11:00:502
2337199629624,4cyclictest4793-21kerneloops07:31:112
2337199629622,5cyclictest4793-21kerneloops12:22:272
2337199629621,6cyclictest4793-21kerneloops08:23:452
2335999629620,8cyclictest4793-21kerneloops09:29:120
2337199628622,5cyclictest4793-21kerneloops10:14:282
2336699628625,2cyclictest4793-21kerneloops11:53:121
2336699628625,2cyclictest4793-21kerneloops07:58:331
2336699628621,6cyclictest4793-21kerneloops12:20:001
2336699628621,5cyclictest4793-21kerneloops11:37:311
2335999628625,2cyclictest4793-21kerneloops08:34:590
2335999628616,10cyclictest4793-21kerneloops09:37:470
2337999627622,4cyclictest4793-21kerneloops07:45:203
2337999627617,8cyclictest4793-21kerneloops09:28:203
2336699627619,6cyclictest4793-21kerneloops07:33:301
2335999627619,6cyclictest4793-21kerneloops07:40:030
2337199626623,2cyclictest4793-21kerneloops09:40:182
2336699626621,4cyclictest4793-21kerneloops07:39:521
2337999625617,6cyclictest4793-21kerneloops09:14:113
2337999625617,6cyclictest4793-21kerneloops08:04:263
2337999625615,8cyclictest4793-21kerneloops12:00:373
2337199625619,4cyclictest4793-21kerneloops07:42:532
2336699625623,1cyclictest4793-21kerneloops09:22:431
2336699625622,2cyclictest4793-21kerneloops12:39:171
2337999624620,2cyclictest4793-21kerneloops09:00:043
2337199624621,2cyclictest4793-21kerneloops09:10:392
2337199624621,2cyclictest4793-21kerneloops08:50:472
2337199624621,2cyclictest4793-21kerneloops08:50:472
2337199624618,4cyclictest4793-21kerneloops09:51:472
2336699624621,2cyclictest4793-21kerneloops10:05:531
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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