You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-06 - 14:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack7slot2.osadl.org (updated Fri Feb 06, 2026 06:45:16)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
45043099138122,7cyclictest811223-21kworker/u4:11+events_unbound06:14:001
4504309910691,6cyclictest451719-21kworker/u4:6+events_unbound05:08:481
4504299910464,19cyclictest25550irq/23-42890000.ethernet05:04:590
450429999183,6cyclictest511715-21kworker/u4:7+events_unbound05:48:560
450429998880,6cyclictest447948-21kworker/u4:1+events_unbound05:23:510
450430997767,8cyclictest455812-21kworker/u4:11+events_unbound05:43:521
450430997568,5cyclictest454403-21kworker/u4:10+events_unbound05:18:501
450429997163,6cyclictest452981-21kworker/u4:0+events_unbound05:18:470
450430996346,11cyclictest455856-21modprobe05:24:591
450429996353,8cyclictest811229-21systemd06:13:590
450430995848,6cyclictest804746-21kworker/u4:10+events_unbound06:20:021
450429995649,4cyclictest568172-21/usr/sbin/munin05:35:440
450430995546,7cyclictest794842-21expr06:05:231
450430995439,6cyclictest774328-21kworker/u4:0+events_unbound06:28:591
450429995433,17cyclictest0-21swapper/006:06:030
450429995336,15cyclictest775475-21grep06:02:290
450430995244,6cyclictest456082-21sshd05:28:501
450430995244,6cyclictest456082-21sshd05:28:501
450429995236,5cyclictest455812-21kworker/u4:11+events_unbound05:50:020
450429995236,5cyclictest455812-21kworker/u4:11+events_unbound05:50:020
450430995038,9cyclictest590787-21multi.sh05:39:331
450430995036,6cyclictest452983-21kworker/u4:4+events_unbound05:13:031
450430995034,11cyclictest815275-21modprobe06:35:011
450429995038,7cyclictest605823-21/usr/sbin/munin05:55:180
450430994942,5cyclictest454403-21kworker/u4:10+events_unbound05:33:001
450430994939,7cyclictest783848-21multi.sh06:03:441
450429994942,5cyclictest595609-21sh05:40:380
45043099483,26cyclictest605539-21fstime05:55:281
45042999484,38cyclictest0-21swapper/006:39:190
450429994839,6cyclictest811481-21sendmail06:20:000
450430994740,5cyclictest511720-21kworker/u4:8+events_unbound05:52:001
450430994740,5cyclictest511720-21kworker/u4:8+events_unbound05:52:001
450429994638,6cyclictest455812-21kworker/u4:11+events_unbound05:25:430
450429994638,6cyclictest455812-21kworker/u4:11+events_unbound05:25:430
450429994539,4cyclictest814264-21aten_r7power_en06:30:160
450430994436,6cyclictest813991-21kworker/u4:4+events_unbound06:36:141
450429994437,5cyclictest813023-21aten_r7power_po06:25:170
450429994437,5cyclictest452191-21fschecks_count05:10:210
450429994437,5cyclictest451390-21sendmail_mailqu05:05:420
450430994235,5cyclictest605063-21execl05:48:301
450430993925,6cyclictest811223-21kworker/u4:11+events_unbound06:16:461
450429993926,10cyclictest1-21systemd06:24:010
450430993831,5cyclictest450406-21cut05:05:011
450429993830,5cyclictest455812-21kworker/u4:11-rpciod05:30:290
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional