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2026-01-22 - 02:00
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot2.osadl.org (updated Wed Jan 21, 2026 12:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3825881998778,6cyclictest3961532-21kworker/u4:6+events_unbound11:15:050
3825881998438,40cyclictest0-21swapper/012:30:120
3825881998334,47cyclictest3917179-21aten_r7power_vo10:20:150
3825882997974,3cyclictest3919177-21kworker/u4:4+events_unbound10:50:001
3825881997969,8cyclictest3927788-21kworker/u4:5+events_unbound10:44:590
3825881997872,4cyclictest3932104-21kworker/u4:7+events_unbound10:39:590
3825881997638,35cyclictest3971799-21latency_hist11:25:020
3825882997571,3cyclictest3910509-21kworker/u4:2+events_unbound10:14:531
3825882997434,14cyclictest3963558-21ssh11:15:101
382588199744,11cyclictest3825854-21munin-run07:10:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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