You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-02 - 16:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot2.osadl.org (updated Mon Mar 02, 2026 12:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39324299127119,6cyclictest488640-21kworker/u4:4+events_unbound10:41:000
39324399116100,8cyclictest518996-21kworker/u4:12+events_unbound11:01:021
39324299112102,7cyclictest518996-21kworker/u4:12+events_unbound11:01:040
39324399111102,6cyclictest377969-21kworker/u4:14+events_unbound07:25:221
3932439910996,6cyclictest575452-21kworker/u4:13+events_unbound12:11:111
3932439910395,6cyclictest497493-21kworker/u4:10+events_unbound11:16:051
3932429910188,6cyclictest484160-21kworker/u4:9+events_unbound10:20:560
3932429910188,6cyclictest484160-21kworker/u4:9+events_unbound10:20:550
3932429910092,6cyclictest506423-21kworker/u4:3+events_unbound10:51:020
393242999788,7cyclictest394464-21kworker/u4:4+events_unbound08:45:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional