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2026-02-23 - 15:03
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot2.osadl.org (updated Mon Feb 23, 2026 12:44:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3350919997667,6cyclictest3372423-21kworker/u4:3+events_unbound08:40:381
3350919997161,8cyclictest3368634-21kworker/u4:4+events_unbound08:50:391
3350918996959,7cyclictest3347179-21kworker/u4:2+events_unbound07:44:590
3350919996759,6cyclictest3548310-21kworker/u4:19+events_unbound12:36:391
3350919996659,5cyclictest3372429-21kworker/u4:9+events_unbound09:20:011
3350918996254,6cyclictest3372422-21kworker/u4:2+events_unbound08:35:020
3350919996052,6cyclictest3371170-21kworker/u4:0+events_unbound08:35:381
3350919996051,6cyclictest3362236-21kworker/u4:10+events_unbound08:10:301
3350919996031,10cyclictest3413290-21ldconfig09:45:311
3350919995936,17cyclictest3481810-21ssh11:05:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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