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2026-02-16 - 11:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot2.osadl.org (updated Mon Feb 16, 2026 00:44:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1408907999890,6cyclictest1587660-21kworker/u4:6+events_unbound00:13:281
1408906999569,19cyclictest54-21kswapd022:30:090
1408906999569,19cyclictest54-21kswapd022:30:090
1408907998027,10cyclictest0-21swapper/122:10:321
1408907997870,6cyclictest1579009-21kworker/u4:11+events_unbound23:52:261
1408907997769,6cyclictest1599967-21kworker/u4:7+events_unbound00:18:311
1408906997743,31cyclictest0-21swapper/000:00:300
1408907997557,6cyclictest1442100-21kworker/u4:21+events_unbound21:26:101
1408906997429,43cyclictest1424336-21aten_r7power_vo20:10:170
1408907997336,8cyclictest1513639-21df22:35:181
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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