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2026-02-02 - 07:11
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot2.osadl.org (updated Mon Feb 02, 2026 00:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
295277899118107,7cyclictest2994452-21kworker/u4:6+events_unbound21:26:090
295277899108101,5cyclictest2953995-21kworker/u4:10+events_unbound19:36:010
29527789910698,6cyclictest3084913-21kworker/u4:9+events_unbound23:26:180
29527799910497,5cyclictest3011479-21kworker/u4:8+events_unbound22:01:101
29527799910496,6cyclictest3045649-21kworker/u4:2+events_unbound22:36:131
29527789910275,21cyclictest54-21kswapd000:25:120
29527789910194,5cyclictest3128272-21kworker/u4:5+events_unbound23:58:240
29527789910092,6cyclictest3110571-21kworker/u4:14+events_unbound23:53:140
2952778999789,6cyclictest3137084-21kworker/u4:4+events_unbound00:08:430
2952778999581,12cyclictest2953996-21kworker/u4:11+events_unbound19:21:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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