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2026-02-09 - 10:54
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot2.osadl.org (updated Mon Feb 09, 2026 00:44:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
105363997970,6cyclictest114166-21kworker/u4:6+events_unbound19:47:001
105361997643,7cyclictest119528-21aten_r7power_vo20:05:170
105361997344,10cyclictest54-21kswapd023:25:020
105361997265,5cyclictest305441-21kworker/u4:3+events_unbound00:38:470
105361997263,7cyclictest130657-21kworker/u4:11+events_unbound21:17:180
105361997257,10cyclictest4062336-21kworker/u4:2+xprtiod19:10:010
105361997162,7cyclictest120465-21kworker/u4:11+events_unbound20:22:050
105361997047,8cyclictest153465-21grep21:30:020
105363996863,3cyclictest115420-21kworker/u4:7+events_unbound20:07:041
105363996860,6cyclictest280008-21kworker/u4:4+events_unbound23:57:271
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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