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2026-02-05 - 07:16
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot2.osadl.org (updated Thu Feb 05, 2026 00:44:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2939095999890,6cyclictest2945456-21kworker/u4:12+events_unbound19:45:230
2939095999778,7cyclictest2980863-21kworker/u4:8+events_unbound21:25:440
2939095999070,6cyclictest2951841-21kworker/u4:5+events_unbound21:00:400
2939095998980,6cyclictest3033866-21kworker/u4:21+events_unbound22:25:570
2939095998979,7cyclictest3120806-21kworker/u4:5+events_unbound00:08:220
2939095998880,6cyclictest2965827-21kworker/u4:6+events_unbound20:55:390
2939096998375,6cyclictest2960777-21kworker/u4:8+events_unbound20:35:361
2939095998375,6cyclictest2946710-21kworker/u4:14+events_unbound20:45:380
2939095998374,7cyclictest3038313-21kworker/u4:23+events_unbound22:30:580
2939095998364,17cyclictest3024913-21kworker/u4:1+events_unbound22:15:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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