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2026-01-29 - 05:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot2.osadl.org (updated Thu Jan 29, 2026 00:44:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15464489910698,6cyclictest1692711-21kworker/u4:0+events_unbound23:26:351
15464489910496,5cyclictest1547750-21kworker/u4:6+events_unbound20:15:591
1546448998880,6cyclictest1609865-21kworker/u4:5+events_unbound21:56:191
1546448998778,6cyclictest1609869-21kworker/u4:9+events_unbound22:01:201
1546446998565,16cyclictest54-21kswapd022:10:080
1546448998466,6cyclictest1614334-21kworker/u4:7+events_unbound22:11:221
1546448998173,6cyclictest1575531-21kworker/u4:2+events_unbound21:16:111
1546446997959,15cyclictest1677295-21ssh23:05:010
1546448997769,5cyclictest1569205-21kworker/u4:17+events_unbound21:10:011
1546446997753,20cyclictest25550irq/23-42890000.ethernet19:10:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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