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2026-02-19 - 13:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot2.osadl.org (updated Thu Feb 19, 2026 00:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13358789910294,6cyclictest1445822-21kworker/u4:6+events_unbound22:46:071
13358789910294,6cyclictest1445822-21kworker/u4:6+events_unbound22:46:071
13358789910079,10cyclictest1337091-21kworker/u4:11-xprtiod19:35:121
1335878998171,5cyclictest1482668-21ssh23:25:291
1335877997969,8cyclictest1343487-21kworker/u4:1+events_unbound19:40:260
1335878997766,8cyclictest1343490-21kworker/u4:6+events_unbound20:20:381
1335877997666,7cyclictest1357551-21kworker/u4:5+events_unbound20:55:430
1335877997568,5cyclictest1337091-21kworker/u4:11+events_unbound19:35:260
1335878996739,24cyclictest0-21swapper/119:20:211
1335878996730,34cyclictest0-21swapper/123:05:321
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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