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2026-03-05 - 17:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot2.osadl.org (updated Thu Mar 05, 2026 12:44:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
35240799120110,8cyclictest417116-21kworker/u4:1+events_unbound10:40:171
35240699118104,10cyclictest54-21kswapd010:45:080
35240699110102,5cyclictest368960-21kworker/u4:6+events_unbound09:10:420
3524079910593,9cyclictest366421-21kworker/u4:2+events_unbound09:00:391
3524069910495,5cyclictest370229-21kworker/u4:7+events_unbound10:05:500
3524079910194,5cyclictest512029-21kworker/u4:0+events_unbound12:16:081
3524079910193,6cyclictest403609-21kworker/u4:2+events_unbound09:35:461
352407999988,8cyclictest343465-21kworker/u4:5+events_unbound07:45:191
352407999889,7cyclictest362584-21kworker/u4:1+events_unbound08:50:391
352407999889,7cyclictest343465-21kworker/u4:5+events_unbound07:55:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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