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2026-02-27 - 04:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot2.osadl.org (updated Fri Feb 27, 2026 00:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39764079910496,6cyclictest3982836-21kworker/u4:16+events_unbound21:02:200
397640899972,45cyclictest4099204-21ssh22:55:291
3976407998655,25cyclictest54-21kswapd022:40:090
3976408998375,6cyclictest4049277-21kworker/u4:5+events_unbound22:12:301
3976407998378,3cyclictest151ktimers/020:47:320
3976408997870,6cyclictest4117850-21kworker/u4:0+events_unbound23:37:411
3976408997670,4cyclictest4156496-21kworker/u4:10+events_unbound00:27:451
3976408997365,5cyclictest4143992-21kworker/u4:16+events_unbound23:47:431
3976408997264,6cyclictest4000997-21kworker/u4:26+events_unbound21:12:211
3976408997164,5cyclictest4019171-21kworker/u4:2+events_unbound21:32:231
3976408997063,5cyclictest4130892-21kworker/u4:5+events_unbound23:42:411
3976408997063,5cyclictest4130892-21kworker/u4:5+events_unbound23:42:411
3976407996860,6cyclictest4120317-21fschecks_count23:20:180
3976408996544,7cyclictest4160883-21kworker/u4:3+events_unbound00:37:471
3976408996458,4cyclictest3743422-21kworker/u4:0+events_unbound19:20:001
3976408996456,6cyclictest4117851-21kworker/u4:1+events_unbound23:17:361
3976408996152,7cyclictest4074774-21kworker/u4:4+events_unbound22:27:311
3976408996052,6cyclictest4002269-21kworker/u4:2+events_unbound20:52:191
3976407996051,5cyclictest0-21swapper/021:15:300
3976407996032,18cyclictest25550irq/23-42890000.ethernet00:30:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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