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2026-01-23 - 13:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa >
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot2.osadl.org (updated Fri Jan 23, 2026 00:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
169263699115101,6cyclictest1742815-21kworker/u4:7+events_unbound21:47:330
1692639999990,6cyclictest1747135-21kworker/u4:8+events_unbound21:37:311
1692639999284,6cyclictest1772518-21kworker/u4:5+events_unbound22:17:441
1692639999284,6cyclictest1772518-21kworker/u4:5+events_unbound22:17:441
1692639999183,6cyclictest1852476-21kworker/u4:1+events_unbound00:08:011
1692636999082,6cyclictest1693841-21kworker/u4:4+events_unbound19:27:120
1692636999076,6cyclictest1696397-21kworker/u4:5+events_unbound19:22:110
1692636998876,9cyclictest54-21kswapd023:25:100
1692636998678,6cyclictest1702801-21kworker/u4:5+events_unbound20:07:170
1692636998274,6cyclictest1698914-21kworker/u4:2+events_unbound19:32:130
1692639998173,6cyclictest1823411-21kworker/u4:4+events_unbound23:17:511
1692639998166,5cyclictest1802069-21kworker/u4:7+events_unbound22:47:471
1692639997669,5cyclictest1890029-21kworker/u4:8+events_unbound00:38:051
1692639997668,6cyclictest1763837-21kworker/u4:16+events_unbound21:57:391
1692636997669,5cyclictest1718050-21kworker/u4:12+events_unbound20:47:220
1692636997258,11cyclictest1750176-21sort21:40:370
1692636996962,5cyclictest1718048-21kworker/u4:6+events_unbound21:02:250
1692636996962,5cyclictest1715509-21kworker/u4:4+events_unbound20:37:220
1692639996862,4cyclictest1718048-21kworker/u4:6+events_unbound20:55:011
169263699687,17cyclictest1723148-21diskmemload22:50:130
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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