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2026-01-26 - 13:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot2.osadl.org (updated Mon Jan 26, 2026 00:44:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
155026999123105,15cyclictest1631442-21kworker/u4:5+events_unbound22:27:000
15502699911489,22cyclictest54-21kswapd021:25:110
15502699910797,8cyclictest1736000-21kworker/u4:2+events_unbound00:33:420
15502699910598,5cyclictest1572035-21kworker/u4:1+events_unbound20:41:370
1550269999989,7cyclictest1583277-21kworker/u4:6+events_unbound21:11:450
1550269999890,6cyclictest1618202-21kworker/u4:6+events_unbound22:01:540
1550269999486,6cyclictest1635811-21kworker/u4:15+events_unbound22:11:550
1550269999183,5cyclictest1722821-21kworker/u4:12+events_unbound23:52:240
1550269999183,5cyclictest1722821-21kworker/u4:12+events_unbound23:52:230
1550269998773,6cyclictest1691797-21kworker/u4:5+events_unbound23:17:100
1550269998679,5cyclictest1718386-21kworker/u4:8+events_unbound00:13:130
1550269998679,5cyclictest1583277-21kworker/u4:6+events_unbound21:16:450
1550269998578,5cyclictest1587797-21kworker/u4:5+events_unbound21:21:470
1550269998477,5cyclictest1601154-21kworker/u4:7+events_unbound21:51:520
1550271997825,30cyclictest0-21swapper/100:10:051
1550269997871,5cyclictest1657855-21kworker/u4:11+events_unbound22:50:010
1550271997728,28cyclictest0-21swapper/122:32:011
1550271997322,29cyclictest0-21swapper/122:50:321
1550269997364,7cyclictest1727201-21kworker/u4:5+events_unbound00:00:010
1550269997265,5cyclictest1564297-21kworker/u4:3+events_unbound20:06:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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