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2026-02-20 - 20:07
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot2.osadl.org (updated Fri Feb 20, 2026 12:44:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3371558999782,13cyclictest3382872-21kworker/u4:5+events_unbound10:00:010
3371558999687,6cyclictest3485235-21kworker/u4:10+events_unbound10:54:420
3371559999487,5cyclictest3434719-21kworker/u4:11+events_unbound09:59:361
3371559999183,6cyclictest3565217-21kworker/u4:12+events_unbound12:30:021
3371558999181,7cyclictest3519502-21kworker/u4:14+events_unbound11:34:530
3371558998476,5cyclictest3426065-21kworker/u4:4+events_unbound10:24:400
3371559998372,7cyclictest3379075-21kworker/u4:5+events_unbound07:45:001
3371558998363,15cyclictest3393264-21apt-get08:35:110
3371559997971,6cyclictest3498095-21kworker/u4:0+events_unbound11:10:001
3371559997971,6cyclictest3498095-21kworker/u4:0+events_unbound11:10:001
3371559997672,2cyclictest3498099-21kworker/u4:6+events_unbound11:04:451
3371558997668,6cyclictest3413040-21kworker/u4:9+events_unbound09:39:320
3371558997467,5cyclictest3518887-21kworker/u4:13+events_unbound11:29:540
3371559997364,7cyclictest3477287-21kworker/u4:2+events_unbound10:38:231
3371559997259,5cyclictest3501781-21kworker/u4:7+events_unbound12:20:001
3371559997259,5cyclictest3501781-21kworker/u4:7+events_unbound12:19:591
3371558997063,5cyclictest3544478-21kworker/u4:4+events_unbound12:15:010
3371559996961,6cyclictest3535940-21kworker/u4:8+events_unbound11:49:561
3371558996859,7cyclictest3477287-21kworker/u4:2+events_unbound10:39:410
3371559996548,6cyclictest3455726-21kworker/u4:1+events_unbound10:34:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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