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2026-01-22 - 00:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot2.osadl.org (updated Wed Jan 21, 2026 12:44:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3825881998778,6cyclictest3961532-21kworker/u4:6+events_unbound11:15:050
3825881998438,40cyclictest0-21swapper/012:30:120
3825881998334,47cyclictest3917179-21aten_r7power_vo10:20:150
3825882997974,3cyclictest3919177-21kworker/u4:4+events_unbound10:50:001
3825881997969,8cyclictest3927788-21kworker/u4:5+events_unbound10:44:590
3825881997872,4cyclictest3932104-21kworker/u4:7+events_unbound10:39:590
3825881997638,35cyclictest3971799-21latency_hist11:25:020
3825882997571,3cyclictest3910509-21kworker/u4:2+events_unbound10:14:531
3825882997434,14cyclictest3963558-21ssh11:15:101
382588199744,11cyclictest3825854-21munin-run07:10:010
3825881997436,35cyclictest3865814-21/usr/sbin/munin09:20:180
3825881997338,32cyclictest3835097-21aten_r7power_vo07:45:170
3825881997338,32cyclictest3835097-21aten_r7power_vo07:45:160
382588199725,60cyclictest4031964-21ssh12:35:320
3825881997139,28cyclictest3854406-21gltestperf09:00:190
3825881997138,30cyclictest3904828-21if_eth010:05:250
3825881996935,32cyclictest3831115-21aten2__07:30:150
3825881996924,41cyclictest0-21swapper/009:15:000
382588199684,11cyclictest4019128-21ssh12:20:270
3825881996824,41cyclictest0-21swapper/011:55:320
3825881996822,43cyclictest25550irq/23-42890000.ethernet11:35:130
3825882996728,16cyclictest3994872-21ssh11:51:331
382588199673,24cyclictest3861858-21ssh09:15:320
382588199672,14cyclictest3909217-21ssh10:10:280
3825882996629,12cyclictest3907193-21ssh10:08:221
3825882996628,11cyclictest3867431-21ssh09:21:491
3825881996657,6cyclictest3873783-21kworker/u4:109:30:010
3825881996642,21cyclictest3993300-21df_abs11:50:160
3825881996632,30cyclictest0-21swapper/008:15:350
3825881996631,32cyclictest3903946-21idleruntime-cro10:05:010
3825881996631,32cyclictest3903946-21idleruntime-cro10:05:010
3825882996528,13cyclictest3882383-21ssh09:39:561
3825882996528,11cyclictest3897358-21ssh09:56:171
3825882996527,15cyclictest3875989-21ssh09:31:381
3825882996527,14cyclictest4021627-21ssh12:23:501
3825882996526,15cyclictest3925081-21ssh10:29:451
3825882996526,15cyclictest3925081-21ssh10:29:441
3825882996526,14cyclictest3963242-21ssh11:14:581
3825882996526,14cyclictest3871487-21ssh09:26:211
3825882996525,11cyclictest3987207-21ssh11:42:471
3825882996524,14cyclictest3944521-21ssh10:51:531
3825882996523,15cyclictest4028352-21ssh12:30:521
382588199653,13cyclictest3879128-21ssh09:35:280
3825881996531,31cyclictest3942653-21cpu10:50:150
3825882996427,12cyclictest4024263-21ssh12:26:091
3825882996426,14cyclictest4011924-21ssh12:11:511
3825882996426,12cyclictest3864448-21ssh09:19:011
3825882996426,11cyclictest3929163-21ssh10:34:311
3825882996426,10cyclictest3978498-21ssh11:32:181
3825882996425,14cyclictest3954594-21ssh11:04:361
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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