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2026-02-04 - 11:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot2.osadl.org (updated Wed Feb 04, 2026 00:44:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
154607299119105,12cyclictest1661643-21kworker/u4:11+events_unbound23:06:370
154607299116108,6cyclictest1548539-21kworker/u4:10+events_unbound20:01:010
154607299112103,6cyclictest1670503-21kworker/u4:5+events_unbound23:01:370
15460729910787,7cyclictest1626990-21kworker/u4:3+events_unbound22:21:320
15460729910698,6cyclictest1544815-21kworker/u4:2+events_unbound19:55:590
15460729910496,6cyclictest1649094-21kworker/u4:10+events_unbound22:51:340
15460729910290,9cyclictest54-21kswapd021:55:070
1546073999890,6cyclictest1623227-21kworker/u4:0+events_unbound22:11:331
1546073999386,5cyclictest1692757-21kworker/u4:10+events_unbound23:26:411
1546072999386,5cyclictest1561182-21kworker/u4:1+events_unbound20:16:050
1546072999184,5cyclictest1561182-21kworker/u4:1+events_unbound20:26:060
1546072999172,15cyclictest54-21kswapd022:00:190
1546073998770,6cyclictest1714257-21kworker/u4:2+events_unbound00:01:481
1546072998678,6cyclictest1692102-21kworker/u4:9+events_unbound23:21:400
1546072998578,5cyclictest1544816-21kworker/u4:3+events_unbound19:50:590
1546072998476,6cyclictest1544813-21kworker/u4:0+events_unbound19:15:510
1546073998379,2cyclictest1568758-21kworker/u4:4+events_unbound21:56:281
1546073998353,16cyclictest0-21swapper/123:00:251
1546072998275,5cyclictest1544813-21kworker/u4:0+events_unbound19:20:520
1546072998275,5cyclictest1314296-21kworker/u4:13+events_unbound19:30:550
1546073998171,7cyclictest1679388-21kworker/u4:0+events_unbound23:31:421
1546073997870,6cyclictest1600353-21kworker/u4:8+events_unbound21:36:211
1546073997810,23cyclictest1704173-21ssh23:35:341
1546072997871,5cyclictest1640279-21kworker/u4:7+events_unbound22:41:350
1546073997467,5cyclictest1578701-21kworker/u4:7+events_unbound21:26:221
1546072997366,5cyclictest1549830-21kworker/u4:11+events_unbound19:25:540
1546073997061,6cyclictest1661643-21kworker/u4:11+events_unbound23:15:001
1546073996863,3cyclictest1568758-21kworker/u4:4+events_unbound20:41:101
1546073996863,3cyclictest1567501-21kworker/u4:19+events_unbound20:36:091
1546072996862,5cyclictest1556136-21kworker/u4:7+events_unbound20:06:020
1546072996762,4cyclictest1631442-21kworker/u4:2+events_unbound22:16:320
1546072996762,4cyclictest1631442-21kworker/u4:2+events_unbound22:16:320
1546072996743,18cyclictest1626990-21kworker/u4:3-xprtiod22:10:110
1546073996649,5cyclictest1536112-21kworker/u4:7+events_unbound19:35:001
1546073996558,5cyclictest1568758-21kworker/u4:4+events_unbound21:35:001
1546072996558,5cyclictest1536112-21kworker/u4:7+events_unbound19:40:560
1546072996355,5cyclictest0-21swapper/021:33:330
1546073996257,3cyclictest1562437-21kworker/u4:13+events_unbound20:21:061
1546073996254,6cyclictest1679388-21kworker/u4:0+events_unbound23:46:441
1546072996255,5cyclictest1583152-21kworker/u4:13+events_unbound21:29:590
1546072996252,8cyclictest388-21dbus-daemon00:36:560
1546072996154,5cyclictest1640279-21kworker/u4:7+events_unbound23:16:390
154607399602,52cyclictest1669214-21ssh22:55:321
1546072996053,5cyclictest1533512-21kworker/u4:5+events_unbound19:35:550
1546073995952,5cyclictest1631442-21kworker/u4:2+events_unbound22:36:341
1546073995952,5cyclictest1631442-21kworker/u4:2+events_unbound22:36:331
1546073995951,6cyclictest1608442-21/usr/sbin/munin21:45:351
1546072995952,5cyclictest1679388-21kworker/u4:0+events_unbound23:31:070
1546072995948,8cyclictest1577000-21df21:10:170
1546072995945,7cyclictest1649094-21kworker/u4:10+events_unbound22:45:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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