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2026-03-04 - 02:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot2.osadl.org (updated Tue Mar 03, 2026 12:44:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
178789799126104,8cyclictest1915715-21kworker/u4:1+events_unbound11:45:190
178789799121113,5cyclictest1885968-21kworker/u4:4+events_unbound11:10:100
17878979910999,7cyclictest54-21kswapd011:05:090
17878979910880,21cyclictest54-21kswapd012:10:090
17878979910857,42cyclictest1905196-21sh10:50:150
1787897999990,6cyclictest1821625-21kworker/u4:0+events_unbound09:14:450
1787897999885,5cyclictest1838512-21kworker/u4:2+events_unbound09:49:520
1787897998980,7cyclictest1860389-21kworker/u4:8+events_unbound10:24:580
1787897998978,5cyclictest1814931-21kworker/u4:1+events_unbound08:59:420
1787897998779,6cyclictest1834188-21kworker/u4:15+events_unbound09:34:490
1787897998779,5cyclictest1983610-21kworker/u4:7+events_unbound12:35:310
1787898998268,10cyclictest0-21swapper/112:10:101
1787897998274,6cyclictest1807197-21kworker/u4:7+events_unbound09:19:450
1787897998265,5cyclictest1834187-21kworker/u4:13+events_unbound09:54:520
1787897998265,5cyclictest1834187-21kworker/u4:13+events_unbound09:54:520
1787898997763,10cyclictest0-21swapper/111:25:121
1787897997669,5cyclictest1937334-21kworker/u4:4+events_unbound11:40:180
1787897997567,5cyclictest1828512-21gcc09:20:280
1787897997466,5cyclictest1784181-21kworker/u4:1+events_unbound07:35:010
1787897997365,6cyclictest1864148-21kworker/u4:11+events_unbound10:09:550
1787898997157,12cyclictest54-21kswapd011:35:171
1787897997163,6cyclictest1967045-21kworker/u4:0+events_unbound12:17:000
1787897997063,5cyclictest1924343-21kworker/u4:5+events_unbound11:20:120
1787897996962,5cyclictest1789115-21kworker/u4:8+events_unbound08:44:410
1787897996951,6cyclictest1907157-21kworker/u4:16+events_unbound10:55:060
1787898996662,3cyclictest271ktimers/109:31:551
1787897996659,5cyclictest1868509-21kworker/u4:12+events_unbound10:17:000
1787897996659,5cyclictest1561147-21kworker/u4:9+events_unbound07:44:260
1787898996352,9cyclictest54-21kswapd011:35:001
1787898996255,5cyclictest1808466-21kworker/u4:10+events_unbound08:35:011
1787897996255,5cyclictest1789115-21kworker/u4:8+events_unbound07:19:230
1787897996255,5cyclictest1789114-21kworker/u4:7+events_unbound08:09:320
1787897996253,7cyclictest1907156-21kworker/u4:15+events_unbound11:01:430
1787898996152,6cyclictest1897149-21kernelversion10:40:211
1787897996154,5cyclictest1789119-21kworker/u4:10+events_unbound07:14:220
1787897996153,6cyclictest1817498-21kworker/u4:14+events_unbound09:09:440
1787897996150,9cyclictest54-21kswapd012:25:060
178789899605,38cyclictest1867352-21ssh10:05:351
1787898996053,5cyclictest1789114-21kworker/u4:7+events_unbound08:05:011
1787897995942,15cyclictest1924340-21kworker/u4:0+events_unbound11:20:000
1787897995750,5cyclictest1962711-21kworker/u4:1+events_unbound12:21:590
1787897995750,5cyclictest1803346-21kworker/u4:3+events_unbound08:49:410
1787897995737,7cyclictest1967045-21kworker/u4:0+events_unbound12:02:590
178789899566,40cyclictest1849258-21ssh09:45:131
1787898995647,7cyclictest54-21kswapd010:50:011
1787897995649,5cyclictest1860389-21kworker/u4:8+events_unbound10:14:590
1787897995649,5cyclictest1784182-21kworker/u4:2+events_unbound07:55:440
1787897995648,6cyclictest1842890-21kworker/u4:3+events_unbound09:41:420
1787897995637,17cyclictest1861777-21systemd09:59:530
1787898995547,6cyclictest1983612-21kworker/u4:9+events_unbound12:25:291
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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