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2026-02-10 - 08:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot2.osadl.org (updated Tue Feb 10, 2026 00:44:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14915399910396,5cyclictest1489067-21kworker/u4:8+events_unbound19:17:140
14915399910394,7cyclictest1629046-21kworker/u4:5+events_unbound23:32:500
1491539999588,5cyclictest1504200-21kworker/u4:16+events_unbound19:57:170
1491539999274,13cyclictest54-21kswapd021:35:080
1491539998577,6cyclictest1646721-21kworker/u4:6+events_unbound23:42:510
1491539998476,6cyclictest1629046-21kworker/u4:5+events_unbound23:17:480
1491539998376,5cyclictest1500433-21kworker/u4:8+events_unbound19:52:170
1491539998164,15cyclictest1633470-21kworker/u4:10+events_unbound23:25:010
1491539998072,6cyclictest1620872-21kworker/u4:8+events_unbound23:02:470
1491539998072,6cyclictest1495302-21kworker/u4:12+events_unbound20:07:190
1491539997771,5cyclictest1489066-21kworker/u4:5+events_unbound19:27:130
1491540997568,5cyclictest1672422-21kworker/u4:5+events_unbound00:12:541
1491539997366,5cyclictest1504200-21kworker/u4:16+events_unbound20:17:190
1491539997365,6cyclictest1603262-21kworker/u4:6+events_unbound23:07:480
1491540997139,30cyclictest1584125-21interrupts22:20:231
1491540997137,32cyclictest1670672-21gltestperf00:00:211
1491540997063,5cyclictest1518102-21kworker/u4:6+events_unbound20:57:251
1491540997035,31cyclictest0-21swapper/123:50:291
1491540997032,35cyclictest0-21swapper/122:10:321
1491540997029,38cyclictest0-21swapper/121:40:151
149154099701,24cyclictest1597510-21ssh22:35:391
149154099692,22cyclictest1696978-21ntpq00:30:341
1491539996854,7cyclictest1603265-21kworker/u4:12+events_unbound22:50:590
149154099676,12cyclictest1557104-21modprobe21:50:011
149154099674,13cyclictest1610263-21ntpq22:50:251
1491540996733,31cyclictest0-21swapper/123:00:401
1491540996730,34cyclictest0-21swapper/122:30:321
1491540996729,10cyclictest1674857-21grep00:05:181
1491540996726,5cyclictest0-21swapper/122:45:271
1491539996726,34cyclictest0-21swapper/000:35:090
1491540996632,32cyclictest1700586-21aten_r7power_cu00:35:201
149154099663,17cyclictest1502488-21ntpq19:50:291
1491540996630,33cyclictest1538472-21sshd21:28:141
1491540996628,34cyclictest0-21swapper/123:55:301
1491540996628,34cyclictest0-21swapper/122:15:241
1491540996626,37cyclictest1561472-21sh21:55:011
1491540996626,36cyclictest1508095-21latency_hist20:15:021
1491539996663,2cyclictest1510539-21kworker/u4:6+events_unbound20:22:210
1491540996552,8cyclictest37-21kcompactd023:15:191
1491540996534,28cyclictest0-21swapper/120:30:221
1491540996528,32cyclictest0-21swapper/122:00:301
1491540996521,6cyclictest0-21swapper/121:39:071
1491539996558,5cyclictest1646721-21kworker/u4:6+events_unbound23:37:510
1491539996557,6cyclictest1529130-21kworker/u4:8+events_unbound21:21:430
1491540996430,31cyclictest0-21swapper/121:15:231
1491539996457,5cyclictest1663632-21kworker/u4:4+events_unbound00:00:030
1491539996419,15cyclictest54-21kswapd022:25:060
1491540996328,4cyclictest0-21swapper/122:05:271
1491540996327,3cyclictest0-21swapper/121:12:171
1491540996326,5cyclictest0-21swapper/122:27:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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