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2026-02-02 - 08:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot2.osadl.org (updated Mon Feb 02, 2026 00:44:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
295277899118107,7cyclictest2994452-21kworker/u4:6+events_unbound21:26:090
295277899108101,5cyclictest2953995-21kworker/u4:10+events_unbound19:36:010
29527789910698,6cyclictest3084913-21kworker/u4:9+events_unbound23:26:180
29527799910497,5cyclictest3011479-21kworker/u4:8+events_unbound22:01:101
29527799910496,6cyclictest3045649-21kworker/u4:2+events_unbound22:36:131
29527789910275,21cyclictest54-21kswapd000:25:120
29527789910194,5cyclictest3128272-21kworker/u4:5+events_unbound23:58:240
29527789910092,6cyclictest3110571-21kworker/u4:14+events_unbound23:53:140
2952778999789,6cyclictest3137084-21kworker/u4:4+events_unbound00:08:430
2952778999581,12cyclictest2953996-21kworker/u4:11+events_unbound19:21:000
2952778999557,32cyclictest54-21kswapd000:15:100
2952778999386,5cyclictest2998995-21kworker/u4:9+events_unbound21:31:080
2952778999362,28cyclictest54-21kswapd022:40:100
2952778999184,5cyclictest3032824-21kworker/u4:5+events_unbound22:21:120
2952778998477,4cyclictest0-21swapper/021:15:310
2952778998374,7cyclictest2966720-21kworker/u4:14+events_unbound21:46:090
2952778998275,5cyclictest3084913-21kworker/u4:9+events_unbound23:11:170
2952778998174,5cyclictest3045653-21kworker/u4:10+events_unbound22:46:150
2952779997625,46cyclictest0-21swapper/122:50:131
2952779997441,30cyclictest2952775-21cyclictest23:41:221
2952779997167,2cyclictest2953989-21kworker/u4:3+events_unbound19:26:011
295277999715,16cyclictest2988836-21ssh21:15:331
2952779997034,32cyclictest0-21swapper/122:15:231
2952779996936,30cyclictest0-21swapper/122:30:331
2952779996932,35cyclictest3143557-21aten_r7power_cu00:15:211
295277999692,23cyclictest3018799-21ntpq21:50:291
2952779996839,27cyclictest3164939-21latency_hist00:40:021
2952779996831,34cyclictest3126927-21open_files23:55:351
2952778996861,5cyclictest2964187-21kworker/u4:6+events_unbound20:11:040
2952779996749,6cyclictest3150322-21kworker/u4:11+events_unbound00:33:501
2952779996737,28cyclictest2963249-21aten_r7power_vo19:50:231
2952779996732,32cyclictest3014933-21vmstat21:45:401
295277999667,16cyclictest0-21swapper/120:00:301
295277999667,16cyclictest0-21swapper/120:00:301
2952779996659,5cyclictest3076128-21kworker/u4:9+events_unbound23:01:151
2952779996642,21cyclictest3083551-21ld23:05:321
2952778996658,6cyclictest2964188-21kworker/u4:7+events_unbound20:01:020
2952778996658,6cyclictest2964188-21kworker/u4:7+events_unbound20:01:020
295277999653,18cyclictest3048771-21ssh22:25:351
2952779996531,30cyclictest0-21swapper/123:10:361
2952779996521,5cyclictest0-21swapper/121:25:361
2952779996434,27cyclictest2983355-21latency_hist21:10:021
2952779996434,27cyclictest2952775-21cyclictest20:00:001
2952779996432,29cyclictest3121843-21aten_r7power_po23:50:161
2952779996428,32cyclictest0-21swapper/120:10:011
2952779996424,37cyclictest0-21swapper/121:35:001
2952779996420,6cyclictest0-21swapper/121:00:291
295277999641,14cyclictest3139838-21ssh00:10:291
2952779996331,28cyclictest0-21swapper/121:20:291
2952779996328,32cyclictest0-21swapper/100:25:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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