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2025-09-19 - 06:25

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot2s.osadl.org (updated Fri Sep 19, 2025 00:49:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
92123899304228,62cyclictest240-21avahi-daemon00:26:080
92123899304228,62cyclictest240-21avahi-daemon00:26:070
9212389928990,111cyclictest967582-21/usr/sbin/munin23:15:120
9212389928990,111cyclictest967582-21/usr/sbin/munin23:15:120
92123899282186,81cyclictest981514-21kworker/u10:8-events_unbound00:22:080
92123899282186,81cyclictest981514-21kworker/u10:8-events_unbound00:22:080
92123899270152,83cyclictest926239-21systemd-userwor19:41:560
92123899270152,83cyclictest926239-21systemd-userwor19:41:560
92123899269170,52cyclictest171rcu_preempt19:36:040
92123899269162,65cyclictest171rcu_preempt20:12:000
92123899269159,72cyclictest959911-21kworker/u10:5-rpciod23:48:190
92123899269159,72cyclictest959911-21kworker/u10:5-rpciod23:48:190
92123899268187,51cyclictest171rcu_preempt19:30:350
92123899268175,74cyclictest949308-21kworker/u9:7+rpciod23:01:140
92123899268163,50cyclictest171rcu_preempt22:37:060
92123899268163,50cyclictest171rcu_preempt22:37:060
92123899267160,68cyclictest171rcu_preempt19:17:080
92123899267160,68cyclictest171rcu_preempt19:17:070
92123899267160,66cyclictest171rcu_preempt23:36:080
92123899266164,67cyclictest980228-21ssh00:15:260
92123899266163,65cyclictest0-21swapper/022:35:070
92123899266163,65cyclictest0-21swapper/022:35:060
92123899266130,102cyclictest0-21swapper/022:47:120
92123899266130,102cyclictest0-21swapper/022:47:110
92123899265168,50cyclictest171rcu_preempt21:07:060
92123899265168,50cyclictest171rcu_preempt21:07:060
92123899265150,77cyclictest984416-21ssh00:35:260
92123899265150,77cyclictest984416-21ssh00:35:260
92123899265116,113cyclictest0-21swapper/021:55:490
92123899265116,113cyclictest0-21swapper/021:55:490
92123899264164,66cyclictest171rcu_preempt21:11:390
92123899264164,66cyclictest171rcu_preempt21:11:390
92123899263177,51cyclictest171rcu_preempt20:25:550
92123899263157,92cyclictest368-21rs:main0
92123899262156,90cyclictest0-21swapper/022:41:150
92123899262156,90cyclictest0-21swapper/022:41:140
92123899261119,92cyclictest0-21swapper/022:26:310
92123899261119,92cyclictest0-21swapper/022:26:310
92123899261111,92cyclictest0-21swapper/020:20:050
92123899261111,92cyclictest0-21swapper/020:20:040
92123899261104,96cyclictest943992-21sh21:24:010
92123899261104,96cyclictest943992-21sh21:24:010
92123899260133,72cyclictest939934-21kworker/u9:7+rpciod21:40:130
92123899260124,117cyclictest940807-21diskmemload21:34:050
92123899260124,117cyclictest940807-21diskmemload21:34:050
92123899260113,112cyclictest0-21swapper/000:31:400
92123899260102,102cyclictest952591-21sh22:04:490
92123899260102,102cyclictest952591-21sh22:04:490
92123899259176,52cyclictest171rcu_preempt19:46:220
92123899259176,52cyclictest171rcu_preempt19:46:220
92123899259171,59cyclictest171rcu_preempt20:00:020
92123899259171,59cyclictest171rcu_preempt20:00:020
92123899258177,51cyclictest171rcu_preempt00:07:100
92123899258177,51cyclictest171rcu_preempt00:07:100
92123899258162,64cyclictest14-21ksoftirqd/021:20:070
92123899258162,64cyclictest14-21ksoftirqd/021:20:070
92123899258109,98cyclictest9150irq/87-eth%d23:31:260
92123899257177,50cyclictest171rcu_preempt23:51:140
92123899257177,50cyclictest171rcu_preempt23:51:140
92123899257175,51cyclictest171rcu_preempt19:20:360
92123899257162,67cyclictest171rcu_preempt22:11:300
92123899257162,67cyclictest171rcu_preempt22:11:300
92123899256177,52cyclictest171rcu_preempt19:11:390
92123899256177,52cyclictest171rcu_preempt19:11:390
92123899256104,89cyclictest946680-21ntpq21:36:190
92123899256104,89cyclictest946680-21ntpq21:36:190
9212389925595,103cyclictest0-21swapper/021:26:520
9212389925595,103cyclictest0-21swapper/021:26:520
92123899255134,89cyclictest0-21swapper/021:02:440
92123899255134,89cyclictest0-21swapper/021:02:440
9212389925498,105cyclictest973602-21kworker/u9:13+rpciod23:55:520
9212389925498,105cyclictest973602-21kworker/u9:13+rpciod23:55:520
92123899254122,68cyclictest0-21swapper/020:20:420
92123899254122,68cyclictest0-21swapper/020:20:420
92123899253167,53cyclictest171rcu_preempt20:35:470
92123899253167,53cyclictest171rcu_preempt20:35:470
92123899253160,49cyclictest171rcu_preempt20:41:240
92123899253128,71cyclictest0-21swapper/023:20:490
92123899253113,92cyclictest953111-21ldconfig22:06:240
92123899253113,92cyclictest953111-21ldconfig22:06:230
92123899252172,50cyclictest171rcu_preempt19:10:070
92123899252169,51cyclictest965778-21ntpq23:06:240
92123899252167,55cyclictest171rcu_preempt20:01:290
92123899252167,55cyclictest171rcu_preempt20:01:290
92123899252156,51cyclictest171rcu_preempt22:16:590
92123899252156,51cyclictest171rcu_preempt22:16:590
92123899252140,97cyclictest0-21swapper/020:45:500
92123899252140,97cyclictest0-21swapper/020:45:500
92123899252101,95cyclictest0-21swapper/022:51:220
92123899252101,95cyclictest0-21swapper/022:51:220
92123899251169,51cyclictest171rcu_preempt20:33:020
92123899251169,51cyclictest171rcu_preempt20:33:010
92123899251123,107cyclictest935484-21kworker/u10:10-rpciod20:56:330
92123899251123,107cyclictest935484-21kworker/u10:10-rpciod20:56:330
92123899250139,96cyclictest0-21swapper/000:01:130
92123899250139,96cyclictest0-21swapper/000:01:120
92123999249167,48cyclictest0-21swapper/120:02:021
92123999249167,48cyclictest0-21swapper/120:02:021
92123899249160,73cyclictest0-21swapper/022:20:370
92123899249156,50cyclictest171rcu_preempt19:50:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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