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2026-03-22 - 15:08

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot2s.osadl.org (updated Sun Mar 22, 2026 12:49:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
397713199275158,80cyclictest0-21swapper/012:01:530
397713199275158,80cyclictest0-21swapper/012:01:530
397713199272163,77cyclictest171rcu_preempt10:40:200
397713199269172,57cyclictest171rcu_preempt07:41:020
397713199268153,78cyclictest353-21ntpd08:01:160
397713199267179,54cyclictest171rcu_preempt12:10:330
397713199267179,54cyclictest171rcu_preempt12:10:320
397713199267173,60cyclictest171rcu_preempt11:15:070
397713199267173,60cyclictest171rcu_preempt11:15:070
397713199266178,56cyclictest171rcu_preempt09:15:300
397713199264178,54cyclictest171rcu_preempt12:30:520
397713199264178,54cyclictest171rcu_preempt12:30:520
397713199263157,91cyclictest0-21swapper/010:45:580
397713199262169,53cyclictest171rcu_preempt08:56:130
397713199262169,53cyclictest171rcu_preempt08:56:120
397713199261156,70cyclictest0-21swapper/011:27:020
397713199260177,53cyclictest171rcu_preempt10:35:080
397713199260157,66cyclictest0-21swapper/007:51:580
397713199260157,66cyclictest0-21swapper/007:51:570
397713199260149,76cyclictest171rcu_preempt10:15:420
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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