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2025-10-17 - 05:29

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot2s.osadl.org (updated Fri Oct 17, 2025 00:48:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
316939099302112,95cyclictest3180971-21ntpq20:21:280
316939099285101,92cyclictest0-21swapper/000:21:050
316939099285101,92cyclictest0-21swapper/000:21:050
316939099283140,104cyclictest3193065-21sshd21:34:200
316939099283140,104cyclictest3193065-21sshd21:34:200
316939099281136,106cyclictest0-21swapper/022:09:080
31693909927982,100cyclictest0-21swapper/023:26:070
316939099278143,86cyclictest3217007-21kworker/u9:3+xprtiod23:56:200
316939099275162,78cyclictest3199646-21kworker/u9:13+rpciod22:25:550
316939099275162,78cyclictest3199646-21kworker/u9:13+rpciod22:25:550
31693909927467,104cyclictest3213332-21rm23:10:060
316939099273138,77cyclictest3182962-21kworker/u9:4+xprtiod21:00:350
316939099272148,77cyclictest171rcu_preempt20:31:500
316939099272148,77cyclictest171rcu_preempt20:31:500
316939099272137,81cyclictest171rcu_preempt20:26:520
316939099272137,81cyclictest171rcu_preempt20:26:520
316939099270135,101cyclictest3184639-21kworker/u10:2+rpciod21:20:350
316939099270135,101cyclictest3184639-21kworker/u10:2+rpciod21:20:350
31693909926981,95cyclictest0-21swapper/000:17:000
31693909926981,95cyclictest0-21swapper/000:16:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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