You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-08 - 09:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #7, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot2s.osadl.org (updated Sun Mar 08, 2026 00:48:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
251942699282170,78cyclictest2519385-21kworker/u10:4+rpciod19:11:180
251942699282170,78cyclictest2519385-21kworker/u10:4+rpciod19:11:170
251942699275140,84cyclictest2566243-21kworker/u9:13+xprtiod23:30:070
251942699275140,84cyclictest2566243-21kworker/u9:13+xprtiod23:30:070
25194269927497,79cyclictest151ktimers/021:12:490
25194269927497,79cyclictest151ktimers/021:12:480
251942699273152,83cyclictest14-21ksoftirqd/021:20:170
251942699273152,83cyclictest14-21ksoftirqd/021:20:160
251942699272164,72cyclictest2554758-21sh22:20:140
251942699271142,79cyclictest2576600-21kworker/u9:8-rpciod00:02:030
251942699271142,79cyclictest2576600-21kworker/u9:8-rpciod00:02:030
251942699270173,63cyclictest171rcu_preempt23:48:040
251942699269150,82cyclictest2581678-21/usr/sbin/munin00:25:350
25194269926774,86cyclictest2570870-21ssh23:35:330
251942699267166,68cyclictest171rcu_preempt21:32:590
251942699267166,68cyclictest171rcu_preempt21:32:590
251942699266171,61cyclictest171rcu_preempt20:51:490
251942699266171,61cyclictest171rcu_preempt20:51:490
251942699265157,75cyclictest0-21swapper/020:21:480
251942699265157,75cyclictest0-21swapper/020:21:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional