You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-11-08 - 06:43

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #7, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot2s.osadl.org (updated Sat Nov 08, 2025 00:49:02)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
324496999270154,100cyclictest0-21swapper/022:50:000
324496999270154,100cyclictest0-21swapper/022:49:590
324496999263144,83cyclictest3274979-21irqstats21:55:500
324496999263144,83cyclictest3274979-21irqstats21:55:490
324496999262131,115cyclictest0-21swapper/023:14:530
324496999262131,115cyclictest0-21swapper/023:14:530
324496999261112,133cyclictest3284979-21tr22:42:080
324496999261112,133cyclictest3284979-21tr22:42:080
324496999261105,140cyclictest722-21snmpd20:15:010
324496999260159,87cyclictest0-21swapper/000:20:440
324496999260159,87cyclictest0-21swapper/000:20:440
324496999260146,98cyclictest0-21swapper/022:05:540
324496999260146,98cyclictest0-21swapper/022:05:530
324496999258163,83cyclictest3297462-21ntp_kernel_pll_23:41:200
324496999258163,83cyclictest3297462-21ntp_kernel_pll_23:41:200
324496999258153,89cyclictest391-21cron19:17:000
324496999258153,89cyclictest391-21cron19:17:000
324496999258148,92cyclictest0-21swapper/000:37:020
324496999258148,92cyclictest0-21swapper/000:37:020
324496999258138,51cyclictest3284229-21sendmail-msp22:40:010
324496999258138,51cyclictest3284229-21sendmail-msp22:40:010
324496999257135,105cyclictest0-21swapper/020:20:010
324496999257127,113cyclictest0-21swapper/000:10:490
324496999256161,79cyclictest0-21swapper/022:21:390
324496999256157,82cyclictest0-21swapper/000:07:140
324496999256157,82cyclictest0-21swapper/000:07:140
324496999254154,85cyclictest0-21swapper/020:31:130
324496999254140,91cyclictest3305429-21kworker/u10:0-rpciod00:30:030
324496999254105,132cyclictest3292170-21ntpq23:16:290
324496999254105,132cyclictest3292170-21ntpq23:16:290
324497099253136,74cyclictest0-21swapper/121:17:051
324496999253153,84cyclictest717-21lldpd00:03:110
324496999253153,84cyclictest717-21lldpd00:03:110
324496999253153,84cyclictest0-21swapper/023:30:510
324496999253153,84cyclictest0-21swapper/023:30:500
324496999253140,54cyclictest171rcu_preempt19:20:160
324496999252151,83cyclictest0-21swapper/021:12:030
324496999252151,83cyclictest0-21swapper/021:12:020
324496999252116,69cyclictest3251941-21/usr/sbin/munin19:50:430
324496999252116,69cyclictest3251941-21/usr/sbin/munin19:50:430
324496999251198,40cyclictest0-21swapper/019:56:450
324496999251198,40cyclictest0-21swapper/019:56:450
324496999251151,86cyclictest3298584-21ntpq23:46:390
324496999251134,102cyclictest9150irq/87-eth%d21:02:030
324496999251134,102cyclictest9150irq/87-eth%d21:02:030
324496999251129,81cyclictest3262112-21kworker/u9:10+rpciod21:15:210
324496999251127,96cyclictest3259540-21sed20:35:530
324496999251127,96cyclictest3259540-21sed20:35:530
324496999251127,57cyclictest171rcu_preempt00:30:480
324496999251127,57cyclictest171rcu_preempt00:30:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional