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2025-10-19 - 14:23

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot2s.osadl.org (updated Sun Oct 19, 2025 00:48:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
393277899326129,106cyclictest0-21swapper/000:26:580
393277899324178,105cyclictest0-21swapper/000:00:010
393277899324178,105cyclictest0-21swapper/000:00:010
393277899317119,107cyclictest0-21swapper/023:45:590
393277899317119,107cyclictest0-21swapper/023:45:590
393277899312168,104cyclictest0-21swapper/023:12:000
393277899312168,104cyclictest0-21swapper/023:12:000
393277899310171,100cyclictest0-21swapper/000:19:570
393277899310165,107cyclictest0-21swapper/021:30:560
393277899309169,100cyclictest0-21swapper/021:46:170
393277899309169,100cyclictest0-21swapper/021:46:170
393277899309168,103cyclictest0-21swapper/023:31:280
393277899306168,99cyclictest0-21swapper/022:02:090
393277899306168,99cyclictest0-21swapper/022:02:090
393277899306168,101cyclictest0-21swapper/000:01:030
393277899306168,101cyclictest0-21swapper/000:01:030
393277899306163,102cyclictest0-21swapper/000:22:020
393277899305182,87cyclictest171rcu_preempt21:50:510
393277899305182,87cyclictest171rcu_preempt21:50:510
393277899305161,104cyclictest0-21swapper/022:27:000
393277899305161,104cyclictest0-21swapper/022:27:000
393277899305129,134cyclictest0-21swapper/000:35:470
393277899303165,99cyclictest0-21swapper/021:56:570
393277899303165,99cyclictest0-21swapper/021:56:570
393277899303162,102cyclictest0-21swapper/022:30:370
393277899303162,102cyclictest0-21swapper/022:30:370
393277899303161,102cyclictest0-21swapper/021:40:460
393277899303161,102cyclictest0-21swapper/021:40:450
393277899301159,104cyclictest0-21swapper/021:16:380
393277899301159,104cyclictest0-21swapper/021:16:380
393277899301131,120cyclictest0-21swapper/019:41:400
393277899301131,120cyclictest0-21swapper/019:41:400
393277899300159,103cyclictest0-21swapper/021:11:510
393277899300159,103cyclictest0-21swapper/021:11:510
393277899299162,97cyclictest0-21swapper/022:05:410
393277899299162,97cyclictest0-21swapper/022:05:410
393277899299160,101cyclictest0-21swapper/021:10:010
393277899299160,101cyclictest0-21swapper/021:10:000
393277899298161,100cyclictest0-21swapper/022:45:080
393277899298161,100cyclictest0-21swapper/022:45:080
393277899298156,104cyclictest0-21swapper/023:01:580
393277899298156,104cyclictest0-21swapper/023:01:580
393277899298153,88cyclictest171rcu_preempt23:36:330
393277899297167,90cyclictest171rcu_preempt21:22:000
393277899297167,90cyclictest171rcu_preempt21:22:000
393277899297156,98cyclictest0-21swapper/021:28:540
393277899297156,98cyclictest0-21swapper/021:28:540
393277899296175,83cyclictest171rcu_preempt23:52:550
393277899296172,87cyclictest171rcu_preempt23:25:340
393277899296172,87cyclictest171rcu_preempt23:25:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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