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2026-06-07 - 22:33

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot2s.osadl.org (updated Sat Jun 06, 2026 00:48:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
225524399275170,70cyclictest0-21swapper/020:40:360
225524399261177,52cyclictest2292936-21grep22:31:250
225524399260145,81cyclictest0-21swapper/023:15:490
225524399260145,81cyclictest0-21swapper/023:15:490
225524399258163,57cyclictest0-21swapper/021:25:450
225524399257163,78cyclictest151ktimers/022:59:230
225524399257163,78cyclictest151ktimers/022:59:230
225524399256169,56cyclictest0-21swapper/021:10:000
225524399256169,56cyclictest0-21swapper/021:10:000
225524399254167,54cyclictest0-21swapper/020:20:470
225524399252165,41cyclictest171rcu_preempt23:20:120
225524399252161,75cyclictest716-21lldpd20:10:320
225524399251158,59cyclictest171rcu_preempt21:00:060
225524399251146,90cyclictest2301491-21ntp_offset23:11:270
225524399250158,57cyclictest171rcu_preempt00:37:120
225524399250158,57cyclictest171rcu_preempt00:37:110
225524399249182,36cyclictest171rcu_preempt19:22:050
225524399249176,42cyclictest171rcu_preempt19:31:470
225524399249176,42cyclictest171rcu_preempt19:31:470
225524399249152,76cyclictest2295549-21kworker/u10:3-rpciod22:55:080
225524399249152,76cyclictest2295549-21kworker/u10:3-rpciod22:55:070
225524399249120,114cyclictest0-21swapper/023:57:020
225524399248164,56cyclictest2269025-21sed20:31:120
225524399248160,55cyclictest171rcu_preempt23:29:210
225524399248155,78cyclictest0-21swapper/023:05:570
225524399248155,78cyclictest0-21swapper/023:05:570
225524399247181,36cyclictest171rcu_preempt23:50:190
225524399247181,36cyclictest171rcu_preempt23:50:190
225524399247177,37cyclictest171rcu_preempt00:31:200
225524399247161,39cyclictest171rcu_preempt23:41:080
225524399247161,39cyclictest171rcu_preempt23:41:080
225524399246176,40cyclictest171rcu_preempt19:55:460
225524399246176,40cyclictest171rcu_preempt19:55:450
225524399246158,60cyclictest712-21lldpd22:20:030
225524399246144,88cyclictest2299215-21kernelversion23:00:460
225524399244175,41cyclictest171rcu_preempt22:02:000
225524399244173,41cyclictest171rcu_preempt22:15:060
225524399244173,41cyclictest171rcu_preempt22:15:060
225524399244158,57cyclictest171rcu_preempt21:01:110
225524399244158,57cyclictest171rcu_preempt21:01:110
225524399244151,78cyclictest0-21swapper/021:21:520
225524399244151,78cyclictest0-21swapper/021:21:520
225524399244119,109cyclictest0-21swapper/020:16:430
225524399243165,60cyclictest0-21swapper/000:20:020
225524399243159,63cyclictest2285904-21kworker/u9:10+rpciod22:25:010
225524399241164,41cyclictest171rcu_preempt00:26:580
225524399241161,48cyclictest171rcu_preempt21:16:010
225524399241161,48cyclictest171rcu_preempt21:16:010
225524399240170,40cyclictest171rcu_preempt00:05:070
225524399240169,42cyclictest171rcu_preempt20:55:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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