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2025-09-16 - 16:29

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot2s.osadl.org (updated Tue Sep 16, 2025 12:48:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
416902899331191,101cyclictest0-21swapper/009:45:580
416902899331191,101cyclictest0-21swapper/009:45:580
416902899321196,88cyclictest19174-21ntpq11:06:100
416902899319184,98cyclictest0-21swapper/011:00:000
416902899319184,98cyclictest0-21swapper/011:00:000
416902899314179,99cyclictest0-21swapper/011:45:450
416902899314179,99cyclictest0-21swapper/011:45:450
416902899301166,98cyclictest0-21swapper/010:51:460
416902899301166,98cyclictest0-21swapper/010:51:460
416902899301157,108cyclictest0-21swapper/007:15:350
416902899301157,108cyclictest0-21swapper/007:15:350
416902899299166,96cyclictest0-21swapper/009:55:020
416902899297121,129cyclictest0-21swapper/008:35:000
416902899297121,129cyclictest0-21swapper/008:35:000
416902899295163,94cyclictest0-21swapper/009:42:080
416902899295163,94cyclictest0-21swapper/009:42:080
416902899295162,98cyclictest0-21swapper/009:16:010
416902899295162,98cyclictest0-21swapper/009:16:010
416902899294179,81cyclictest171rcu_preempt08:36:120
416902899294135,110cyclictest5151-21ntp_states09:56:470
416902899294135,110cyclictest5151-21ntp_states09:56:460
416902899293174,85cyclictest171rcu_preempt11:57:060
416902899293174,85cyclictest171rcu_preempt11:57:060
416902899292161,94cyclictest0-21swapper/011:21:240
416902899292161,94cyclictest0-21swapper/011:21:240
416902899292125,130cyclictest0-21swapper/010:47:120
416902899292125,130cyclictest0-21swapper/010:47:110
416902899291164,79cyclictest171rcu_preempt08:40:100
416902899291164,79cyclictest171rcu_preempt08:40:090
416902899291150,96cyclictest171rcu_preempt09:05:510
416902899291150,96cyclictest171rcu_preempt09:05:500
416902899291147,95cyclictest0-21swapper/007:36:240
416902899291147,95cyclictest0-21swapper/007:36:240
416902899290150,93cyclictest171rcu_preempt08:26:590
416902899289130,111cyclictest0-21swapper/008:05:490
416902899289130,111cyclictest0-21swapper/008:05:490
416902899288158,94cyclictest0-21swapper/012:25:350
416902899288127,103cyclictest0-21swapper/008:20:510
416902899288125,118cyclictest4171575-21latency_hist07:25:050
416902999287178,53cyclictest0-21swapper/109:55:591
416902999287178,53cyclictest0-21swapper/109:55:591
416902899287182,79cyclictest171rcu_preempt09:00:000
416902899287182,79cyclictest171rcu_preempt09:00:000
416902899287161,89cyclictest4170702-21kworker/u9:9+rpciod07:47:020
416902899287161,81cyclictest0-21swapper/010:22:000
416902899287161,81cyclictest0-21swapper/010:22:000
416902899287148,94cyclictest0-21swapper/011:12:350
416902899287124,101cyclictest0-21swapper/009:30:550
416902899287124,101cyclictest0-21swapper/009:30:550
416902899287112,126cyclictest25247-21sh11:35:230
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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