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2026-01-18 - 05:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot2.osadl.org (updated Sun Jan 18, 2026 00:44:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
318913099110102,6cyclictest3292804-21kworker/u4:12+events_unbound22:52:581
31891299910193,6cyclictest3361146-21kworker/u4:10+events_unbound00:13:110
3189130999788,6cyclictest3258932-21kworker/u4:14+events_unbound21:57:451
3189129998881,5cyclictest3238025-21kworker/u4:9+events_unbound21:32:400
3189130998779,6cyclictest3284814-21kworker/u4:1+events_unbound22:32:511
3189129998349,31cyclictest3307732-21latency_hist22:55:020
318912999733,23cyclictest3224001-21ssh21:15:360
318912999724,19cyclictest3245159-21ssh21:40:340
3189129996962,5cyclictest3382136-21kworker/u4:14+events_unbound00:23:110
3189129996860,6cyclictest3280517-21kworker/u4:4+events_unbound22:22:480
3189129996838,28cyclictest3317399-21cat23:05:380
318912999683,21cyclictest3333407-21ssh23:25:110
3189130996759,6cyclictest3218493-21kworker/u4:7+events_unbound21:07:311
3189129996635,29cyclictest3195621-21aten2__19:35:170
3189129996633,30cyclictest3328853-21ssh23:20:000
3189129996633,30cyclictest0-21swapper/021:55:220
3189129996630,33cyclictest0-21swapper/023:55:320
3189130996556,6cyclictest3271857-21kworker/u4:10+events_unbound22:20:011
3189129996527,34cyclictest3363769-21/usr/sbin/munin00:00:260
318912999652,16cyclictest3389461-21ssh00:31:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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