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2026-03-04 - 10:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot2.osadl.org (updated Wed Mar 04, 2026 00:44:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2482769999279,10cyclictest54-21kswapd000:35:110
2482769999279,10cyclictest54-21kswapd000:35:110
2482769999129,45cyclictest25550irq/23-42890000.ethernet20:15:080
2482771998777,7cyclictest2618461-21kworker/u4:10+events_unbound23:17:301
2482769998459,20cyclictest54-21kswapd022:30:090
2482771998271,8cyclictest54-21kswapd023:15:001
2482771997938,7cyclictest0-21swapper/123:25:261
2482771997764,9cyclictest0-21swapper/122:45:371
2482769997661,6cyclictest0-21swapper/000:10:110
2482771997061,6cyclictest2558219-21kworker/u4:17+events_unbound22:02:081
2482771996949,14cyclictest2654651-21latency_hist23:55:011
2482769996943,20cyclictest2592980-21kworker/u4:6-rpciod22:45:150
2482771996859,6cyclictest2481497-21kworker/u4:4+events_unbound19:26:421
248276999682,8cyclictest2487408-21sshd19:25:310
2482769996558,5cyclictest2618462-21kworker/u4:12+events_unbound23:37:320
2482771996453,8cyclictest2592980-21kworker/u4:6+events_unbound23:32:311
2482769996454,8cyclictest2588581-21kworker/u4:8+events_unbound22:52:280
2482769996425,13cyclictest2488040-21apt-get19:30:130
2482771996355,5cyclictest2472826-21kworker/u4:17+events_unbound19:41:461
2482769996232,10cyclictest2552873-21ntpq21:55:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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