You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-08 - 10:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Sun Feb 08, 2026 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1283274619sleep1284-21ps19:04:050
188799253191cyclictest20526-21latency_hist22:43:550
188799248222cyclictest29752-21fschecks_time23:19:380
188799247217cyclictest4320-21date21:39:180
188799246217cyclictest32649-21diskmemload21:23:110
188799246217cyclictest15881-21idleruntime20:09:140
188799244217cyclictest14672-21fschecks_count20:04:040
188799244211cyclictest24950-21latency23:00:140
188799244180cyclictest23842-21proc_pri22:55:440
188799244178cyclictest11335-21ssh22:06:070
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional