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2026-02-24 - 02:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Tue Feb 24, 2026 00:44:53)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218232141415sleep21820-21cut19:03:160
2280099262237cyclictest1114-21sh22:12:170
2280099259230cyclictest2726-21lxpanel20:15:090
2280099259194cyclictest22530-21munin-node0
2280099256227cyclictest29269-21sed19:34:390
2280099255229cyclictest2726-21lxpanel00:11:200
2280099254226cyclictest27195-21ssh21:46:390
2280099253224cyclictest25908-21ssh23:51:100
2280099252229cyclictest2857-21fschecks_time00:29:170
2280099250224cyclictest21116-21ssh23:32:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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