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2026-02-15 - 10:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Sun Feb 15, 2026 00:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21181242415sleep21182-21grep19:03:560
2172899247219cyclictest22937-21latency_hist23:43:520
2172899246221cyclictest31571-21cpuspeed00:18:360
2172899246221cyclictest1521-21cpu00:28:310
2172899244216cyclictest29624-21munin-node0
2172899243217cyclictest21948-21munin-node0
2172899243178cyclictest26898-21ssh23:59:090
2172899242213cyclictest1827-21if_err_eth022:19:400
2172899242211cyclictest16673-21df_inode21:08:580
2172899241216cyclictest25616-21perl21:44:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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