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2026-01-25 - 08:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Sun Jan 25, 2026 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
794299269241cyclictest17551-21munin-run22:09:110
794299269239cyclictest12673-21df_inode23:59:420
79429926375cyclictest12812-21if_eth019:29:420
794299263236cyclictest5776-21ntpq21:21:190
794299263231cyclictest2642-21diskmemload23:50:300
794299259227cyclictest9348-21ssh21:35:400
794299259227cyclictest19151-21sleep00:25:410
794299258229cyclictest16967-21latency_hist19:49:000
794299258225cyclictest25014-21munin-run22:38:540
794299257233cyclictest17819-21netwatch00:20:300
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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