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2026-02-23 - 13:12
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Mon Feb 23, 2026 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
660799256227cyclictest10350-21ssh23:56:230
660799255226cyclictest20791-21munin-node0
660799253226cyclictest28298-21munin-run22:58:230
660799251219cyclictest11436-21uniq21:49:060
660799250225cyclictest17278-21ssh22:13:390
660799249221cyclictest7044-21ssh23:43:070
660799249221cyclictest30887-21ssh23:08:270
660799249217cyclictest11341-21chrt19:28:390
660799247220cyclictest25584-21ssh22:46:380
660799246222cyclictest741-21sendmail23:18:040
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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