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2026-02-25 - 23:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Wed Feb 25, 2026 12:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
227272171514sleep22730-21latencyplot07:07:560
2279199274134cyclictest2853-21chrt08:03:050
2279199265132cyclictest14202-21munin-node0
2279199256136cyclictest24205-21perl09:34:180
2279199256133cyclictest3576-21runrttasks12:30:580
2279199255133cyclictest25621-21munin-node0
227919925494cyclictest4332-21if_err_eth008:08:450
2279199245124cyclictest31471-21cpuspeed12:13:160
2279199243125cyclictest29593-21processes09:55:280
24906224214sleep24907-21mailstats11:45:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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