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2026-03-04 - 17:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Wed Mar 04, 2026 12:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9652232419sleep9654-21unixbench_singl07:03:310
1009299237207cyclictest14814-21ssh09:46:540
1009299236190cyclictest5301-21df_inode11:18:280
1009299235172cyclictest16474-21ssh09:53:460
1009299233172cyclictest19137-21if_eth010:04:150
1009299232206cyclictest15414-21cat11:57:540
1009299231202cyclictest22991-21ssh12:28:510
1009299231166cyclictest29644-21ssh10:46:100
1009299230203cyclictest23636-21munin-node0
1009299229205cyclictest11792-21ssh11:43:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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