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2026-02-18 - 11:29
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Wed Feb 18, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13940279021sleep13941-21timerandwakeup19:03:550
144059926370cyclictest8210-21df_inode21:03:430
1440599263235cyclictest31618-21sshd22:40:170
144059925751cyclictest15290-21munin-node0
144059925667cyclictest2927-21ntpdc20:39:310
1440599256231cyclictest19023-21chrt19:28:290
1440599255226cyclictest21671-21sort21:59:370
1440599255225cyclictest27465-21runrttasks22:24:020
1440599254230cyclictest25458-21munin-node0
1440599254229cyclictest2317-21munin-node0
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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