You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-16 - 21:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Fri Jan 16, 2026 12:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
278502135918sleep27848-21zcat07:04:430
2848599240210cyclictest24989-21ssh11:25:390
2848599236210cyclictest23364-21ssh11:17:200
2848599236207cyclictest11569-21missed_timers10:31:020
2848599235210cyclictest2834-21snmpd09:23:380
2848599233209cyclictest3013-21sendmail-mta09:58:200
2848599233208cyclictest19811-21ssh11:03:230
2848599232208cyclictest6615-21sh12:21:190
2848599231205cyclictest32537-21munin-node0
2848599229159cyclictest7530-21df07:59:300
2848599228202cyclictest2064-21ssh12:03:330
2848599228198cyclictest7011-21ssh10:12:410
2848599228198cyclictest29243-21ssh11:41:420
2848599227202cyclictest15540-21tune2fs08:34:380
2848599227197cyclictest3352-21ssh12:07:590
2848599227168cyclictest3903-21ssh12:10:140
2848599227163cyclictest2953-21runrttasks09:09:570
2848599226199cyclictest10045-21ssh12:35:150
2848599225198cyclictest21287-21ssh11:09:230
2848599224199cyclictest955-21cpu11:59:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional