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2026-03-04 - 12:49
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Wed Mar 04, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
306802104919sleep30678-21gzip19:03:250
3129699267102cyclictest16688-21sh22:38:030
3129699265233cyclictest2953-21runrttasks00:33:170
3129699262233cyclictest10511-21sh22:13:390
3129699260231cyclictest29886-21wc21:22:580
3129699259234cyclictest1896-21netwatch23:47:160
3129699259228cyclictest26947-21ssh21:10:350
3129699258230cyclictest21546-21munin-node0
3129699257227cyclictest32623-21ssh21:33:330
3129699256224cyclictest6284-21munin-node0
312969925488cyclictest11112-21ssh22:15:360
3129699254228cyclictest27522-21processes23:20:070
3129699254224cyclictest20972-21ntp_offset20:43:590
3129699254223cyclictest27805-21if_eth021:14:140
312969925394cyclictest23842-21cpu20:57:590
3129699253227cyclictest20779-21diskmemload22:53:510
3129699253226cyclictest8456-21ssh22:05:070
3129699252227cyclictest15790-21netwatch20:21:330
3129699252224cyclictest23989-21ssh23:05:440
3129699252221cyclictest7166-21munin-node0
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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