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2026-01-14 - 09:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Wed Jan 14, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4849238019sleep4850-21sshd19:05:450
523699272101cyclictest30666-21ssh23:11:240
523699260136cyclictest16547-21grep00:25:110
523699255129cyclictest11678-21netwatch00:05:040
52369925491cyclictest26275-21latency_hist22:54:420
523699253131cyclictest32067-21ssh23:17:170
18283223417sleep18286-21cut20:05:370
523699232206cyclictest12674-21munin-node0
523699232166cyclictest2862-21cut23:30:090
523699231107cyclictest2726-21lxpanel23:45:060
523699226196cyclictest5118-21df_inode21:30:030
15409222620sleep15411-21sh00:20:230
523699225201cyclictest12920-21kworker/u2:200:34:460
523699225199cyclictest18337-21ssh22:23:070
523699224201cyclictest4849-21ssh21:28:580
523699224199cyclictest29709-21ssh23:07:390
523699224197cyclictest7688-21munin-node0
523699224157cyclictest11835-21perl00:05:270
523699224152cyclictest11446-21sort21:54:590
523699223198cyclictest6569-21ssh21:35:240
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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