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2026-02-27 - 16:51
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Fri Feb 27, 2026 12:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
25436284019sleep25433-21cat07:03:250
2620199263238cyclictest6668-21chrt10:18:460
2620199259229cyclictest28576-21cpu09:38:080
262019925899cyclictest24705-21cpuspeed09:23:110
2620199257227cyclictest19863-21latency11:09:400
2620199256232cyclictest9840-21munin-run12:38:140
2620199256230cyclictest31912-21cpuspeed07:33:090
2620199255224cyclictest5146-21ssh10:12:320
2620199255106cyclictest12143-21ssh10:39:340
262019925487cyclictest31427-21processes11:55:130
2620199254230cyclictest11370-21chrt10:36:270
2620199254229cyclictest30276-21ssh11:50:300
2620199254225cyclictest23517-21rm11:24:270
262019925397cyclictest21639-21ssh11:17:090
2620199253222cyclictest4160-21latency_hist10:08:420
2620199253106cyclictest20632-21timerandwakeup09:04:340
2620199252222cyclictest2726-21lxpanel09:45:220
2620199252219cyclictest28101-21munin-node0
262019925194cyclictest27797-21ntpq07:14:030
2620199251226cyclictest32016-21sh09:50:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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