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2026-02-19 - 13:58
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Thu Feb 19, 2026 00:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29391287720sleep29392-21df19:03:230
3045899264238cyclictest4776-21df_inode00:03:470
3045899261228cyclictest21600-21netwatch20:50:340
304589926085cyclictest25194-21munin-run21:08:210
3045899260233cyclictest31809-21sshd21:34:150
3045899260205cyclictest17226-21rm22:44:440
304589925951cyclictest16143-21latency_hist20:28:310
304589925871cyclictest7850-21runrttasks22:06:580
3045899258233cyclictest30469-21forks21:29:070
3045899257231cyclictest27659-21processes23:25:270
3045899257108cyclictest4276-21munin-run21:53:280
3045899257101cyclictest2953-21runrttasks19:24:230
3045899256221cyclictest21749-21ssh23:02:210
304589925545cyclictest6283-21if_err_eth000:09:300
3045899255227cyclictest13656-21munin-node0
3045899255106cyclictest4983-21ssh21:55:260
3045899254226cyclictest8548-21rm22:09:490
304589925394cyclictest340-21latency_hist19:18:350
304589925289cyclictest2505-21rm21:46:010
304589925289cyclictest17415-21date20:33:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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