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2026-01-17 - 22:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Sat Jan 17, 2026 12:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1773499261234cyclictest25299-21fschecks_time10:00:220
1773499259233cyclictest14935-21munin-node0
1773499256225cyclictest28669-21munin-node0
1773499254229cyclictest17673-21ssh09:30:050
177349925348cyclictest14069-21ssh11:25:480
177349925247cyclictest2834-21snmpd11:36:040
1773499252221cyclictest2994-21chrt10:40:380
1773499252220cyclictest32319-21munin-run10:29:300
1773499251222cyclictest12496-21diskmemload12:30:120
1773499251192cyclictest10100-21cpu11:09:190
1773499249223cyclictest1099-21munin-node0
1773499249221cyclictest24507-21ssh09:56:560
1773499249217cyclictest8119-21df08:49:250
1773499248220cyclictest22454-21latency_hist11:59:540
1773499248219cyclictest13561-21diskmemload11:24:040
1773499248218cyclictest16392-21df_inode09:25:030
1773499247223cyclictest26968-21netwatch10:06:360
1773499247222cyclictest2726-21lxpanel12:00:510
1773499247205cyclictest17732-21cyclictest11:54:380
177349924661cyclictest12463-21df11:19:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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