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2026-03-04 - 00:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Tue Mar 03, 2026 12:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20152264321sleep20151-21munin-node0
2107599238214cyclictest29979-21runrttasks10:04:270
2107599237170cyclictest16505-21ssh09:09:590
2107599235210cyclictest20687-21ssh11:35:350
2107599234208cyclictest21960-21rm09:32:360
2107599231206cyclictest3429-21ssh12:36:100
2107599231206cyclictest13814-21df_inode11:08:350
2107599230207cyclictest4507-21ping08:17:290
2107599230205cyclictest18591-21munin-run11:28:040
2107599230170cyclictest10473-21tune2fs08:43:250
12563223015sleep12564-21cpuspeed08:53:020
2107599229206cyclictest14737-21munin-node0
2107599229203cyclictest2953-21runrttasks10:23:380
2107599229201cyclictest20682-21ssh09:27:190
2107599229166cyclictest5686-21munin-run08:22:510
2107599229162cyclictest29690-21chrt12:12:240
2107599228202cyclictest1548-21rt-features10:20:130
2107599228199cyclictest6076-21runrttasks10:38:110
2107599228197cyclictest6445-21sshd10:39:150
2107599227202cyclictest31609-21ssh12:19:530
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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