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2026-03-06 - 03:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Fri Mar 06, 2026 00:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4882242320sleep491-21mailstats19:03:250
102399266238cyclictest16481-21mailstats20:14:130
102399265235cyclictest7044-21proc_pri00:05:030
102399264234cyclictest10201-21runrttasks00:18:450
102399261200cyclictest32763-21munin-node0
102399252221cyclictest31351-21grep21:20:150
102399251202cyclictest12222-21sort22:14:460
10239924964cyclictest2494-21ssh23:47:200
102399249224cyclictest23410-21chrt22:59:360
102399249224cyclictest16887-21diskmemload22:33:520
102399249224cyclictest11078-21sh22:10:050
102399249223cyclictest20228-21ssh22:47:130
102399249221cyclictest5110-21munin-run23:57:470
10239924870cyclictest30386-21df_inode23:28:300
102399248224cyclictest28756-21sh21:09:250
102399248223cyclictest3067-21chrt21:37:300
102399248220cyclictest29015-21munin-node0
102399248219cyclictest20961-21missed_timers22:49:480
102399248216cyclictest28232-21diskmemload22:33:220
102399248204cyclictest1755-21ssh21:32:410
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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