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2026-02-22 - 15:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Sun Feb 22, 2026 12:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28445297821sleep28444-21cut07:03:190
26889223713sleep26890-21sh11:27:570
2941999231206cyclictest1851-21munin-run11:58:330
2941999231205cyclictest30729-21df11:43:330
2941999230207cyclictest22854-21ssh11:10:490
2941999230205cyclictest2953-21runrttasks09:40:290
2941999230205cyclictest25842-21df_inode11:23:520
26804223019sleep26805-21latency_hist09:18:480
2941999229168cyclictest13355-21munin-node0
2941999228204cyclictest743-21df11:53:370
2941999228164cyclictest21664-21ping11:06:200
2941999227196cyclictest6625-21munin-node0
2941999226202cyclictest12473-21ps10:30:220
2941999226160cyclictest28364-21df_inode11:33:560
2941999225200cyclictest10353-21awk12:30:400
2941999225199cyclictest6721-21munin-run10:08:070
2941999225164cyclictest17555-21ssh10:50:160
2941999225161cyclictest4849-21perl12:09:160
32499222415sleep32498-21sed07:19:440
2941999224199cyclictest9252-21rm10:18:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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