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2026-01-14 - 02:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Tue Jan 13, 2026 12:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26480227621sleep26478-21sort07:04:280
2745099262231cyclictest18188-21cpu08:54:190
2745099257190cyclictest6387-21/usr/sbin/munin07:59:220
2745099255230cyclictest28028-21ssh09:36:180
2745099255227cyclictest9823-21latency_hist10:34:480
2745099253224cyclictest1030-21munin-node0
2745099252226cyclictest11404-21munin-node0
2745099250222cyclictest32463-21df_inode09:54:520
2745099249220cyclictest21552-21diskmemload10:59:190
2745099249215cyclictest5871-21ssh12:27:580
2745099247219cyclictest24898-21ssh09:24:090
2745099246215cyclictest2726-21lxpanel12:12:480
2745099246213cyclictest29814-21latency_hist11:54:540
2745099245220cyclictest4119-21runrttasks10:10:450
2745099245220cyclictest2726-21lxpanel12:35:560
2745099245216cyclictest10445-21df_inode08:19:380
2745099245184cyclictest13892-21ssh10:50:030
2745099244218cyclictest21552-21diskmemload10:19:570
2745099244215cyclictest26431-21ssh11:40:140
2745099244214cyclictest30059-21ssh09:44:550
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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