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2026-02-23 - 14:52
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Mon Feb 23, 2026 12:44:38)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14141284825sleep14142-21cat07:08:080
1416799264243cyclictest20412sleep08:38:040
1416799255121cyclictest19142-21irqstats09:49:400
1416799255120cyclictest0-21swapper08:56:360
1416799255114cyclictest2824-21find08:39:320
1416799254127cyclictest341-21fschecks_count10:44:050
141679925269cyclictest13893-21sort11:39:100
1416799252123cyclictest24494-21df_inode07:53:280
1416799252116cyclictest2726-21lxpanel12:11:560
1416799252113cyclictest23851-21ssh10:08:380
1416799252111cyclictest10974-21chrt09:16:220
1416799252110cyclictest15931-21ssh09:36:440
1416799251100cyclictest32484-21/usr/sbin/munin10:43:270
1416799250124cyclictest21953-21chrt10:00:250
1416799250119cyclictest29490-21sshd08:14:290
1416799250118cyclictest24746-21sh12:22:540
1416799250110cyclictest9949-21ssh11:23:290
1416799249102cyclictest21115-21munin-run12:08:040
141679924884cyclictest15082-21latency_hist09:33:330
1416799248120cyclictest27349-21timerandwakeup08:04:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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