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2026-01-14 - 23:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Wed Jan 14, 2026 12:44:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15933247025sleep15934-21cat07:04:380
1666499265239cyclictest2726-21lxpanel08:37:480
1666499265238cyclictest318072sleep08:15:120
1666499263129cyclictest29869-21netwatch10:24:410
1666499260233cyclictest28098-21ssh10:16:530
1666499260103cyclictest23423-21ssh12:07:180
1666499259128cyclictest15318-21sh09:24:570
1666499259110cyclictest17245-21sh09:33:570
166649925889cyclictest20419-21memory09:46:090
1666499257109cyclictest2844-21if_eth010:45:400
1666499253126cyclictest12015-21kernelversion09:11:010
1666499253125cyclictest28147-21sh07:59:400
166649925297cyclictest8844-21df_inode11:09:490
166649925290cyclictest23857-21kernelversion07:40:110
166649925191cyclictest17582-21netwatch07:11:530
1666499251113cyclictest27542-21ssh12:25:010
1666499250121cyclictest23644-21ssh09:59:230
1666499250114cyclictest26079-21munin-run12:19:270
166649924997cyclictest26834-21egrep07:54:180
166649924973cyclictest3525-21munin-run08:34:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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