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2026-01-16 - 08:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Fri Jan 16, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15580250725sleep15581-21cpu19:04:150
1663399279252cyclictest29984-21sendmail_mailst00:31:320
1663399261105cyclictest31872-21ping00:39:400
1663399260233cyclictest10807-21diskmemload23:14:490
1663399260112cyclictest13313-21entropy23:25:020
1663399259231cyclictest12940-21sh23:23:220
1663399258226cyclictest27271-21missed_timers19:55:120
1663399257231cyclictest20669-21df_inode23:54:540
166339925694cyclictest11423-21diskmemload21:55:430
166339925595cyclictest2954-21netwatch20:16:390
166339925288cyclictest28177-21netwatch22:15:360
1663399252118cyclictest14533-21sh21:21:170
1663399252103cyclictest27215-21sh00:20:500
1663399251224cyclictest2726-21lxpanel20:49:150
1663399251120cyclictest11179-21netwatch21:05:510
166339925091cyclictest2834-21snmpd20:02:520
1663399250113cyclictest17498-21sh23:41:260
1663399250111cyclictest7843-21ssh23:02:440
1663399249222cyclictest27044-21ssh22:11:060
1663399249222cyclictest15721-21latency_hist23:34:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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