You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-06 - 07:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Thu Feb 05, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2245099261226cyclictest15762-21if_eth023:09:590
2245099261113cyclictest1773-21ls19:59:420
2245099259230cyclictest25429-21cpuspeed23:48:510
2245099259226cyclictest8140-21sh22:40:110
2245099259104cyclictest31879-21grep19:49:280
2245099258226cyclictest2953-21runrttasks20:58:090
224509925789cyclictest4061-21sh00:32:090
2245099257110cyclictest25718-21grep23:49:460
224509925675cyclictest1816-21ssh22:15:120
2245099256224cyclictest28992-21fschecks_count21:54:360
2245099255224cyclictest16910-21fschecks_count23:14:380
2245099254227cyclictest22276-21egrep21:28:430
2245099254227cyclictest21995-21ssh23:34:470
2245099253226cyclictest2726-21lxpanel21:42:400
2245099253220cyclictest2676-21df_inode20:03:590
224509925287cyclictest10796-21netwatch20:39:200
2245099252226cyclictest20950-21sh21:23:290
2245099252101cyclictest19409-21ssh21:16:590
224509925189cyclictest27949-21latency_hist23:59:260
2245099251226cyclictest5412-21fschecks_count22:29:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional