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2026-01-15 - 06:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Thu Jan 15, 2026 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2611199259194cyclictest5916-21cpu00:29:200
2611199251225cyclictest22895-21chrt21:16:430
2611199244217cyclictest11750-21ssh22:41:500
2611199244213cyclictest13134-21ssh22:47:350
2611199243214cyclictest1658-21df19:44:260
2611199243149cyclictest29790-21df_inode23:54:510
2611199242213cyclictest22235-21sh21:14:350
2611199241216cyclictest9880-21sh22:34:580
2611199241216cyclictest6189-21latency_hist20:04:170
2611199241216cyclictest10748-21cpu20:24:190
2611199241174cyclictest22779-21memory23:25:570
2611199241162cyclictest20912-21latency_hist23:19:490
2611199240215cyclictest26880-21sh21:33:100
2611199240214cyclictest30186-21load21:46:000
2611199240212cyclictest3828-21chrt00:20:290
2611199239214cyclictest9077-21ssh22:31:190
2611199239175cyclictest7029-21munin-run00:34:150
2611199238212cyclictest28727-21sh23:49:540
2611199238210cyclictest8417-21latency_hist20:14:290
2611199238210cyclictest7145-21ssh22:24:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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