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2026-03-02 - 20:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Mon Mar 02, 2026 12:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
69299251222cyclictest11478-21sh12:19:410
69299247214cyclictest27932-21diskmemload10:58:520
69299246214cyclictest13160-21ssh10:18:080
69299245218cyclictest16872-21munin-run10:33:070
69299244220cyclictest2726-21lxpanel11:55:460
69299244216cyclictest31081-21ssh11:29:110
69299244213cyclictest13881-21ping08:04:090
69299243220cyclictest685-21cyclictest10:52:360
69299243218cyclictest8713-21sh12:08:460
69299242214cyclictest20244-21rm10:45:200
69299242212cyclictest7349-21kernelversion09:54:350
69299242212cyclictest26038-21ls08:58:440
69299242176cyclictest3739-21sendmail_mailqu07:19:170
69299240215cyclictest15361-21runrttasks08:11:120
69299240212cyclictest2953-21runrttasks07:54:020
69299240176cyclictest15823-21ls08:13:340
69299240173cyclictest913-21chrt09:29:370
69299240170cyclictest28092-21wc09:08:250
69299239215cyclictest4000-21ssh09:41:210
69299239215cyclictest23107-21sed08:44:250
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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