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2026-03-01 - 08:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Sun Mar 01, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1541399276146cyclictest17988-21cpu22:23:080
1541399262137cyclictest3698-21runrttasks21:24:560
154139926189cyclictest31902-21diskmemload22:25:410
1541399257125cyclictest6932-21diskmemload21:38:410
1541399246121cyclictest14183-21netwatch00:18:110
154139923670cyclictest9134-21sh23:57:510
1541399233166cyclictest9142-21munin-run21:48:020
1541399225160cyclictest13425-21ssh22:04:300
1541399224202cyclictest20737-21ssh22:33:550
1541399224194cyclictest2953-21runrttasks19:29:070
154139922354cyclictest7213-21uname23:49:300
1541399223197cyclictest4554-21df_inode21:28:510
1541399223155cyclictest15163-21ssh00:21:460
1541399222155cyclictest27378-21memory22:59:450
1541399221197cyclictest21447-21chrt19:51:170
1541399221196cyclictest2953-21runrttasks23:24:100
1541399221195cyclictest11990-21rm00:08:580
1541399220191cyclictest10468-21rm21:53:070
1541399219192cyclictest467-21latency_hist23:23:440
1541399219156cyclictest31035-21chrt23:14:190
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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