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2026-01-30 - 02:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Fri Jan 30, 2026 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6927246319sleep6925-21head19:04:280
736299266237cyclictest17712-21fschecks_count19:54:170
736299253225cyclictest10720-21munin-run19:23:500
736299250222cyclictest19904-21rm00:29:480
736299250219cyclictest13716-21irqstats21:55:240
736299249221cyclictest2726-21lxpanel00:07:390
736299249217cyclictest15875-21munin-run00:13:510
736299247216cyclictest27581-21ssh22:50:340
736299247185cyclictest19823-21perl22:20:010
736299246217cyclictest6715-21ssh23:36:220
736299246177cyclictest21285-21ssh22:25:450
736299245218cyclictest8437-21munin-run19:13:470
736299244211cyclictest21942-21munin-node0
736299244177cyclictest7164-21df_inode21:29:420
736299243176cyclictest18447-21latency_hist22:14:270
736299242217cyclictest26706-21diskmemload22:46:580
736299242214cyclictest16750-21ssh22:07:240
736299242212cyclictest4484-21cpu21:18:590
736299242175cyclictest25922-21df_inode22:44:250
736299241216cyclictest24448-21ssh22:38:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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