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2026-01-25 - 00:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Sat Jan 24, 2026 12:44:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30663286619sleep30661-21sed07:04:380
3107399264136cyclictest2726-21lxpanel11:58:530
3107399260106cyclictest3962-21ssh09:51:000
310739925694cyclictest8800-21interrupts10:10:200
3107399256126cyclictest32284-21if_eth011:45:150
310739925592cyclictest1173-21if_eth009:40:180
3107399255127cyclictest19397-21ssh10:52:170
3107399255123cyclictest8492-21ssh12:19:380
3107399254112cyclictest13266-21ssh12:38:120
3107399253130cyclictest25135-21apt-get11:16:130
3107399252233cyclictest31062sleep09:47:480
3107399252123cyclictest25977-21grep09:09:240
3107399252120cyclictest317-21processes07:15:130
3107399250122cyclictest21337-21munin-node0
3107399250116cyclictest9575-21/usr/sbin/munin12:24:170
310739924974cyclictest10163-21cut12:25:380
3107399248116cyclictest16088-21sed10:39:440
3107399247120cyclictest2726-21lxpanel11:37:450
3107399247117cyclictest3930-21ping12:00:470
3107399246119cyclictest2376-21rs:main0
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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