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2026-01-29 - 02:15
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Thu Jan 29, 2026 00:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18644292511sleep18646-21modprobe19:04:160
193759926274cyclictest2726-21lxpanel23:33:430
1937599262237cyclictest20624-21ssh21:34:110
1937599262235cyclictest21610-21munin-node0
1937599261231cyclictest3692-21head20:20:260
1937599259235cyclictest11440-21chrt23:04:410
1937599257231cyclictest31522-21chrt20:00:330
1937599256232cyclictest24401-21munin-run21:49:000
1937599256231cyclictest27523-21ssh22:00:230
1937599256230cyclictest13017-21munin-node0
193759925580cyclictest10714-21munin-node0
1937599253228cyclictest7138-21ssh22:48:060
193759925291cyclictest22342-21sendmail_mailst23:46:220
1937599252228cyclictest868-21ntp_kernel_pll_00:30:500
1937599252228cyclictest13303-21sh23:11:090
193759925193cyclictest1312-21runrttasks20:10:370
193759925186cyclictest10910-21latency_hist20:54:080
1937599251223cyclictest28867-21rm00:13:180
1937599251223cyclictest24903-21ping21:50:150
1937599250221cyclictest24196-1kworker/0:2H00:08:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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