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2026-02-22 - 02:59
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Sun Feb 22, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
194332100222sleep19436-21cpu19:03:120
2052299271243cyclictest17926-21latency_hist23:28:500
2052299257192cyclictest25291-21cpuspeed21:48:250
2052299254210cyclictest14984-21ssh23:16:240
2052299253225cyclictest27445-21latency_hist19:38:290
2052299252182cyclictest31561-21munin-node0
2052299250223cyclictest2726-21lxpanel20:27:210
2052299248223cyclictest31842-21sh00:24:040
2052299247184cyclictest2002-21chrt22:24:360
2052299246217cyclictest15285-21diskmemload00:33:570
2052299246182cyclictest11348-21ssh23:01:000
2052299245220cyclictest14496-21runrttasks21:03:500
2052299245218cyclictest726-21fschecks_count20:03:410
2052299244219cyclictest10885-21df20:48:240
2052299244217cyclictest19890-21sshd23:36:190
2052299243182cyclictest2822-21latency_hist20:13:240
2052299243178cyclictest26619-21cpu00:03:190
2052299242220cyclictest397-21df_inode22:18:460
2052299242217cyclictest30266-21munin-run22:08:040
2052299242217cyclictest2953-21runrttasks22:29:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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