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2026-01-15 - 19:01
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Thu Jan 15, 2026 12:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
494199269134cyclictest10208-21sshd12:00:010
494199264119cyclictest25591-21sendmail_mailst10:51:330
494199261135cyclictest19638-21munin-run10:29:180
3925225415sleep3922-21cut07:04:220
494199253130cyclictest2975-21runrttasks09:21:380
494199253121cyclictest3669-21munin-run11:34:210
49419925290cyclictest21503-21diskmemload10:35:560
494199252125cyclictest12200-21cpu09:59:170
49419925195cyclictest13860-21interrupts10:05:320
494199249122cyclictest31564-21sh11:15:310
49419924891cyclictest13736-21diskmemload12:13:560
494199248123cyclictest7984-21munin-node0
494199248123cyclictest28432-21chrt08:51:110
494199247120cyclictest12193-21cat07:40:170
494199245120cyclictest6015-21netwatch07:14:070
494199245119cyclictest516-21ssh11:21:220
494199245116cyclictest22248-21if_eth008:24:550
494199244121cyclictest24249-21processes10:46:250
494199244119cyclictest29868-21cpu08:59:210
49419924386cyclictest21615-21netwatch08:20:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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