You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-22 - 21:42
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Thu Jan 22, 2026 12:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1903244217sleep1902-21wc07:09:030
19109926198cyclictest4562-21missed_timers09:40:160
191099261233cyclictest20762-21rt-features08:30:160
191099261131cyclictest14692-21latency_hist10:24:240
19109925892cyclictest2726-21lxpanel11:25:030
191099258102cyclictest30927-21df_inode11:34:470
191099257131cyclictest9599-21apt10:04:070
191099257111cyclictest14538-21latency_hist08:04:080
191099257109cyclictest9015-21chrt12:15:400
191099256101cyclictest29150-1diskmemload12:07:220
191099253129cyclictest29021-21chrt09:07:150
191099253119cyclictest24252-21netwatch11:07:080
19109925280cyclictest6140-21ssh09:50:050
191099250128cyclictest22812-21ssh11:01:250
191099250126cyclictest22028-21cpu10:59:070
191099250124cyclictest10705-21netwatch07:45:290
191099250121cyclictest12194-21latency_hist07:54:040
191099250120cyclictest1231-21runrttasks09:27:140
191099250119cyclictest29700-21ssh11:29:510
191099248118cyclictest27243-21fschecks_count11:20:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional