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2026-02-21 - 02:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Sat Feb 21, 2026 00:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2928289220sleep2929-21egrep19:08:130
300299261236cyclictest5253-21ssh23:53:140
30029925745cyclictest1668-21ssh21:24:500
30029925651cyclictest31224-21munin-run21:13:240
300299255229cyclictest12791-21ssh22:10:250
300299253223cyclictest1614-21cpu23:38:190
30029925253cyclictest11397-21df_inode00:18:550
300299252221cyclictest15251-21chrt20:01:510
300299251224cyclictest24715-21fschecks_time22:59:160
300299250224cyclictest32459-21egrep21:18:250
300299250222cyclictest27326-21ssh23:09:480
300299250221cyclictest2865-21/usr/sbin/munin23:43:330
300299250219cyclictest27951-21latency_hist20:58:340
300299249221cyclictest23754-21ssh22:55:110
300299248224cyclictest26737-21latency_hist20:53:200
300299248221cyclictest8767-21ssh00:07:430
300299247223cyclictest3657-21munin-run21:33:230
300299247222cyclictest18535-21perl22:34:260
300299247214cyclictest9729-21munin-node0
300299246220cyclictest6160-21df21:43:270
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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