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2026-02-28 - 17:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Sat Feb 28, 2026 12:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
11682232724sleep11680-21vmstat07:03:420
1208899238174cyclictest14515-21chrt07:18:270
1208899235210cyclictest15376-21ssh09:42:300
1208899234173cyclictest19786-21chrt09:59:560
1208899233206cyclictest12957-21munin-run09:33:120
1208899232207cyclictest11079-21ssh09:24:480
1208899232205cyclictest27118-21munin-node0
1208899232202cyclictest26162-21sh12:34:450
1208899231203cyclictest26673-21munin-node0
1208899231166cyclictest10301-21ssh11:30:570
1208899231165cyclictest13775-21ps09:35:210
1208899230204cyclictest6836-21diskmemload12:26:240
1208899230204cyclictest14494-21df_inode11:48:420
1208899230202cyclictest2726-21lxpanel09:09:380
1208899229204cyclictest21678-21/usr/sbin/munin10:08:190
1208899229204cyclictest12209-21ssh11:39:050
1208899229202cyclictest32413-21ssh10:49:560
1208899229199cyclictest5047-21chrt11:09:320
1208899229199cyclictest14285-21munin-run11:48:030
1208899229197cyclictest27344-21ssh10:30:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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