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2026-02-16 - 12:53
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack7slot3.osadl.org (updated Mon Feb 16, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
874099284264cyclictest295112sleep22:53:000
874099271147cyclictest21330-21ssh22:20:010
874099259134cyclictest23443-21latency_hist22:29:030
874099256123cyclictest24914-21if_eth020:19:070
874099254123cyclictest9488-21timerandwakeup19:09:510
87409925286cyclictest19399-21sh00:23:020
874099252130cyclictest20737-21munin-node00:28:220
874099250126cyclictest12453-21if_err_eth019:24:010
87409924991cyclictest17262-21processes19:44:360
87409924982cyclictest2726-21lxpanel23:30:160
874099249127cyclictest14502-21sh21:51:550
87409924885cyclictest3018-21rt-features21:04:390
87409924784cyclictest25763-21netwatch22:38:180
874099247109cyclictest2282-21ssh23:13:430
87409924590cyclictest429-21memory20:54:170
874099233171cyclictest22673-21sed20:09:110
874099231169cyclictest27016-21munin-run22:43:150
874099230204cyclictest20936-21latency_hist22:18:530
874099229163cyclictest8843-21ssh21:29:340
874099224197cyclictest3477-21diskmemload21:55:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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