You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-15 - 00:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #7, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot3s.osadl.org (updated Sat Feb 14, 2026 12:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2513823030,3sleep325141-21missed_timers07:05:563
2583122490,4sleep10-21swapper/107:07:401
2542421030,3sleep00-21swapper/010:05:480
34192860,11sleep07850irq/56-dwc_otg_12:01:040
202892860,1sleep20-21swapper/209:50:532
59802730,3sleep30-21swapper/307:41:013
2641299727,36cyclictest0-21swapper/011:30:500
2641299723,32cyclictest0-21swapper/007:45:450
2641299723,32cyclictest0-21swapper/007:45:450
256432690,4sleep20-21swapper/207:06:032
2642499682,29cyclictest7850irq/56-dwc_otg_10:15:472
2641299687,30cyclictest0-21swapper/010:50:480
2641299671,28cyclictest0-21swapper/010:35:470
2642499657,7cyclictest7950irq/56-dwc_otg_08:36:042
2642499657,7cyclictest7950irq/56-dwc_otg_08:36:042
2641299653,30cyclictest0-21swapper/010:40:470
26412996412,4cyclictest0-21swapper/009:15:470
2641299636,23cyclictest0-21swapper/008:45:470
2641299621,33cyclictest0-21swapper/012:15:460
2641299621,33cyclictest0-21swapper/012:15:460
2643099614,30cyclictest0-21swapper/309:00:443
2641299615,23cyclictest0-21swapper/011:05:470
2642099603,27cyclictest0-21swapper/107:30:461
2641299596,7cyclictest0-21swapper/008:10:450
2641299583,12cyclictest0-21swapper/009:45:470
26412995815,7cyclictest0-21swapper/007:25:460
2641299572,28cyclictest0-21swapper/010:20:470
2641299572,28cyclictest0-21swapper/010:20:470
26412995716,8cyclictest0-21swapper/011:45:480
2641299571,31cyclictest23103-21grep11:26:030
133742570,2sleep213376-21grep08:01:042
2641299565,29cyclictest26426-21sh07:10:370
2641299565,29cyclictest26426-21sh07:10:370
26412995626,7cyclictest12110-21latency_hist08:00:350
2641299558,26cyclictest13-21rcuc/010:11:000
26412995534,5cyclictest7950irq/56-dwc_otg_09:35:520
2641299552,30cyclictest0-21swapper/009:30:470
26412995522,8cyclictest9753-21grep07:51:020
2643099545,11cyclictest0-21swapper/310:10:463
2642499547,16cyclictest0-21swapper/211:05:402
2642499544,13cyclictest0-21swapper/210:40:502
26412995439,5cyclictest12340-21ls12:26:030
2641299543,26cyclictest0-21swapper/010:55:460
2641299541,22cyclictest32317-21ls08:55:490
2641299535,27cyclictest0-21swapper/012:21:010
2641299534,29cyclictest23423-21ls08:30:540
26412995320,17cyclictest9-21ksoftirqd/011:00:550
2641299531,33cyclictest19479-21aten_rbpower_cu08:20:490
2641299531,27cyclictest14296-21grep12:31:030
2641299531,27cyclictest0-21swapper/008:15:480
2641299526,27cyclictest0-21swapper/010:25:570
2641299523,10cyclictest0-21swapper/011:40:470
2641299523,10cyclictest0-21swapper/011:40:470
26412995226,12cyclictest7850irq/56-dwc_otg_07:21:010
26412995222,15cyclictest7850irq/56-dwc_otg_09:01:010
2643099518,24cyclictest7850irq/56-dwc_otg_07:10:373
2643099518,24cyclictest7850irq/56-dwc_otg_07:10:373
26424995113,17cyclictest7750irq/56-dwc_otg07:10:372
26424995113,17cyclictest7750irq/56-dwc_otg07:10:372
2641299514,36cyclictest7850irq/56-dwc_otg_08:50:490
26412995123,5cyclictest7750irq/56-dwc_otg12:00:350
2641299511,30cyclictest5720-21grep07:40:580
246052514,10sleep00-21swapper/007:05:500
2642499501,7cyclictest0-21swapper/210:10:472
2642099503,37cyclictest0-21swapper/110:35:471
2642099502,22cyclictest7850irq/56-dwc_otg_07:10:371
2642099502,22cyclictest7850irq/56-dwc_otg_07:10:371
2641299507,40cyclictest0-21swapper/009:40:400
2641299507,15cyclictest0-21swapper/009:25:480
26412995026,4cyclictest0-21swapper/008:40:350
26412995026,4cyclictest0-21swapper/008:40:350
2641299501,27cyclictest31122-21wget11:50:480
2643099492,6cyclictest7850irq/56-dwc_otg_11:20:483
2641299499,37cyclictest101ktimersoftd/007:30:460
2641299497,5cyclictest9-21ksoftirqd/008:41:030
26412994943,4cyclictest101ktimersoftd/009:10:490
2641299492,28cyclictest23373-21latency_hist10:00:350
2641299492,28cyclictest0-21swapper/011:10:570
26412994911,19cyclictest9-21ksoftirqd/012:36:030
2643099486,19cyclictest0-21swapper/309:15:483
26412994825,11cyclictest4692-21cat12:05:560
26412994822,13cyclictest0-21swapper/012:10:580
26412994819,18cyclictest0-21swapper/008:01:390
26412994819,15cyclictest29878-21wc10:16:020
2643099471,7cyclictest0-21swapper/307:50:463
2642499477,26cyclictest0-21swapper/207:30:462
26412994725,9cyclictest0-21swapper/009:50:450
26412994721,10cyclictest0-21swapper/009:25:350
2641299471,33cyclictest5010-21grep09:10:350
2642099464,12cyclictest0-21swapper/109:15:481
26412994618,16cyclictest14505-21cat08:05:540
2643099457,24cyclictest0-21swapper/311:50:473
2643099457,24cyclictest0-21swapper/307:55:503
2642499457,24cyclictest16519-21sshd11:10:492
2642499452,6cyclictest0-21swapper/212:20:452
2642099457,24cyclictest0-21swapper/110:50:481
2642099452,9cyclictest0-21swapper/108:10:451
2642099452,3cyclictest7750irq/56-dwc_otg09:40:401
2641299452,23cyclictest0-21swapper/011:15:540
2643099447,23cyclictest0-21swapper/310:20:493
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional