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2026-02-28 - 18:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot3s.osadl.org (updated Sat Feb 28, 2026 12:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1875725620,6sleep30-21swapper/307:06:113
1764422240,2sleep017647-21aten_rbpower_cu07:05:560
32412980,7sleep1221ktimersoftd/109:21:121
19436999128,29cyclictest0-21swapper/012:20:560
1943699905,53cyclictest0-21swapper/007:30:540
1943699905,53cyclictest0-21swapper/007:30:540
1943699873,66cyclictest0-21swapper/010:45:540
19436998422,37cyclictest0-21swapper/008:10:530
292932770,4sleep01943699cyclictest07:36:050
1943699776,69cyclictest0-21swapper/007:15:470
19436997717,31cyclictest0-21swapper/007:10:440
19436997555,4cyclictest16769-21latency_hist11:30:420
1943699737,50cyclictest24865-21idleruntime-cro07:25:420
1943699734,38cyclictest0-21swapper/010:10:540
1943699733,55cyclictest14309-21latency_hist08:25:420
1943699721,3cyclictest0-21swapper/009:00:420
1943699715,49cyclictest18740-21grep08:36:060
1943699714,52cyclictest26206-21basename11:55:550
1943699702,53cyclictest0-21swapper/007:50:530
181582700,2sleep30-21swapper/311:31:113
1943699696,7cyclictest9450irq/48-DMA10:44:550
1943699696,7cyclictest9450irq/48-DMA10:44:550
19436996913,30cyclictest7919-21idleruntime-cro12:35:420
19436996912,11cyclictest0-21swapper/008:15:540
19436996912,11cyclictest0-21swapper/008:15:540
259122670,2sleep30-21swapper/311:55:423
1943699676,45cyclictest0-21swapper/010:05:540
1943699657,45cyclictest10605-21switchtime11:11:070
19436996352,3cyclictest0-21swapper/010:20:550
1943699634,42cyclictest0-21swapper/009:50:530
1943699633,45cyclictest2737-21ntpq09:21:050
284612620,2sleep20-21swapper/210:31:082
1943699628,34cyclictest0-21swapper/012:05:520
1943699625,36cyclictest31712-21head07:41:130
19436996221,22cyclictest7850irq/56-dwc_otg_09:40:520
19436996126,9cyclictest101ktimersoftd/009:10:420
1943699612,49cyclictest17645-21awk11:31:040
1943699612,44cyclictest0-21swapper/009:35:530
1943699599,47cyclictest845-21latency_hist12:15:430
19436995945,5cyclictest101ktimersoftd/008:30:500
19436995835,9cyclictest0-21swapper/012:36:060
1943699581,21cyclictest7850irq/56-dwc_otg_08:00:560
19436995810,36cyclictest0-21swapper/011:15:530
42052570,2sleep20-21swapper/207:56:042
1943699572,44cyclictest0-21swapper/009:16:010
19436995722,22cyclictest0-21swapper/009:15:420
1943699571,45cyclictest19058-21fschecks_count11:35:580
1943699571,35cyclictest25342-21cut07:25:580
19436995630,9cyclictest14341-21modprobe08:25:430
1943699561,38cyclictest0-21swapper/007:48:470
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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