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2026-02-02 - 02:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Sun Feb 01, 2026 12:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
206732115013sleep20675-21sendmail_mailst07:04:200
212419926882cyclictest6705-21proc_pri10:40:550
2124199259131cyclictest22325-21cpu11:43:510
2124199256121cyclictest5098-21sshd10:34:590
2124199255130cyclictest19752-21netwatch11:33:100
212419925485cyclictest23606-21ssh11:48:580
212419925288cyclictest3573-21latency_hist08:13:460
2124199252129cyclictest14046-21modprobe11:09:580
2124199252124cyclictest11790-21runrttasks11:00:510
212419925193cyclictest2377-21cpu08:08:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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