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2026-01-26 - 00:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Sun Jan 25, 2026 12:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
171962176321sleep17198-21timerandwakeup07:04:310
1773699266239cyclictest9314-21ssh11:03:340
177369926582cyclictest32217-21processes10:26:160
1773699264238cyclictest6786-21latency_hist10:54:280
1773699262204cyclictest24459-21munin-node0
177369926190cyclictest27043-21diskmemload10:06:000
177369926181cyclictest2726-21lxpanel08:00:280
1773699260232cyclictest9791-21munin-node0
1773699259230cyclictest24609-21latency_hist12:04:250
177369925894cyclictest12935-21netwatch11:18:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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