You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-28 - 09:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Sat Feb 28, 2026 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3000287021sleep3001-21cat19:03:230
379099271243cyclictest3442-21uname23:39:320
379099266219cyclictest16186-21ssh00:33:010
379099261195cyclictest4124-21processes21:30:300
379099257233cyclictest17445-21ls20:08:160
379099255183cyclictest11869-21sh22:02:160
379099254198cyclictest22099-21df_inode22:43:410
379099251224cyclictest6102-21ifplugd23:43:510
379099250223cyclictest2457-21ssh23:35:410
379099250223cyclictest2112-21df_inode21:23:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional