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2026-02-26 - 19:40
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Thu Feb 26, 2026 12:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
65672194218sleep6570-21uptime07:03:420
698299252223cyclictest11576-21egrep07:28:110
698299251223cyclictest21466-21ssh10:28:090
698299250222cyclictest6688-21df_inode11:38:360
698299247218cyclictest24196-1kworker/0:2H09:11:390
698299247181cyclictest14440-21ssh12:09:330
698299246221cyclictest4135-21cpu09:18:090
698299246219cyclictest2954-21netwatch09:21:480
698299245220cyclictest10471-21cat07:23:130
698299245218cyclictest19599-21fschecks_count08:03:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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