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2026-01-29 - 15:50
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Thu Jan 29, 2026 12:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299089926489cyclictest22587-21latency_hist11:09:120
2990899261230cyclictest801-21munin-run09:43:560
299089926082cyclictest29384-21processes11:36:110
2990899260232cyclictest22752-21chrt11:09:470
2990899258231cyclictest9158-21cut07:59:280
2990899257228cyclictest1153-21runrttasks07:24:290
2990899256197cyclictest2376-21rs:main0
2990899255230cyclictest14362-21runrttasks08:21:470
299089925486cyclictest9142-21ssh12:24:340
299089925476cyclictest24671-1diskmemload09:33:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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