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2026-01-23 - 10:44
[ 290.152] (II) VESA: driver for VESA chipsets: vesa >
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Fri Jan 23, 2026 00:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9648232621sleep9649-21fschecks_count19:04:110
1061599267234cyclictest31913-21sh22:54:310
1061599262236cyclictest19000-21processes00:11:140
1061599258228cyclictest23113-21latency_hist20:04:070
1061599255190cyclictest7550-21diskmemload23:25:490
1061599249223cyclictest1111-21munin-node0
1061599247181cyclictest8734-21ssh21:22:080
1061599245220cyclictest2834-21snmpd23:30:290
1061599244216cyclictest1021-21ssh23:00:200
1061599244212cyclictest4512-21munin-run23:14:090
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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