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2026-03-02 - 00:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Sun Mar 01, 2026 12:44:42)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13455279921sleep13454-21cpu07:03:010
1450199264204cyclictest16380-21timerandwakeup07:14:270
1450199263192cyclictest22873-21irqstats12:14:260
1450199260234cyclictest12434-21ps09:20:200
1450199255229cyclictest17988-21cut09:43:410
1450199251225cyclictest26408-21ssh12:29:000
1450199251221cyclictest17730-21df_inode11:53:390
1450199251189cyclictest24002-21chrt10:08:350
1450199250216cyclictest7780-21munin-node0
1450199248223cyclictest14248-21df09:28:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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