You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-03-09 - 03:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Mon Mar 09, 2026 00:44:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26494284718sleep26491-21latency_hist19:07:460
2651799295274cyclictest157942sleep22:54:360
2651799249224cyclictest32662-21sshd19:33:490
2651799245219cyclictest21703-21perl21:09:010
2651799244218cyclictest2726-21lxpanel22:21:470
2651799238212cyclictest3013-21sendmail-mta21:21:390
2651799236172cyclictest24026-21ssh23:28:050
2651799235209cyclictest5324-21ssh22:13:160
2651799235190cyclictest13500-21df20:32:570
2651799234174cyclictest2953-21runrttasks00:21:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional