You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-27 - 09:20
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Fri Feb 27, 2026 00:44:54)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15168233218sleep15169-21if_err_eth019:03:160
1603599271136cyclictest29583-21munin-node0
160359926190cyclictest10849-21cpu21:08:110
1603599258131cyclictest27473-21latency_hist19:58:230
160359925795cyclictest10012-21fschecks_count23:14:070
1603599255120cyclictest5036-21chrt20:41:250
160359925486cyclictest13174-21netwatch21:18:020
1603599254121cyclictest30992-21latency_hist00:38:350
1603599253117cyclictest19403-21ssh21:43:020
1603599253110cyclictest22684-21runrttasks21:55:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional