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2026-01-26 - 12:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Mon Jan 26, 2026 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2796099264238cyclictest25668-21munin-node0
2796099259193cyclictest21449-21ssh23:15:290
2796099257226cyclictest2726-21lxpanel21:49:210
2796099253224cyclictest19814-21df23:09:240
2796099252219cyclictest5777-21latency_hist19:53:590
2796099249220cyclictest7176-21ping22:18:470
2796099248222cyclictest8120-21latency_hist20:04:030
2796099248222cyclictest2726-21lxpanel22:07:110
2796099247222cyclictest29998-21runrttasks19:16:210
2796099247222cyclictest1040-21runrttasks00:05:080
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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