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2026-02-20 - 07:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Fri Feb 20, 2026 00:44:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
185582114726sleep18559-21sleep19:07:270
1868099265215cyclictest23246-21ssh21:49:140
1868099262234cyclictest22520-21date23:58:500
1868099253224cyclictest2329-21uniq20:18:520
1868099253222cyclictest13417-21diskmemload23:20:300
1868099252224cyclictest24174-21sleep00:05:030
1868099252218cyclictest6888-21ssh22:54:100
1868099252188cyclictest30656-21perl22:19:280
1868099252181cyclictest31182-21cpuspeed20:03:230
1868099249220cyclictest19600-21ping19:11:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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