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2026-03-06 - 01:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot3.osadl.org (updated Thu Mar 05, 2026 12:44:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23764270715sleep23760-21grep07:03:290
242049926977cyclictest2542-21ps07:54:070
242049926273cyclictest16812-21chrt11:08:340
2420499258227cyclictest19344-21munin-node0
2420499257224cyclictest2953-21runrttasks08:10:230
2420499256224cyclictest2953-21runrttasks10:10:230
2420499255227cyclictest18447-21ssh11:14:380
2420499254226cyclictest1560-21latency_hist10:08:330
2420499253227cyclictest21130-21runrttasks09:16:190
2420499253225cyclictest30108-21chrt09:52:360
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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