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2026-02-10 - 03:25
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Tue Feb 10, 2026 00:45:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23976997749,15cyclictest28366irq/58-eth022:30:133
2396899721,39cyclictest32518-21ssh23:10:132
23958996810,9cyclictest131rcu_preempt20:10:121
23949995924,29cyclictest131rcu_preempt00:30:140
2394999589,5cyclictest131rcu_preempt22:55:160
2394999589,5cyclictest131rcu_preempt22:55:160
2394999562,42cyclictest12333-21ssh22:05:150
2394999556,45cyclictest25764-21ssh00:00:130
2396899533,37cyclictest17553-21ssh21:50:142
23968995321,13cyclictest22000-21ssh23:40:142
23968994941,4cyclictest27-21ksoftirqd/223:45:112
23976994838,5cyclictest28366irq/58-eth023:25:143
23976994838,5cyclictest28366irq/58-eth023:25:143
2396899445,27cyclictest25183-21ssh22:30:122
2394999448,3cyclictest131rcu_preempt23:00:140
2394999442,25cyclictest3884-21ssh23:30:120
2397699432,25cyclictest28366irq/58-eth021:20:123
2396899421,27cyclictest924-21snmpd22:20:152
2395899425,5cyclictest21-21ksoftirqd/121:30:141
2394999421,37cyclictest4724-21ssh21:25:140
2395899413,10cyclictest21-21ksoftirqd/119:55:131
2394999413,29cyclictest13754-21ssh21:30:130
2396899402,21cyclictest32533-21ssh00:02:472
2397699392,24cyclictest28366irq/58-eth022:40:143
2394999393,21cyclictest9957-21ssh21:10:140
23949993920,16cyclictest12-21ksoftirqd/019:45:140
2396899377,12cyclictest27-21ksoftirqd/222:35:112
2397699364,17cyclictest28366irq/58-eth023:40:143
2396899362,28cyclictest27332-21ssh23:25:152
2396899362,28cyclictest27332-21ssh23:25:152
2396899362,16cyclictest2536-21fschecks_count00:05:152
23958993618,14cyclictest21-21ksoftirqd/100:25:141
2394999368,19cyclictest31866-21ssh21:40:140
2394999361,22cyclictest26653-21ssh21:55:130
2396899352,26cyclictest7609-21/usr/sbin/munin23:50:162
2396899341,16cyclictest28848-21ssh22:50:122
2394999348,4cyclictest131rcu_preempt23:55:130
23949993416,5cyclictest12-21ksoftirqd/000:15:110
2396899335,19cyclictest22346irq/40-dwc2_hso22:10:152
2396899331,23cyclictest3344-21ssh22:00:142
2396899331,18cyclictest9558-21diskmemload22:25:142
2394999334,19cyclictest9558-21diskmemload23:35:150
2397699322,20cyclictest28366irq/58-eth020:05:143
2397699322,16cyclictest28366irq/58-eth022:10:153
2397699321,17cyclictest28366irq/58-eth021:50:133
2396899322,23cyclictest0-21swapper/200:21:152
23976993115,8cyclictest28366irq/58-eth023:45:123
2397699311,17cyclictest28366irq/58-eth022:20:153
2396899313,7cyclictest18248-21ssh23:20:132
23968993112,14cyclictest6067-21sshd00:25:152
2395899317,7cyclictest21-21ksoftirqd/123:35:151
2394999311,23cyclictest12-21ksoftirqd/021:05:130
2396899303,19cyclictest0-21swapper/200:35:142
2396899303,18cyclictest22346irq/40-dwc2_hso19:55:142
2395899304,7cyclictest21-21ksoftirqd/120:20:121
2394999302,19cyclictest12-21ksoftirqd/020:00:120
2397699292,20cyclictest28366irq/58-eth023:35:133
23976992916,9cyclictest28366irq/58-eth023:10:153
2397699291,15cyclictest28366irq/58-eth019:45:153
2395899292,22cyclictest3773-21ssh00:22:481
2394999292,20cyclictest31358-21cat23:45:160
2397699285,4cyclictest0-21swapper/321:55:133
2397699282,14cyclictest28366irq/58-eth022:25:133
2397699281,16cyclictest28366irq/58-eth023:30:133
2396899285,14cyclictest22346irq/40-dwc2_hso20:55:132
2396899284,13cyclictest22346irq/40-dwc2_hso20:15:132
2396899283,12cyclictest22346irq/40-dwc2_hso19:50:122
2396899282,7cyclictest11329-21ssh00:10:132
2396899282,21cyclictest0-21swapper/223:00:142
2396899282,14cyclictest22346irq/40-dwc2_hso22:05:142
2395899282,22cyclictest16733-21ssh23:55:151
2395899282,19cyclictest31359-21if_eth123:45:161
23958992810,3cyclictest21-21ksoftirqd/122:35:021
2394999283,19cyclictest12-21ksoftirqd/020:10:130
2394999282,20cyclictest9558-21diskmemload23:53:160
2397699273,16cyclictest0-21swapper/323:50:173
2397699273,15cyclictest0-21swapper/300:35:143
2397699272,14cyclictest28366irq/58-eth023:00:133
23976992715,7cyclictest28366irq/58-eth022:45:143
2397699271,21cyclictest28366irq/58-eth000:10:143
2397699271,12cyclictest28366irq/58-eth000:15:113
2396899274,12cyclictest22346irq/40-dwc2_hso19:35:122
2396899273,9cyclictest0-21swapper/200:33:152
2396899272,20cyclictest0-21swapper/220:40:132
2396899271,19cyclictest23485-21ssh23:05:152
2395899279,3cyclictest131rcu_preempt22:25:131
2395899273,11cyclictest24049-21ssh00:35:141
2395899272,17cyclictest18735-21ssh00:30:271
23958992712,5cyclictest0-21swapper/122:40:281
23958992710,9cyclictest0-21swapper/100:00:111
2394999275,3cyclictest131rcu_preempt19:35:120
2394999272,16cyclictest28078-21ssh21:20:130
2397699264,11cyclictest321rcuc/321:30:143
23976992616,5cyclictest28366irq/58-eth021:35:123
2396899263,14cyclictest22346irq/40-dwc2_hso19:10:112
2396899262,14cyclictest9558-21diskmemload21:45:132
2395899269,15cyclictest21-21ksoftirqd/121:53:121
2397699255,13cyclictest0-21swapper/321:25:143
2397699253,14cyclictest0-21swapper/300:21:153
2396899252,9cyclictest0-21swapper/220:20:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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