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2026-02-23 - 06:57
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Mon Feb 23, 2026 00:45:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
435999571,35cyclictest8796-21sh22:50:132
435199554,44cyclictest17914-21ssh21:25:121
434399554,7cyclictest131rcu_preempt19:55:140
435199541,41cyclictest23287-21ssh22:40:121
435999512,12cyclictest0-21swapper/221:40:122
435199482,34cyclictest26234-21ssh00:30:141
435199473,39cyclictest12518-21ssh21:40:131
437199467,21cyclictest28366irq/58-eth023:25:143
4359994522,18cyclictest27-21ksoftirqd/221:45:122
4359994518,19cyclictest27-21ksoftirqd/219:20:132
4343994411,23cyclictest12-21ksoftirqd/020:50:130
437199432,25cyclictest28366irq/58-eth023:30:133
434399431,3cyclictest131rcu_preempt21:40:130
4371994222,14cyclictest28366irq/58-eth022:50:123
4371994210,16cyclictest28366irq/58-eth022:35:143
4371994210,16cyclictest28366irq/58-eth022:35:143
434399423,6cyclictest131rcu_preempt19:10:130
434399412,23cyclictest7147-21ssh21:55:130
435199382,30cyclictest17836-21ssh22:55:131
437199379,17cyclictest28366irq/58-eth021:25:123
4371993716,14cyclictest28366irq/58-eth022:45:143
437199371,19cyclictest28366irq/58-eth000:05:123
435199373,20cyclictest21427-21ssh23:15:141
435999362,26cyclictest29162-21tr23:00:212
435999362,18cyclictest924-21snmpd23:36:202
435999362,17cyclictest18392-21kthreadcore23:30:222
434399365,4cyclictest131rcu_preempt22:15:130
437199351,21cyclictest28366irq/58-eth019:25:133
437199351,20cyclictest28366irq/58-eth019:50:133
435999354,19cyclictest5239-21ssh22:30:132
437199342,19cyclictest28366irq/58-eth023:20:143
435199342,22cyclictest3534-21ssh21:35:131
434399343,6cyclictest131rcu_preempt22:05:130
4343993419,9cyclictest0-21swapper/000:05:120
434399341,6cyclictest131rcu_preempt00:00:130
434399341,29cyclictest2804-21ssh00:35:160
437199333,15cyclictest28366irq/58-eth020:50:153
435999331,24cyclictest17823-21ssh22:55:112
435199332,26cyclictest26795-21ssh23:00:131
434399335,21cyclictest16154-21ssh22:00:130
434399332,28cyclictest3432-21ssh23:05:150
434399332,23cyclictest24791-21ssh23:35:120
437199323,16cyclictest28366irq/58-eth000:20:133
435999325,18cyclictest0-21swapper/221:50:122
435999323,20cyclictest22346irq/40-dwc2_hso19:40:132
435999323,18cyclictest22346irq/40-dwc2_hso00:05:122
435999321,27cyclictest17308-21rm00:25:142
4359993212,11cyclictest27-21ksoftirqd/220:15:142
435199322,23cyclictest14234-21ssh22:35:141
435199322,23cyclictest14234-21ssh22:35:131
437199315,19cyclictest28366irq/58-eth022:40:133
4371993116,9cyclictest28366irq/58-eth021:55:123
4351993120,7cyclictest0-21swapper/121:05:121
434399315,15cyclictest26997-21ssh21:30:140
434399312,21cyclictest15849-21ssh23:30:150
4343993113,6cyclictest121ksoftirqd/021:45:120
437199302,17cyclictest28366irq/58-eth000:30:143
435999302,22cyclictest14376-21ssh21:58:212
434399305,22cyclictest8885-21ssh21:20:130
4343993023,3cyclictest12-21ksoftirqd/019:50:130
434399301,16cyclictest8330-21ssh00:20:140
435199292,21cyclictest3876-21ssh23:59:211
4343992915,7cyclictest121ksoftirqd/019:40:120
437199283,18cyclictest0-21swapper/323:37:213
437199283,16cyclictest0-21swapper/322:17:213
435999283,14cyclictest22346irq/40-dwc2_hso20:50:132
435999282,21cyclictest17079-21ssh22:17:222
435999282,20cyclictest1472-21ssh23:40:142
435999282,11cyclictest0-21swapper/221:26:222
435999282,10cyclictest20609-21ssh22:37:222
435999282,10cyclictest20609-21ssh22:37:212
435999281,22cyclictest21695-21ssh22:01:212
435199286,13cyclictest0-21swapper/121:20:131
435199282,18cyclictest22837-21tr22:20:221
434399283,3cyclictest131rcu_preempt21:10:110
434399282,20cyclictest24835-21ssh00:28:470
4343992820,3cyclictest0-21swapper/022:45:120
435999273,8cyclictest0-21swapper/223:59:202
435999273,7cyclictest0-21swapper/222:20:222
435999271,16cyclictest30348-21ssh23:20:162
435199272,17cyclictest6853-21ssh23:25:131
434399276,16cyclictest31829-21diskmemload00:15:140
434399274,13cyclictest22092-21kworker/u8:022:50:120
4343992721,3cyclictest6874-21ssh23:25:140
437199265,11cyclictest28366irq/58-eth022:30:133
437199263,11cyclictest0-21swapper/300:38:213
437199262,17cyclictest28366irq/58-eth022:20:143
435999264,13cyclictest22346irq/40-dwc2_hso21:15:122
4359992612,11cyclictest13003-21unixbench_multi21:20:292
435999261,14cyclictest31830-21ssh00:15:142
435199263,15cyclictest4335-21cyclictest20:45:131
435199261,20cyclictest18783-21apt-get19:25:011
434399265,6cyclictest12492-21ssh23:10:140
437199253,11cyclictest0-21swapper/323:00:123
437199251,15cyclictest28366irq/58-eth020:55:143
435999253,15cyclictest22346irq/40-dwc2_hso20:05:122
435999252,5cyclictest28685-21ssh22:25:142
435999252,5cyclictest28685-21ssh22:25:142
435999251,8cyclictest3510-21ssh21:35:122
435199259,7cyclictest21-21ksoftirqd/119:56:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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