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2026-02-15 - 21:05
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Sun Feb 15, 2026 12:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20302995537,10cyclictest28366irq/58-eth009:20:113
20289995217,3cyclictest131rcu_preempt11:45:131
20296995132,9cyclictest27-21ksoftirqd/210:25:142
2028999493,36cyclictest2461-21ssh12:10:121
20296994822,16cyclictest0-21swapper/207:30:132
2028999489,8cyclictest131rcu_preempt12:35:131
2028999474,7cyclictest131rcu_preempt08:45:141
2028999472,6cyclictest131rcu_preempt08:55:131
2029699462,28cyclictest19538-21ssh10:30:142
2028999451,33cyclictest7468-21ssh10:05:151
2028099451,40cyclictest20154-21ssh11:25:130
2030299444,26cyclictest28366irq/58-eth010:20:133
2028999431,32cyclictest2445-21ssh11:15:141
20289994214,20cyclictest21-21ksoftirqd/110:15:141
2029699413,24cyclictest16430-21ssh10:10:142
2029699413,19cyclictest17233-21ssh12:00:142
2029699413,19cyclictest17233-21ssh12:00:132
2029699412,31cyclictest31308-21ssh09:23:152
20296994118,8cyclictest13014-21ssh09:50:132
2029699411,5cyclictest0-21swapper/209:00:142
2029699411,5cyclictest0-21swapper/209:00:132
2028099415,32cyclictest19543-21ssh10:30:150
2028999402,6cyclictest131rcu_preempt10:55:131
2028999402,30cyclictest4942-21ssh10:40:141
2028099401,34cyclictest21953-21ssh09:55:130
2030299392,22cyclictest28366irq/58-eth010:25:143
20289993920,13cyclictest21-21ksoftirqd/112:15:121
2028999391,29cyclictest5591-21ssh12:30:121
2028099391,29cyclictest17248-21ssh12:00:140
2028099391,29cyclictest17248-21ssh12:00:140
2028099381,25cyclictest5304-21ssh11:35:120
20302993722,12cyclictest0-21swapper/309:15:123
2029699372,21cyclictest29054-21ssh09:58:152
2028999371,30cyclictest30923-21ssh10:00:131
20280993712,5cyclictest131rcu_preempt12:05:140
20280993712,5cyclictest131rcu_preempt12:05:130
2030299362,23cyclictest28366irq/58-eth012:25:123
20302993619,11cyclictest28366irq/58-eth010:40:133
2029699362,28cyclictest26860-21ssh09:39:382
2029699362,18cyclictest12938-21sh10:06:152
2028099363,25cyclictest29073-21ssh12:25:120
20280993622,10cyclictest5899-21diskmemload09:25:160
2029699354,23cyclictest0-21swapper/210:55:142
2028999355,23cyclictest4133-21ssh09:45:151
2030299349,16cyclictest28366irq/58-eth011:25:123
2030299344,18cyclictest28366irq/58-eth010:35:143
2030299343,21cyclictest28366irq/58-eth011:35:123
20302993424,7cyclictest28366irq/58-eth009:30:113
20302993419,8cyclictest0-21swapper/308:40:143
20302993417,11cyclictest0-21swapper/309:50:133
2029699342,20cyclictest28484-21ssh10:35:132
20289993421,8cyclictest21-21ksoftirqd/108:50:111
2028999340,26cyclictest0-21swapper/109:10:141
20302993317,13cyclictest0-21swapper/311:05:133
2028099332,6cyclictest12-21ksoftirqd/009:45:120
20302993217,12cyclictest0-21swapper/308:55:133
20302993119,9cyclictest0-21swapper/309:35:133
2028999312,4cyclictest131rcu_preempt09:15:121
2028999312,12cyclictest0-21swapper/107:10:131
20289993113,11cyclictest0-21swapper/108:10:111
2028099311,23cyclictest14467-21ssh12:35:140
20302993019,8cyclictest28366irq/58-eth009:25:143
20302993014,13cyclictest28366irq/58-eth010:55:133
2029699305,20cyclictest25953-21ssh11:10:122
2029699305,16cyclictest0-21swapper/211:25:132
2029699303,18cyclictest22346irq/40-dwc2_hso09:25:152
2029699302,21cyclictest1713-21ssh10:20:152
2029699302,21cyclictest0-21swapper/207:20:142
2028999302,20cyclictest9678-21ssh09:30:111
2028099302,11cyclictest12-21ksoftirqd/010:10:120
2028099301,24cyclictest4920-21sh10:40:130
2030299292,20cyclictest28366irq/58-eth007:30:133
20289992910,12cyclictest21-21ksoftirqd/107:20:131
2028099292,19cyclictest10728-21df10:25:150
2028099292,17cyclictest26952-21kworker/u8:112:20:130
20302992822,3cyclictest0-21swapper/307:50:113
20302992822,3cyclictest0-21swapper/307:50:113
20302992822,2cyclictest0-21swapper/307:10:123
20302992816,8cyclictest0-21swapper/312:35:133
20302992816,6cyclictest28366irq/58-eth012:10:113
2029699283,20cyclictest0-21swapper/210:04:162
2029699282,20cyclictest0-21swapper/207:15:152
2029699282,11cyclictest0-21swapper/209:49:392
2029699281,15cyclictest2444-21sh11:15:142
2029699281,13cyclictest22817-21sh10:50:112
2028999282,19cyclictest13191-21fschecks_count09:50:151
2028999281,3cyclictest131rcu_preempt10:20:131
20280992818,6cyclictest0-21swapper/009:20:120
20280992814,4cyclictest12-21ksoftirqd/012:14:100
20302992721,3cyclictest0-21swapper/312:05:113
20302992721,3cyclictest0-21swapper/312:05:113
20302992718,4cyclictest0-21swapper/309:55:273
20302992716,6cyclictest0-21swapper/309:40:133
20302992714,10cyclictest28366irq/58-eth012:15:133
2029699272,16cyclictest22346irq/40-dwc2_hso08:40:132
2029699271,9cyclictest14446-21ssh12:35:122
2029699271,21cyclictest924-21snmpd12:10:122
2028999278,3cyclictest131rcu_preempt11:00:171
2028099277,3cyclictest131rcu_preempt10:05:260
2028099273,3cyclictest131rcu_preempt10:55:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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