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2026-04-15 - 06:01

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Wed Apr 15, 2026 00:45:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
718499785,49cyclictest16923-21ssh23:10:130
7198995913,8cyclictest131rcu_preempt20:00:121
7218995746,7cyclictest35966irq/58-eth022:15:153
7210995334,13cyclictest7557-21ssh22:45:242
7198995312,18cyclictest21-21ksoftirqd/100:35:101
718499503,8cyclictest12-21ksoftirqd/000:20:120
7184995030,5cyclictest12-21ksoftirqd/023:20:130
721099484,33cyclictest27364-21ssh22:40:152
7218994718,20cyclictest35966irq/58-eth023:15:163
721099440,30cyclictest26159-21ssh23:15:162
719899445,36cyclictest6453-21ssh23:40:141
721899434,26cyclictest35966irq/58-eth021:45:143
719899423,32cyclictest10342-21ssh00:00:141
7198994211,18cyclictest21-21ksoftirqd/100:10:151
7198994211,18cyclictest21-21ksoftirqd/100:10:151
718499422,30cyclictest5083-21ssh00:15:130
719899411,31cyclictest3984-21ssh22:45:141
718499401,5cyclictest131rcu_preempt21:30:150
721899393,23cyclictest35966irq/58-eth022:50:123
721899381,23cyclictest35966irq/58-eth023:40:123
721899371,21cyclictest35966irq/58-eth000:10:133
721899371,21cyclictest35966irq/58-eth000:10:123
7198993720,11cyclictest21-21ksoftirqd/100:05:161
718499373,30cyclictest9239-21ssh22:30:140
718499373,29cyclictest11355-21ssh21:20:120
721899365,17cyclictest35966irq/58-eth023:35:133
7210993617,13cyclictest27346irq/40-dwc2_hso22:10:112
7210993613,19cyclictest131rcu_preempt00:35:112
719899365,24cyclictest14329-21ssh22:15:151
7218993521,9cyclictest35966irq/58-eth022:00:133
7218993515,11cyclictest321rcuc/320:50:133
719899353,21cyclictest21-21ksoftirqd/119:25:141
7198993524,7cyclictest25178-21diskmemload22:25:131
7198993524,7cyclictest25178-21diskmemload22:25:121
718499351,23cyclictest13062-21sh22:50:140
721099342,28cyclictest32524-21ssh22:25:132
721099342,28cyclictest32524-21ssh22:25:132
719899344,20cyclictest11407-21kworker/u8:122:05:121
7184993421,5cyclictest12-21ksoftirqd/020:45:140
721099332,18cyclictest27346irq/40-dwc2_hso23:20:152
719899331,23cyclictest2249-21ssh21:15:151
718499316,19cyclictest12-21ksoftirqd/022:15:140
718499312,22cyclictest5164-21ssh22:10:110
721099302,21cyclictest19162-21ntp_192.168.11423:45:262
721099302,11cyclictest24504-21ntp_states23:30:262
721099293,20cyclictest1263-21ssh23:55:152
721099293,11cyclictest0-21swapper/221:27:242
721099292,16cyclictest27346irq/40-dwc2_hso20:40:152
719899292,20cyclictest3864-21rm23:37:241
719899292,20cyclictest26850-21ntpq00:25:251
719899291,21cyclictest6212-21rm21:35:141
7198992910,11cyclictest7174-21cyclictest00:30:141
718499291,25cyclictest20459-21ssh21:25:130
7184992910,13cyclictest12-21ksoftirqd/019:10:130
721099284,14cyclictest27346irq/40-dwc2_hso22:20:132
721099284,13cyclictest27346irq/40-dwc2_hso19:30:132
721099283,19cyclictest27346irq/40-dwc2_hso19:40:142
721099283,14cyclictest25598-21ssh21:10:152
721099282,10cyclictest0-21swapper/223:37:252
7210992820,4cyclictest27-21ksoftirqd/223:40:132
721099281,21cyclictest28454-21ssh00:10:152
721099281,21cyclictest28454-21ssh00:10:142
721099281,16cyclictest11775-21ssh23:25:122
719899283,20cyclictest10219-21ssh21:55:141
719899282,21cyclictest19374-21ssh22:00:131
7198992812,11cyclictest21-21ksoftirqd/123:32:251
721899273,18cyclictest0-21swapper/300:04:263
721099274,8cyclictest0-21swapper/222:35:132
721099274,7cyclictest24599-21ssh23:50:112
721099274,18cyclictest0-21swapper/200:20:142
721099272,17cyclictest27346irq/40-dwc2_hso20:35:142
721099272,10cyclictest0-21swapper/220:00:132
721099271,21cyclictest25027-21latency19:25:222
7210992711,10cyclictest0-21swapper/221:55:132
719899272,19cyclictest29038-21ssh22:21:251
721899261,17cyclictest0-21swapper/322:45:143
721099263,19cyclictest27-21ksoftirqd/223:10:142
721099263,16cyclictest27346irq/40-dwc2_hso00:25:132
721099261,20cyclictest1152-21ssh21:50:142
721099261,12cyclictest6308-21ssh21:35:142
719899267,11cyclictest7174-21cyclictest20:40:131
719899263,17cyclictest22137-21ssh22:55:141
719899262,18cyclictest24118-21ssh21:25:261
7198992614,3cyclictest21-21ksoftirqd/122:10:071
7218992512,6cyclictest0-21swapper/321:10:143
721099251,13cyclictest27346irq/40-dwc2_hso19:20:132
719899251,17cyclictest27363-21sh22:40:141
718499255,16cyclictest29843-21ssh23:35:120
718499254,14cyclictest20791-21ssh23:30:110
718499254,13cyclictest0-21swapper/020:05:120
721899243,13cyclictest0-21swapper/322:21:243
721899243,13cyclictest0-21swapper/321:35:133
7218992416,5cyclictest35966irq/58-eth022:05:143
721099242,18cyclictest17314-21ssh21:21:512
721099241,8cyclictest16004-21ssh23:09:262
719899247,8cyclictest21-21ksoftirqd/123:48:561
719899242,18cyclictest24497-21ssh21:45:141
719899242,17cyclictest25178-21diskmemload23:29:251
719899241,19cyclictest7612-21ls23:05:021
718499241,17cyclictest11802-21ssh23:25:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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