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2026-04-14 - 22:29

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Tue Apr 14, 2026 12:45:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22403996547,13cyclictest35966irq/58-eth011:30:133
22403996547,13cyclictest35966irq/58-eth011:30:133
2239599642,40cyclictest24014-21ssh12:15:132
2237999563,46cyclictest17025-21ssh09:50:120
2238199543,40cyclictest14750-21ssh12:10:131
2238199492,38cyclictest17671-21ssh09:15:141
2238199483,34cyclictest9863-21sshd12:25:131
2237999483,37cyclictest17656-21ssh09:15:120
2237999472,40cyclictest20970-21ssh10:45:140
2237999467,26cyclictest12-21ksoftirqd/011:55:130
2240399449,23cyclictest35966irq/58-eth012:10:123
2238199431,36cyclictest24717-21ssh11:40:151
2237999433,7cyclictest131rcu_preempt11:25:150
2237999433,7cyclictest131rcu_preempt09:30:120
2237999433,7cyclictest131rcu_preempt09:30:120
2237999431,33cyclictest0-21swapper/008:05:130
22395994225,10cyclictest7804-21ssh09:45:132
2237999422,4cyclictest131rcu_preempt09:35:150
2237999422,4cyclictest131rcu_preempt09:35:150
2237999411,34cyclictest19039-21ssh12:30:140
22395993915,12cyclictest0-21swapper/211:30:132
22395993915,12cyclictest0-21swapper/211:30:122
2239599391,27cyclictest8095-21diskmemload11:50:132
2238199391,27cyclictest7421-21ssh10:20:121
2238199383,29cyclictest29015-21ssh12:00:131
2239599372,18cyclictest3827-21ssh12:03:242
22381993729,4cyclictest0-21swapper/108:50:141
2240399362,24cyclictest35966irq/58-eth007:50:123
2240399362,24cyclictest35966irq/58-eth007:50:123
2238199362,22cyclictest15475-21ssh11:35:151
2240399351,19cyclictest35966irq/58-eth007:30:133
2240399344,18cyclictest35966irq/58-eth011:50:133
2240399342,23cyclictest35966irq/58-eth010:05:123
2239599342,22cyclictest8499-21ssh09:10:132
2240399332,21cyclictest35966irq/58-eth007:20:133
2240399332,21cyclictest35966irq/58-eth007:20:133
2239599332,24cyclictest9881-21ssh12:25:142
22379993314,8cyclictest12-21ksoftirqd/010:10:130
22403993215,9cyclictest35966irq/58-eth009:35:153
22403993215,9cyclictest35966irq/58-eth009:35:143
2239599322,15cyclictest1605-21awk11:10:012
2237999322,22cyclictest19958-21ssh11:20:010
2237999322,19cyclictest1465-21ssh11:45:140
22395993110,15cyclictest0-21swapper/210:34:462
2239599304,19cyclictest0-21swapper/208:25:102
2239599302,21cyclictest10519-21ntp_192.168.11410:55:242
22395993013,9cyclictest27-21ksoftirqd/210:28:032
2239599301,21cyclictest11738-21ssh10:40:152
2239599301,21cyclictest11738-21ssh10:40:152
2238199302,21cyclictest10625-21ssh11:50:121
2240399292,17cyclictest35966irq/58-eth012:00:123
2239599292,22cyclictest5087-21ssh10:53:242
22395992912,4cyclictest27-21ksoftirqd/209:39:072
22395992912,4cyclictest27-21ksoftirqd/209:39:062
2238199292,19cyclictest0-21swapper/109:10:131
2237999298,8cyclictest0-21swapper/012:20:130
2237999293,16cyclictest6913-21ssh10:55:130
2240399282,14cyclictest35966irq/58-eth008:20:123
22403992814,10cyclictest35966irq/58-eth009:20:263
2239599284,16cyclictest27346irq/40-dwc2_hso07:50:132
2239599284,16cyclictest27346irq/40-dwc2_hso07:50:132
2239599283,19cyclictest0-21swapper/211:21:252
2239599282,21cyclictest10798-21ssh11:15:022
2239599282,18cyclictest27346irq/40-dwc2_hso11:40:162
2239599281,19cyclictest0-21swapper/207:40:142
2239599281,16cyclictest27346irq/40-dwc2_hso08:55:152
2239599281,16cyclictest27346irq/40-dwc2_hso08:55:152
22395992811,5cyclictest0-21swapper/211:49:192
2237999283,20cyclictest0-21swapper/011:43:240
22379992814,5cyclictest131rcu_preempt09:40:150
2240399272,13cyclictest0-21swapper/309:10:133
2239599278,8cyclictest27-21ksoftirqd/210:37:342
2239599278,13cyclictest27-21ksoftirqd/212:23:222
2239599277,10cyclictest0-21swapper/209:56:232
2238199276,9cyclictest21-21ksoftirqd/108:15:021
22381992710,8cyclictest0-21swapper/111:28:311
2240399262,18cyclictest0-21swapper/311:10:243
2240399262,14cyclictest35966irq/58-eth012:25:133
2239599264,9cyclictest3577-21ssh09:25:152
2239599264,17cyclictest27346irq/40-dwc2_hso08:45:122
2239599263,17cyclictest27346irq/40-dwc2_hso07:55:122
2238199269,4cyclictest21-21ksoftirqd/110:53:511
2238199269,11cyclictest0-21swapper/109:29:471
2238199268,8cyclictest21-21ksoftirqd/110:17:461
2238199262,18cyclictest8499-21ssh11:12:241
22381992613,7cyclictest0-21swapper/109:38:071
22381992613,7cyclictest0-21swapper/109:38:071
22381992613,7cyclictest0-21swapper/109:33:511
22381992613,7cyclictest0-21swapper/109:33:501
2238199261,17cyclictest26279-21ssh09:55:131
2237999268,3cyclictest131rcu_preempt09:20:290
22379992615,8cyclictest12-21ksoftirqd/012:05:130
22379992612,11cyclictest10601-21cat11:30:280
22379992612,11cyclictest10601-21cat11:30:280
2240399258,11cyclictest0-21swapper/310:53:233
2240399252,16cyclictest35966irq/58-eth012:15:133
2239599258,4cyclictest27-21ksoftirqd/211:56:212
2239599254,13cyclictest27346irq/40-dwc2_hso10:05:132
2239599252,18cyclictest16809-21ssh11:16:242
2239599252,17cyclictest0-21swapper/208:00:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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