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2026-08-23 - 11:52

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Sun Aug 23, 2026 00:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29466995432,12cyclictest12-21ksoftirqd/021:45:120
2947599531,41cyclictest24928-21ssh22:45:121
2947599531,38cyclictest1548-21ssh22:50:131
2946699532,11cyclictest131rcu_preempt00:30:140
2946699503,34cyclictest26733-21ssh23:40:120
2947599461,38cyclictest19195-21ssh21:30:151
2946699463,33cyclictest10422-21ssh00:25:120
29493994525,13cyclictest35966irq/58-eth022:55:153
29493994327,7cyclictest35966irq/58-eth021:40:123
2946699422,5cyclictest131rcu_preempt23:15:120
2946699422,32cyclictest3224-21ssh22:15:130
2946699422,32cyclictest3224-21ssh22:15:120
2946699422,30cyclictest12258-21ssh22:20:140
29466994214,21cyclictest12-21ksoftirqd/020:45:150
2947599390,29cyclictest0-21swapper/120:35:131
2946699391,30cyclictest0-21swapper/000:35:140
2948599372,18cyclictest24578-21ssh23:37:562
2948599362,16cyclictest261rcuc/221:45:112
2947599361,24cyclictest10164-21ssh21:25:131
2946699365,22cyclictest12-21ksoftirqd/021:00:140
2949399352,21cyclictest35966irq/58-eth020:15:123
2949399352,21cyclictest35966irq/58-eth020:15:123
2947599357,17cyclictest15063-21diskmemload23:50:131
2946699354,23cyclictest3377-21ssh23:45:120
2949399342,19cyclictest35966irq/58-eth000:00:143
2949399333,15cyclictest35966irq/58-eth022:25:133
2948599332,24cyclictest0-21swapper/221:30:142
2947599332,23cyclictest10551-21ssh22:55:141
29466993319,12cyclictest12-21ksoftirqd/023:25:120
29493993224,6cyclictest321rcuc/320:55:133
2948599322,24cyclictest0-21swapper/223:33:562
2947599322,20cyclictest15050-21kworker/u8:221:10:131
29466993216,10cyclictest0-21swapper/020:10:120
2948599311,2cyclictest131rcu_preempt21:50:122
2949399305,14cyclictest35966irq/58-eth021:55:123
2949399304,14cyclictest0-21swapper/321:30:143
29493993020,7cyclictest35966irq/58-eth023:40:133
2948599302,23cyclictest27608-1kworker/u9:123:57:432
2948599302,20cyclictest27346irq/40-dwc2_hso22:50:152
2947599303,19cyclictest17691-21ssh23:35:111
29493992919,7cyclictest35966irq/58-eth022:00:143
2948599294,6cyclictest28436-21ssh00:35:142
2948599294,19cyclictest27346irq/40-dwc2_hso22:05:152
29475992917,8cyclictest15063-21diskmemload22:40:171
29475992911,13cyclictest15545-21kworker/u8:223:57:431
29466992914,10cyclictest8591-21sh22:00:130
2949399284,17cyclictest0-21swapper/321:25:133
2949399283,13cyclictest35966irq/58-eth022:45:123
2949399281,16cyclictest35966irq/58-eth023:10:123
2948599283,16cyclictest27346irq/40-dwc2_hso21:20:142
2948599282,17cyclictest27346irq/40-dwc2_hso21:40:122
2948599282,17cyclictest27346irq/40-dwc2_hso20:30:132
2948599282,15cyclictest27346irq/40-dwc2_hso21:15:132
2948599282,11cyclictest30536-21ssh00:00:152
2948599282,11cyclictest0-21swapper/220:10:132
2948599281,21cyclictest0-21swapper/220:25:142
2948599281,20cyclictest27346irq/40-dwc2_hso22:15:132
2948599281,20cyclictest27346irq/40-dwc2_hso22:15:132
2947599281,16cyclictest4814-21ssh21:40:131
2946699282,20cyclictest31593-21ssh23:24:570
2946699281,21cyclictest6930-21ssh22:35:140
2949399275,19cyclictest0-21swapper/300:10:153
2949399275,19cyclictest0-21swapper/300:10:143
2949399274,13cyclictest0-21swapper/300:25:133
29493992718,5cyclictest321rcuc/320:05:143
29493992714,6cyclictest36066irq/59-eth023:55:123
29493992712,6cyclictest0-21swapper/321:05:133
2949399271,18cyclictest0-21swapper/321:20:133
2948599273,16cyclictest27346irq/40-dwc2_hso20:35:132
2948599272,19cyclictest0-21swapper/222:30:142
2948599271,15cyclictest28209-21ssh21:35:142
2947599273,15cyclictest21274-21ssh22:25:131
29475992715,7cyclictest21-21ksoftirqd/121:05:131
2947599271,22cyclictest14124-21ssh23:15:131
2946699272,22cyclictest26642-21ssh22:10:150
2946699272,22cyclictest26642-21ssh22:10:140
2949399263,15cyclictest0-21swapper/323:20:143
2949399262,14cyclictest35966irq/58-eth021:35:133
29493992616,6cyclictest0-21swapper/319:30:133
2948599263,12cyclictest27346irq/40-dwc2_hso20:55:132
2948599262,18cyclictest8309-21ssh00:22:562
2948599261,14cyclictest23906-21ls20:45:182
2948599261,13cyclictest10550-21sh22:55:142
29475992613,10cyclictest7217-21ssh23:45:271
2946699262,19cyclictest1203-21sh21:20:150
2946699262,18cyclictest16429-21ssh23:33:550
29466992613,6cyclictest0-21swapper/021:55:110
2946699261,18cyclictest19510-21sh23:00:130
2949399252,17cyclictest36066irq/59-eth021:10:133
2948599252,8cyclictest15063-21diskmemload23:19:562
2948599251,17cyclictest27346irq/40-dwc2_hso20:20:122
2947599253,19cyclictest7058-21ssh00:05:151
2947599251,18cyclictest23087-21ssh23:20:141
29475992510,7cyclictest48-21kcompactd020:50:121
2949399243,13cyclictest0-21swapper/323:35:123
2949399241,14cyclictest35966irq/58-eth000:35:133
2948599242,17cyclictest27346irq/40-dwc2_hso00:15:142
2948599242,17cyclictest27346irq/40-dwc2_hso00:15:142
2948599242,17cyclictest0-21swapper/223:53:572
29485992412,4cyclictest7034-21ntp_states23:45:252
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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