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2026-08-05 - 14:41

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Wed Aug 05, 2026 00:45:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30402996747,15cyclictest35966irq/58-eth021:25:113
30402996037,11cyclictest35966irq/58-eth021:50:133
3038599603,33cyclictest131rcu_preempt22:55:131
30377995610,6cyclictest131rcu_preempt00:20:140
3038599556,45cyclictest1636-21ssh23:25:111
3038599556,45cyclictest1636-21ssh23:25:101
3038599525,40cyclictest31059-21ssh00:35:171
30385994611,10cyclictest131rcu_preempt19:30:141
3040299454,27cyclictest35966irq/58-eth022:25:143
3040299431,23cyclictest35966irq/58-eth022:40:153
3040299423,22cyclictest35966irq/58-eth023:50:123
3038599421,33cyclictest10698-21ssh23:30:111
3039399412,25cyclictest8468-21ssh22:35:132
3040299403,24cyclictest35966irq/58-eth023:20:123
3037799394,27cyclictest18367-21ssh00:10:140
3039399384,6cyclictest0-21swapper/222:10:132
30385993811,19cyclictest21-21ksoftirqd/123:35:171
3037799381,23cyclictest2236-21ssh21:20:130
3040299373,19cyclictest35966irq/58-eth023:00:153
3040299373,17cyclictest35966irq/58-eth019:10:133
3037799371,31cyclictest12963-21ssh00:25:150
3040299352,17cyclictest35966irq/58-eth000:00:123
30402993519,11cyclictest35966irq/58-eth021:55:133
3037799354,19cyclictest16497-21ssh21:10:140
3037799342,28cyclictest19864-21ssh23:35:170
3040299331,21cyclictest0-21swapper/321:15:153
3037799337,7cyclictest131rcu_preempt23:20:120
3040299324,18cyclictest35966irq/58-eth022:00:153
30402993216,8cyclictest0-21swapper/321:05:143
3040299321,18cyclictest35966irq/58-eth021:35:153
3039399323,18cyclictest27346irq/40-dwc2_hso00:30:132
30385993219,8cyclictest0-21swapper/100:20:131
3037799324,11cyclictest12-21ksoftirqd/023:05:140
30402993114,13cyclictest35966irq/58-eth023:40:143
3039399313,17cyclictest0-21swapper/223:35:172
30393993123,5cyclictest27346irq/40-dwc2_hso23:55:132
3038599313,18cyclictest131rcu_preempt20:45:111
3038599312,21cyclictest11130-21sh23:46:271
30402993020,6cyclictest0-21swapper/323:35:173
3039399306,18cyclictest7902-1kworker/2:1H22:50:042
3039399304,10cyclictest2399-21kthreadcore23:25:192
3039399304,10cyclictest2399-21kthreadcore23:25:182
3039399303,21cyclictest0-21swapper/223:11:182
3039399303,20cyclictest0-21swapper/219:45:152
3039399303,17cyclictest27346irq/40-dwc2_hso22:45:142
30385993010,15cyclictest21-21ksoftirqd/123:05:161
3037799303,4cyclictest131rcu_preempt22:45:130
3040299292,16cyclictest35966irq/58-eth022:55:133
3040299292,10cyclictest35966irq/58-eth023:55:143
3039399293,19cyclictest27346irq/40-dwc2_hso19:50:132
3039399293,15cyclictest27346irq/40-dwc2_hso20:20:102
3039399292,20cyclictest0-21swapper/223:50:142
3039399292,20cyclictest0-21swapper/220:45:112
3039399292,15cyclictest17539-21ssh22:40:142
3038599291,24cyclictest22798-21ssh22:25:141
3038599291,21cyclictest24169-21ssh21:50:121
3038599291,20cyclictest27983-21ssh22:10:151
3040299282,15cyclictest35966irq/58-eth020:25:143
3039399288,12cyclictest27-21ksoftirqd/223:06:122
3039399286,13cyclictest27346irq/40-dwc2_hso23:45:132
3039399284,14cyclictest27346irq/40-dwc2_hso20:55:152
3039399283,13cyclictest27-21ksoftirqd/220:40:302
3039399282,18cyclictest27346irq/40-dwc2_hso20:25:142
3038599285,4cyclictest131rcu_preempt23:55:131
3038599281,20cyclictest15119-21ssh21:45:121
30385992811,13cyclictest131rcu_preempt21:25:101
3040299271,17cyclictest35966irq/58-eth023:45:143
3039399278,4cyclictest27-21ksoftirqd/221:17:322
3039399273,18cyclictest27346irq/40-dwc2_hso19:15:142
3039399273,11cyclictest27-21ksoftirqd/200:17:242
30393992712,4cyclictest27-21ksoftirqd/223:20:332
3038599275,18cyclictest6077-21ssh21:40:151
30377992713,4cyclictest12-21ksoftirqd/023:15:160
3039399266,6cyclictest27-21ksoftirqd/200:21:122
30377992613,4cyclictest12-21ksoftirqd/023:30:190
3037799261,19cyclictest31917-21ssh00:35:240
3039399259,3cyclictest27-21ksoftirqd/221:56:092
3039399257,8cyclictest27-21ksoftirqd/221:11:382
3039399255,8cyclictest27-21ksoftirqd/221:25:102
3039399255,13cyclictest27-21ksoftirqd/222:04:562
3039399253,7cyclictest131rcu_preempt21:05:152
3039399253,14cyclictest27346irq/40-dwc2_hso23:40:142
3039399251,9cyclictest8330-21ssh00:04:202
3039399251,9cyclictest16528-21ssh00:08:192
30393992513,9cyclictest261rcuc/220:30:132
30393992513,9cyclictest19435-21ssh22:21:302
3039399251,16cyclictest20323-21acpi21:30:122
3039399251,16cyclictest16079-21diskmemload23:15:142
3039399250,17cyclictest5721-21ls21:40:012
3038599251,17cyclictest73-21kswapd000:30:151
3037799254,13cyclictest131rcu_preempt21:50:100
30377992514,3cyclictest12-21ksoftirqd/022:56:320
3037799251,21cyclictest6087-21ssh21:40:150
3037799251,20cyclictest29468-21ssh21:35:160
3039399249,3cyclictest27-21ksoftirqd/200:25:032
3039399247,4cyclictest27-21ksoftirqd/222:57:402
3039399246,8cyclictest27-21ksoftirqd/222:07:142
3039399243,16cyclictest27346irq/40-dwc2_hso20:00:132
3039399241,14cyclictest8242-21awk22:15:242
3039399240,11cyclictest10396-21timerandwakeup21:00:302
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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