You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-27 - 05:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Fri Feb 27, 2026 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1764699588,12cyclictest21-21ksoftirqd/120:55:111
1765599542,5cyclictest0-21swapper/219:40:152
1763099503,6cyclictest131rcu_preempt19:40:140
17665994924,13cyclictest28366irq/58-eth023:35:123
17630994528,9cyclictest11979-21ssh21:50:140
1765599422,32cyclictest15585-21systemd23:02:312
1763099427,8cyclictest131rcu_preempt23:15:120
1763099427,8cyclictest131rcu_preempt23:15:120
1763099423,11cyclictest12-21ksoftirqd/022:10:120
1765599403,20cyclictest11978-21sh21:50:132
1765599402,19cyclictest8654-21sh21:46:302
1765599401,31cyclictest0-21swapper/219:50:112
1763099402,10cyclictest12-21ksoftirqd/020:05:110
1765599392,29cyclictest23372-21ssh22:50:122
17646993911,7cyclictest21-21ksoftirqd/122:10:121
1765599382,13cyclictest10672-21usage_Anybus00:10:312
1765599382,13cyclictest10672-21usage_Anybus00:10:312
1763099381,28cyclictest2340-21ssh23:50:130
1763099371,22cyclictest12801-21ssh23:20:110
1765599363,25cyclictest0-21swapper/221:40:302
1765599362,28cyclictest16373-21ssh21:34:292
1765599362,18cyclictest924-21snmpd23:42:372
1763099361,26cyclictest2910-21ssh21:45:140
1765599356,14cyclictest27292-21cat21:20:302
17630993512,9cyclictest12-21ksoftirqd/023:29:300
1765599341,27cyclictest3806-21ssh23:15:152
1765599341,27cyclictest3806-21ssh23:15:142
1766599322,17cyclictest28366irq/58-eth022:00:143
17665993215,11cyclictest0-21swapper/323:14:303
1765599323,23cyclictest0-21swapper/221:38:302
1764699321,5cyclictest131rcu_preempt00:30:141
1765599315,13cyclictest22346irq/40-dwc2_hso19:30:112
1765599313,18cyclictest22346irq/40-dwc2_hso23:35:132
1764699315,16cyclictest3935-21diskmemload21:20:131
1765599306,4cyclictest131rcu_preempt20:05:122
1765599302,11cyclictest32004-21users23:10:302
1764699308,5cyclictest131rcu_preempt21:25:131
1764699302,20cyclictest24682-21ssh22:15:131
1763099307,7cyclictest131rcu_preempt23:30:130
1763099304,9cyclictest0-21swapper/019:35:120
1763099301,20cyclictest8160-21ssh21:30:120
1765599293,21cyclictest0-21swapper/200:18:312
1765599293,19cyclictest0-21swapper/221:18:302
1765599293,11cyclictest0-21swapper/221:27:162
1765599292,11cyclictest23796-21ssh23:06:292
1764699292,22cyclictest30012-21sh22:00:141
17646992916,10cyclictest21-21ksoftirqd/122:30:131
1764699291,21cyclictest12807-21ssh23:20:111
1763099294,7cyclictest131rcu_preempt23:58:310
1763099293,4cyclictest131rcu_preempt22:50:110
1763099291,22cyclictest942-21ssh00:25:110
1766599283,20cyclictest28366irq/58-eth020:35:123
1766599282,17cyclictest28366irq/58-eth023:20:133
1765599283,16cyclictest22346irq/40-dwc2_hso20:20:142
1765599282,19cyclictest32362-21ssh22:55:132
1765599282,16cyclictest20406-21ssh00:00:142
1765599282,16cyclictest15662-21ssh22:10:142
1765599281,20cyclictest73-21kswapd000:25:132
17646992818,8cyclictest21-21ksoftirqd/119:10:111
1766599273,11cyclictest28366irq/58-eth020:40:093
17665992710,11cyclictest0-21swapper/322:59:303
1765599273,16cyclictest22346irq/40-dwc2_hso21:05:112
1765599273,14cyclictest22346irq/40-dwc2_hso20:45:152
1765599272,20cyclictest0-21swapper/220:25:132
17646992722,2cyclictest6264-21ssh00:10:141
17646992722,2cyclictest6264-21ssh00:10:141
1763099272,19cyclictest14743-21ssh23:01:300
1763099272,18cyclictest12425-21cat23:35:300
1763099271,20cyclictest24626-21ssh21:38:300
1763099271,19cyclictest0-21swapper/020:15:130
1764699262,18cyclictest12426-21usage_EthcTask23:35:301
17646992613,4cyclictest21-21ksoftirqd/123:50:211
1763099261,19cyclictest2945-21ssh23:14:310
1763099261,18cyclictest25773-21ssh23:45:130
1765599253,17cyclictest22346irq/40-dwc2_hso22:05:122
1765599253,15cyclictest22346irq/40-dwc2_hso20:00:142
1765599252,18cyclictest22346irq/40-dwc2_hso21:55:132
1765599252,17cyclictest24349-21ssh00:20:122
1765599252,15cyclictest22346irq/40-dwc2_hso23:30:122
1764699259,4cyclictest0-21swapper/122:36:371
17646992518,3cyclictest131rcu_preempt19:30:101
17646992513,3cyclictest21-21ksoftirqd/100:17:561
1763099251,3cyclictest131rcu_preempt20:34:300
1763099251,18cyclictest26338-21ssh21:40:150
1766599248,10cyclictest0-21swapper/323:40:313
1766599243,10cyclictest0-21swapper/321:13:303
1766599242,15cyclictest28366irq/58-eth019:45:133
1766599242,10cyclictest0-21swapper/323:07:293
1765599249,11cyclictest25368-21cut23:25:242
1765599240,21cyclictest1628-21timerandwakeup20:30:292
1765599240,17cyclictest27143-21ls21:00:182
1764699249,4cyclictest27245-21irqcore21:00:201
17630992413,7cyclictest6849-21sed00:10:190
17630992413,7cyclictest6849-21sed00:10:190
17630992412,4cyclictest12-21ksoftirqd/000:09:030
1763099241,11cyclictest28122-21latency_hist22:35:020
1763099241,11cyclictest27409-21kthreadcore19:50:190
1766599232,12cyclictest28366irq/58-eth000:05:123
1766599231,11cyclictest0-21swapper/321:30:133
1765599233,14cyclictest22346irq/40-dwc2_hso20:55:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional