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2026-05-05 - 05:27

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Tue May 05, 2026 00:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1162999552,10cyclictest12-21ksoftirqd/020:30:110
1164199533,8cyclictest131rcu_preempt19:15:131
1164199522,9cyclictest131rcu_preempt22:20:131
1165299492,24cyclictest22433-21ssh22:00:142
11652994918,25cyclictest27-21ksoftirqd/222:55:132
1164199461,32cyclictest21709-21ssh23:30:141
1164199442,34cyclictest10139-21ssh21:35:121
1166099433,19cyclictest35966irq/58-eth000:35:123
1164199433,20cyclictest11665-21ssh22:10:251
1162999433,34cyclictest28467-21ssh00:10:130
11629994330,6cyclictest0-21swapper/023:00:140
1162999432,32cyclictest167-21systemd-network00:35:120
1166099424,24cyclictest35966irq/58-eth023:00:133
1164199413,31cyclictest3804-21ssh23:20:131
1164199413,31cyclictest3804-21ssh23:20:131
1164199401,29cyclictest12777-21rm23:25:151
1166099393,21cyclictest35966irq/58-eth022:40:103
1166099392,22cyclictest35966irq/58-eth022:45:123
1165299391,31cyclictest4544-21ssh21:50:132
1162999381,31cyclictest16875-21ssh22:15:110
1165299372,18cyclictest5546-21kthreadcore22:25:232
1165299361,26cyclictest20353-21sh22:35:112
1164199364,23cyclictest5775-21ssh22:45:121
1162999362,26cyclictest13680-21missed_timers21:35:230
1162999361,29cyclictest11390-21ssh22:30:120
1165299351,16cyclictest22854-21ssh00:25:132
1165299351,16cyclictest22854-21ssh00:25:132
1165299341,4cyclictest131rcu_preempt23:00:132
1166099338,16cyclictest35966irq/58-eth022:05:123
1165299325,18cyclictest27346irq/40-dwc2_hso23:40:132
1164199322,25cyclictest25078-21ssh23:50:131
1164199322,19cyclictest31827-21ssh00:30:121
11629993225,3cyclictest15688-21ssh21:20:130
1166099311,20cyclictest35966irq/58-eth000:05:173
1165299312,24cyclictest930-21snmpd19:20:142
1165299312,19cyclictest27346irq/40-dwc2_hso22:30:122
1164199315,16cyclictest1546-21ssh23:55:121
1164199312,23cyclictest16145-21ssh23:45:131
1162999312,22cyclictest9305-21ssh23:05:150
1166099306,15cyclictest35966irq/58-eth020:55:123
1166099303,13cyclictest35966irq/58-eth022:50:143
1166099302,16cyclictest35966irq/58-eth023:10:113
1166099302,16cyclictest0-21swapper/321:45:113
1165299304,16cyclictest27727-21kworker/u8:022:50:152
1165299302,23cyclictest14706-21ssh22:12:512
1165299302,21cyclictest0-21swapper/220:35:132
1165299300,22cyclictest31362-21ssh22:05:142
1164199306,19cyclictest21-21ksoftirqd/122:15:131
11641993011,13cyclictest30210-21ssh21:10:111
1166099292,17cyclictest35966irq/58-eth019:35:123
1165299293,18cyclictest27346irq/40-dwc2_hso23:30:132
1165299293,11cyclictest0-21swapper/219:40:132
1165299292,19cyclictest27346irq/40-dwc2_hso21:15:142
1165299292,17cyclictest27346irq/40-dwc2_hso00:20:112
11652992912,12cyclictest12776-21sh23:25:152
11641992911,10cyclictest14111-21kworker/1:020:20:121
11641992911,10cyclictest14111-21kworker/1:020:20:121
11629992915,10cyclictest151rcuc/021:30:130
1166099283,18cyclictest0-21swapper/322:32:543
1166099281,17cyclictest35966irq/58-eth000:15:133
1165299284,17cyclictest27346irq/40-dwc2_hso21:05:152
1165299284,14cyclictest27346irq/40-dwc2_hso19:25:142
1165299282,21cyclictest32688-21ssh22:22:522
1165299282,19cyclictest27346irq/40-dwc2_hso21:35:122
1165299282,11cyclictest27-21ksoftirqd/221:33:232
11641992818,6cyclictest19083-21sh21:40:141
11641992818,5cyclictest0-21swapper/120:15:141
1162999289,13cyclictest14668-1kworker/u9:021:25:130
1162999281,23cyclictest6755-21ssh21:15:140
1162999281,21cyclictest7226-21ssh23:40:130
1166099273,13cyclictest35966irq/58-eth021:20:133
1165299273,16cyclictest27346irq/40-dwc2_hso00:10:122
1165299272,15cyclictest1562-21ssh23:55:132
1165299272,11cyclictest0-21swapper/219:55:132
1165299272,10cyclictest0-21swapper/221:00:142
1165299272,10cyclictest0-21swapper/221:00:142
1165299271,21cyclictest3631-21ssh21:49:232
11652992712,12cyclictest0-21swapper/223:15:022
1162999274,6cyclictest0-21swapper/023:35:120
1162999274,17cyclictest19595-21ssh00:05:170
1162999274,16cyclictest14797-21ssh22:50:140
1162999272,19cyclictest30903-21ssh00:29:230
1162999272,19cyclictest30903-21ssh00:29:230
1162999272,18cyclictest15148-21sh22:13:230
1162999271,20cyclictest18182-21ssh23:10:130
11629992711,8cyclictest12-21ksoftirqd/022:01:490
1165299269,14cyclictest14113-21cron20:20:012
1165299264,5cyclictest0-21swapper/220:20:122
1165299264,5cyclictest0-21swapper/220:20:122
1165299263,19cyclictest27346irq/40-dwc2_hso00:35:112
1165299262,17cyclictest29818-21diskmemload21:40:142
11652992611,9cyclictest20506-21ssh22:15:232
1165299261,10cyclictest30598-21ssh23:35:122
1162999263,19cyclictest20355-21ssh22:35:110
1166099254,10cyclictest35966irq/58-eth021:25:133
1166099252,17cyclictest0-21swapper/323:59:223
1166099252,16cyclictest35966irq/58-eth021:30:123
1165299254,15cyclictest27346irq/40-dwc2_hso00:00:122
1165299254,13cyclictest27346irq/40-dwc2_hso19:10:132
1165299254,10cyclictest27346irq/40-dwc2_hso20:55:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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