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2026-02-05 - 22:34
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Thu Feb 05, 2026 00:45:09)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
758999598,4cyclictest131rcu_preempt20:45:130
758999598,4cyclictest131rcu_preempt20:45:120
761299572,34cyclictest12914-21ssh22:50:112
7589995431,18cyclictest25737-21diskmemload22:25:140
758999541,23cyclictest30047-21ssh21:30:120
7612995319,20cyclictest131rcu_preempt23:15:132
760099501,8cyclictest131rcu_preempt19:45:121
758999501,39cyclictest18375-21ssh22:35:140
761299488,15cyclictest131rcu_preempt19:35:142
7612994835,10cyclictest261rcuc/222:35:132
758999483,35cyclictest7748-21ssh23:05:120
758999482,39cyclictest22670-21ssh00:25:140
762099454,27cyclictest28366irq/58-eth021:50:133
762099453,24cyclictest28366irq/58-eth023:55:123
758999445,9cyclictest10688-21ssh21:55:130
7612994217,10cyclictest261rcuc/221:30:122
758999429,30cyclictest0-21swapper/000:15:140
758999423,28cyclictest11563-21ssh23:25:130
762099412,25cyclictest28366irq/58-eth023:15:123
7612994122,16cyclictest131rcu_preempt21:10:132
761299402,25cyclictest27-21ksoftirqd/222:40:132
761299402,25cyclictest27-21ksoftirqd/222:40:132
760099408,25cyclictest1654-21kworker/u8:122:10:131
7600993915,21cyclictest21-21ksoftirqd/120:30:131
7600993910,23cyclictest21-21ksoftirqd/100:05:131
760099384,31cyclictest8338-21ssh00:35:121
7620993720,8cyclictest28366irq/58-eth022:50:123
761299372,10cyclictest131rcu_preempt19:25:132
762099363,19cyclictest28366irq/58-eth000:30:143
762099362,22cyclictest28366irq/58-eth021:45:133
7620993621,9cyclictest0-21swapper/322:20:123
762099362,18cyclictest28366irq/58-eth023:05:123
761299363,11cyclictest18972-21ssh00:05:122
761299362,26cyclictest16743-21ssh23:10:122
760099365,20cyclictest20672-21ssh23:30:141
760099362,28cyclictest9308-21ssh22:30:131
7612993419,11cyclictest25737-21diskmemload21:20:132
758999341,25cyclictest23672-21ssh22:20:120
762099333,18cyclictest28366irq/58-eth021:35:133
7620993322,5cyclictest0-21swapper/322:45:143
758999331,23cyclictest19802-21ssh22:00:130
758999331,23cyclictest19802-21ssh22:00:130
762099327,16cyclictest28366irq/58-eth023:45:133
762099327,16cyclictest28366irq/58-eth023:45:133
762099323,16cyclictest28366irq/58-eth023:30:133
7620993218,11cyclictest0-21swapper/300:05:123
7612993212,10cyclictest27-21ksoftirqd/223:40:142
760099322,20cyclictest1541-21sh21:50:121
7600993221,8cyclictest0-21swapper/123:40:141
760099312,3cyclictest0-21swapper/122:55:121
758999312,14cyclictest25878-21ssh00:07:570
758999311,27cyclictest24386-21sh23:50:130
7620993017,6cyclictest0-21swapper/320:25:143
761299306,14cyclictest22346irq/40-dwc2_hso00:00:112
761299301,18cyclictest0-21swapper/220:20:132
760099301,20cyclictest26156-21ssh21:10:141
7600993011,16cyclictest21-21ksoftirqd/100:25:141
760099300,26cyclictest3938-21ssh22:45:141
762099293,15cyclictest28366irq/58-eth021:10:133
761299292,21cyclictest0-21swapper/221:00:172
761299292,20cyclictest0-21swapper/219:50:142
761299292,17cyclictest261rcuc/221:45:122
760099291,23cyclictest4671-21rm00:15:151
758999293,8cyclictest0-21swapper/000:14:570
758999292,20cyclictest14646-21ssh22:15:130
7620992818,8cyclictest0-21swapper/320:15:123
7620992816,8cyclictest0-21swapper/323:10:133
7620992812,12cyclictest28366irq/58-eth022:05:143
761299285,14cyclictest22346irq/40-dwc2_hso20:05:102
761299283,19cyclictest28847-21ssh22:05:142
761299282,21cyclictest22346irq/40-dwc2_hso21:05:142
761299282,19cyclictest0-21swapper/219:15:142
761299282,10cyclictest11501-21ssh00:17:582
761299281,17cyclictest2521-21ssh23:20:122
761299281,10cyclictest2817-21ssh21:15:142
760099283,17cyclictest18360-21ssh22:35:121
760099281,20cyclictest1001-21ssh23:55:131
7620992722,2cyclictest0-21swapper/322:40:133
7620992722,2cyclictest0-21swapper/322:40:133
7620992720,2cyclictest0-21swapper/323:25:123
7620992713,8cyclictest28366irq/58-eth022:30:143
761299274,12cyclictest22346irq/40-dwc2_hso22:25:132
761299272,13cyclictest15359-21ssh23:45:142
761299272,13cyclictest15359-21ssh23:45:132
761299271,18cyclictest5459-21find20:15:122
761299271,16cyclictest22346irq/40-dwc2_hso20:30:142
760099272,19cyclictest17153-21ssh00:03:191
762099263,16cyclictest0-21swapper/300:03:193
7620992620,2cyclictest0-21swapper/320:35:113
7620992618,5cyclictest0-21swapper/321:40:123
7620992614,8cyclictest0-21swapper/322:25:153
762099261,11cyclictest28366irq/58-eth020:30:133
761299269,9cyclictest27-21ksoftirqd/221:25:132
761299266,2cyclictest131rcu_preempt23:00:282
761299263,16cyclictest9529-21kworker/2:200:20:162
761299262,15cyclictest22346irq/40-dwc2_hso23:35:112
761299262,13cyclictest22346irq/40-dwc2_hso20:50:132
758999262,9cyclictest0-21swapper/019:45:120
758999262,17cyclictest21980-21ssh22:55:130
7620992518,4cyclictest0-21swapper/323:20:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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