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2026-02-27 - 17:41
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Fri Feb 27, 2026 12:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26115997041,22cyclictest0-21swapper/207:45:132
2609499544,6cyclictest131rcu_preempt10:30:100
26129995334,14cyclictest28366irq/58-eth012:05:113
2609499534,7cyclictest131rcu_preempt07:55:120
2609499520,9cyclictest131rcu_preempt09:50:110
2609499520,9cyclictest131rcu_preempt09:50:110
2610599475,36cyclictest5370-21ssh12:05:101
2610599442,34cyclictest30769-21ssh09:20:131
2612999433,21cyclictest28366irq/58-eth012:30:103
2612999432,31cyclictest28366irq/58-eth010:35:133
2610599434,27cyclictest21475-21ssh11:20:121
2610599434,27cyclictest21475-21ssh11:20:121
2610599432,35cyclictest10890-21ssh11:50:131
2609499433,4cyclictest131rcu_preempt10:40:130
2609499411,29cyclictest949-21ssh10:15:140
2611599394,29cyclictest261rcuc/209:45:132
2612999372,19cyclictest28366irq/58-eth010:00:123
26105993727,4cyclictest131rcu_preempt10:05:111
2610599361,22cyclictest27023-21ssh12:35:121
26094993617,12cyclictest0-21swapper/009:15:110
2611599356,9cyclictest8614-21ssh10:55:122
26105993414,4cyclictest21-21ksoftirqd/108:55:141
26105993414,11cyclictest21-21ksoftirqd/110:00:141
2609499341,24cyclictest10884-21ssh11:50:120
2612999333,19cyclictest28366irq/58-eth008:05:123
26129993316,9cyclictest28366irq/58-eth011:10:123
2611599333,21cyclictest3294-21ssh11:10:132
26105993319,10cyclictest0-21swapper/108:50:121
2612999322,15cyclictest28366irq/58-eth010:25:133
2611599322,22cyclictest2822-21ssh09:56:312
2610599321,24cyclictest23474-21ssh12:15:141
2609499322,3cyclictest131rcu_preempt12:15:120
2612999314,14cyclictest0-21swapper/312:15:123
2612999312,19cyclictest28366irq/58-eth012:00:123
26115993113,11cyclictest261rcuc/210:40:132
2611599311,18cyclictest7407-21ssh09:25:142
2610599315,19cyclictest3298-21sh11:10:121
2610599312,22cyclictest8627-21ssh10:55:131
2612999301,19cyclictest28366irq/58-eth008:50:123
2612999301,15cyclictest28366irq/58-eth011:20:113
2612999301,15cyclictest28366irq/58-eth011:20:113
2611599304,14cyclictest22346irq/40-dwc2_hso08:20:132
2611599303,15cyclictest22346irq/40-dwc2_hso08:00:122
2611599294,16cyclictest22346irq/40-dwc2_hso09:50:112
2611599294,16cyclictest22346irq/40-dwc2_hso09:50:112
2610599295,7cyclictest131rcu_preempt10:28:311
2610599293,16cyclictest21-21ksoftirqd/107:20:121
2610599292,22cyclictest16380-21ssh12:28:311
26105992917,7cyclictest12359-21diskmemload09:50:131
26105992917,7cyclictest12359-21diskmemload09:50:131
2610599291,22cyclictest30627-21ssh11:25:141
2609499292,20cyclictest11133-21ssh12:06:310
2611599284,15cyclictest22346irq/40-dwc2_hso11:35:142
2611599282,10cyclictest24320-21ssh09:33:572
2609499287,18cyclictest12-21ksoftirqd/008:00:120
2609499282,20cyclictest1928-21ssh11:45:130
2609499281,3cyclictest131rcu_preempt12:25:120
2612999273,16cyclictest0-21swapper/312:28:313
26129992719,5cyclictest28366irq/58-eth011:30:133
26129992717,6cyclictest321rcuc/310:30:113
2611599274,14cyclictest22346irq/40-dwc2_hso07:35:122
2611599274,12cyclictest0-21swapper/211:50:122
2610599272,19cyclictest25372-21ssh11:40:131
2610599272,19cyclictest12359-21diskmemload10:30:311
2610599272,16cyclictest13741-21ssh10:40:151
2609499274,20cyclictest16241-21ssh11:35:130
2609499272,20cyclictest24309-21ssh09:33:560
2609499272,19cyclictest25615-21ssh09:35:130
2609499272,13cyclictest7210-21ssh11:30:110
2611599263,16cyclictest22346irq/40-dwc2_hso09:00:132
2611599263,15cyclictest22346irq/40-dwc2_hso10:30:122
2611599261,7cyclictest499066ssh10:15:302
2610599261,17cyclictest12778-21ssh09:10:141
2609499261,3cyclictest131rcu_preempt11:55:130
2609499261,2cyclictest131rcu_preempt11:05:130
2612999255,12cyclictest0-21swapper/311:55:143
2612999253,16cyclictest28366irq/58-eth007:30:123
2612999253,14cyclictest0-21swapper/311:40:133
2612999252,16cyclictest28366irq/58-eth008:55:133
2611599259,5cyclictest27-21ksoftirqd/208:05:132
2611599255,11cyclictest25611-21ssh09:35:122
2611599252,18cyclictest7166-21ssh09:40:312
2611599252,17cyclictest22596-21kworker/u8:111:25:052
2611599251,7cyclictest1855366ssh11:17:022
26105992513,8cyclictest0-21swapper/109:30:131
2610599251,16cyclictest15355-21kworker/u8:210:45:131
2609499251,19cyclictest11382-21ssh09:45:130
2609499251,14cyclictest30872-21df09:20:150
2612999243,14cyclictest0-21swapper/310:40:153
2611599241,7cyclictest544666ssh12:21:092
2611599241,7cyclictest2438966ssh10:10:142
2611599241,7cyclictest2142466ssh11:20:102
2611599241,7cyclictest2142466ssh11:20:092
26115992417,4cyclictest0-21swapper/211:45:132
2611599241,6cyclictest2904066ssh12:16:202
2609499245,6cyclictest12-21ksoftirqd/012:30:160
2609499241,17cyclictest3285-21ssh11:10:110
2609499241,17cyclictest18981-21apt-get10:25:130
2612999234,13cyclictest0-21swapper/309:20:143
2612999233,14cyclictest0-21swapper/309:50:313
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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