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2026-06-22 - 22:29

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot4s.osadl.org (updated Mon Jun 22, 2026 12:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
676699511,9cyclictest131rcu_preempt12:25:140
6801994931,13cyclictest0-21swapper/310:05:143
676699443,5cyclictest131rcu_preempt09:20:110
676699441,4cyclictest131rcu_preempt10:55:120
680199436,26cyclictest35966irq/58-eth011:00:133
6778994318,17cyclictest21-21ksoftirqd/109:35:141
6778994318,17cyclictest21-21ksoftirqd/109:35:141
676699424,35cyclictest12144-21ssh11:45:110
676699423,34cyclictest14003-21ssh11:10:140
676699413,35cyclictest14148-21ssh09:40:130
676699407,11cyclictest131rcu_preempt08:15:130
680199391,32cyclictest35966irq/58-eth010:35:133
676699397,24cyclictest8623-21ssh09:55:100
680199383,19cyclictest35966irq/58-eth011:40:123
679199372,26cyclictest19718-21ssh09:25:122
679199372,18cyclictest5262-21ssh11:58:402
677899372,24cyclictest24746-21ssh10:40:121
676699373,31cyclictest28104-21ssh12:30:130
680199363,19cyclictest35966irq/58-eth012:20:123
676699363,29cyclictest30082-21ssh10:25:120
6766993621,9cyclictest131rcu_preempt08:00:130
680199351,17cyclictest35966irq/58-eth011:45:133
679199351,29cyclictest12183-21ssh10:15:122
679199342,25cyclictest29863-21ssh10:40:482
6791993415,14cyclictest0-21swapper/208:00:132
679199335,16cyclictest27346irq/40-dwc2_hso11:45:112
679199332,5cyclictest0-21swapper/208:35:122
680199322,18cyclictest35966irq/58-eth011:10:153
6801993216,11cyclictest35966irq/58-eth010:45:123
6801993213,11cyclictest35966irq/58-eth009:45:123
6791993212,14cyclictest0-21swapper/212:10:122
679199321,19cyclictest21144-21ssh10:20:122
677899322,24cyclictest22969-21ssh11:15:131
677899321,22cyclictest28654-21ssh09:30:111
677899321,22cyclictest28654-21ssh09:30:101
676699321,25cyclictest1309-21ssh10:45:120
680199313,17cyclictest35966irq/58-eth008:35:133
680199312,17cyclictest35966irq/58-eth012:05:133
679199316,19cyclictest17685-21ssh10:00:142
679199313,17cyclictest23085-21diskmemload09:45:122
679199302,18cyclictest0-21swapper/211:10:152
676699302,22cyclictest21093-21ssh12:06:060
676699301,4cyclictest131rcu_preempt11:20:110
680199291,19cyclictest35966irq/58-eth008:30:133
679199293,16cyclictest27346irq/40-dwc2_hso11:00:132
679199293,16cyclictest27346irq/40-dwc2_hso07:20:132
679199292,11cyclictest930-21snmpd11:21:402
6791992911,12cyclictest27-21ksoftirqd/211:25:572
6791992910,11cyclictest131rcu_preempt09:19:112
677899293,16cyclictest6809-21ssh12:00:131
6766992910,4cyclictest12-21ksoftirqd/010:05:120
680199283,16cyclictest0-21swapper/310:40:493
6801992810,6cyclictest0-21swapper/310:31:103
679199282,20cyclictest0-21swapper/211:40:132
679199282,11cyclictest23218-21ssh12:08:402
679199282,10cyclictest12602-21ssh12:01:402
6791992810,11cyclictest27-21ksoftirqd/209:38:002
6791992810,11cyclictest27-21ksoftirqd/209:37:592
677899286,10cyclictest0-21swapper/110:15:121
677899282,16cyclictest6677-21ssh10:30:141
6778992811,6cyclictest21-21ksoftirqd/110:00:111
676699285,16cyclictest12-21ksoftirqd/009:45:110
676699282,21cyclictest12207-21ssh10:15:120
676699282,18cyclictest3151-21ssh11:40:120
676699282,17cyclictest8510-21ssh11:25:120
676699281,21cyclictest24755-21sh10:40:120
680199279,6cyclictest0-21swapper/311:35:043
680199272,6cyclictest0-21swapper/311:08:403
680199272,21cyclictest35966irq/58-eth010:10:133
680199272,21cyclictest35966irq/58-eth010:10:123
6801992712,10cyclictest0-21swapper/310:25:233
680199271,11cyclictest0-21swapper/311:55:203
680199271,10cyclictest0-21swapper/309:20:023
679199279,6cyclictest27-21ksoftirqd/210:32:012
679199272,11cyclictest10181-21ssh12:20:132
679199272,10cyclictest22767-21ssh11:30:582
679199271,8cyclictest25203-21ssh09:10:132
679199271,20cyclictest0-21swapper/208:45:142
679199271,11cyclictest7063-21ssh12:16:412
677899272,19cyclictest7024-21sh11:23:411
677899272,19cyclictest2462-21ssh11:39:411
677899272,19cyclictest17562-21ssh12:23:401
677899271,21cyclictest24800-21diskmemload12:35:111
676699272,19cyclictest13344-21ssh10:32:400
680199269,6cyclictest0-21swapper/311:17:513
680199269,6cyclictest0-21swapper/310:04:283
680199263,8cyclictest0-21swapper/312:10:153
680199261,9cyclictest0-21swapper/310:20:133
680199261,15cyclictest35966irq/58-eth009:20:123
679199269,4cyclictest27-21ksoftirqd/210:47:502
679199262,19cyclictest0-21swapper/211:35:142
6791992613,8cyclictest27-21ksoftirqd/210:36:402
679199261,14cyclictest30102-21ssh10:25:142
6791992610,10cyclictest131rcu_preempt09:52:172
677899265,13cyclictest0-21swapper/111:50:121
677899264,12cyclictest24800-21diskmemload09:25:121
677899262,9cyclictest0-21swapper/108:20:051
677899262,4cyclictest131rcu_preempt08:45:131
677899262,18cyclictest19183-21ssh11:10:531
676699262,18cyclictest28147-21sh11:15:540
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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