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2026-08-21 - 06:45

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot4s.osadl.org (updated Fri Aug 21, 2026 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
26668997117,6cyclictest131rcu_preempt20:35:122
2666899639,14cyclictest131rcu_preempt20:25:112
26680995928,23cyclictest35966irq/58-eth023:45:153
2664899554,18cyclictest12-21ksoftirqd/023:55:130
2664899554,18cyclictest12-21ksoftirqd/023:55:130
2666099523,40cyclictest15352-21ssh23:35:151
26648995119,9cyclictest131rcu_preempt21:50:140
2666099492,5cyclictest131rcu_preempt00:20:131
26668994615,12cyclictest0-21swapper/223:45:142
2664899463,36cyclictest12850-21ssh21:10:130
2664899454,36cyclictest29321-21ssh21:55:120
2664899446,35cyclictest25612-21ssh21:35:140
2668099424,23cyclictest35966irq/58-eth021:25:153
2668099422,27cyclictest35966irq/58-eth022:50:123
2664899425,27cyclictest14991-21ssh22:05:140
26680994020,13cyclictest35966irq/58-eth023:00:133
2666099405,7cyclictest21-21ksoftirqd/121:10:111
26660994025,7cyclictest0-21swapper/123:50:141
2668099393,25cyclictest35966irq/58-eth020:20:133
26668993820,12cyclictest27-21ksoftirqd/221:10:132
2666099381,4cyclictest131rcu_preempt19:55:141
26648993822,12cyclictest12-21ksoftirqd/022:55:130
2666899372,19cyclictest10747-21ssh21:44:562
26660993727,6cyclictest8548-21kworker/1:219:25:141
2668099363,22cyclictest35966irq/58-eth020:30:133
2668099362,17cyclictest35966irq/58-eth000:25:133
2666899362,28cyclictest2600-21sh00:39:562
2664899368,21cyclictest12-21ksoftirqd/022:35:120
2668099353,20cyclictest35966irq/58-eth021:30:143
26680993510,18cyclictest35966irq/58-eth023:05:143
2666899358,22cyclictest31445-21ssh22:50:142
2664899351,29cyclictest24338-21ssh23:40:120
26648993510,20cyclictest12-21ksoftirqd/019:10:120
2668099345,20cyclictest35966irq/58-eth023:25:123
2668099342,19cyclictest35966irq/58-eth000:20:133
26668993411,15cyclictest0-21swapper/219:55:122
2666099340,25cyclictest17453-21ssh00:30:151
2664899348,18cyclictest12-21ksoftirqd/000:05:160
2664899344,19cyclictest27982-21ssh00:00:130
2664899344,19cyclictest27982-21ssh00:00:120
2664899343,18cyclictest12-21ksoftirqd/020:35:130
2668099332,18cyclictest35966irq/58-eth020:40:123
26680993316,11cyclictest0-21swapper/321:36:563
26668993322,7cyclictest30951-21ssh21:20:132
2666099338,17cyclictest21-21ksoftirqd/100:05:151
26660993315,11cyclictest21-21ksoftirqd/120:10:121
2666099331,27cyclictest0-21swapper/119:20:101
2668099324,18cyclictest35966irq/58-eth023:20:123
2668099321,16cyclictest35966irq/58-eth020:00:133
2666899324,8cyclictest0-21swapper/220:10:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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