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2025-09-14 - 10:07

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot4s.osadl.org (updated Sun Sep 14, 2025 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1414699666,49cyclictest27775-21ssh00:35:161
1414699623,42cyclictest13152-21ssh00:25:151
14169994626,11cyclictest25366irq/58-eth021:40:143
1414699463,10cyclictest21-21ksoftirqd/122:00:141
1414699455,8cyclictest131rcu_preempt20:35:141
1414699455,8cyclictest131rcu_preempt20:35:141
1414699441,12cyclictest21-21ksoftirqd/121:50:151
1416999426,21cyclictest25366irq/58-eth021:45:183
1416999404,20cyclictest25366irq/58-eth000:25:153
1414699394,8cyclictest21-21ksoftirqd/121:25:151
1415999372,11cyclictest27-21ksoftirqd/221:30:162
1414699376,6cyclictest131rcu_preempt23:20:171
14146993721,9cyclictest21-21ksoftirqd/122:28:341
1416999363,22cyclictest25366irq/58-eth023:10:143
1414699363,6cyclictest131rcu_preempt20:30:121
14146993622,8cyclictest21-21ksoftirqd/122:45:051
1414699360,3cyclictest131rcu_preempt22:10:131
1416999356,19cyclictest25366irq/58-eth000:10:163
1414699351,4cyclictest131rcu_preempt23:50:161
1416999345,16cyclictest25366irq/58-eth000:05:173
1416999344,17cyclictest25366irq/58-eth020:10:103
1416999343,18cyclictest25366irq/58-eth020:25:143
1415999345,17cyclictest131rcu_preempt22:05:252
1413899343,28cyclictest13974-21ssh22:00:150
14169993313,14cyclictest25366irq/58-eth019:50:133
14169993212,16cyclictest25366irq/58-eth021:50:143
1414699322,9cyclictest21-21ksoftirqd/120:55:171
14138993214,13cyclictest6190-21ssh21:55:150
1413899321,27cyclictest17288-21sh23:25:150
1413899321,27cyclictest17288-21sh23:25:150
1416999317,11cyclictest0-21swapper/321:15:153
1415999319,15cyclictest27-21ksoftirqd/200:07:422
1415999315,11cyclictest27-21ksoftirqd/222:40:342
14159993024,3cyclictest21846irq/40-dwc2_hso19:30:162
14159993016,3cyclictest30628-21ssh00:15:052
14159993015,9cyclictest21219-21ssh21:42:212
1415999299,8cyclictest27-21ksoftirqd/222:26:302
14159992924,3cyclictest27-21ksoftirqd/221:55:152
1415999292,19cyclictest27255-21ssh22:50:162
1415999292,19cyclictest27255-21ssh22:50:152
14159992915,8cyclictest0-21swapper/219:45:122
1415999291,21cyclictest3148-21ssh22:12:352
1415999291,21cyclictest28456-21ssh22:30:172
14159992912,11cyclictest0-21swapper/222:18:412
1415999291,11cyclictest24149-21/usr/sbin/munin21:25:342
1413899292,21cyclictest31967-21rm23:55:140
1413899292,21cyclictest31967-21rm23:55:140
1413899290,7cyclictest12-21ksoftirqd/022:35:160
1416999283,16cyclictest0-21swapper/323:23:153
1415999286,8cyclictest27-21ksoftirqd/219:40:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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