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2026-05-13 - 02:21

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot4s.osadl.org (updated Tue May 12, 2026 12:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2539996736,17cyclictest35966irq/58-eth011:55:153
250699501,37cyclictest1724-21ssh11:40:140
253999444,26cyclictest35966irq/58-eth009:50:123
253999442,25cyclictest35966irq/58-eth009:55:133
253999435,23cyclictest35966irq/58-eth012:15:133
253999435,23cyclictest35966irq/58-eth012:15:123
251599431,29cyclictest28916-21ssh11:55:161
251599431,12cyclictest9909-21ssh10:15:131
250699400,35cyclictest16227-21ssh09:25:130
2539993915,17cyclictest0-21swapper/311:30:143
2506993917,3cyclictest12-21ksoftirqd/010:55:140
251599371,28cyclictest14591-21sh12:05:151
253999362,20cyclictest35966irq/58-eth012:25:133
2530993527,5cyclictest6042-21ssh09:55:132
253999344,14cyclictest35966irq/58-eth010:20:113
251599345,7cyclictest0-21swapper/108:45:141
253999334,24cyclictest35966irq/58-eth011:05:123
253999332,19cyclictest35966irq/58-eth010:05:143
253999324,19cyclictest35966irq/58-eth010:40:153
253999321,19cyclictest35966irq/58-eth011:35:133
253099321,16cyclictest29363-21ssh09:50:122
251599325,19cyclictest21-21ksoftirqd/110:45:111
253999313,19cyclictest35966irq/58-eth010:00:133
2539993112,11cyclictest35966irq/58-eth009:30:133
253999311,19cyclictest35966irq/58-eth009:25:133
253099314,18cyclictest27346irq/40-dwc2_hso08:10:132
253099312,20cyclictest27346irq/40-dwc2_hso11:35:142
253099311,20cyclictest18976-21ssh10:20:132
253999291,16cyclictest0-21swapper/311:15:123
253099295,17cyclictest261rcuc/210:55:132
253099294,16cyclictest27346irq/40-dwc2_hso07:10:142
2530992911,12cyclictest10776-21ssh11:45:142
251599291,23cyclictest11278-21ssh09:40:131
2506992916,8cyclictest12-21ksoftirqd/012:20:130
253999287,15cyclictest321rcuc/308:00:143
253999282,16cyclictest35966irq/58-eth012:35:143
253099282,21cyclictest0-21swapper/207:45:162
253099282,20cyclictest0-21swapper/208:50:142
253099282,15cyclictest16048-21sh11:30:142
2515992820,5cyclictest20949-21diskmemload09:10:151
251599280,20cyclictest21383-21ssh11:15:131
253999273,11cyclictest35966irq/58-eth009:45:133
253999273,10cyclictest0-21swapper/311:20:143
253999272,13cyclictest35966irq/58-eth010:45:123
253999272,11cyclictest35966irq/58-eth012:30:123
253099273,16cyclictest27346irq/40-dwc2_hso08:05:132
253099273,16cyclictest27346irq/40-dwc2_hso08:05:122
253099272,19cyclictest27346irq/40-dwc2_hso07:15:132
253099271,15cyclictest20285-21ssh09:45:132
250699271,13cyclictest27659-21idleruntime-cro10:25:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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