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2026-07-10 - 06:01

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot4s.osadl.org (updated Fri Jul 10, 2026 00:45:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2892999706,6cyclictest131rcu_preempt21:25:141
2891899564,6cyclictest131rcu_preempt00:25:160
2891899487,28cyclictest28852-21ssh00:00:140
2892999473,35cyclictest16445-21ssh22:05:121
2891899472,40cyclictest5453-21ssh00:05:140
2894599451,34cyclictest0-21swapper/321:40:153
28937994411,14cyclictest11894-21cat22:00:322
2892999444,36cyclictest27212-21rm00:35:131
2891899443,10cyclictest131rcu_preempt23:55:150
2891899421,15cyclictest131rcu_preempt22:05:140
2893799412,27cyclictest27-21ksoftirqd/223:30:122
2891899411,27cyclictest30646-21ssh23:25:150
2894599404,20cyclictest35966irq/58-eth023:45:143
2894599393,26cyclictest35966irq/58-eth020:50:123
2894599393,25cyclictest35966irq/58-eth000:00:133
2893799392,19cyclictest13881-21sh22:39:562
2893799382,28cyclictest15207-21ssh21:26:322
2892999382,33cyclictest12715-21ssh23:15:161
2894599376,25cyclictest35966irq/58-eth000:30:143
28945993717,13cyclictest35966irq/58-eth023:15:153
2893799372,23cyclictest18459-21ssh21:30:112
2894599363,26cyclictest35966irq/58-eth000:15:143
2894599362,27cyclictest35966irq/58-eth021:35:143
2893799363,25cyclictest18089-21ssh23:00:132
2892999362,26cyclictest5309-21ssh22:35:131
2894599355,25cyclictest35966irq/58-eth021:15:173
2894599353,18cyclictest35966irq/58-eth022:20:143
28945993421,7cyclictest35966irq/58-eth023:10:123
2893799333,20cyclictest25169-21ssh23:40:142
28937993313,12cyclictest0-21swapper/200:00:142
2891899332,22cyclictest21671-21ssh23:20:120
2893799323,22cyclictest0-21swapper/200:22:382
2894599314,18cyclictest35966irq/58-eth021:05:133
2893799313,21cyclictest0-21swapper/221:51:322
2891899312,3cyclictest131rcu_preempt23:00:120
2894599301,17cyclictest35966irq/58-eth023:05:143
28945993011,15cyclictest0-21swapper/322:30:143
2893799302,21cyclictest0-21swapper/222:25:162
2893799302,16cyclictest27346irq/40-dwc2_hso19:40:132
2892999303,5cyclictest131rcu_preempt21:40:131
2894599291,17cyclictest35966irq/58-eth019:40:123
2893799293,17cyclictest27346irq/40-dwc2_hso00:10:152
2893799292,20cyclictest0-21swapper/219:30:132
2893799292,19cyclictest27346irq/40-dwc2_hso22:20:142
28937992912,11cyclictest261rcuc/219:20:122
2893799291,13cyclictest3638-21rm23:10:122
28929992922,4cyclictest21974-21ssh21:50:121
2891899291,25cyclictest9527-21ssh21:25:150
2893799286,7cyclictest27-21ksoftirqd/222:41:332
2893799284,18cyclictest27346irq/40-dwc2_hso20:45:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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