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2026-03-14 - 01:32

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot4s.osadl.org (updated Fri Mar 13, 2026 12:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1507199674,45cyclictest21536-21ssh10:15:120
1508499585,38cyclictest3434-21ssh10:05:121
1507199584,45cyclictest14831-21ssh12:35:130
15098995718,24cyclictest0-21swapper/211:55:122
1507199564,7cyclictest131rcu_preempt08:25:130
1507199564,7cyclictest131rcu_preempt08:25:130
1507199553,45cyclictest5496-21ssh11:00:120
1507199545,7cyclictest131rcu_preempt08:55:120
1507199532,4cyclictest131rcu_preempt12:00:110
15071995232,17cyclictest12-21ksoftirqd/009:50:110
1508499513,37cyclictest31018-21ssh11:50:121
1509899495,33cyclictest12492-21ssh10:10:112
1509899461,31cyclictest14519-21ssh11:05:112
1509899461,31cyclictest14519-21ssh11:05:112
15071994624,10cyclictest12-21ksoftirqd/009:40:120
1511199453,27cyclictest28366irq/58-eth011:55:133
15111994527,11cyclictest28366irq/58-eth012:35:123
1509899451,25cyclictest2264-21ssh12:10:112
1509899451,25cyclictest2264-21ssh12:10:112
1511199444,25cyclictest28366irq/58-eth011:20:123
1511199442,26cyclictest28366irq/58-eth010:40:113
1509899433,17cyclictest10860-21ssh10:45:122
1507199431,4cyclictest131rcu_preempt07:40:120
1511199429,20cyclictest28366irq/58-eth007:40:133
1507199403,3cyclictest131rcu_preempt11:15:120
1508499398,19cyclictest17199-21kworker/u8:109:55:131
15071993925,3cyclictest12-21ksoftirqd/011:20:120
15098993829,5cyclictest0-21swapper/207:10:132
1508499372,25cyclictest32207-21ssh09:45:141
1507199361,23cyclictest20290-21ssh12:20:120
1511199356,23cyclictest28366irq/58-eth011:15:133
1511199354,19cyclictest28366irq/58-eth010:20:113
1509899351,28cyclictest9218-21cut12:30:222
1507199352,24cyclictest13254-21kthreadcore12:15:210
1507199351,27cyclictest25623-21sh12:05:120
15111993417,13cyclictest0-21swapper/310:50:113
15098993415,14cyclictest27-21ksoftirqd/208:45:122
15098993310,16cyclictest0-21swapper/211:48:132
1508499334,20cyclictest21977-21ssh11:45:151
1507199332,22cyclictest14538-21ssh11:05:130
1507199332,22cyclictest14538-21ssh11:05:130
1511199322,18cyclictest28366irq/58-eth009:10:113
1509899321,26cyclictest14262-21kthreadcore12:15:212
1508499321,22cyclictest7641-21ssh11:55:131
1507199322,22cyclictest4074-21ssh12:28:200
1511199315,18cyclictest28366irq/58-eth011:40:123
1509899311,15cyclictest3307-21sh11:34:482
15098993111,3cyclictest0-21swapper/209:30:132
1508499312,23cyclictest9449-21ssh11:36:221
1511199305,13cyclictest28366irq/58-eth009:25:123
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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