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2026-04-28 - 15:56

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot4s.osadl.org (updated Tue Apr 28, 2026 00:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2504399643,44cyclictest26810-21ssh22:30:140
25051995950,3cyclictest13791-21sh22:05:121
25071995536,12cyclictest35966irq/58-eth023:10:133
2504399553,43cyclictest27865-21ssh00:00:140
2505999522,40cyclictest0-21swapper/220:00:132
25043995231,6cyclictest12-21ksoftirqd/023:55:110
2504399494,33cyclictest31817-21ssh00:20:140
2507199482,27cyclictest35966irq/58-eth022:00:133
2505999483,4cyclictest27346irq/40-dwc2_hso21:40:132
2505999474,34cyclictest27880-21ssh00:00:152
2505199412,32cyclictest30572-21ssh22:50:141
2507199401,35cyclictest0-21swapper/321:15:143
2504399392,5cyclictest131rcu_preempt21:20:130
2504399381,27cyclictest22843-21ssh22:10:110
2507199373,26cyclictest35966irq/58-eth000:05:143
2507199371,32cyclictest0-21swapper/300:30:133
2505999372,19cyclictest17870-21ssh23:17:502
2505999372,18cyclictest14106-21sh22:57:522
2505999371,29cyclictest0-21swapper/222:30:132
25071993623,8cyclictest35966irq/58-eth021:20:123
2507199362,20cyclictest35966irq/58-eth000:10:133
25059993521,8cyclictest261rcuc/222:25:112
2504399352,28cyclictest12489-21ssh22:40:130
2504399351,29cyclictest6004-21ssh21:25:130
2505199341,23cyclictest28114-21rm21:55:131
2505999332,15cyclictest0-21swapper/200:25:452
2505199331,25cyclictest16304-21ssh23:00:121
2507199321,28cyclictest35966irq/58-eth000:15:143
2507199321,27cyclictest0-21swapper/321:30:133
2505999321,15cyclictest841-21ssh00:37:442
2507199316,21cyclictest0-21swapper/321:10:143
2507199316,21cyclictest0-21swapper/321:10:133
2507199313,23cyclictest0-21swapper/321:55:133
25071993124,4cyclictest35966irq/58-eth021:25:123
2507199310,28cyclictest0-21swapper/322:10:113
2505199311,8cyclictest22361-21latency_hist00:15:011
2507199302,22cyclictest35966irq/58-eth022:40:133
2507199302,20cyclictest35966irq/58-eth023:15:133
25071993018,8cyclictest35966irq/58-eth023:45:153
25071993018,8cyclictest35966irq/58-eth023:45:143
2507199301,20cyclictest0-21swapper/322:35:103
2507199300,28cyclictest0-21swapper/323:35:143
2507199300,23cyclictest0-21swapper/323:25:133
2507199300,23cyclictest0-21swapper/323:25:123
2505999304,11cyclictest0-21swapper/219:10:142
25043993021,4cyclictest12-21ksoftirqd/021:15:150
2507199292,24cyclictest35966irq/58-eth000:20:133
2507199291,25cyclictest0-21swapper/319:45:133
2505999293,10cyclictest0-21swapper/200:33:042
2505999292,11cyclictest29010-21ssh23:40:442
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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