You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-01-21 - 23:26
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot7s.osadl.org (updated Wed Jan 21, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1505229988,6sleep20-21swapper/207:05:262
1549229074,11sleep30-21swapper/307:06:373
1542228774,9sleep00-21swapper/007:05:400
1568628464,16sleep10-21swapper/107:09:071
128582550,0sleep30-21swapper/311:27:183
1584099300,30cyclictest0-21swapper/210:05:132
1584099260,25cyclictest0-21swapper/211:50:562
1583499260,1cyclictest0-21swapper/010:18:590
15838992524,1cyclictest0-21swapper/110:41:311
15838992424,0cyclictest0-21swapper/111:45:081
15838992415,4cyclictest8122-21df11:05:151
1583899240,2cyclictest0-21swapper/112:37:051
1583899240,2cyclictest0-21swapper/112:37:041
1583899230,5cyclictest0-21swapper/110:20:121
15834992220,1cyclictest8448-21diskmemload10:11:140
1583499220,2cyclictest0-21swapper/011:12:100
15844992121,0cyclictest0-21swapper/310:41:353
15840992120,1cyclictest0-21swapper/210:49:032
171012200,0sleep30-21swapper/309:34:223
1584499201,4cyclictest141rcu_preempt09:45:253
1584499200,1cyclictest0-21swapper/309:27:093
1584099200,19cyclictest0-21swapper/211:40:152
15834992020,0cyclictest0-21swapper/011:55:430
1583499200,2cyclictest0-21swapper/010:35:290
1583499200,1cyclictest0-21swapper/011:44:120
1583499200,19cyclictest0-21swapper/012:10:160
1583899193,2cyclictest141rcu_preempt10:34:551
1584499181,16cyclictest0-21swapper/312:02:533
1584499180,1cyclictest0-21swapper/312:37:183
1584499180,1cyclictest0-21swapper/312:37:183
1584499180,18cyclictest0-21swapper/310:25:163
1583499180,15cyclictest0-21swapper/009:28:420
1584499171,15cyclictest0-21swapper/311:20:083
1584499170,17cyclictest0-21swapper/309:19:523
1584499170,16cyclictest0-21swapper/311:49:113
1584099170,4cyclictest0-21swapper/210:35:132
1583899170,3cyclictest0-21swapper/109:50:341
1583899170,2cyclictest0-21swapper/110:28:341
1583499170,16cyclictest28825-21apache_volume12:35:140
1583499170,16cyclictest28825-21apache_volume12:35:130
85452160,0sleep00-21swapper/011:05:180
1584499163,3cyclictest141rcu_preempt10:54:033
1584499162,10cyclictest7535-21apache_volume11:05:133
1584099161,2cyclictest141rcu_preempt09:45:512
1584099160,1cyclictest0-21swapper/211:57:242
1584099160,1cyclictest0-21swapper/209:30:202
1583899160,1cyclictest0-21swapper/112:31:061
1583899160,1cyclictest0-21swapper/112:31:051
1583899160,1cyclictest0-21swapper/109:12:501
1583899160,16cyclictest0-21swapper/111:29:151
1583899160,16cyclictest0-21swapper/110:48:131
1583899160,0cyclictest0-21swapper/110:35:181
1583499160,1cyclictest0-21swapper/011:47:270
1583499160,1cyclictest0-21swapper/009:45:390
1583499160,13cyclictest0-21swapper/009:50:510
1584499156,7cyclictest24270-21wget11:15:123
15844991514,1cyclictest0-21swapper/312:21:313
1584499150,2cyclictest0-21swapper/312:17:573
1584499150,1cyclictest0-21swapper/312:25:033
1584099150,15cyclictest0-21swapper/211:45:442
1583499152,7cyclictest17937-21perf09:34:590
1583499151,3cyclictest3268-21sh12:00:160
1584499142,0cyclictest141rcu_preempt12:08:203
1584499141,1cyclictest141rcu_preempt10:00:183
15844991410,3cyclictest26318-21awk09:39:593
15844991410,3cyclictest22489-21wc10:15:223
15840991413,1cyclictest0-21swapper/212:13:222
15840991413,1cyclictest0-21swapper/208:30:132
15840991411,2cyclictest25001-21cut08:35:162
15840991411,2cyclictest10396-21grep08:05:132
1584099141,11cyclictest8939-21ssh09:10:112
15840991410,3cyclictest29237-21wc07:35:222
15840991410,3cyclictest18707-21ls12:10:002
15840991410,3cyclictest15645-21grep08:15:172
1584099140,12cyclictest0-21swapper/211:13:562
15838991413,1cyclictest38150irq/131-snd_hda09:46:171
15838991411,2cyclictest10859-21head08:05:151
15838991410,3cyclictest2082-21sh11:01:091
1583499148,2cyclictest225-21systemd-journal08:45:010
1583499146,7cyclictest25359-21perf07:30:000
1583499143,5cyclictest0-21swapper/008:20:010
15834991410,2cyclictest12416-21cat08:10:010
15834991410,1cyclictest0-21swapper/011:03:290
1583499140,13cyclictest31068-21dump-pmu-power10:59:590
1584499139,3cyclictest32717-21wc11:00:203
1584499139,3cyclictest21137-21wc08:25:263
1584499139,2cyclictest28471-21grep08:40:263
1584499137,4cyclictest26279-21cut07:30:173
15844991310,2cyclictest28602-21cut07:35:173
15844991310,2cyclictest2030-21grep07:45:273
15844991310,2cyclictest13073-21rm09:50:253
1584099139,3cyclictest6324-21head10:25:172
1584099139,3cyclictest21490-21wc09:55:272
1584099139,3cyclictest21490-21wc09:55:272
1584099139,2cyclictest20298-21cut08:25:182
1584099138,3cyclictest21118-21tr07:20:142
1584099138,2cyclictest0-21swapper/210:15:002
1584099132,9cyclictest807-21swap11:00:262
1584099132,10cyclictest1750-21runrttasks10:41:442
15840991312,1cyclictest0-21swapper/210:01:422
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional