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2026-04-02 - 16:58

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack7slot7s.osadl.org (updated Thu Apr 02, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
158929866,8sleep20-21swapper/207:07:482
142629077,9sleep00-21swapper/007:05:400
159728157,6sleep30-21swapper/307:07:533
145627958,6sleep10-21swapper/107:06:031
43322640,0sleep30-21swapper/310:58:003
41942460,0sleep30-21swapper/309:40:183
1858993029,1cyclictest0-21swapper/209:53:352
1861992810,7cyclictest141rcu_preempt11:36:313
185899270,27cyclictest0-21swapper/212:07:352
185899260,26cyclictest0-21swapper/209:31:502
185699260,21cyclictest141rcu_preempt11:46:181
185699256,8cyclictest25-21ksoftirqd/112:20:171
1856992521,4cyclictest25-21ksoftirqd/109:10:001
1858992421,2cyclictest32-21ksoftirqd/211:40:002
185899240,23cyclictest0-21swapper/209:44:212
185899240,1cyclictest0-21swapper/209:59:012
1856992422,2cyclictest25-21ksoftirqd/111:25:441
185199240,1cyclictest0-21swapper/010:10:140
1858992323,0cyclictest0-21swapper/210:45:362
185899230,23cyclictest0-21swapper/209:27:192
185699230,1cyclictest0-21swapper/111:08:261
186199227,14cyclictest39-21ksoftirqd/311:01:203
185899226,15cyclictest0-21swapper/211:05:382
1858992221,1cyclictest0-21swapper/209:12:492
185899220,22cyclictest0-21swapper/212:21:422
185899220,22cyclictest0-21swapper/211:33:512
185899220,22cyclictest0-21swapper/210:19:592
185899220,22cyclictest0-21swapper/209:47:022
185699221,21cyclictest25-21ksoftirqd/110:05:401
1851992221,1cyclictest0-21swapper/011:45:390
1861992119,1cyclictest17045-21diskmemload12:03:233
1861992117,3cyclictest0-21swapper/312:30:023
1861992110,1cyclictest141rcu_preempt07:25:133
185899210,21cyclictest0-21swapper/210:39:252
185699213,2cyclictest0-21swapper/110:32:411
1856992120,1cyclictest0-21swapper/111:16:551
1856992119,1cyclictest0-21swapper/110:26:011
1856992117,4cyclictest38150irq/131-snd_hda11:42:151
185699210,20cyclictest0-21swapper/109:00:191
185199210,20cyclictest0-21swapper/011:58:300
1861992019,1cyclictest39-21ksoftirqd/310:46:373
1861992019,1cyclictest17045-21diskmemload11:22:593
1861992016,4cyclictest0-21swapper/309:15:003
1861992015,4cyclictest29522-21grep09:55:183
186199200,1cyclictest0-21swapper/311:52:133
185899200,20cyclictest0-21swapper/212:19:182
185899200,19cyclictest0-21swapper/210:50:572
185899200,19cyclictest0-21swapper/210:50:562
185199200,19cyclictest0-21swapper/010:56:100
186199197,2cyclictest26835-21sh12:29:203
186199195,12cyclictest0-21swapper/311:10:163
1861991912,7cyclictest0-21swapper/310:40:123
1861991910,8cyclictest17045-21diskmemload11:41:063
186199190,4cyclictest0-21swapper/312:38:143
186199190,4cyclictest0-21swapper/312:38:143
185899192,1cyclictest141rcu_preempt10:44:442
1856991915,1cyclictest25-21ksoftirqd/111:12:291
185699190,4cyclictest141rcu_preempt11:54:001
185699190,1cyclictest0-21swapper/110:45:281
1851991919,0cyclictest0-21swapper/010:29:170
185199190,18cyclictest0-21swapper/012:25:060
186199187,6cyclictest381rcuc/312:15:153
1861991817,1cyclictest0-21swapper/312:20:213
1861991816,1cyclictest17045-21diskmemload09:17:373
186199181,4cyclictest0-21swapper/310:24:243
186199180,1cyclictest0-21swapper/311:57:123
185899180,18cyclictest0-21swapper/211:22:172
185899180,18cyclictest0-21swapper/210:09:432
185699185,13cyclictest25-21ksoftirqd/110:51:081
185699185,13cyclictest25-21ksoftirqd/110:51:071
1856991816,2cyclictest25-21ksoftirqd/110:03:161
1856991812,6cyclictest25-21ksoftirqd/112:10:121
185699180,1cyclictest141rcu_preempt10:43:031
186199174,12cyclictest0-21swapper/310:15:143
186199173,10cyclictest0-21swapper/310:35:123
1861991713,4cyclictest39-21ksoftirqd/311:17:353
1861991710,6cyclictest0-21swapper/309:24:203
1858991712,3cyclictest32-21ksoftirqd/209:15:012
185899170,17cyclictest0-21swapper/212:04:432
1856991715,1cyclictest241rcuc/112:30:251
185699171,1cyclictest141rcu_preempt09:47:001
185199174,0cyclictest141rcu_preempt10:00:320
1851991717,0cyclictest0-21swapper/009:45:100
1851991716,1cyclictest0-21swapper/010:09:260
185199170,2cyclictest0-21swapper/011:41:530
185199170,17cyclictest0-21swapper/012:21:000
186199167,7cyclictest39-21ksoftirqd/310:29:183
186199167,7cyclictest17045-21diskmemload11:08:083
186199164,11cyclictest23698-21sensors10:30:213
1861991614,2cyclictest39-21ksoftirqd/310:07:393
1861991614,1cyclictest0-21swapper/311:25:143
185899160,15cyclictest0-21swapper/211:15:182
185699168,4cyclictest17045-21diskmemload12:39:171
185699168,4cyclictest17045-21diskmemload12:39:171
185699162,2cyclictest25-21ksoftirqd/110:12:071
1856991615,0cyclictest0-21swapper/108:40:191
1856991614,2cyclictest241rcuc/109:10:151
1856991613,3cyclictest25-21ksoftirqd/110:35:131
185699160,14cyclictest0-21swapper/110:16:141
185199161,3cyclictest0-21swapper/007:25:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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