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2026-03-03 - 13:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Tue Mar 03, 2026 00:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2580821500,1sleep00-21swapper/022:41:470
574729172,13sleep20-21swapper/219:05:152
570829075,10sleep00-21swapper/019:05:080
762028661,9sleep30-21swapper/319:07:133
776427857,6sleep10-21swapper/119:09:031
222522550,0sleep10-21swapper/122:59:381
793499280,0cyclictest0-21swapper/222:19:212
792899280,28cyclictest0-21swapper/022:03:500
793499260,26cyclictest0-21swapper/200:22:122
7930992624,1cyclictest27865-21ps00:00:211
7928992625,1cyclictest0-21swapper/023:26:290
793099252,22cyclictest0-21swapper/100:05:131
792899253,19cyclictest141rcu_preempt21:19:550
792899251,3cyclictest141rcu_preempt22:18:270
792899250,1cyclictest0-21swapper/000:00:450
793499240,24cyclictest0-21swapper/221:54:102
793099240,19cyclictest0-21swapper/121:34:551
792899247,6cyclictest13-21ksoftirqd/000:15:520
793099230,1cyclictest0-21swapper/122:20:121
792899234,14cyclictest13-21ksoftirqd/022:45:190
793699227,2cyclictest21461-21ssh22:39:553
793499220,22cyclictest0-21swapper/222:04:502
7928992221,1cyclictest13-21ksoftirqd/023:20:220
7928992220,1cyclictest737-21diskmemload22:13:130
793699215,2cyclictest0-21swapper/322:12:063
793699212,1cyclictest0-21swapper/323:59:563
793699210,1cyclictest141rcu_preempt23:30:373
7934992121,0cyclictest0-21swapper/200:11:342
7934992117,1cyclictest32-21ksoftirqd/220:25:002
793499211,14cyclictest0-21swapper/221:40:122
7934992110,1cyclictest141rcu_preempt23:48:352
793499210,21cyclictest0-21swapper/221:24:022
793099210,1cyclictest0-21swapper/100:34:441
7928992120,1cyclictest13-21ksoftirqd/021:30:330
7928992114,7cyclictest13-21ksoftirqd/022:53:310
7928992114,2cyclictest13-21ksoftirqd/022:32:480
7928992110,6cyclictest13-21ksoftirqd/022:25:430
793499208,11cyclictest25853-21cron00:00:002
793099200,1cyclictest737-21diskmemload22:42:581
793099200,14cyclictest0-21swapper/121:14:501
792899202,8cyclictest13-21ksoftirqd/000:12:150
792899201,3cyclictest2017-21ssh21:49:100
793699190,1cyclictest0-21swapper/323:54:193
793499196,13cyclictest291irq_work/200:27:192
7934991917,2cyclictest32-21ksoftirqd/223:17:292
7934991917,1cyclictest32-21ksoftirqd/222:12:002
793499190,17cyclictest0-21swapper/223:51:042
793499190,17cyclictest0-21swapper/200:16:132
793499190,0cyclictest0-21swapper/223:32:292
7930991918,1cyclictest0-21swapper/122:46:121
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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