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2026-04-22 - 04:22

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Wed Apr 22, 2026 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
134029171,16sleep30-21swapper/319:07:563
117728874,9sleep00-21swapper/019:05:530
139828744,39sleep20-21swapper/219:08:392
141727857,6sleep10-21swapper/119:08:551
59732550,0sleep00-21swapper/000:10:190
94522510,0sleep10-21swapper/100:31:401
258572480,0sleep00-21swapper/023:43:580
1582992521,3cyclictest23192-21grep21:00:171
158699240,23cyclictest0-21swapper/221:52:082
159199232,0cyclictest141rcu_preempt23:11:003
158699230,23cyclictest0-21swapper/219:48:062
158699230,23cyclictest0-21swapper/200:16:162
158699230,0cyclictest0-21swapper/223:32:012
159199220,1cyclictest0-21swapper/300:20:143
158699220,1cyclictest0-21swapper/200:24:402
158699220,0cyclictest0-21swapper/222:05:252
1582992221,1cyclictest0-21swapper/122:59:411
159199210,2cyclictest0-21swapper/321:35:153
158699210,21cyclictest0-21swapper/222:32:482
158699210,1cyclictest0-21swapper/223:35:392
158699210,1cyclictest0-21swapper/223:16:402
158699210,1cyclictest0-21swapper/221:35:042
159199203,0cyclictest141rcu_preempt23:02:023
159199202,0cyclictest141rcu_preempt21:40:243
1591992018,1cyclictest39-21ksoftirqd/321:15:543
158699200,1cyclictest0-21swapper/222:18:342
158699200,1cyclictest0-21swapper/221:20:412
1582992019,1cyclictest0-21swapper/100:15:211
1591991917,1cyclictest1142-21runrttasks22:25:103
1591991917,1cyclictest0-21swapper/323:30:453
158699190,1cyclictest0-21swapper/200:06:322
158699190,19cyclictest0-21swapper/221:31:112
158699190,0cyclictest0-21swapper/222:46:372
158299191,18cyclictest27015-21diskmemload21:34:201
159199182,0cyclictest141rcu_preempt23:21:563
1591991816,1cyclictest0-21swapper/323:35:143
1591991816,1cyclictest0-21swapper/322:08:473
1591991816,1cyclictest0-21swapper/321:29:573
158699180,1cyclictest0-21swapper/223:03:532
158699180,1cyclictest0-21swapper/200:02:462
158699180,0cyclictest0-21swapper/223:06:352
1582991817,1cyclictest0-21swapper/123:31:531
1582991817,1cyclictest0-21swapper/122:37:381
158299181,3cyclictest0-21swapper/123:50:121
158299180,7cyclictest27015-21diskmemload22:20:451
157799180,18cyclictest0-21swapper/021:50:490
159199171,5cyclictest0-21swapper/323:55:133
1591991713,1cyclictest39-21ksoftirqd/322:46:173
158699170,17cyclictest0-21swapper/223:42:182
158699170,0cyclictest0-21swapper/200:10:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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