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2026-08-03 - 17:47

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Mon Aug 03, 2026 12:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7536210693,8sleep00-21swapper/007:08:020
747628775,8sleep20-21swapper/207:07:162
243192860,1sleep1241rcuc/112:36:201
737928471,9sleep30-21swapper/307:06:003
737028365,14sleep10-21swapper/107:05:541
7782992825,3cyclictest0-21swapper/210:56:332
778299270,26cyclictest0-21swapper/209:39:262
7784992524,1cyclictest0-21swapper/310:32:053
778299250,24cyclictest0-21swapper/209:48:502
778299240,24cyclictest0-21swapper/211:49:352
778299240,23cyclictest0-21swapper/212:23:302
39652240,1sleep00-21swapper/008:10:000
7784992222,0cyclictest0-21swapper/309:16:313
778299220,21cyclictest0-21swapper/212:15:412
7777992218,4cyclictest13-21ksoftirqd/011:57:370
778499211,0cyclictest0-21swapper/310:36:543
778499210,1cyclictest0-21swapper/310:50:523
778299210,4cyclictest0-21swapper/211:22:092
264612210,0sleep339-21ksoftirqd/310:41:583
7784992020,0cyclictest0-21swapper/311:58:223
778499200,1cyclictest0-21swapper/309:49:563
778499200,0cyclictest0-21swapper/309:40:473
778299200,18cyclictest0-21swapper/211:25:372
7782991913,5cyclictest0-21swapper/211:55:302
778299190,1cyclictest0-21swapper/211:10:392
778299190,19cyclictest0-21swapper/212:34:212
778299190,0cyclictest0-21swapper/212:05:512
7777991913,2cyclictest13-21ksoftirqd/012:02:010
7784991816,1cyclictest0-21swapper/310:21:323
778299182,3cyclictest141rcu_preempt11:01:362
7782991816,2cyclictest0-21swapper/209:41:132
7782991814,3cyclictest0-21swapper/210:36:032
778299180,17cyclictest0-21swapper/210:47:042
778299180,17cyclictest0-21swapper/209:24:272
777999181,8cyclictest0-21swapper/109:30:541
777999180,18cyclictest0-21swapper/110:37:501
7777991816,1cyclictest0-21swapper/011:08:340
142032180,0sleep00-21swapper/010:35:180
7782991717,0cyclictest0-21swapper/211:18:252
7782991716,1cyclictest25690-21ssh10:03:032
7782991716,1cyclictest0-21swapper/211:39:432
7782991715,2cyclictest0-21swapper/209:53:422
778299170,17cyclictest0-21swapper/209:32:492
778299170,0cyclictest0-21swapper/211:52:432
778299170,0cyclictest0-21swapper/211:05:132
777999172,2cyclictest7892-21ssh12:26:411
777999170,15cyclictest0-21swapper/110:48:531
7784991615,1cyclictest0-21swapper/308:20:133
778499160,13cyclictest0-21swapper/311:31:523
7782991615,1cyclictest0-21swapper/210:05:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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