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2026-07-06 - 14:04

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Mon Jul 06, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
389210264,34sleep00-21swapper/019:05:580
66128472,8sleep20-21swapper/219:09:042
35228370,8sleep30-21swapper/319:05:323
45428164,13sleep10-21swapper/119:06:431
82199280,0cyclictest0-21swapper/022:29:180
82199260,26cyclictest0-21swapper/021:37:030
821992523,1cyclictest0-21swapper/019:25:120
83199241,20cyclictest0-21swapper/323:11:083
82799240,21cyclictest0-21swapper/221:58:552
825992422,1cyclictest25-21ksoftirqd/123:04:351
82599240,1cyclictest0-21swapper/123:47:281
82199240,23cyclictest0-21swapper/023:05:530
82599230,1cyclictest0-21swapper/121:44:371
83199220,0cyclictest0-21swapper/321:38:283
82599220,0cyclictest0-21swapper/123:56:551
821992222,0cyclictest0-21swapper/023:12:580
827992120,1cyclictest0-21swapper/200:22:342
82199210,2cyclictest0-21swapper/000:35:310
82199210,20cyclictest0-21swapper/021:30:130
825992018,1cyclictest25-21ksoftirqd/122:22:391
82599200,19cyclictest25832-21diskmemload21:14:041
82199200,16cyclictest0-21swapper/022:55:560
82799195,3cyclictest0-21swapper/223:36:242
82599192,3cyclictest25832-21diskmemload00:11:381
82599192,1cyclictest25832-21diskmemload23:38:041
82599190,2cyclictest0-21swapper/120:50:141
82599190,1cyclictest0-21swapper/123:21:521
831991815,2cyclictest39-21ksoftirqd/322:36:113
82799181,1cyclictest7415-21ssh22:54:272
82799180,18cyclictest0-21swapper/223:15:032
82599185,12cyclictest241rcuc/100:00:121
82599180,2cyclictest0-21swapper/122:29:491
82599180,2cyclictest0-21swapper/122:04:231
82199180,1cyclictest0-21swapper/021:43:200
82199180,1cyclictest0-21swapper/000:02:330
82199180,16cyclictest0-21swapper/021:23:350
83199174,12cyclictest0-21swapper/322:22:563
83199171,1cyclictest141rcu_preempt00:22:583
83199171,1cyclictest0-21swapper/323:59:093
827991716,1cyclictest0-21swapper/223:14:522
825991715,1cyclictest25-21ksoftirqd/123:41:281
831991615,1cyclictest0-21swapper/322:30:333
83199160,16cyclictest0-21swapper/321:33:193
82799160,1cyclictest0-21swapper/222:29:072
82599162,2cyclictest141rcu_preempt21:53:161
82199164,8cyclictest24526-21grep22:45:140
82199160,0cyclictest141rcu_preempt23:54:470
82199160,0cyclictest0-21swapper/000:29:370
83199153,2cyclictest141rcu_preempt21:18:293
83199150,14cyclictest0-21swapper/322:00:033
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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