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2026-09-24 - 20:08

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Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Thu Sep 24, 2026 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
677229567,9sleep00-21swapper/007:05:280
688529467,9sleep30-21swapper/307:06:493
499729077,9sleep20-21swapper/207:05:032
705328164,13sleep10-21swapper/107:09:001
171702550,0sleep00-21swapper/010:36:540
722299271,2cyclictest141rcu_preempt10:38:031
722799251,1cyclictest0-21swapper/310:37:213
7222992523,2cyclictest25-21ksoftirqd/111:23:411
722299250,1cyclictest0-21swapper/110:57:491
7224992423,1cyclictest0-21swapper/210:15:052
722299243,5cyclictest141rcu_preempt11:07:181
722299242,8cyclictest25-21ksoftirqd/112:13:381
7222992423,1cyclictest0-21swapper/110:11:391
7222992419,4cyclictest29739-21runrttasks11:43:061
7227992317,3cyclictest39-21ksoftirqd/311:26:083
7222992320,2cyclictest0-21swapper/111:50:421
722299231,1cyclictest241rcuc/107:30:191
722299230,3cyclictest0-21swapper/112:38:131
722299230,1cyclictest0-21swapper/112:08:551
722299230,19cyclictest0-21swapper/109:37:481
722299230,19cyclictest0-21swapper/109:37:481
722499220,0cyclictest0-21swapper/211:37:352
722299220,22cyclictest0-21swapper/110:29:311
722299220,21cyclictest0-21swapper/109:42:431
7227992116,3cyclictest39-21ksoftirqd/307:25:013
722799210,3cyclictest141rcu_preempt12:08:113
7222992120,1cyclictest25-21ksoftirqd/109:56:231
7222992120,1cyclictest0-21swapper/109:24:081
722299211,14cyclictest16011-21kworker/1:110:40:161
722799208,9cyclictest39-21ksoftirqd/311:08:483
7227992018,1cyclictest0-21swapper/307:15:133
7227992016,3cyclictest29367-21ssh10:44:583
7227992012,4cyclictest39-21ksoftirqd/312:35:093
722799201,1cyclictest141rcu_preempt10:30:193
722799201,19cyclictest381rcuc/312:32:303
7222992019,1cyclictest0-21swapper/111:46:201
722299201,18cyclictest2530-21aten2_r7power_v12:25:131
722299200,1cyclictest0-21swapper/112:32:301
722299200,17cyclictest0-21swapper/110:23:121
722799192,3cyclictest141rcu_preempt11:34:483
722799192,2cyclictest141rcu_preempt09:25:463
722499194,14cyclictest0-21swapper/210:27:512
722499191,3cyclictest0-21swapper/211:56:542
722499190,0cyclictest0-21swapper/209:45:092
7222991917,1cyclictest38150irq/131-snd_hda11:58:531
721799195,7cyclictest24790-21sendmail12:00:000
722799183,2cyclictest141rcu_preempt12:28:263
722799181,4cyclictest39-21ksoftirqd/309:33:103
7227991813,2cyclictest381rcuc/310:59:473
722799180,0cyclictest141rcu_preempt12:10:343
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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