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2026-09-02 - 23:14

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Wed Sep 02, 2026 12:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17634210274,9sleep00-21swapper/007:09:590
1729729178,9sleep20-21swapper/207:05:392
1743528566,15sleep10-21swapper/107:07:271
1747928269,9sleep30-21swapper/307:08:023
299952810,1sleep10-21swapper/112:34:291
1772399289,15cyclictest32-21ksoftirqd/208:50:212
17723992711,5cyclictest32-21ksoftirqd/212:12:032
17723992624,1cyclictest32-21ksoftirqd/211:54:212
17723992512,3cyclictest32-21ksoftirqd/211:26:532
1772399240,1cyclictest0-21swapper/209:48:422
17725992310,2cyclictest39-21ksoftirqd/309:23:003
1772599230,2cyclictest0-21swapper/309:05:223
17723992321,1cyclictest32-21ksoftirqd/210:31:442
1772599222,3cyclictest141rcu_preempt10:20:133
17725992220,1cyclictest39-21ksoftirqd/310:03:053
17725992216,4cyclictest39-21ksoftirqd/309:35:523
1772599220,2cyclictest0-21swapper/311:30:483
1772399220,1cyclictest0-21swapper/211:17:552
1771599220,2cyclictest0-21swapper/011:47:240
1771599220,1cyclictest0-21swapper/009:20:280
17725992118,2cyclictest39-21ksoftirqd/310:30:003
17725992112,1cyclictest39-21ksoftirqd/310:14:173
1772399214,2cyclictest141rcu_preempt10:55:272
17723992119,1cyclictest32-21ksoftirqd/210:29:012
17723992117,1cyclictest141rcu_preempt10:02:192
17723992113,2cyclictest32-21ksoftirqd/210:38:182
1772399211,2cyclictest141rcu_preempt10:53:072
17719992119,1cyclictest0-21swapper/109:25:201
1772399201,8cyclictest29278-21pmu-power09:20:222
1772399200,4cyclictest141rcu_preempt07:40:222
1772399200,1cyclictest141rcu_preempt08:35:022
1772399200,19cyclictest0-21swapper/212:25:132
17719992019,1cyclictest25-21ksoftirqd/111:19:301
17719992017,2cyclictest0-21swapper/110:50:141
1771999200,1cyclictest0-21swapper/112:28:081
1771999200,1cyclictest0-21swapper/112:20:131
1772599199,1cyclictest39-21ksoftirqd/311:42:073
1772399198,2cyclictest32-21ksoftirqd/209:10:042
1772399195,1cyclictest141rcu_preempt11:20:222
17723991916,1cyclictest32-21ksoftirqd/209:26:252
1772399190,1cyclictest0-21swapper/211:36:372
1771599192,16cyclictest0-21swapper/010:05:130
1772599187,1cyclictest141rcu_preempt11:55:213
1772599182,4cyclictest141rcu_preempt09:10:113
1772599180,3cyclictest141rcu_preempt10:31:443
1772399186,2cyclictest141rcu_preempt09:57:272
1772399182,2cyclictest141rcu_preempt12:06:292
17723991813,1cyclictest141rcu_preempt12:34:312
1771999182,2cyclictest141rcu_preempt11:56:531
1771999181,6cyclictest28290-21cpuspeed_turbos11:35:141
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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