You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-03 - 10:18

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Fri Jul 03, 2026 00:43:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28578210576,9sleep00-21swapper/019:06:540
2855429667,10sleep30-21swapper/319:06:373
2875028866,6sleep10-21swapper/119:09:081
2855828667,8sleep20-21swapper/219:06:402
2891099252,2cyclictest141rcu_preempt23:49:142
2890499250,22cyclictest0-21swapper/023:30:130
28912992416,5cyclictest39-21ksoftirqd/321:46:323
2891299241,2cyclictest0-21swapper/323:40:033
28912992220,1cyclictest0-21swapper/321:40:133
2891099220,1cyclictest0-21swapper/223:39:592
2890799213,17cyclictest0-21swapper/123:15:171
2890799210,0cyclictest0-21swapper/122:40:421
2891299200,3cyclictest0-21swapper/322:51:413
2890799204,1cyclictest21916-21diskmemload22:10:371
28910991917,2cyclictest0-21swapper/223:57:502
28910991914,4cyclictest32-21ksoftirqd/200:00:222
2891099190,17cyclictest0-21swapper/200:31:362
28904991918,1cyclictest0-21swapper/021:34:250
2890499190,19cyclictest0-21swapper/022:28:360
2890499190,0cyclictest0-21swapper/020:35:130
2891299180,17cyclictest0-21swapper/322:47:193
2891299180,16cyclictest0-21swapper/322:29:513
2891099180,1cyclictest0-21swapper/222:45:142
2891099180,1cyclictest0-21swapper/222:05:512
28907991815,2cyclictest0-21swapper/123:21:261
2890799180,17cyclictest0-21swapper/122:33:491
28904991816,1cyclictest13-21ksoftirqd/019:45:150
2890499180,18cyclictest0-21swapper/021:10:120
28910991713,1cyclictest32-21ksoftirqd/221:58:552
28907991713,3cyclictest25-21ksoftirqd/100:35:221
2890799170,1cyclictest0-21swapper/123:41:191
2890799170,16cyclictest0-21swapper/123:10:531
2891299167,5cyclictest0-21swapper/322:09:593
28912991615,1cyclictest0-21swapper/323:25:143
2891099169,2cyclictest32-21ksoftirqd/223:12:022
2891099161,0cyclictest141rcu_preempt23:16:162
2891099160,1cyclictest141rcu_preempt21:42:072
2891099160,16cyclictest0-21swapper/221:38:522
2891099160,15cyclictest0-21swapper/200:38:542
28907991615,1cyclictest0-21swapper/100:20:281
28907991615,1cyclictest0-21swapper/100:20:271
28907991615,1cyclictest0-21swapper/100:17:001
2890799161,1cyclictest13959-21ssh23:58:311
2890799160,15cyclictest0-21swapper/100:25:581
2890499164,6cyclictest0-21swapper/022:02:230
28904991615,1cyclictest0-21swapper/000:10:520
2890499160,1cyclictest0-21swapper/022:09:320
28910991511,1cyclictest32-21ksoftirqd/222:03:492
2891099150,5cyclictest0-21swapper/200:07:002
2891099150,15cyclictest0-21swapper/223:07:132
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional