You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-07-23 - 11:18

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Thu Jul 23, 2026 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1091229066,8sleep00-21swapper/019:06:050
1117328875,9sleep20-21swapper/219:09:292
1097728861,9sleep30-21swapper/319:06:573
1106727969,6sleep10-21swapper/119:08:071
1130399270,27cyclictest0-21swapper/221:52:012
1130399270,26cyclictest0-21swapper/222:43:242
1130099261,13cyclictest0-21swapper/123:00:141
1130399230,22cyclictest0-21swapper/223:45:052
1130399230,22cyclictest0-21swapper/222:36:352
11296992322,1cyclictest0-21swapper/000:05:150
11296992320,2cyclictest13-21ksoftirqd/023:20:000
56152220,0chrt5616-21aten2_r7power_c21:30:151
1130099220,1cyclictest0-21swapper/122:11:051
11303992116,4cyclictest32-21ksoftirqd/221:31:292
11296992120,1cyclictest0-21swapper/019:53:040
1129699210,1cyclictest0-21swapper/021:20:030
1130699200,3cyclictest0-21swapper/300:22:063
1130399200,20cyclictest0-21swapper/200:26:012
1130099204,8cyclictest15157-21cat22:55:011
1130099200,19cyclictest0-21swapper/122:16:221
1130099200,19cyclictest0-21swapper/100:10:231
1129699200,20cyclictest0-21swapper/022:43:240
1130399196,12cyclictest0-21swapper/223:29:312
1129699193,2cyclictest25915-21hddtemp_smartct22:20:170
1129699190,17cyclictest0-21swapper/022:13:360
57082180,0sleep20-21swapper/223:08:252
1130699180,16cyclictest0-21swapper/323:30:493
11303991817,1cyclictest32-21ksoftirqd/223:20:562
1130399180,1cyclictest3893-21diskmemload00:20:322
1130399180,16cyclictest0-21swapper/223:10:092
1130399180,11cyclictest0-21swapper/219:35:142
1129699180,3cyclictest0-21swapper/022:45:140
1129699180,17cyclictest0-21swapper/021:29:260
11306991716,1cyclictest0-21swapper/321:37:123
11306991715,1cyclictest0-21swapper/321:10:143
1130699170,16cyclictest0-21swapper/300:29:423
1130399171,3cyclictest141rcu_preempt00:10:122
11303991713,1cyclictest32-21ksoftirqd/221:55:302
1130399170,1cyclictest0-21swapper/222:00:502
1130399170,16cyclictest0-21swapper/223:37:452
1130399170,14cyclictest0-21swapper/221:21:292
1130099173,2cyclictest141rcu_preempt23:33:421
1129699170,1cyclictest0-21swapper/000:26:150
1129699170,16cyclictest0-21swapper/022:36:350
11306991615,1cyclictest0-21swapper/322:25:593
1130399161,14cyclictest0-21swapper/200:35:142
1130399160,7cyclictest0-21swapper/221:43:302
1130399160,7cyclictest0-21swapper/221:43:302
1130399160,2cyclictest0-21swapper/221:15:122
1130399160,16cyclictest0-21swapper/220:07:112
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional