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2026-05-26 - 20:28

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Tue May 26, 2026 12:43:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1839210877,26sleep00-21swapper/007:09:060
183029080,6sleep10-21swapper/107:08:591
174329077,9sleep20-21swapper/207:07:522
177128471,9sleep30-21swapper/307:08:133
181062750,0sleep30-21swapper/311:38:163
321452470,0sleep10-21swapper/109:50:311
200299360,35cyclictest21914-21kworker/3:111:06:333
2002993028,1cyclictest21914-21kworker/3:111:32:033
2002993027,2cyclictest0-21swapper/311:30:003
1996992922,5cyclictest25-21ksoftirqd/109:26:221
2002992827,1cyclictest4658-21kworker/3:009:59:033
200099280,28cyclictest0-21swapper/209:11:102
200099280,19cyclictest141rcu_preempt10:32:342
2002992724,2cyclictest4658-21kworker/3:009:42:433
199199270,0cyclictest0-21swapper/009:25:110
199199260,24cyclictest0-21swapper/011:59:540
2002992524,1cyclictest21914-21kworker/3:112:00:043
2002992523,1cyclictest21914-21kworker/3:111:14:233
2002992521,3cyclictest4658-21kworker/3:009:35:143
200299251,23cyclictest4658-21kworker/3:009:45:533
1996992419,1cyclictest25-21ksoftirqd/112:07:001
2002992319,3cyclictest21914-21kworker/3:110:06:033
200299231,22cyclictest21914-21kworker/3:110:48:333
200299230,23cyclictest4658-21kworker/3:009:19:133
200299220,20cyclictest0-21swapper/309:29:303
200099220,1cyclictest0-21swapper/212:19:502
200099220,19cyclictest0-21swapper/211:19:492
199199223,14cyclictest30888-21ssh12:05:140
2002992119,2cyclictest21914-21kworker/3:111:20:233
200299211,20cyclictest21914-21kworker/3:112:23:573
200299210,21cyclictest21914-21kworker/3:110:39:343
200299210,21cyclictest0-21swapper/310:18:203
1996992119,2cyclictest25-21ksoftirqd/110:10:201
199199210,21cyclictest0-21swapper/010:11:330
2002992019,1cyclictest4658-21kworker/3:010:01:143
2002992018,2cyclictest21914-21kworker/3:111:55:433
2002992018,2cyclictest21914-21kworker/3:111:04:043
200099200,3cyclictest0-21swapper/212:00:242
199699208,3cyclictest141rcu_preempt08:20:231
1996992018,2cyclictest25-21ksoftirqd/111:24:481
1996992017,1cyclictest141rcu_preempt09:31:511
1996992017,0cyclictest0-21swapper/112:39:531
199699200,1cyclictest0-21swapper/112:16:511
2002991917,2cyclictest21914-21kworker/3:112:05:233
2002991916,3cyclictest4658-21kworker/3:009:33:533
2000991917,1cyclictest0-21swapper/211:40:252
1996991917,2cyclictest25-21ksoftirqd/110:15:271
199699190,3cyclictest141rcu_preempt11:02:141
1991991919,0cyclictest0-21swapper/011:43:260
1991991919,0cyclictest0-21swapper/010:39:200
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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