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2026-02-01 - 11:24
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #7, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack7slot7s.osadl.org (updated Sun Feb 01, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1655621400,0sleep00-21swapper/023:54:500
4069210074,9sleep00-21swapper/019:06:530
218129643,48sleep30-21swapper/319:05:113
399129178,9sleep20-21swapper/219:05:552
411728867,17sleep10-21swapper/119:07:301
75102650,0sleep20-21swapper/221:54:232
446299240,1cyclictest0-21swapper/321:48:273
445999240,23cyclictest0-21swapper/222:31:172
446299230,21cyclictest0-21swapper/300:34:203
445999230,22cyclictest0-21swapper/221:58:212
445999230,21cyclictest0-21swapper/222:16:152
445999230,21cyclictest0-21swapper/222:12:542
445999220,20cyclictest0-21swapper/221:31:452
445999220,19cyclictest0-21swapper/220:30:132
4459992120,1cyclictest0-21swapper/221:22:372
4457992118,1cyclictest0-21swapper/100:35:481
445799211,1cyclictest141rcu_preempt21:46:261
445799210,1cyclictest0-21swapper/123:15:481
446299202,16cyclictest3210-21apache_processe22:30:113
446299201,1cyclictest0-21swapper/300:10:053
446299200,1cyclictest0-21swapper/323:04:153
445999200,20cyclictest0-21swapper/222:02:552
445799200,19cyclictest997-21awk21:30:271
4452992013,3cyclictest28710-21grep22:25:240
446299190,2cyclictest0-21swapper/323:34:143
446299190,19cyclictest0-21swapper/322:57:393
446299190,17cyclictest0-21swapper/321:35:513
445999196,8cyclictest0-21swapper/220:40:002
4459991918,1cyclictest0-21swapper/221:46:242
4459991917,2cyclictest0-21swapper/223:03:582
445999190,19cyclictest0-21swapper/223:35:112
4457991917,1cyclictest0-21swapper/100:15:161
4457991913,3cyclictest141rcu_preempt22:42:031
445799190,2cyclictest0-21swapper/100:24:551
445299190,17cyclictest0-21swapper/020:15:130
446299181,7cyclictest0-21swapper/300:15:133
4459991816,1cyclictest22365-21hddtemp_smartct19:45:162
4459991816,1cyclictest18479-21apache_processe00:35:142
445999180,18cyclictest0-21swapper/223:20:332
445999180,18cyclictest0-21swapper/200:12:312
4462991717,0cyclictest0-21swapper/300:20:363
4457991716,1cyclictest0-21swapper/122:56:111
4457991714,2cyclictest25-21ksoftirqd/123:43:321
445799170,17cyclictest0-21swapper/100:34:241
446299169,6cyclictest311-21sh22:09:243
4462991611,3cyclictest31891-21expr23:25:183
446299160,2cyclictest0-21swapper/323:57:183
445999160,1cyclictest0-21swapper/223:52:522
445999160,1cyclictest0-21swapper/223:14:532
445999160,1cyclictest0-21swapper/222:58:522
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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