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2026-02-04 - 11:19
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Wed Feb 04, 2026 01:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
310928410,10sleep03107-21uptime19:05:530
36829914270,55cyclictest2980-21basename21:15:160
36829913671,48cyclictest22202-21sshd00:39:340
368299136110,15cyclictest0-21swapper/019:10:030
36829913270,46cyclictest26044-21chrt22:46:350
36829913270,21cyclictest16422-21df20:00:160
36829913175,44cyclictest11885-21munin-plugin-st00:00:020
36829912893,26cyclictest19408-21irqstats22:20:300
36829912769,18cyclictest15295-21memory19:55:360
36829912680,35cyclictest1276-21runrttasks22:25:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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