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2026-01-28 - 16:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Wed Jan 28, 2026 13:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7728211510,11sleep07718-21/usr/sbin/munin07:10:020
7774991688,46cyclictest19835-21ntp_states07:55:410
7774991647,18cyclictest20468-21apt-get10:07:070
77749916343,101cyclictest6836-21cron09:15:080
77749916327,119cyclictest787-21haveged12:25:080
77749916113,15cyclictest1408-21nginx10:19:220
7774991598,18cyclictest7711-21apt-get07:12:080
7774991597,116cyclictest1408-21nginx10:04:190
77749915946,93cyclictest10150irq/55-4a10000007:15:400
77749915924,15cyclictest10250irq/56-4a10000012:19:350
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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