You are here: Home / Technical Services / OSADL QA Farm Real-time / 
2026-02-26 - 13:23
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Thu Feb 26, 2026 01:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27913218123,131sleep027923-21memory19:05:240
28818991616,98cyclictest445-21apt-get19:25:270
28818991609,116cyclictest18273-21users20:31:340
28818991608,92cyclictest31290-21apt-get19:18:120
28818991607,131cyclictest6827-21sshd19:47:400
28818991607,101cyclictest25055-21/usr/sbin/munin21:00:110
28818991579,110cyclictest1305-21snmpd20:45:010
28818991579,108cyclictest1305-21snmpd20:50:030
28818991578,127cyclictest14935-21/usr/sbin/munin00:31:020
288189915710,107cyclictest29281-21ntp_states19:10:390
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional