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2026-02-05 - 02:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Thu Feb 05, 2026 01:44:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24903213360,10sleep024904-21irqstats19:05:330
257929917339,115cyclictest10250irq/56-4a10000022:53:180
257929917022,16cyclictest22759-21latency_hist21:05:040
257929916542,108cyclictest2075-21ntpq19:40:350
257929916528,14cyclictest10250irq/56-4a10000000:14:010
257929916437,115cyclictest1408-21nginx21:10:500
257929916430,20cyclictest13479-21sendmail-msp00:40:020
257929916331,13cyclictest0-21swapper/020:54:170
257929916328,13cyclictest10250irq/56-4a10000000:08:560
257929916229,12cyclictest0-21swapper/020:49:160
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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