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2026-03-02 - 17:04
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Mon Mar 02, 2026 13:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5397221317,32sleep00-21swapper/007:06:150
59059913042,34cyclictest4885-21apt-get11:17:240
59059912342,62cyclictest11467-21users09:35:490
59059912257,49cyclictest1305-21snmpd11:25:270
59059912242,36cyclictest1934-21df09:00:170
59059912034,34cyclictest9705-21wget09:30:140
59059911935,34cyclictest14688-21users11:55:490
59059911755,32cyclictest25194-21sendmail-msp12:40:030
59059911736,41cyclictest12314-21df_inode09:40:180
59059911664,35cyclictest3650irq/20-4900000010:45:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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