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2026-02-22 - 09:38
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Sun Feb 22, 2026 01:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7776225328,187sleep01305-21snmpd19:09:190
79239912455,51cyclictest6130-21ntpq23:15:380
79239912437,32cyclictest5800-21ntp_states21:05:420
79239912266,37cyclictest1-21systemd20:45:450
79239912245,21cyclictest23605-21apt-get20:12:090
79239911944,21cyclictest22858-21ntp_states00:21:120
79239911842,23cyclictest17045-21aten_r7power_cu00:00:130
79239911756,46cyclictest14117-21/usr/sbin/munin19:35:020
79239911745,18cyclictest12394-21ntp_states23:40:410
79239911740,37cyclictest20626-21cron00:15:010
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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