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2026-03-03 - 19:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Tue Mar 03, 2026 13:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
27798221231,51sleep00-21swapper/007:09:050
27970991646,136cyclictest1305-21snmpd11:41:520
279709916216,18cyclictest1408-21nginx10:15:480
27970991606,133cyclictest1305-21snmpd10:31:370
27970991606,133cyclictest11856-21chrt08:13:050
279709916016,16cyclictest1408-21nginx09:23:500
27970991597,130cyclictest23319-21/usr/sbin/munin11:05:120
279709915937,109cyclictest26300-21/usr/sbin/munin09:10:450
27970991588,17cyclictest19982-21sh10:50:420
27970991587,130cyclictest10022-21apt-config12:20:210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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