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2026-01-30 - 05:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Fri Jan 30, 2026 01:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
23217221032,55sleep00-21swapper/019:08:430
234319912198,13cyclictest0-21swapper/019:10:040
234319910850,44cyclictest101ktimersoftd/022:52:060
234319910748,21cyclictest24876-21runrttasks23:30:270
234319910463,26cyclictest101ktimersoftd/000:18:210
23431999731,14cyclictest101ktimersoftd/000:27:090
23431999543,37cyclictest0-21swapper/019:15:370
23431999450,31cyclictest101ktimersoftd/020:52:100
23431999356,22cyclictest101ktimersoftd/000:00:060
23431999334,39cyclictest0-21swapper/021:23:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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