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2026-01-21 - 08:08
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Wed Jan 21, 2026 01:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5564226129,192sleep05557-21/usr/sbin/munin19:05:120
67499911145,52cyclictest21365-21wget22:15:130
67499910929,61cyclictest1408-21nginx21:52:360
67499910522,31cyclictest23134-21df00:30:140
67499910445,40cyclictest19401-21wc22:06:260
67499910351,35cyclictest16056-21runrttasks19:45:430
67499910327,55cyclictest1305-21snmpd23:53:590
67499910124,24cyclictest6336-21ntp_states21:15:410
67499910045,36cyclictest1276-21runrttasks20:31:170
6749999943,38cyclictest18423-21seq19:55:380
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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