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2026-02-03 - 09:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Tue Feb 03, 2026 01:44:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19362212370,10sleep019361-21sshd19:06:350
198419912644,49cyclictest15217-21wget23:05:110
198419912262,44cyclictest2660-21irqstats20:05:300
198419912256,47cyclictest21131-21sshd19:12:350
198419912044,20cyclictest28813-21diskstats19:40:370
198419912043,37cyclictest3869-21munin-run22:20:020
198419911946,53cyclictest28036-21sh19:40:000
198419911946,36cyclictest380-21seq22:05:160
198419911844,34cyclictest23753-21/usr/sbin/munin21:30:180
198419911843,37cyclictest1844-21awk22:10:370
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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