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2026-01-31 - 00:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Fri Jan 30, 2026 13:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18710220628,50sleep00-21swapper/007:07:260
19081991639,109cyclictest17300-21apt-get11:17:070
19081991608,130cyclictest32200-21/usr/sbin/munin12:15:310
19081991608,112cyclictest19015-21ntpq09:15:370
190819916034,108cyclictest10250irq/56-4a10000008:24:390
19081991599,105cyclictest21541-21apt-get07:22:120
190819915827,112cyclictest3904-21sshd08:15:190
190819915628,106cyclictest1305-21snmpd09:01:000
19081991559,100cyclictest28694-21wget07:45:110
19081991558,108cyclictest29781-21ntp_states12:05:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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