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2026-02-20 - 20:18
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Fri Feb 20, 2026 13:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
218359916058,16cyclictest26211-21mailstats07:25:460
21522213844,62sleep00-21swapper/007:07:540
6615211110,11sleep06618-21irqstats12:30:270
2407421109,11sleep01305-21snmpd09:24:040
3199821074,12sleep031763-21/usr/sbin/munin09:55:280
218359910442,45cyclictest10250irq/56-4a10000007:20:150
90722986,12sleep09066-21ntp_states08:26:230
71552986,81sleep07158-21df_inode08:20:180
223752975,80sleep022373-21diskstats11:25:210
31712966,78sleep03179-21users12:15:480
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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