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2026-03-08 - 04:10
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Sun Mar 08, 2026 01:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9289222235,152sleep00-21swapper/019:07:060
9700991648,105cyclictest17272-21/usr/sbin/munin19:40:420
9700991637,96cyclictest23693-21apt-get00:18:170
97009916117,110cyclictest26630-21apt-get22:27:090
9700991609,113cyclictest8309-21apt-get23:17:120
9700991607,113cyclictest8410-21memory21:10:590
9700991598,130cyclictest1305-21snmpd21:48:200
9700991596,109cyclictest12689-21ntpq19:20:390
9700991578,96cyclictest10356-21irqstats23:25:310
9700991568,128cyclictest25696-21runrttasks22:20:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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