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2026-01-29 - 16:39
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Thu Jan 29, 2026 13:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
30549219520,33sleep00-21swapper/007:08:130
308269917238,30cyclictest10250irq/56-4a10000009:36:330
308269917043,30cyclictest3650irq/20-4900000009:27:110
308269916832,30cyclictest101ktimersoftd/012:20:130
308269916752,16cyclictest10150irq/55-4a10000008:40:300
308269916636,29cyclictest11047-21runrttasks10:05:200
308269916635,14cyclictest10250irq/56-4a10000009:05:550
308269916121,27cyclictest2133-21munin-run07:25:010
30826991596,35cyclictest29045-21ntpq11:15:410
308269915755,16cyclictest24980-21latency_hist08:55:030
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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