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2026-01-15 - 22:06
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Thu Jan 15, 2026 13:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24220212250,12sleep024218-21/usr/sbin/munin07:05:120
25320991719,106cyclictest2754-21/usr/sbin/munin12:00:300
25320991647,116cyclictest1305-21snmpd08:11:060
25320991597,89cyclictest965-21apt-get11:57:110
253209915831,91cyclictest0-21swapper/012:36:100
25320991577,94cyclictest27303-21apt-get09:27:090
253209915721,121cyclictest30625-21fw_conntrack07:30:240
253209915526,107cyclictest1305-21snmpd11:30:520
253209915525,112cyclictest5544-21wget08:00:140
25320991548,124cyclictest1989-21/usr/sbin/munin09:50:110
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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