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2026-02-01 - 19:37
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Sun Feb 01, 2026 13:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1129220828,52sleep00-21swapper/007:05:470
17169916642,105cyclictest24182-21proc_pri10:41:260
17169916329,114cyclictest10673-21cron09:50:040
17169916321,122cyclictest15655-21latency_hist10:10:030
17169916130,110cyclictest7432-21/usr/sbin/munin11:45:140
1716991598,39cyclictest1305-21snmpd11:31:380
1716991587,19cyclictest30056-21df11:05:180
17169915837,108cyclictest801-21dbus-daemon08:40:020
17169915828,18cyclictest1305-21snmpd11:54:230
17169915820,12cyclictest10250irq/56-4a10000007:29:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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