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2026-02-02 - 20:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Mon Feb 02, 2026 13:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
22122220528,51sleep00-21swapper/007:06:130
226329917046,106cyclictest3650irq/20-4900000010:52:140
226329916743,108cyclictest10250irq/56-4a10000011:45:140
226329916416,14cyclictest0-21swapper/008:50:120
226329916328,20cyclictest1305-21snmpd10:41:360
226329916131,112cyclictest13469-21dpkg08:40:080
226329916125,16cyclictest1408-21nginx10:25:320
226329916038,103cyclictest3650irq/20-4900000008:42:110
226329916031,108cyclictest1643-21/usr/sbin/munin07:55:380
226329915927,113cyclictest3541-21apt-key08:00:180
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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