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2026-02-01 - 07:09
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Sun Feb 01, 2026 01:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
499829090,12sleep04997-21proc_pri19:05:320
5756991657,25cyclictest1408-21nginx20:06:310
57569916427,14cyclictest10250irq/56-4a10000021:55:150
57569916227,13cyclictest0-21swapper/020:12:490
57569916129,99cyclictest754-21systemd-journal23:48:370
57569916110,18cyclictest15378-40gzip00:00:120
57569916023,118cyclictest9160-21ntpq23:35:370
57569915948,93cyclictest10150irq/55-4a10000023:50:280
57569915936,112cyclictest15894-21runrttasks19:50:140
57569915930,12cyclictest10250irq/56-4a10000020:31:340
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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