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2026-02-25 - 19:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Wed Feb 25, 2026 13:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24958221831,51sleep00-21swapper/007:08:080
2524799163140,14cyclictest90652sleep012:16:450
252479914650,40cyclictest30759-21apt-get11:42:090
252479913442,37cyclictest12657-21apt-get08:27:080
252479913353,37cyclictest28700-21ntp_states07:21:210
252479913265,23cyclictest7804-21cat08:05:180
252479913175,38cyclictest25905-21sshd09:15:310
252479913037,38cyclictest9680-21apt-get10:17:110
252479912855,54cyclictest754-21systemd-journal12:00:010
252479912852,54cyclictest22275-21ntp_states09:00:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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