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2026-02-28 - 12:43
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Sat Feb 28, 2026 01:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31912220727,49sleep00-21swapper/019:09:550
319889917891,76cyclictest0-21swapper/019:10:040
2248021079,13sleep022478-21ntp_states20:40:370
319889910525,31cyclictest787-21haveged21:20:040
319889910344,43cyclictest101ktimersoftd/023:40:170
2111121039,14sleep0101ktimersoftd/020:35:290
319889910057,25cyclictest101ktimersoftd/023:27:080
319889910046,33cyclictest8644-21/usr/sbin/munin19:45:270
38692996,11sleep03920-21/usr/sbin/munin19:25:460
167182995,12sleep01305-21snmpd00:33:400
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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