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2026-01-23 - 23:17
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Fri Jan 23, 2026 13:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1297822424161,383sleep012560-21kworker/0:007:05:140
141039916439,104cyclictest0-21swapper/011:40:590
141039916235,30cyclictest107242chrt11:28:180
14103991577,15cyclictest19178-21apt-get12:11:150
141039915749,14cyclictest10150irq/55-4a10000010:40:110
141039915747,17cyclictest19281-21cut12:10:080
141039915447,15cyclictest10150irq/55-4a10000011:10:130
141039915061,11cyclictest101ktimersoftd/010:55:270
141039914940,27cyclictest101ktimersoftd/009:59:020
141039914938,30cyclictest19107-21seq09:42:570
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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