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2026-02-27 - 14:47
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Fri Feb 27, 2026 13:44:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
6150229331,76sleep05961-21/usr/sbin/munin07:05:160
714899139116,14cyclictest213692sleep008:05:440
71489912958,32cyclictest1408-21nginx09:09:020
71489912954,58cyclictest2563-21ps11:05:420
71489912551,54cyclictest28301-21http08:35:040
71489912439,33cyclictest21683-21wget12:20:200
71489912339,31cyclictest18676-21fw_forwarded_lo07:55:270
71489912149,34cyclictest17585-21ntp_states07:50:380
71489912143,36cyclictest9235-21apt-get07:17:060
71489912075,36cyclictest22443-21apt-get10:17:060
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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