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2026-01-21 - 15:13
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack7slot8.osadl.org (updated Wed Jan 21, 2026 13:44:18)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29637221131,54sleep00-21swapper/007:05:350
302489917342,112cyclictest10250irq/56-4a10000007:39:470
30248991637,29cyclictest17403-21latency_hist12:35:030
302489916238,12cyclictest8950irq/40-mmc108:12:110
302489916140,13cyclictest10150irq/55-4a10000007:25:250
30248991597,19cyclictest1971-21seq07:22:130
302489915922,16cyclictest30195-21wget11:20:120
302489915844,13cyclictest10150irq/55-4a10000011:50:100
30248991577,22cyclictest2010-21node07:54:290
302489915752,94cyclictest31681-21/usr/sbin/munin11:25:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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