You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2025-05-11 - 17:04
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 50 million
Resolution of latency scale: reduced 
Duration: 5 hours, 33 minutes
Characteristics of the highest latencies:
System rack8slot1.osadl.org (updated Sun May 11, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1800799206153,0cyclictest0-21swapper08:41:480
1800799204110,0cyclictest0-21swapper08:52:300
1800799203106,0cyclictest0-21swapper08:31:280
1800799202107,0cyclictest0-21swapper11:52:170
1800799202104,0cyclictest0-21swapper12:17:290
1800799200117,0cyclictest0-21swapper11:58:500
1800799200105,0cyclictest0-21swapper11:39:310
1800799200105,0cyclictest0-21swapper10:42:160
1800799199142,0cyclictest0-21swapper07:48:020
1800799199103,0cyclictest0-21swapper07:26:490
1800799197139,0cyclictest0-21swapper07:40:260
1800799197103,0cyclictest0-21swapper09:40:430
17172219739,0sleep017199-21missed_timers06:47:070
1800799195137,0cyclictest0-21swapper11:12:050
1800799195136,0cyclictest0-21swapper10:40:290
1800799195121,0cyclictest0-21swapper12:12:040
1800799195114,0cyclictest0-21swapper10:02:080
1800799195104,0cyclictest0-21swapper12:08:500
1800799195101,0cyclictest0-21swapper08:27:350
180079919490,0cyclictest0-21swapper08:02:270
180079919299,0cyclictest0-21swapper07:24:420
180079919297,0cyclictest0-21swapper10:26:540
1800799192117,0cyclictest0-21swapper07:57:530
1800799192112,0cyclictest0-21swapper08:51:020
180079919194,0cyclictest0-21swapper06:51:370
1800799191139,0cyclictest0-21swapper11:07:530
1800799191111,0cyclictest0-21swapper08:12:350
1800799191110,0cyclictest0-21swapper07:54:350
1800799191109,0cyclictest0-21swapper09:52:200
180079919094,0cyclictest0-21swapper07:02:310
1800799190120,0cyclictest0-21swapper10:52:460
1800799190115,0cyclictest0-21swapper10:22:360
1800799190113,0cyclictest0-21swapper09:44:410
1800799190111,0cyclictest0-21swapper11:44:060
1800799190111,0cyclictest0-21swapper11:19:290
1800799190111,0cyclictest0-21swapper09:28:460
1800799190110,0cyclictest0-21swapper09:13:370
1800799190107,0cyclictest0-21swapper07:08:050
180079918994,0cyclictest0-21swapper11:27:320
1800799189134,0cyclictest0-21swapper08:20:190
1800799189115,0cyclictest0-21swapper09:01:350
1800799189113,0cyclictest0-21swapper11:02:260
1800799189113,0cyclictest0-21swapper08:07:370
1800799189110,0cyclictest0-21swapper12:04:200
1800799189109,0cyclictest0-21swapper10:59:480
1800799189109,0cyclictest0-21swapper06:59:300
1800799188134,0cyclictest0-21swapper10:07:480
1800799188111,0cyclictest0-21swapper10:14:440
1800799188109,0cyclictest0-21swapper11:24:280
180079918796,0cyclictest0-21swapper11:46:490
1800799187132,0cyclictest0-21swapper10:49:190
1800799187111,0cyclictest0-21swapper07:18:020
1800799187109,0cyclictest0-21swapper09:10:360
1800799187108,0cyclictest0-21swapper07:15:490
1800799187107,0cyclictest0-21swapper07:35:070
1800799186134,0cyclictest12634-21aten2.4_r8power09:46:460
1800799186112,0cyclictest0-21swapper10:17:110
1800799186110,0cyclictest0-21swapper11:32:350
180079918593,0cyclictest0-21swapper09:21:490
1800799185132,0cyclictest3355-21runrttasks09:16:200
1800799185109,0cyclictest0-21swapper07:45:020
1800799185108,0cyclictest0-21swapper08:40:260
1800799185106,0cyclictest0-21swapper08:24:200
1800799184128,0cyclictest0-21swapper09:33:440
1800799184109,0cyclictest0-21swapper10:35:130
1800799184104,0cyclictest0-21swapper09:59:450
1800799183128,0cyclictest0-21swapper08:58:590
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional