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2026-05-31 - 06:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot2.osadl.org (updated Tue May 19, 2026 06:45:08)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
216211399151138,8cyclictest80-21hwrng06:33:251
216211399144126,6cyclictest80-21hwrng06:12:561
216211399144126,6cyclictest80-21hwrng06:12:561
216211299144135,5cyclictest80-21hwrng05:52:270
216211299138129,5cyclictest80-21hwrng06:19:050
216211599122112,5cyclictest80-21hwrng06:31:223
216211399120103,12cyclictest80-21hwrng06:36:291
216211399120103,12cyclictest80-21hwrng06:36:291
2162112991182,15cyclictest2527902-21sh06:33:190
216211599113104,7cyclictest80-21hwrng05:38:073
216211599113104,7cyclictest80-21hwrng05:38:073
21621159911297,10cyclictest80-21hwrng06:30:203
216211499111103,6cyclictest80-21hwrng05:23:472
216211599110101,6cyclictest80-21hwrng05:14:343
216211599110101,6cyclictest80-21hwrng05:14:343
216211399109100,5cyclictest80-21hwrng05:22:451
216211599108101,4cyclictest80-21hwrng05:49:233
21621129910519,35cyclictest0-21swapper/006:35:380
21621129910519,35cyclictest0-21swapper/006:35:380
21621159910494,7cyclictest80-21hwrng06:04:443
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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