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2026-08-29 - 14:37
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack8slot2.osadl.org (updated Wed Aug 19, 2026 12:43:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31621249916672,71cyclictest0-21swapper/309:41:093
316212199158140,9cyclictest80-21hwrng10:51:360
31621229915424,85cyclictest31-21ksoftirqd/108:25:201
316212299149119,26cyclictest80-21hwrng10:18:501
31621219913597,23cyclictest10450irq/205-8000000.ethernet-rx011:19:150
3162123991311,45cyclictest3303156-21df11:25:352
316212199131119,9cyclictest80-21hwrng09:22:310
316212199131119,8cyclictest80-21hwrng09:16:230
316212199131115,5cyclictest80-21hwrng10:56:440
316212499130119,6cyclictest80-21hwrng11:16:113
316212299129117,8cyclictest80-21hwrng09:11:151
316212199129113,13cyclictest80-21hwrng10:04:300
316212299128118,5cyclictest80-21hwrng09:33:471
316212199128112,12cyclictest80-21hwrng12:15:340
31621239912755,57cyclictest0-21swapper/210:30:012
316212399127112,4cyclictest80-21hwrng09:00:002
316212399127112,4cyclictest80-21hwrng09:00:002
316212399127111,6cyclictest80-21hwrng08:06:452
316212299127110,8cyclictest80-21hwrng09:44:011
316212199127119,5cyclictest80-21hwrng12:14:330
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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