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2026-10-22 - 03:12
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot3.osadl.org (updated Thu Oct 22, 2026 01:11:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5103
"cycles":100000000,5102
"load":"idle",5101
"condition":{5100
"clock":"2667"5098
"family":"x86",5097
"vendor":"Intel",5096
"processor":{5094
"dataset":"2024-01-08T03:37:02+0100"5092
"origin":"2024-01-08T00:43:21+0100",5091
"timestamps":{5090
"granularity":"microseconds"5088
3117:23:205086
48,17:22:505085
39,17:22:505084
23,17:22:505083
"maxima":[5082
017:22:505079
0,17:22:505078
0,17:22:505077
0,17:22:505076
0,17:22:505075
0,17:22:505074
0,17:22:505073
0,17:22:505072
0,17:22:505071
0,17:22:505070
0,17:22:505069
0,17:22:505068
0,17:22:505067
0,17:22:505066
0,17:22:505065
0,17:22:505064
0,17:22:505063
0,17:22:505062
0,17:22:505061
0,17:22:505060
0,17:22:505059
0,17:22:505058
0,17:22:505057
0,17:22:505056
0,17:22:505055
0,17:22:505054
0,17:22:505053
0,17:22:505052
0,17:22:505051
0,17:22:505050
0,17:22:505049
0,17:22:505048
0,17:22:505047
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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