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2025-12-21 - 08:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack8slot3.osadl.org (updated Sun Dec 21, 2025 01:11:07)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5103
"cycles":100000000,5102
"load":"idle",5101
"condition":{5100
"clock":"2667"5098
"family":"x86",5097
"vendor":"Intel",5096
"processor":{5094
"dataset":"2024-01-08T03:37:02+0100"5092
"origin":"2024-01-08T00:43:21+0100",5091
"timestamps":{5090
"granularity":"microseconds"5088
3110:51:075086
48,10:50:375085
39,10:50:375084
23,10:50:375083
"maxima":[5082
010:50:375079
0,10:50:375078
0,10:50:375077
0,10:50:375076
0,10:50:375075
0,10:50:375074
0,10:50:375073
0,10:50:375072
0,10:50:375071
0,10:50:375070
0,10:50:375069
0,10:50:375068
0,10:50:375067
0,10:50:375066
0,10:50:375065
0,10:50:375064
0,10:50:375063
0,10:50:375062
0,10:50:375061
0,10:50:375060
0,10:50:375059
0,10:50:375058
0,10:50:375057
0,10:50:375056
0,10:50:375055
0,10:50:375054
0,10:50:375053
0,10:50:375052
0,10:50:375051
0,10:50:375050
0,10:50:375049
0,10:50:375048
0,10:50:375047
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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